EC24C64BNF2GR [E-CMOS]
64K-bit 2-WIRE SERIAL EEPROM;
| 型号： | EC24C64BNF2GR |
| 厂家： | 
E-CMOS Corporation |
| 描述： | 64K-bit 2-WIRE SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Description
Features
The EC24C64B provides 65,536 bits of serial
electrically erasable and programmable read-
only memory (EEPROM) organized as 8192
words of 8 bits each. The device’s cascadable
feature allows up to 8 devices to share a
common 2-wire bus. The device is optimized
for use in many industrial and commercial
applications where low-power and low-voltage
operations are essential.
Low Operation Voltage： VCC = 1.7V to 5.5V
Internally Organized.. 8192x8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Bidirectional Data Transfer Protocol
1 MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility
Write Protect Pin for Hardware Data Protection
32-byte Page Write Modes(Partial Page Writes are
Allowed)
Self-timed Write Cycle (5 ms max)
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 40 Years
TDFN-8 packages(RoHS compliant and Halogen-free)
Pin Description
Pin Configuration
Pin Name
A0 - A2
SDA
Functions
Devices Address Inputs
Serial Data Input / Output
Serial Clock Input
Write Protect
TDFN-8
SCL
WP
GND
VCC
Ground
Power Supply
Top View
Ordering Information
Marking Information
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Figure 1. Block Diagram
E-CMOS Corp. (www.ecmos.com.tw)
Page 2 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Pin Descriptions
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device
and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hardwired or left not connected for hardware compatibility with other EC24C64B devices. When the pins
are hardwired, as many as eight 64K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section). If the pins are left floating,
the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to
the circuit board VCC plane is <3pF, if coupling is >3pF, ECMOS recommends connecting the address
pins to GND.
WRITE PROTECT (WP): The EC24C64B has a Write Protect pin that provides hardware data
protection. The WP pin allows normal write operations when connected to ground (GND). When the Write
Protect pin is connected to VCC, all write operations to the memory are inhibited. If the pin is left floating,
the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane
is <3pF. If coupling is >3pF, ECMOS recommends connecting the WP to GND. Switching WP to
VCC prior to a write operation creates a software write protected function.
Write Protect Description
Part of the Memory Protected
WP Pin Status
EC24C64B
Full (64K) Memory
WP=VCC
WP=GND
Normal Read/Write Operations
Memory Organization
EC24C64B, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires
a 13-bit data word address for random word addressing.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on
the SDA pin may change only during SCL low time periods (refer to Figure 4). Data changes
during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (refer to Figure 5).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 5).
ACKNOWLEDGE: All address and data words are serially transmitted to and from the EEPROM in 8-
bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has
received each word.
STANDBY MODE: The EC24C64B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations.
Memory RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be
reset in following these steps:
1. Clock up to 9 Cycles.
2. Look for SDA high in each cycle while SCL is high and then,
3. Create a start condition as SDA is high.
E-CMOS Corp. (www.ecmos.com.tw)
Page 3 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Bus Timing
Figure 2．SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3
．SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Figure 4
．Data Validity
Figure 5
．Start and Stop Definition
Figure 6
．Output Acknowledge
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Device Addressing
The 64K EEPROM device requires a 8-bit device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 7).
The device address word consists of a mandatory one,zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices.
The 64K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on
the same bus. These bits must compare to their corresponding hard wired input pins. The A2, A1
and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are
allowed to float.The Module package device address word also consists of a mandatory one,
zero sequence for the first four most significant bits. The next 3 bits are all zero.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device
address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby
state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small
noise spikes from activating the device.
DATA SECURITY: The EC24C64B has a hardware data protection scheme that allows the user to
write protect the entire memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word address following the device address
word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with
a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate
the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write
cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM
will not respond until the write is complete (refer to Figure 8).
PAGE WRITE: The 64K EEPROM is capable of 32-byte page writes. A page write is initiated the
same way as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word,
the microcontroller can transmit up to 31more data words. The EEPROM will respond with a zero after
each data word received.The microcontroller must terminate the page write sequence with a stop
condition (refer to Figure 9).
The data word address lower five bits are internally incremented following the receipt of each data word.
The higher data wordaddressbits are not incremented, retaining the memory page row location.When the
word address,internally generated,reaches the page boundary,the following byte is placed at the
beginning of the same page.Ifmore than 32 data words are transmitted to the EEPROM, the data word
address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM
inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition
followed by the device address word.The read/write bit is representative of the operation desired. Only
if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or
write sequence to continue.
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to one.There are three read operations: current address
read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address
accessed during the last read or write operation,incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address “roll over” during read is
from the last byte of the last memory page to the first byte of the first page. The address “roll over”
during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller does not
respond with an input zero but does generate a following stop condition (refer to Figure 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word
address. Once the device address word and data word address are clocked in and acknowledged by
the EEPROM, the microcontroller must generate another start condition. The microcontroller now
initiates a current address read by sending a device address with the read/write select bit high.
The EEPROM acknowledges the device address and serially clocks out the data word. The
microcontroller does not respond with a zero but does generate a following stop condition (refer to
Figure 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random
address read. After the microcontroller receives a data word, it responds with an acknowledge. As
long as the EEPROM receives an acknowledge, it will continue to increment the data word address
and serially clock out sequential data words. When the memory address limit is reached, the data
word address will “roll over” and the sequential read will continue. The sequential read operation is
terminated when the microcontroller does not respond with a zero but does generate a following
stop condition (refer to Figure 12).
Figure 7
．Device Address
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Figure 8
．Byte Write
Figure 9
．Page Write
Figure 10
．Current Address Read
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Figure 11
．
Random Read
Figure 12
．
Sequential Read
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Electrical Characteristics
Operating Temperature
-55
-65
°
C to +125
°
C
C
Storage Temperature
°C to +150
°
Voltage on Any Pin with Respect to
Ground
-1.0V to +7.0V
Maximum Operating Voltage
DC Output Current
6.25V
5.0 mA
*NOTICE: Stresses beyond those listed under “Absolute MaximumRatings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of this specification
are not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
Applicable over recommended operating range from: T
(unless otherwise noted).
A
= -40°C to +85°C, VCC = +1.7V to +5.5V,
Parameter
Supply Voltage
Symbol
VCC
ICC1
ICC2
ISB1
Min.
1.7
Typ.
Max.
5.5
1.0
3.0
1.0
6.0
3.0
3.0
Unit
V
Condition
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC=1.7V
Standby Current VCC=5.5V
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Output Low Level VCC =3.0V
Output Low Level VCC =1.7V
0.4
2.0
mA
mA
μA
uA
μA
μA
V
V
V
V
READ at 400 kHz
WRITE at 400 kHz
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
ISB2
ILI
0.1
0.05
ILO
(1)
VIL
-0.6
VCC x 0.7
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VOL2
VOL1
IOL = 2.1 mA
IOL = 0.15 mA
0.2
Note (1):VIL min and VIH max are reference only and are not tested
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.7V
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Symbol
Min.
-
-
Typ.
-
-
Max.
8
6
Unit
pF
pF
Condition
VI/O = 0V
VIN = 0V
(2)
CI/O
(2)
CIN
Note(2):This parameter is characterized and is not 100% tested.
E-CMOS Corp. (www.ecmos.com.tw)
Page 10 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
AC Electrical Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF
(unless otherwise noted). Test Condition are listed Note2.
VCC =5.5V
VCC=1.7V
VCC=2.5V
Parameter
Symbol
Units
Min.
Max.
Min.
Max.
Min.
Max.
1000
-
-
50
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time1
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
Start Hold Time
fSCL
tLOW
tHIGH
tI
-
1.3
0.6
-
400
-
-
100
0.9
1000
-
0.4
0.4
-
kHz
μs
μs
ns
μs
0.45
0.45
50
tAA
0.02
0.02
0.5
0.55
0.02
0.55
1
tBUF
1.3
-
0.5
-
μs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
0.6
0.6
0
100
-
-
-
-
-
0.25
0.25
0
0.25
0.25
0
-
-
-
μs
μs
μs
ns
μs
ns
μs
ns
ms
Start Setup Time
Data In Hold Time
Data In Setup Time
100
100
-
-
0.25
20
-
-
0.3
100
-
-
5
Inputs Rise Time1
0.3
300
-
-
5
0.3
100
Inputs Fall Time1
-
Stop Setup Time
Data Out Hold Time
Write Cycle Time
0.6
20
-
0.25
20
tWR
5
3.3V, 25°C, Page Mode
Endurance1
1M
-
Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ
Input pulse voltages: 0.3 x VCC to 0.7 x VCC
Input rise and fall time: ≦50 ns
Input and output timing reference voltages: 0.5 x VCC
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 12
3H29N-Rev.F001
EC24C64B
64K-bit 2-WIRE SERIAL EEPROM
Mechanical Dimensions
OUTLINE DRAWING TDFN-8
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 12
3H29N-Rev.F001
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