EC25C256NM1GR [E-CMOS]
256Kbits SPI Serial EEPROM;
| 型号： | EC25C256NM1GR |
| 厂家： | 
E-CMOS Corporation |
| 描述： | 256Kbits SPI Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EC25C256
256Kbits SPI Serial EEPROM
General Description
The EC25C256 is an industrial standard The EC25C256 also offers an additional page, named the
electrically erasable programmable read only Identification Page(64 bytes) which can be written and
memory (EEPROM) Product that utilizes (later) permanently locked in
standard Serial Peripheral Interface (SPI) for Identification Page offers
Read-only mode. This
flexibility in the application
communications. The EC25C256 contains
memory array of 256K bits (32,768x 8), which is used to store unique
organized in 64 bytes per page. and/or parameters specific to the production line.
a
board production line, as the Identification Page can be
identification parameters
This EEPROM operates in a wide voltage range In order to refrain the state machine from entering into a
from 1.7V to 5.5V,which fits most application. Wrong state during power-up sequence or a power
The device provides low-power operations and toggle off-on condition, a power on reset circuit is
low standby current. The product is offered in implemented. During power-up, the device does not
Lead-free, RoHS, halogen free or Green package. respond to any instructions until the supply voltage
The available package types are 8-pin SOP,
TSSOP and UDFN.
(VCC)has reached an acceptable stable level above the
reset threshold voltage. Once VCC passes the power on
The functionalities of the EC25C256 are optimized reset threshold, the device is reset and enters into
for most applications, such as consumer Standby mode. This should also avoid any inadvertent
electronics,
industrial, medical ,instrumentation, commercial down process, the device will enter into standby mode,
and others, where low-power and low-voltage once VCC drops below the power on reset threshold
wireless,
telecommunication, Write operations during power-up stage. During power-
Are vital. This product has a compatible SPI voltage. In addition, the device will be in standby mode
interface: Chip-Select ( CS ), Serial Data In (SI), after receiving the Stop command, provided that no
Serial Data Out (SO) and Serial Clock (SCK) internal write operation is in progress. Nevertheless,
for
a Hold feature via HOLD pin allows the device operating level.
entering into suspended state whenever
high-speed communication. Furthermore, it is illegal to send a command unless the VCC is within its
a
necessary and resuming the communication
without re-initializing the serial sequence. A
Status Register facilitates
a
flexible write
protection mechanism and device Status
monitoring.
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Features
Serial Peripheral Interface (SPI) Compatible
Supports Mode 0 (0,0) and Mode 3 (1,1)
Wide-voltage Operation
VCC = 1.7V to 5.5V
Low power CMOS
Block Write Protection
Protect 1/4, 1/2, or Entire Array
—
—
Self timed write cycle: 5 ms (max.)
Additional Write lockable Page (Identification
—
page)
High-reliability
—
—
Standby current: ≤1 μA (1.7V)
Operating current: ≤2 mA (1.7V)
—
—
Endurance: 1 million cycles
Data retention: 100 years
Operating frequency: 20 MHz (5.5V)
Memory organization: 256Kb (32,768 x 8)
Byte and Page write (up to 64 bytes)
Industrial temperature grade
Packages (8-pin): SOP, TSSOP and DFN
Lead-free, RoHS, Halogen free, Green
—
Partial page write allowed
Ordering Information & Marking Information
EC25C XXXN XX X X
R：Tape & Reel
G：Green
Device Function
256＝256Kbit
(32768×8)
M1：SOP-8
E1：TSSOP-8
F2：DFN-8
Package type
Part Number
Marking
Marking Information
25C256：Part No
25C256
LLLLL
SOP-8
EC25C256NM1GR
YYWWT
25C256
LLLLL
LLLLL：the last five numbers of wafer lot number
YYWW：Date Code.
T ：Internal tracking Code
TSSOP-8
DFN-8
EC25C256NE1GR
EC25C256NF2GR
YYWWT
C256：Part No
LLL：the last three numbers of wafer lot number
T：Internal tracking Code
C256
LLLT
E-CMOS Corp. (www.ecmos.com.tw)
Page 2 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Functional Block Diagram
Serial Interface Description
Master：The device that provides a clock signal.
Slave：EC25C256.
Transmitter/Receiver：The EC25C256 has both data input (SI) and data output (SO).
MSB：MSB (Most Significant Bit) is the first bit being transmitted or received.
Op-Code：Operational instruction code typically sent to the EC25C256 is the first byte of information
transmitted after is Low. If the Op-Code is a valid instruction as listed in Table 3, then it will be
decoded appropriately. It is prohibited to send an invalid Op-Code.
E-CMOS Corp. (www.ecmos.com.tw)
Page 3 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Pin Configuration
(SOP-8/TSSOP-8)
(DFN-8)
Pin Definition
Pin No.
Pin Name
I/O
Definition
1
2
3
4
5
6
7
8
I
O
I
Chip Select
CS
SO
Serial Data Output
Write Protect Input
Ground
WP
GND
-
SI
I
Serial Data Input
Serial Clock
SCK
I
I
Hold function
HOLD
VCC
-
Supply Voltage
Pin Descriptions
Chip Select (
)
The CS pin is used to enable or disable the device. Upon power-up, CS must follow the supply voltage. When
the device is ready for instruction input, this signal requires a High-to-Low transition. Once CS is stable at Low,
the device is enabled. Then the master and slave can communicate among each other through SCK, SI, and
SO pins. Upon completion of transmission, CS must be driven to High in order to stop the operation or start
the internal write operation. And the device will enter into standby mode, unless an internal write operation is in
progress. During this mode, SO becomes high impedance.
Serial Clock (SCK)
Under the SPI modes (0,0) and (1,1),this clock signal provides synchronization between the master and
EC25C256.Typically,Op-Codes,addresses and data are latched from SI at the rising edge of SCK, while data
from SO are clocked out at the falling edge of SCK.
Serial Data Input (SI)
Data Input pin.
Serial Data Output(SO)
Data output pin.
Write Protect (
)
This active Low input signal is utilized to initiate Hardware Write Protection mode. This mode prevents the
Block Protection bits and the WPEN bit in the Status Register from being modified. To activate the Hardware
Write Protection, WP must be Low simultaneously when WPEN is set to 1.
Hold (
)
This feature is used to suspend the device in the middle of a serial sequence and temporarily ignore further
communication on the bus (SI,SO,SCK).The HOLD signal transitions must occur only when SCK is Low and be
held stable during SCK transitions. Connecting HOLD to High disables this feature. Figure.8 shows Hold timing.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Device Operation
Status Register
The Status Register accessible by the user consists of 8-bits data for write protection control and write status.
It Hardware Write Protection is enabled or WEN is set to 0. If neither is true, it can be modified by a valid
instruction. becomes Read-Only under any of the following conditions:
Table 1: Status Register
Bit
Symbol
Name
Description
When RDY = 0, device is ready for an instruction.
0
Ready
RDY
When RDY = 1, device is busy.
As busy, device only accepts Read Status Register command.
This represents the write protection status of the device.
When WEN = 0, Status Register and entire array cannot be modified, regardless
1
WEN
Write Enable
the setting of WPEN,WP pin or block protection.
Write Enable command (WREN) can be used to set WEN to 1.
Upon power-up stage, WEN is reset to 0.
2
3
BP0
BP1
Block Protect Bit
Block Protect Bit
Despite of the status on WPEN, WP or WEN, BP0 and BP1 configure any
combinations of the four blocks being protected (Table2).
They are non-volatile memory and programmed to 0 by factory.
4
5
6
X
X
X
Don’t Care
Don’t Care
Don’t Care
Values can be either 0 or 1, but are not retained. Mostly always 0, except during
write operation.
This bit can be utilized to enable Hardware Write Protection, together with
WP pin. If enabled, Status Register becomes read-only. However, the memory
array is not protected by this mode. Hardware Write Protection requires the
7
WPEN
Write Protect Enable
setting of WP = 0 and WPEN = 1. Otherwise, it is disabled.
WPEN cannot be altered from 1 to 0 if WP is already set to Low. (Table 4 for
write protection)
Note: During internal write cycles, bits 0 to 7 are temporarily 1's.
Table 2: Block Protection by BP0 and BP1
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
0
0
0
1
1
0
1
0
1
None
1 (1/4)
2 (1/2)
3 (All)
6000h-7FFFh
4000h-7FFFh
0000h-7FFFh
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Op-Code Instructions
The operations of the EC25C256 are controlled by a set of instruction Op-Codes (Table3) that are clocked-in
serially via SI pin. To initiate an instruction, the chip select(CS) must be Low. Subsequently, each Low-to-High
transition of the clock (SCK) will latch a stable level from SI. After the 8-bit Op-Code, it may continue to latch-in
an address and/or data output, data are latched out at the falling edge of SCK. All communications start with
MSB first. Upon the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS
must be brought to High in order to end the transaction and start the operation. The device will enter into
Standby Mode after the operation is completed. data from SI accordingly, or to output data from SO. During
Table3: Instruction Op-Codes[1,2,3]
Name
WREN
Op-Code
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
1000 X011[4]
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Array
Write Data to Array
Address
Data (SI)
Data (SO)
-
-
-
-
-
-
-
-
-
WRDI
RDSR
D7-D
0
-
WRSR
-
D7-D
0
READ
-
A
A
A
15-A
15-A
15-A
0
0
0
D7
-D , ...
0
WRITE
-
D
7
-D
0
, ...
, ...
Read Identification Page
Read the page dedicated to
identification
-
-
-
-
D7
-D
0
1000 X010[4]
1000 X010[5]
1000 X010[5]
Write Identification Page
Read Lock Status
Lock ID
Write the page dedicated to
identification
A
A
A
15-A
15-A
15-A
0
0
0
D
7
-D
-D
-D
0, ...
0, ...
0
, ...
Reads the lock status of the
Identification Page.
D7
Locks the Identification page in
read-only mode.
D7
Notes:
[1] X = Don’t care bit. However, it is recommended to be “0”.
[2]Some address bits may be don’t care (Table 5).
[3] It is strongly recommended that an appropriate format of Op-Code must be entered. Otherwise, it maycause
unexpected phenomenon to be occurred. Nevertheless, it is illegal to input invalid any Op-Code.
[4] Address bit A10 must be 0, all other address bits are Don’t Care.
[5] Address bit A10 must be 1, all other address bits are Don’t Care.
Write Enable
When VCC is initially applied ,the device powers up with both status register and entire array in a write-
disabled state. Upon completion of Write Disable(WRDI),Write Status Register(WRSR) or Write Data to Array
(WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a Write
Enable (WREN) instruction is necessary to set WEN to 1 (Figure.2).
Write Disable
The device can be completely protected from modification by resetting WEN to 0 through the Write Disable
(WRDI) instruction (Figure.3).
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Read Status Register
The Read Status(RDSR) instruction reviews the status of Write Protect Enable, Block Protection setting
(Table 2), Write Enable state and RDY status. RDSR is the only instruction accepted when write
a
cycle is under way. It is recommended that the status of Write Enable and RDY be checked, especially prior
to an attempted modification of data. These 8 bits information can be repeatedly output on SO after the initial
Op-Code (Figure.4)
.
Write Status Register
The Write Status Register(WRSR) instruction allows the user to choose a Block Protection setting and set or
reset the WPENbit. The values of the other data bits incorporated into WRSR can be 0 or 1 and are not stored
in the Status Register. WRSR will be ignored unless both following conditions are true: a) WEN=1, due to a
prior WREN instruction; and b) Hardware Write Protection is not enabled(Table 4). Except for RDY status, the
values in the Status Register remain unchanged until the moment when the write cycle is completed and the
register is updated. Note that WPEN can be changed from 1 to 0 only if WP is already set High. Once
completed, WEN is reset for complete chip write protection (Fig.5).
Read Data
This instruction includes an Op-Code and 16-bit address, then results the selected data to be shifted out from
SO. Following the first data byte, additional sequential data can be output. If the data byte of the last
address is initially output, then address will rollover to the first address in the array, and the output could loop
indefinitely. At any time, a rising CS signal ceases the operation (Figure.6).
Write Data
The WRITE instruction contains an Op-Code, a 16-bit address and the first data byte. Additional data bytes
may be supplied sequentially after the first byte. Each WRITE instruction can affect up to 64 bytes of data in a
page. Each page has a starting address XXXXXXXX XX000000 and an ending address XXXXXXXX XX111111.
After the last byte of data in a page is input, the address rolls over to the beginning of the same page. If more
than 64 bytes of data is input during a single instruction, then only the last 64 bytes will be retained, but the
initial data will be overwritten. The contents of the array defined by Block Protection cannot be modified as long
as that block configuration is selected. The contents of the array outside the Block Protection can only be
modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction is initiated
prior to WRITE. Once Write operation is completed, WEN is reset for complete chip write protection (Figure.7)
Besides, Hardware Write Protection has no affect on the memory array.
Read Identification Page
The Identification Page (64 bytes) is an additional page which can be written and(later) permanently locked in
Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 3).
The Chip Select signal ( CS ) is first driven low, the bits of the instruction byte and address bytes are then
shifted in, on Serial Data input (SI). Address bit A10 must be 0, address bits [A15:A11] and [A9:A6] are Don't
Care, and the data byte pointed to by [A5:A0] is shifted out on Serial Data output (SO). If Chip Select ( CS )
continues to be driven low, the internal address register is automatically incremented, and the byte of data at
the new address is shifted out. The number of bytes to read in the ID page must not exceed the page
boundary(e.g. when reading the ID page from location 24d, the number of bytes should be less than or
equal to 40d, as the ID page boundary is 64 bytes). The read cycle is terminated by driving Chip Select ( CS )
high. The rising edge of the Chip Select ( CS ) signal can occur at any time during the cycle. The first byte
addressed can be any byte within any page (Figure.8).The instruction is not accepted, and is not executed, if a
write cycle is currently in progress.
Write Identification Page
The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked
in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table3), the
Chip Select signal (CS) is first driven low. The bits of the instruction byte, address byte, and at least one data
byte are then shifted in on Serial Data input (SI). Address bit A10 must be 0, address bits [A15:A11] and
[A9:A6] are Don't Care, the [A5:A0] address bits define the byte address inside the identification page. The
instruction sequence is shown in Figure 9.
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Read Lock Status
The Read Lock Status instruction (see Table 3) allows to check if the Identification Page is locked (or not) in
read-only mode. The Read Lock Status sequence is defined with the Chip Select(CS) first driven low. The bits
of the instruction byte and address bytes are then shifted in on Serial Data input (SI). Address bit A10 must be
1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial
Data output (SO). It is at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select ( CS )
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip
Select ( CS ) high (Figure10).
Lock ID
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction
can be accepted, a Write Enable(WREN) instruction must have been executed. The Lock ID instruction is
issued by driving Chip Select (CS) low, sending the instruction code, the address and a data byte on Serial
Data input (SI), and driving Chip Select(CS) high. In the address sent, A10 must be equal to 1, all other
address bits are Don't Care. The data byte sent must be equal to the binary value xxxxxx1x, where x = Don't
Care. Chip Select ( CS ) must be driven high after the rising edge of Serial Clock(SCK) that latches in the
eighth bit of the data byte, and before the next rising edge of Serial Clock(SCK). Otherwise, the Lock ID
instruction is not executed. Driving Chip Select(CS) high at a byte boundary of the input data triggers the self-
timed write cycle whose duration is TWR. The instruction sequence is shown in Figure 11.
The instruction is not accepted, and so not executed, under the following conditions:
— If the Write Enable Latch (WEL) bit has not been set to 1(by previously executing a Write Enable
instruction).
— If Status register bits (BP1,BP0) = (1,1).
— If a write cycle is already in progress.
— If the device has not been deselected, by Chip Select(CS) being driven high, at a byte boundary (after the
eighth bit, b0, of the last data byte that was latched in).
— If the Identification page is locked by the Lock Status bit.
Table 4: Write Protection
Hardware Write
Protection
Status Register
WPEN
WEN
Inside Block
Outside Block
WP
(WPEN, BP1, BP0)
0
0
1
1
X
X
X
X
0
0
1
1
Not Enabled
Not Enabled
Enabled
0
1
0
1
0
1
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Unprotected
Read-only
Read-only
Unprotected
Read-only
Read-only
Read-only
Unprotected
Enabled
Unprotected
Read-only
Not Enabled
Not Enabled
Unprotected
Note: X = Don't care bit.
Table 5: Address Key
Name
EC25C256
A
N
A
14-A
0
Don't Care Bits
A
15
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Diagrams
Figure 1. Synchronous Data Timing
Figure 2. WREN Timing
Figure 3. WRDI Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Figure 4. RDSR Timing
Figure 5. WRSR Timing
Figure 6. READ Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 10 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Figure 7. WRITE Timing
Figure 8. Read Identification Page
Figure 9. Write Identification Page
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Figure 10. Read Lock Status
Figure 11. Lock ID
Figure 12. HOLD Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Electrical Characteristics
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
-0.5 to + 6.5
–0.5 to VCC + 0.5
–55 to +125
–65 to +150
5
V
VS
V
VP
°C
°C
mA
TBIAS
TSTG
IOUT
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition outside those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: ECMOS offers Industrial grade for Commercial applications (0C to +70C).
Capacitance
Symbol
Parameter[1,2]
Conditions
VIN = 0V
Max.
6
Unit
pF
CIN
Input Capacitance
Input / Output
Capacitance
CI/O
VI/O = 0V
8
pF
Note: (1) Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
(2) Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
E-CMOS Corp. (www.ecmos.com.tw)
Page 13 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
VCC
VIH
Parameter
Supply Voltage
VCC
Test Conditions
Min.
1.7
Max.
Unit
5.5
V
V
Input High Voltage
0.7* VCC
-0.3
-2
VCC+1
Input Low Voltage
V
VIL
0.3* VCC
Input Leakage Current
Output Leakage Current
2
2
μA
μA
V
ILI
VIN = 0V To VCC
-2
ILO
VOUT = 0V To VCC, CS= VCC
IOH = -0.1mA
1.7
2.5
5
—
—
—
0.2
0.4
0.4
2
0.8*VCC
0.8*VCC
0.8*VCC
—
Output High Voltage
Output Low Voltage
Write Operating Current
Read Operating Current
Standby Current
VOH
VOL
ICC1
ICC2
ISB
V
IOH = -0.4mA
V
IOH = -2 mA
1.7
2.5
5
V
IOL = 0.15 mA
—
V
IOL = 1.5 mA
—
V
IOL = 2 mA
1.7
2.5
5
Write at 5 MHz, SO=Open
Write at 10 MHz, SO=Open
Write at 20 MHz, SO=Open
Read at 5 MHz, SO=Open
Read at 10 MHz, SO=Open
Read at 20 MHz, SO=Open
—
mA
mA
mA
mA
mA
mA
μA
μA
μA
—
2
—
3
1.7
2.5
5
—
1
—
3
—
5
1.7
2.5
5
—
1
VIN= VCC or GND, CS= VCC
VIN= VCC or GND,CS= VCC
VIN= VCC or GND,CS= VCC
—
1
—
2
E-CMOS Corp. (www.ecmos.com.tw)
Page 14 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
1.7V
Min.
0
V
CC<2.5V
2.5V
Min.
0
V
CC<4.5V
4.5V
Min.
0
VCC
5.5V
Max.
20
1
[1]
Parameter
Symbol
Unit
Max.
5
Max.
10
1
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
MHz
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
F
SCK
RI
FI
WH
WL
CS
—
1
—
—
—
20
20
25
25
25
5
T
—
1
—
1
1
T
80
80
100
100
100
20
20
20
20
0
—
—
—
—
—
—
—
—
—
80
—
80
80
80
5
40
40
50
50
50
10
10
10
10
0
—
—
—
—
—
—
—
—
—
40
—
40
40
40
5
—
T
—
T
—
T
—
T
CSS
CSH
CS Setup Time
—
T
CS Hold Time
Data In Setup Time
Data In Hold Time
—
TSU
5
—
TH
5
—
THD
HOLDSetup Time
5
—
TCD
HOLDHold Time
Output Valid
[2]
0
20
—
TV
Output Hold Time
0
0
0
T
HO
0
0
0
25
40
40
5
T
LZ
HOLDto Output Low Z
—
—
—
—
—
T
HZ
HOLDto Output High Z
Output Disable Time
—
—
T
T
DIS
WC
Write Cycle Time
—
—
Notes: [1] The parameters are characterized but not 100% tested.
[2] CL = 30pF (typical)
E-CMOS Corp. (www.ecmos.com.tw)
Page 15 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
Package Information
SOP -8
DIMENSIONS IN MILLIMETERS
DIMENSIONS IN INCHES
SYMBOLS
MIN
1.35
0.10
0.33
4.80
5.80
3.80
NOM
MAX
1.75
0.25
0.51
5.00
6.20
4.00
MIN
NOM
MAX
0.069
0.010
0.020
0.197
0.244
0.157
A
A1
b
--
--
0.053
0.004
0.013
0.189
0.228
0.150
--
--
--
--
--
--
D
E
E1
e
--
--
--
--
1.27 BSC.
--
0.050 BSC.
L
0.38
1.27
8°
0.015
0
0.050
8°
L1
ZD
Θ
0.25 BSC.
0.545 REF.
--
0.010 BSC.
0.021 REF.
--
0
Note:
1. Controlling Dimension：MM
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
E-CMOS Corp. (www.ecmos.com.tw)
Page 16 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
TSSOP -8
DIMENSIONS IN MILLIMETERS
DIMENSIONS IN INCHES
SYMBOLS
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
A2
b
c
D
E
E1
e
L
Θ
--
--
--
1.00
--
1.20
0.15
1.05
0.30
0.20
3.10
4.50
--
--
0.047
0.006
0.041
0.012
0.008
0.122
0.177
0.05
0.80
0.19
0.09
2.90
4.30
0.002
0.031
0.007
0.004
0.114
0.169
--
0.039
--
--
--
3.00
4.40
6.4 BSC
0.65 BSC
0.60
--
0.118
0.173
0.252 BSC
0.026 BSC
0.024
--
0.45
0
0.75
8°
0.018
0
0.030
8°
Note:
1. Controlling Dimension：MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar
E-CMOS Corp. (www.ecmos.com.tw)
Page 17 of 18
4J09N-Rev.F001
EC25C256
256Kbits SPI Serial EEPROM
DFN-8
DIMENSIONS IN MILLIMETERS
DIMENSIONS IN INCHES
SYMBOLS
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
b
0.50
0.00
0.18
0.55
--
0.25
0.60
0.05
0.30
0.020
0.000
0.007
0.022
--
0.010
0.024
0.002
0.012
A2
D
D2
E
E2
e
K
0.152 REF
2.00 BSC
1.40
3.00 BSC
1.30
0.006 REF
0.079 BSC
0.055
0.118 BSC
0.051
1.25
1.15
1.50
1.40
0.049
0.045
0.059
0.055
0.50 BSC.
--
0.020 BSC.
--
0.40
0.20
--
0.40
0.016
0.008
--
0.016
L
0.30
0.012
Note:
1. Controlling Dimension：MM
2. Drawing is not to scale
E-CMOS Corp. (www.ecmos.com.tw)
Page 18 of 18
4J09N-Rev.F001
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