EH3525ETTS-1.8432M TR [ECLIPTEK]
CMOS, Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD);
| 型号： | EH3525ETTS-1.8432M TR |
| 厂家： | 
Ecliptek |
| 描述： | CMOS, Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) 石英晶振 |
| 文件： | 总6页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoHS
Pb
EH3525ETTS-1.8432M
EH35 25 ET
TS -1.8432M
Series
Nominal Frequency
1.8432MHz
RoHS Compliant (Pb-free) 5.0V 4 Pad 3.2mm x 5mm
Ceramic SMD HCMOS/TTL High Frequency Oscillator
Pin 1 Connection
Tri-State (Disabled Output: High Impedance)
Frequency Tolerance/Stability
±25ppm Maximum
Duty Cycle
50 ±10(%)
Operating Temperature Range
-40°C to +85°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
1.8432MHz
Frequency Tolerance/Stability
±25ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25°C,
Shock, and Vibration)
Aging at 25°C
±5ppm/year Maximum
Operating Temperature Range
Supply Voltage
-40°C to +85°C
5.0Vdc ±10%
Input Current
50mA Maximum (No Load)
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load (IOH = -16mA)
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load (IOL = +16mA)
6nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load or at 20% to 80% of waveform with
HCMOS Load)
Duty Cycle
50 ±10(%) (Measured at 1.4Vdc with TTL Load or at 50% of waveform with HCMOS Load)
10TTL Load or 50pF HCMOS Load Maximum
CMOS
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State (Disabled Output: High Impedance)
Tri-State Input Voltage (Vih and Vil)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to
enable output.
Absolute Clock Jitter
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
10mSec Maximum
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
Gross Leak Test
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
Temperature Cycling
Vibration
MIL-STD-883, MEthod 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 1 of 6
EH3525ETTS-1.8432M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN CONNECTION
1
2
3
4
Tri-State
Ground/Case Ground
Output
1.20 ±0.20 (x4)
3.20
±0.20
1.00 ±0.20 (x4)
Supply Voltage
LINE MARKING
4
3
1
2
1
E1.8432
5.00
±0.20
2.54
±0.15
E=Ecliptek Designator
1.20
±0.20
(x4)
2.20
±0.15
1.3
MAX
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.2 (X4)
1.4 (X4)
Solder Land
(X4)
1.14
1.0
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 2 of 6
EH3525ETTS-1.8432M
OUTPUT WAVEFORM & TIMING DIAGRAM
VIH
VIL
VOH
80% or 2.0VDC
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
50% or 1.4VDC
20% or 0.8VDC
VOL
tPLZ
tPZL
Fall
Time
Rise
Time
TW
T
Duty Cycle (%) = TW/T x 100
Test Circuit for TTL Output
RL Value
(Ohms)
Output Load
Drive Capability
CL Value
(pF)
390
780
15
15
6
10TTL
5TTL
Frequency
Counter
1100
2000
2200
2TTL
Oscilloscope
15
3
10LSTTL
1TTL
Table 1: RL Resistance Value and CL Capacitance
Value Vs. Output Load Drive Capability
Probe
Supply
Voltage
(Note 2)
RL
(Note 4)
(VDD
)
Output
_
+
Current
Meter
+
+
+
Power
Supply
0.01µF
(Note 1)
Power
Supply
_
Voltage
Meter
0.1µF
(Note 1)
CL
(Note 3)
Ground
_
_
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and VDD pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance.
Note 4: Resistance value RL is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 3 of 6
EH3525ETTS-1.8432M
Test Circuit for CMOS Output
Frequency
Counter
Oscilloscope
Probe
(Note 2)
Supply
Voltage
(VDD
)
Output
_
+
Current
Meter
+
+
Power
Supply
0.01µF
(Note 1)
Voltage
Meter
0.1µF
(Note 1)
CL
(Note 3)
Ground
_
_
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and VDD pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 4 of 6
EH3525ETTS-1.8432M
Recommended Solder Reflow Methods
Critical Zone
TL to TP
TP
Ramp-up
Ramp-down
TL
TS Max
TS Min
tL
tP
tSPreheat
t 25°C to Peak
Time (t)
High Temperature Infrared/Convection
TS MAX to TL (Ramp-up Rate)
3°C/second Maximum
Preheat
- Temperature Minimum (TS MIN)
- Temperature Typical (TS TYP)
- Temperature Maximum (TS MAX)
- Time (tS MIN)
150°C
175°C
200°C
60 - 180 Seconds
Ramp-up Rate (TL to TP)
3°C/second Maximum
Time Maintained Above:
- Temperature (TL)
- Time (tL)
217°C
60 - 150 Seconds
Peak Temperature (TP)
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
Target Peak Temperature (TP Target)
Time within 5°C of actual peak (tp)
Ramp-down Rate
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 5 of 6
EH3525ETTS-1.8432M
Recommended Solder Reflow Methods
Critical Zone
TL to TP
TP
Ramp-up
Ramp-down
TL
TS Max
TS Min
tL
tP
tSPreheat
t 25°C to Peak
Time (t)
Low Temperature Infrared/Convection 240°C
TS MAX to TL (Ramp-up Rate)
5°C/second Maximum
Preheat
- Temperature Minimum (TS MIN)
- Temperature Typical (TS TYP)
- Temperature Maximum (TS MAX)
- Time (tS MIN)
N/A
150°C
N/A
60 - 120 Seconds
Ramp-up Rate (TL to TP)
5°C/second Maximum
Time Maintained Above:
- Temperature (TL)
- Time (tL)
150°C
200 Seconds Maximum
Peak Temperature (TP)
240°C Maximum
Target Peak Temperature (TP Target)
Time within 5°C of actual peak (tp)
Ramp-down Rate
240°C Maximum 1 Time / 230°C Maximum 2 Times
10 seconds Maximum 2 Times / 80 seconds Maximum 1 Time
5°C/second Maximum
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
N/A
Level 1
Low Temperature Manual Soldering
185°C Maximum for 10 seconds Maximum, 2 times Maximum.
High Temperature Manual Soldering
260°C Maximum for 5 seconds Maximum, 2 times Maximum.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/17/2010 | Page 6 of 6
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