EMK43H2J-50.000M TR [ECLIPTEK]
CMOS, MEMS Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 2.0mm x 2.5mm Plastic Surface Mount (SMD) MEMS Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 2.0mm x 2.5mm Plastic Surface Mount (SMD);
| 型号： | EMK43H2J-50.000M TR |
| 厂家： | 
Ecliptek |
| 描述： | CMOS, MEMS Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 2.0mm x 2.5mm Plastic Surface Mount (SMD) MEMS Clock Oscillators LVCMOS (CMOS) 3.3Vdc 4 Pad 2.0mm x 2.5mm Plastic Surface Mount (SMD) |
| 文件： | 总5页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoHS
Pb
EMK43H2J-50.000M
EMK43 H 2 J -50.000M
Series
Nominal Frequency
RoHS Compliant (Pb-free) 4 Pad 2mm x 2.5mm SMD
3.3Vdc LVCMOS MEMS Oscillator
50.000MHz
Output Control Function
Power Down (Disabled Output: Logic Low)
Frequency Tolerance/Stability
±50ppm Maximum over -40°C to +85°C
Duty Cycle
50 ±5(%)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
50.000MHz
Frequency Tolerance/Stability
±50ppm Maximum over -40°C to +85°C (Inclusive of all conditions: Calibration Tolerance at 25°C,
Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change,
First Year Aging at 25°C, 260°C Reflow, Shock, and Vibration)
Aging at 25°C
±1ppm Maximum First Year
Operating Temperature Range
Supply Voltage
-40°C to +85°C
3.3Vdc ±10%
Input Current
25mA Maximum
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
90% of Vdd Minimum (IOH=-8mA)
10% of Vdd Maximum (IOL=+8mA)
2nSec Maximum (Measured from 20% to 80% of waveform)
50 ±5(%) (Measured at 50% of waveform)
15pF Maximum
Duty Cycle
Load Drive Capability
Output Logic Type
CMOS
Output Control Function
Output Control Input Voltage
Standby Current
Power Down (Disabled Output: Logic Low)
+0.7Vdd Minimum or No Connect to Enable Output, +0.3Vdd Maximum to Disable Output
50µA Maximum (Disabled Output: Logic Low)
250pSec Maximum, 100pSec Typical
50mSec Maximum
Peak to Peak Jitter (tPK)
Start Up Time
Storage Temperature Range
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
MIL-STD-883, Method 3015, Class 2, HBM 2000V
Flammability
UL94-V0
Mechanical Shock
Moisture Resistance
Moisture Sensitivity Level
Resistance to Soldering Heat
Resistance to Solvents
Solderability
MIL-STD-883, Method 2002, Condition G, 30,000G
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003 (Pads on Bottom of Package Only)
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 1011, Condition B
MIL-STD-883, Method 2007, Condition A, 20G
Temperature Cycling
Thermal Shock
Vibration
www.ecliptek.com | Specification Subject to Change Without Notice | Rev J 2/17/2010 | Page 1 of 5
EMK43H2J-50.000M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN CONNECTION
1
2
3
4
Power Down
Ground
0.85
±0.15
2.00
±0.15
0.65 ±0.10 (x4)
0.08
Output
MAX
Supply Voltage
2
R0.33
±0.10
3
4
LINE MARKING
2.50
±0.15
1.65
±0.10
1
XXXX
0.65
XXXX=Ecliptek
Manufacturing Lot Code
±0.10
(x4)
1
R0.32
±0.10
0.70
±0.15
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.10 (X4)
1.10 (X4)
Solder Land
(X4)
0.50
0.30
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev J 2/17/2010 | Page 2 of 5
EMK43H2J-50.000M
OUTPUT WAVEFORM & TIMING DIAGRAM
VIH
VIL
VOH
80% of Waveform
OUTPUT DISABLE
(LOGIC LOW)
50% of Waveform
20% of Waveform
VOL
tPLZ
tPZL
Fall
Time
Rise
Time
TW
T
Duty Cycle (%) = TW/T x 100
Test Circuit for CMOS Output
Frequency
Counter
Oscilloscope
Probe
(Note 2)
Supply
Voltage
(VDD
)
Output
_
+
Current
Meter
+
+
Power
Supply
0.01µF
(Note 1)
Voltage
Meter
0.1µF
(Note 1)
CL
(Note 3)
Ground
_
_
Tri-State or
Power Down
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and VDD pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev J 2/17/2010 | Page 3 of 5
EMK43H2J-50.000M
Recommended Solder Reflow Methods
Critical Zone
TL to TP
TP
Ramp-up
Ramp-down
TL
TS Max
TS Min
tL
tP
tSPreheat
t 25°C to Peak
Time (t)
High Temperature Infrared/Convection
TS MAX to TL (Ramp-up Rate)
3°C/second Maximum
Preheat
- Temperature Minimum (TS MIN)
- Temperature Typical (TS TYP)
- Temperature Maximum (TS MAX)
- Time (tS MIN)
150°C
175°C
200°C
60 - 180 Seconds
Ramp-up Rate (TL to TP)
3°C/second Maximum
Time Maintained Above:
- Temperature (TL)
- Time (tL)
217°C
60 - 150 Seconds
Peak Temperature (TP)
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
Target Peak Temperature (TP Target)
Time within 5°C of actual peak (tp)
Ramp-down Rate
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
www.ecliptek.com | Specification Subject to Change Without Notice | Rev J 2/17/2010 | Page 4 of 5
EMK43H2J-50.000M
Recommended Solder Reflow Methods
Critical Zone
TL to TP
TP
Ramp-up
Ramp-down
TL
TS Max
TS Min
tL
tP
tSPreheat
t 25°C to Peak
Time (t)
Low Temperature Infrared/Convection 240°C
TS MAX to TL (Ramp-up Rate)
5°C/second Maximum
Preheat
- Temperature Minimum (TS MIN)
- Temperature Typical (TS TYP)
- Temperature Maximum (TS MAX)
- Time (tS MIN)
N/A
150°C
N/A
60 - 120 Seconds
Ramp-up Rate (TL to TP)
5°C/second Maximum
Time Maintained Above:
- Temperature (TL)
- Time (tL)
150°C
200 Seconds Maximum
Peak Temperature (TP)
240°C Maximum
Target Peak Temperature (TP Target)
Time within 5°C of actual peak (tp)
Ramp-down Rate
240°C Maximum 1 Time / 230°C Maximum 2 Times
10 seconds Maximum 2 Times / 80 seconds Maximum 1 Time
5°C/second Maximum
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
N/A
Level 1
Low Temperature Manual Soldering
185°C Maximum for 10 seconds Maximum, 2 times Maximum.
High Temperature Manual Soldering
260°C Maximum for 5 seconds Maximum, 2 times Maximum.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev J 2/17/2010 | Page 5 of 5
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