EL7556AC [ELANTEC]
Programmable CPU Power Supply Unit; 可编程CPU供电单元
| 型号： | EL7556AC |
| 厂家： | 
ELANTEC SEMICONDUCTOR |
| 描述： | Programmable CPU Power Supply Unit |
| 文件： | 总13页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7556AC
Programmable CPU Power Supply Unit
Features
General Description
• EL7556C Pin Compatible
• Improved Temperature and
Voltage Ranges
• 6A Continuous Load Current
• Precision Internal 1% Reference
• 1.0V to 3.8V Output Voltage
• Internal Power MOSFETs
• >90% Efficiency
The EL7556AC is an adjustable synchronous DC:DC switching regu-
lator optimized for a 5V input and 1.0-3.8V output. By combining
integrated NMOS power FETS with a fused-lead package the
EL7556AC can supply up to 6A continuous output current without the
use of external power devices or discrete heat sinks, thereby minimiz-
ing design effort and overall system cost.
On chip resistorless current sensing is used to achieve stable, highly
efficient, current-mode control. The EL7556AC also incorporates the
VCC2DET function to directly interface with the Intel P54 and P55
microprocessors. Depending on the state of VCC2DET the output
voltage is internally preset to 3.50V or a user adjustable voltage using
two external resistors. In both internal and external feedback modes
the active-high PWRGD output indicates when the regulator output is
within ±10% of the programmed voltage. An on-board sensor moni-
tors die temperature (OT) for over-temperature conditions and can be
connected directly to OUTEN to provide automatic thermal shutdown.
Adjustable oscillator frequency and slope compensation allow added
flexibility in overall system design.
• Synchronous Switching
• Adjustable Slope Compensation
• Over Temperature Indicator
• Pulse by Pulse Current Limiting
• Operates up to 1MHz
• 1.5% Typical Output Accuracy
• Adjustable Oscillator w/Sync
• Remote Enable/Disable
• Intel P54 and P55 Compatible
• VCC2DET Interface
• Internal Soft Start
Connection Diagram
Applications
• PC Motherboards
R4
R3
• Local high power CPU supplies
• 5V to 1.0V DC-DC Conversion
• Portable Electronics/Instruments
• P54 and P55 Regulators
V
IN
100Ω
150Ω
D3
D2
1
2
3
4
5
6
7
8
9
FB1
CREF
FB2 28
CP 27
C4
0.1µF
C7
C 5
D4
1µF
R1
150pF
CSLOPE C2V 26
C11
• GTL+ Bus Power Supply
C8 220pF
68Ω
COSC
VDD
VIN
VSS 25
VHI 24
LX 23
D1
R6
R5
0.22µF
5Ω
C 6 68Ω
Ordering Information
0.1µF
VSSP
VIN
LX 22
Part No
Temp. Range
Package
Outline #
L1
2.5µH
C9
C12
LX 21
EL7556ACM -40°C to +85°C 28-Lead SOIC
MDP0027
V
OUT
V
IN
C10
1mF
660µF
0.1µF
VSSP
LX 20
C3
10 VSSP
11 VSSP
12 VSSP
VSSP 19
VSSP 18
TEST 17
16
1µF
Connect to VSSP for
external feedback
VCC2DET
13
PWRGD
14 OUTEN
OT 15
EL7556AC
C3, C4, C5, C6, C7 C8 - ceramic
C5, C11 - ceramic or tantalum
C9 - Sprague 594D337X10010R2T 2X330µF
C10 - Sprague 594D337X10010R2T 3X330µF
L1 - Pulse Engineering, PE-53681
D1-D4: BAT54S fast diode
Manufactured under U.S. Patents No. 5,723,974 and No. 5,793,126
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2000 Elantec, Inc.
EL7556AC
Programmable CPU Power Supply Unit
Absolute Maximum Ratings (T = 25 °C)
A
Storage Temperature Range
-65°C to +150°C
Output Pins
-0.3V below GND, +0.3V above VDD
Supply (VIN
Ambient Operating Temperature
)
6.0V
Operating Junction Temperature
Peak Output Current
135°C
-40°C to +85°C
9A
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified
temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VDD = VIN = 5V, COSC = 1nF, CSLOPE=470pF, TA=25°C unless otherwise specified.
Parameter
General
IDD
Description
Conditions
Min
Typ
Max
Units
VDD Supply Current
OUTEN=4V, FOSC=120kHz
OUTEN=0
11
0.1
25
mA
mA
mA
V
IDDOFF
IVIN
VDD Standby Current
VIN No Load Current
Output Initial Accuracy
Output Initial Accuracy
OUTEN=0
3
5
VOUT1
VOUT2
VCC2DET=4V, IL=3A(See Fig. 1)
3.450
2.450
3.500
2.500
3.550
2.550
VCC2DET=0V, IL=3A R3=150Ω, R4=100Ω
V
(See Fig. 1)
VOUTLINE
VOUTLOAD
Output line Regulation
Output Load Regulation
VDD=5V, ±10%
-1
-1
1
1
%
%
0A<ILOAD<6A, Relative to IL=3A. Continu-
ous Mode of Operation (Fig.1)
RSHORT
Short Circuit Load Resistance
IL=6A Prior to Continuous Application of
RSHORT. OUTEN Connected to OT.
100
mΩ
II MAX
VOUTTC
TOT
Current Limit
9
A
%
Output Tempco
-40°C<Ta<85°C
±1
Over Temperature Threshold
Over Temperature Hysteresis
135
40
°C
°C
%
THYS
VPWRGD
Power Good Threshold Relative to Programmed VCC2SEL=4V, VOUT=3.50V
Output Voltage
±6
±10
±14
VDDOFF
VDDON
VHYS
Minimum VDD for Shutdown
Maximum VDD for Startup
3.15
V
V
4.15
Input Hysteresis
Soft start slope
VHYS=VDDON-VDDOFF
0.5
7
V
MSS
V/msec
%
D
Maximum duty cycle
96
MAX
Controller - Inputs
IPUP
VCC2DET, OUTEN Pull Up Current
VCC2DET, OUTEN=0
OT=0V
10
23
14
28.5
2
18
34
µA
µA
µA
kΩ
V
ICSLOPE
IFB1
Cslope Charging Current
FB1 Input Pull Up Current
Over Temperature Pull Up Resistance
VCC2DET, OUTEN Input High
VCC2DET, OUTEN Input Low
Powergood Drive High
ROT
30
4
40
50
.8
VIH
VIL
V
VOH PWGD
VOL PWGD
ILoad=1mA
ILoad=-1mA
3.5
V
Powergood Drive Low
1.0
V
Controller - Reference
VREF
Reference Accuracy
IREF=0
1.247
0.5
1.260
50
1.273
0.5
V
VREFTC
VREFLOAD
Reference Voltage Tempco
Reference Load Regulation
ppm/ºC
%/ºC
0<ILOAD<100µA
2
EL7556AC
Programmable CPU Power Supply Unit
Electrical Characteristics
VDD = VIN = 5V, COSC = 1nF, CSLOPE=470pF, TA=25°C unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
Units
Controller - Doubler
VC2V
Voltage Doubler Output
Vdd=5V, ILOAD=10mA
7.1
7.7
8.3
V
Controller - Oscillator
FRAMP
IOSC CHG
IOSC DIS
FOSC
Oscillator Ramp Amplitude
Oscillator Charge Current
1.2
150
5
V
µA
mA
kHz
ns
.2V<VOSC<1.4V
.2V<VOSC<1.4V
Oscillator Discharge Current
Oscillator initial accuracy
100
18
120
50
140
Minimum oscillator sync width
t
sync
Power - FET
ILEAK
LX Output Leakage to VSS
Composite FET Resistance
RDSON Tempco
LX=0V
100
30
µA
mΩ
mΩ/ºC
ns
RDSON
RDSONTC
0.1
10
t
FET break before make delay
brm
High side FET minimum on time (LEB)
t
140
ns
LEB
3
EL7556AC
Programmable CPU Power Supply Unit
Typical Performance Curves
Efficiency vs. I (V =3.5V)
LOAD OUT
Efficiency vs. I (V =5.0V)
LOAD DD
V
=V =5.0V (±10%)
DD IN
96%
94%
92%
90%
88%
86%
84%
82%
80%
100%
95%
90%
85%
80%
75%
70%
T =25°C
A
V
=4.5V
DD
V
=3.5V
OUT
V
OUT
=2.5V
V
DD
=5.0V
V
DD
=5.5V
V
OUT
=1.0V
0.5 1.5 2.5 3.5 4.5 5.5 6.5
0.5 1.5 2.5 3.5 4.5 5.5 6.0
I
(A)
I
(A)
OUT
OUT
Line Regulation (C =100pF)
SLOPE
Load Regulation (C =100pF)
SLOPE
3.54
3.53
3.52
3.51
3.50
3.49
3.48
3.47
3.46
3.54
3.53
3.52
3.51
3.50
3.49
3.48
3.47
3.46
TA=25°C
TA=25°C
V =5.5V
IN
I
=0.5A
OUT
V =5.0V
IN
I
=3A
OUT
V =4.5V
IN
I
=6A
OUT
4.5V
5.0V
(V)
5.5V
0.5
3.0
(A)
6.0
I
V
OUT
IN
Load Regulation vs. C (V =5.0V)
SLOPE IN
Line Regulation vs. C (I =3A)
SLOPE OUT
I
=3A, +3A, -2.5A
V
=V =5.0V ±10%
OUT
DD IN
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
0.8%
0.7%
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
TA=25°C
TA=25°C
V
=3.5V
OUT
V
=3.5V
OUT
V
OUT
=2.5V
V
OUT
=2.5V
V
OUT
=1.0V
V
OUT
=1.0V
50
75
100
125
150
175
50
75
100
125
150
175
C
SLOPE
(pF)
C
SLOPE
(pF)
4
EL7556AC
Programmable CPU Power Supply Unit
Line Regulation vs. C
Load Regulation vs. C
SLOPE
SLOPE
V =V =5.0V ±10%
IN DD
I
=3A, +3A, -2.5A
OUT
0.8%
0.7%
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
0.8%
0.7%
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
0.0%
TA=25°C
TA=25°C
V =4.5V
IN
I
=6A
OUT
V =5.0V
IN
I
=.5A
V =5.5V
IN
OUT
50
75
100
125
150
175
50
75
100
125
150
175
C
SLOPE
(pF)
C
SLOPE
(pF)
V Variation vs. Programmed Output
OUT
V
OUT
vs. C
SLOPE
(V =5.0V, I =.5A)
IN LOAD
Voltage (V =(1+R3/R4))
IDEAL
1.5%
1.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
TA=25°C
TA=25°C
C
=100pF
C =220pF
OSC
SLOPE
0.5%
V =1.0V
OUT
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
V
=2.5V
=3.5V
OUT
Loop Gain Induced Error
V
OUT
50
75
100
125
150
175
1.0 1.5 2.0 2.5 3.0 3.5 4.0
(V)
V
IDEAL
C
SLOPE
(pF)
F
OSC
vs. C
OSC
F
OSC
vs. Temp
10000
1000
100
10
520
510
500
490
480
470
460
450
TA=25°C
V =4.5V
DD
V
=5.0V
DD
V
=5.5V
DD
1
0
10
100
1000
(pF)
10000
20 40 60 80 100 120 140
C
Temp (°C)
SLOPE
5
EL7556AC
Programmable CPU Power Supply Unit
I(V ) vs. F
IN
OSC
I(V ) + I(V ) vs. F
OSC
DD
IN
16
14
12
10
8
60
50
40
30
20
10
0
TA=25°C
OUTEN=V
TA=25°C
OUTEN=V
V =5.5V
DD
DD
V
=5.5V
=5.0V
DD
DD
V
DD
=5.0V
V
DD
V =4.5V
DD
6
V
DD
=4.5V
4
Discontinuous Mode
2
Discontinuous Mode
Continuous Mode
Continuous Mode
0
200
400
600
800
1000
200
400
600
800
1000
F
(kHz)
OSC
F
(kHz)
OSC
I
DD
+ IV vs. F
IN
OSC
I(V ) vs. F
DD
OSC
2.0
1.5
1.0
50
45
40
35
30
25
20
15
10
5
TA=25°C
V
=5.5V
DD
V
=5.5V
OUTEN=V
DD
DD
V
=5.0V
DD
V
DD
=5.0V
V
DD
=4.5V
V
DD
=4.5V
0
10
100
(kHz)
1000
200
400
600
800
1000
F
OSC
F
OSC
(kHz)
Minimum Output Voltage vs. F
OSC
Power On Reset
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
40
Tj=120°C
V =5.5V
DD
TA=25°C
OUTEN=V
DD
30
20
10
0
F =500k
OSC
V
=5.0V
DD
V
=4.5V
DD
200
400
600
800
1000
2.5
3.0
3.5
4.0
4.5
5.0
F
OSC
(kHz)
VDD(V)
6
EL7556AC
Programmable CPU Power Supply Unit
Maximum I
vs. Temp
LOAD
Theta JM vs. Cu Area
7556 Demo Board (31°C/W)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
41
39
37
35
33
31
29
27
25
100 LFM
Board with no
Components
Still Air
OUTEN connected to OT
Board with Inductor
0.00 1.00 2.00 3.00 4.00 5.00 6.00
30
40
50
60
70
2
Bare Cu Area (in )
T
A
(°C)
R
DSON
vs. Temp
38
36
34
32
30
28
26
24
22
20
25
50
75
100
125
0
Temp (°C)
7
EL7556AC
Programmable CPU Power Supply Unit
Pin Description
(I=Input O=Output S=Supply)
Pin Number
Pin Name
Pin Type
Function
1
FB1
I
Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected to exter-
nal resistor divider between VOUT and GND. A 2µA pull-up current forces VOUT to VSS in the event that
FB1is floating and VCC2DET is inadvertently connected to GND.
2
3
CREF
I
I
Bandgap reference bypass capacitor. Typically 0.1µF to VSS.
CSLOPE
Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is normally
1:1.5.
4
5
COSC
VDD
I
Oscillator timing capacitor. FOSC(Hz) can be approximated by: FOSC(Hz)= 0.0001/COSC. COSC in Farads.
S
S
S
S
S
S
S
S
I
Power Supply for PWM control circuitry. Normally the same potential as VIN.
6
VIN
Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET.
7
VSSP
VIN
Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS FET.
8
Same as pin 6.
Same as pin 7.
Same as pin 7.
Same as pin 7.
Same as pin 7.
9
VSSP
VSSP
VSSP
VSSP
VCC2DET
10
11
12
13
VCC2DET interface logic input. When driven to logic 1 VOUT=3.500V. When driven to logic 0 the PWM uses
FB1 to determine VOUT: VOUT=1.0V*(1+R3/R4).
14
15
OUTEN
OT
I
The switching regulator output is enabled when logic 1. The reference voltage output operates whenever the
power supply is quAlified (VDD>VPOR) regardless of the state of this pin.
O
Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135°C, returns to the high
state when die temperature has cooled to 100°C.
16
17
18
19
20
21
22
23
24
25
26
27
28
PWRGD
TEST
VSSP
VSSP
LX
O
I
Power good window comparator output. Logic 1 when regulator output is within ±10% of programmed voltage.
Test pin. Must be connected to VSSP in normal operation.
S
S
O
O
O
O
I
Same as pin 7.
Same as pin 7.
Inductor drive pin. High current switching output whose average voltage equAls the regulator output voltage.
LX
Same as pin 20.
LX
Same as pin 20
LX
Same as pin 20
VHI
VSS
C2V
CP
Gate drive to high-side driver. Bootstrapped from LX with a 0.1µF capacitor.
Ground return for the control circuitry.
S
I
Connected to voltage doubler output. Supplies gate drive to the low-side driver.
O
I
Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC
Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT=3.5V.
.
FB2
8
PWRGD, Pin 16
CP, Pin 27
-
FB1, Pin1
2-1 MUX
+
FB2, Pin 28
C2V, Pin 26
VHI, Pin 24
V2X
-
+
-
VCCDET, Pin 13
CSLOPE, Pin 3
VDD and VIN,
Pin 5,6,8
+
Current Sense
CREF, Pin 27
LEB T
DELAY
1.26V
-
+
Σ
Current Limit
Q
-
R
S
OUTEN, Pin 14
LX, Pin 20-23
-
Q
+
PWM
+
4V
VDD
R
SS
VSSP, Pin 9-12,
18-19
UVLO
VDD
C
SS
FF
+
R
S
-
-
S
Zero Cross Detect
+
COSC, Pin 4
-
R
OT, Pin 15
+
Over Temp Sensor
V
SS,
Pin 25
7 5 5 E 6 L A C
EL7556AC
Programmable CPU Power Supply Unit
Applications Information
the relatively large LC time constants found in power
supply applications generally results in low bandwidth
and poor transient response. By directly monitoring
changes in inductor current via a series sense resistor the
controller’s response time is not entirely limited by the
output LC filter and can react more quickly to changes in
line or load conditions. This feed-forward characteristic
also simplifies AC loop compensation since it adds a
zero to the overall loop response. Through proper selec-
tion of the current-feedback to voltage-feedback ratio,
the overall loop response will approach a one pole sys-
tem. The resulting system offers several advantages over
traditional voltage control systems, including simpler
loop compensation, pulse by pulse current limiting,
rapid response to line variation and good load step
response.
Circuit Description
General
The EL7556AC is a fixed frequency, current mode con-
trolled DC:DC converter with integrated N-channel
power MOSFETS and a high precision reference. The
device incorporates all of the active circuitry required to
implement a cost effective, user-programmable 6A syn-
chronous buck converter suitable for use in CPU power
supplies. By combining fused-lead packaging technol-
ogy with an efficient synchronous switching
architecture, high power outputs (21W) can be realized
without the use of discrete external heat sinks.
Theory of Operation
The EL7556AC is composed of 7 major blocks:
1. PWM Controller
The heart of the controller is a triple-input direct sum-
ming comparator which sums voltage feedback, current
feedback and slope compensating ramp signals together.
Slope compensation is required to prevent system insta-
bility which occurs in current-mode topologies
operating at duty-cycles greater than 50% and is also
used to define the open-loop gain of the overall system.
The compensation ramp amplitude is user adjustable and
is set using a single external capacitor (CSLOPE). Each
comparator input is weighted and determines the load
and line regulation characteristics of the system. Current
feedback is measured by sensing the inductor current
flowing through the high-side switch whenever it is con-
ducting. At the beginning of each oscillator period the
high-side NMOS switch is turned on and CSLOPE
ramps positively from its reset state (VREF potential).
The comparator inputs are gated off for a minimum
period of time (LEB) after the high-side switch is turned
on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of errone-
ous voltages at the comparator inputs due to switching
noise. When programming low regulator output voltages
the LEB delay will limit the maximum operating fre-
quency of the circuit since the LEB will result in a
minimum duty-cycle regardless of the PWM error volt-
age. This relationship is shown in the performance
curves. If the inductor current exceeds the maximum
2. Output Voltage Mode Select
3. NMOS Power FETS and Drive Circuitry
4. Bandgap Reference
5. Oscillator
6. Temperature Sensor
7. Power Good and Power On Reset
PWM Controller
The EL7556AC regulates output voltage through the use
of current-mode controlled pulse width modulation. The
three main elements in a PWM controller are the feed-
back loop and reference, a pulse width modulator whose
duty cycle is controlled by the feedback error signal, and
a filter which averages the logic level modulator output.
In a step-down (buck) converter, the feedback loop
forces the time-averaged output of the modulator to
equal the desired output voltage. Unlike pure voltage-
mode control systems current-mode control utilizes dual
feedback loops to provide both output voltage and
inductor current information to the controller. The volt-
age loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output volt-
age is equal to the time-average of the modulator output
current limit (I
), a secondary over-current com-
LMAX
10
EL7556AC
Programmable CPU Power Supply Unit
parator will terminate the high-side switch. If I
and external components D1-D3 and C5-C6. The CP
output is a low resistance inverter driven at one-half the
oscillator frequency. This is used in conjunction with
D2-D3 to generate a 7.5V (typical) voltage on the C2V
pin which provides gate drive to the low-side NMOS
switch and associated level shifter. In order to use an
NMOS switch for the high-side drive it is necessary to
drive the gate voltage above the source voltage (LX).
This is accomplished by boot-strapping the VHI pin
above the C2V voltage with capacitor C6 and diode D1.
When the low-side switch is turned on the LX voltage is
close to GND potential and capacitor C6 is charged
through diodes D1-D3 to approximately 6.9V. At the
beginning of the next cycle the high side switch turns on
and the LX pin begins to rise from GND to VDD poten-
tial. As the LX pin rises the positive plate of capacitor
C6 follows and eventually reaches a value of approxi-
mately 11.2V, for VDD=5V. This voltage is then level
shifted and used to drive the gate of the high-side FET,
via the VHI pin.
LMAX
has not been reached, the regulator output voltage is then
compared to the reference voltage VREF. The resultant
error voltage is summed with the current feedback and
slope compensation ramp. The high-side switch remains
on until all three comparator inputs have summed to
zero, at which time the high-side switch is turned off and
the low-side switch is turned on. In order to eliminate
cross-conduction of the high-side and low-side switches
a 10ns break-before-make delay is incorporated in the
switch driver circuitry. In the continuous mode of opera-
tion the low-side switch will remain on until the end of
the oscillator period. In order to improve the low current
efficiency of the EL7556AC, a zero-crossing compara-
tor senses when the inductor transitions through zero.
Turning off the low-side switch at zero inductor current
prevents forward conduction through the internal clamp-
ing diodes (LX to VSSP) when the low-side switch turns
off, reducing power dissipation. The output enable
(OUTEN) input allows the regulator output to be dis-
abled by an external logic control signal.
Reference
Output Voltage Mode Select
A 1% temperature compensated band gap reference is
integrated in the EL7556AC. The external CREF capac-
itor acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection.
A value of 0.1uF is recommended.
The VCC2DET multiplexes the FB1 and FB2 pins to the
PWM controller. A logic 1 on VCC2DET selects the
FB2 input and forces the output voltage to the internally
programmed value of 3.50V. A logic zero on VCC2DET
selects FB1 and allows the output to be programmed
from 1.0 to 3.8V. In general:
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately
96%. Operating frequency can be adjusted through the
COSC pin or can be driven by an external clock source.
If the oscillator is driven by an external source, care
must be taken in the selection of CSLOPE. Since the
COSC and CSLOPE values determine the open loop
gain of the system, changes to COSC require corre-
sponding changes to CSLOPE in order to maintain a
constant gain ratio. The recommended ratio of COSC to
CSLOPE is 1.5:1
Vout=1.0V (1+R3/R4) Volt.
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and
loop-gain are changed. This is shown in the performance
curves. (The output voltage is factory trimmed to mini-
mize error at a 2.50V output). A 2uA pull-up current
from FB1 to VIN forces VOUT to GND in the event that
FB1 is not used and the VCC2DET is inadvertently tog-
gled between the internal and external feedback mode of
operation.
NMOS Power FETS and Drive Circuitry
Temperature Sensor
The EL7556AC integrates low resistance (25mΩ)
NMOS FETS to achieve high efficiency at 6A. Gate
drive for both the high-side and low-side switches is
derived through a charge pump consisting of the CP pin
An internal temperature sensor continuously monitors
die temperature. In the event that die temperature
exceeds the thermal trip-point, the OT pin will output a
logic 0. The upper and lower trip points are set to 135 ºC
11
EL7556AC
Programmable CPU Power Supply Unit
and 100 ºC respectively. To enable thermal shutdown
this pin should be tied directly to OUTEN. Use of this
feature is recommended during normal operation
with the application of air flow. For example, the addi-
tion of 100LFM reduces the thermal resistance by
approximately 15% and can extend the operating ambi-
ent to 77ºC (typical). Since the thermal performance of
the IC is heavily dependent on the board layout, the sys-
tem designer should exercise care during the design
phase to ensure that the IC will operate under the worst-
case environmental conditions.
Power Good and Power On Reset
During power up the output regulator will be disabled
until VIN reaches a value of approximately 4.0V.
Approximately 500mV of hysteresis is present to elimi-
nate noise induced oscillations.
Under-voltage and over-voltage conditions on the regu-
lator output are detected through an internal window
comparator. A logic 1 on the PWRGD output indicates
that regulated output voltage is within ±10% of the nom-
inally programmed output voltage. Although small, the
typical values of the PWRGD threshold will vary with
changes to external feedback (and resultant loop gain) of
the system. This dependence is shown in the typical per-
formance curves.
Thermal Management
The EL7556AC utilizes fused-lead packaging technol-
ogy in conjunction with the system board layout to
achieve a lower thermal resistance than typically found
in standard 28 lead SOIC packages. By fusing multiple
leads to the die substrate thermal energy flows through a
thermally conductive path (metal) instead of thermally
resistive plastic. After conducting heat from the die to
the leads, heat transfer occurs by convection. If a suffi-
cient amount of metal area is connected to the package
leads a junction-to-ambient resistance of 31ºC/W can be
achieved compared to 100 ºC/W found in standard pack-
ages. The general relationship between board area and
thermal resistance for this package is shown in the per-
formance curves. It can be readily seen that the thermal
resistance approaches an asymptotic value of approxi-
mately 31ºC/W. Additional information can be found in
Application Note #8 (Measuring the Thermal Resistance
of Power Surface-Mount Packages), and Application
Note #13 (EL75XX Thermal Design Considerations).
If the thermal shutdown pin is connected to OUTEN the
IC will enter thermal shutdown when the maximum
junction temperature is reached. For a thermal shutdown
of 135ºC and power dissipation of 2.2W the ambient
temperature is limited to a maximum value of 67ºC (typ-
ical). The ambient temperature range can be extended
12
EL7556AC
Programmable CPU Power Supply Unit
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
Elantec Semiconductor, Inc.
675 Trade Zone Blvd
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
Fax:
(408) 945-9305
European Office: +441-18-977-6020
Japan Technical Center: +81-45-682-5820
Internet: http://www.elantec.com
Printed in U.S.A.
13
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