EBD11ED8ADFB-5C [ELPIDA]
1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks); 1GB无缓冲DDR SDRAM DIMM ( 128M字X72位, 2级)型号: | EBD11ED8ADFB-5C |
厂家: | ELPIDA MEMORY |
描述: | 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks) |
文件: | 总19页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11ED8ADFB-5 (128M words × 72 bits, 2 Ranks)
Description
Features
The EBD11UD8ADFB is 128M words × 72 bits, 2 ranks
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 18 pieces of 512M bits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
• 2.6V power supply
• Data rate: 400Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0408E30 (Ver. 3.0)
Date Published February 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2003-2004
EBD11ED8ADFB-5
Ordering Information
Data rate
Mbps (max.)
Component JEDEC speed bin
(CL-tRCD-tRP)
Contact
pad
Part number
Package
Mounted devices
EBD11ED8ADFB-5B
EBD11ED8ADFB-5C
DDR400B (3-3-3)
DDR400C (3-4-4)
EDD5108ADTA-5B
EDD5108ADTA-5B, -5C
400
184-pin DIMM
Gold
Pin Configurations
Front side
1 pin
52 pin53 pin 92 pin
93 pin
144 pin 145 pin 184 pin
Back side
Pin No.
1
Pin name
VREF
DQ0
VSS
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin name
Pin No.
Pin name
VSS
Pin No.
Pin name
VSS
DQS8
A0
93
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
2
94
DQ4
DM8/ DQS17
A10
3
CB2
95
DQ5
4
DQ1
DQS0
DQ2
VDD
DQ3
NC
VSS
96
VDD
CB6
5
CB3
97
DM0/DQS9
DQ6
VDD
6
BA1
98
CB7
7
DQ32
VDD
DQ33
DQS4
DQ34
VSS
99
DQ7
VSS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
VSS
DQ36
DQ37
VDD
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
NC
NC
VSS
NC
DM4/DQS13
DQ38
DQ39
VSS
DQ8
DQ9
DQS1
VDD
CK1
VDD
BA0
DQ12
DQ13
DM1/DQS10
VDD
DQ35
DQ40
VDD
/WE
DQ44
/RAS
/CK1
VSS
DQ14
DQ15
CKE1
VDD
DQ45
VDD
DQ41
/CAS
VSS
DQ10
DQ11
CKE0
VDD
DQ16
DQ17
DQS2
VSS
/CS0
/CS1
DQS5
DQ42
DQ43
VDD
NC
NC
DM5/DQS14
VSS
DQ20
A12
DQ46
DQ47
NC
VSS
DQ21
A11
DQ48
DQ49
VSS
VDD
A9
DM2/DQS11
VDD
DQ52
DQ53
NC
DQ18
A7
/CK2
DQ22
Data Sheet E0408E30 (Ver. 3.0)
2
EBD11ED8ADFB-5
Pin No.
30
Pin name
VDD
DQ19
A5
Pin No.
76
Pin name
CK2
Pin No.
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Pin name
A8
Pin No.
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin name
VDD
31
77
VDD
DQ23
VSS
DM6/DQS15
DQ54
DQ55
VDD
32
78
DQS6
DQ50
DQ51
VSS
33
DQ24
VSS
DQ25
DQS3
A4
79
A6
34
80
DQ28
DQ29
VDD
35
81
NC
36
82
VDDID
DQ56
DQ57
VDD
DQ60
DQ61
VSS
37
83
DM3/DQS12
A3
38
VDD
DQ26
DQ27
A2
84
39
85
DQ30
VSS
DM7/DQS16
DQ62
DQ63
VDD
40
86
DQS7
DQ58
DQ59
VSS
41
87
DQ31
CB4
42
VSS
A1
88
43
89
CB5
SA0
44
CB0
90
NC
VDD
SA1
45
CB1
91
SDA
CK0
SA2
46
VDD
92
SCL
/CK0
VDDSPD
Data Sheet E0408E30 (Ver. 3.0)
3
EBD11ED8ADFB-5
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A12
A0 to A12
A0 to A9, A11
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
Bank select address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
VDD identification flag
No connection
NC
Data Sheet E0408E30 (Ver. 3.0)
4
EBD11ED8ADFB-5
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
256 bytes
device
2
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
07H
0DH
0BH
02H
48H
00H
04H
50H
70H
02H
82H
08H
08H
DDR SDRAM
3
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
4
11
5
2
6
72
7
Module data width continuation
0
8
Voltage interface level of this assembly 0
SSTL2
5.0ns*1
0.7ns*1
ECC
7.6µs
× 8
9
DDR SDRAM cycle time, CL = 3
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
0
0
0
1
0
0
10
11
12
13
14
Primary SDRAM width
Error checking SDRAM width
× 8
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0EH
04H
1CH
01H
02H
20H
2,4,8
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
4
2, 2.5, 3
0
1
Differential
Clock
SDRAM module attributes
22
23
SDRAM device attributes: General
Minimum clock cycle time at CL = 2.5
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
C0H
60H
VDD ± 0.2V
6.0ns*1
Maximum data access time (tAC) from
clock at CL = 2.5
Minimum clock cycle time at CL = 2
Maximum data access time (tAC) from
clock at CL = 2
24
25
26
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
70H
75H
75H
0.7ns*1
0.75ns*1
0.75ns*1
Minimum row precharge time (tRP)
-5B
-5C
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
-5B
-5C
Minimum active to precharge time
(tRAS)
Module rank density
27
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
3CH
48H
28H
15ns
18ns
10ns
28
29
0
0
0
1
0
1
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
3CH
48H
28H
80H
15ns
18ns
30
31
40ns
512M bytes
Data Sheet E0408E30 (Ver. 3.0)
5
EBD11ED8ADFB-5
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0.6ns*1
Address and command setup time
32
33
34
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
60H
60H
40H
before clock (tIS)
Address and command hold time after
clock (tIH)
Data input setup time before clock
(tDS)
0.6ns*1
0.4ns*1
35
Data input hold time after clock (tDH)
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
40H
00H
0.4ns*1
36 to 40
Superset information
Future use
Active command period (tRC)
-5B
-5C
Auto refresh to active/
Auto refresh command cycle (tRFC)
41
42
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
0
0
37H
3CH
46H
55ns*1
60ns*1
70ns*1
43
SDRAM tCK cycle max. (tCK max.)
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20H
28H
50H
00H
00H
8ns*1
44
Dout to DQS skew
0.4ns*1
0.5ns*1
Future use
45
Data hold skew (tQHS)
Superset information
SPD Revision
46 to 61
62
Checksum for bytes 0 to 62
-5B
-5C
63
1
1
0
0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
B2H
CFH
7FH
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
66
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH
00H
Elpida Memory
67 to 71
(ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
45H
42H
44H
31H
31H
45H
44H
38H
41H
44H
46H
42H
2DH
35H
E
B
D
1
1
E
D
8
A
D
F
B
—
5
Module part number
-5B
87
0
1
0
0
0
0
1
0
42H
B
-5C
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
43H
20H
30H
20H
C
88 to 90
91
Module part number
Revision code
Revision code
(Space)
Initial
(Space)
92
Data Sheet E0408E30 (Ver. 3.0)
6
EBD11ED8ADFB-5
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
Year code
(HEX)
Week code
(HEX)
93
Manufacturing date
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
××
××
94
Manufacturing date
95 to 98
Module serial number
99 to 127 Manufacture specific data
Note: 1.These specifications are defined based on component specification, not module.
Data Sheet E0408E30 (Ver. 3.0)
7
EBD11ED8ADFB-5
Block Diagram
/CS1
/CS0
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
DM0/DQS9
DQS0
DQS
DQ
/CS DM
DQS
DQ
/CS DM
8
8
8
8
8
8
8
8
DQ0 to DQ7
DQS1
U1
U10
RS
RS
RS
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ8 to DQ15
DQS2
U11
U2
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
DQ16 to DQ23
DQS3
U3
U12
RS
RS
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ24 to DQ31
DQS4
U13
U4
RS
RS
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ32 to DQ39
DQS5
U14
U5
RS
RS
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ40 to DQ47
DQS6
U6
U15
RS
RS
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ48 to DQ55
DQS7
U16
U7
RS
RS
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQ56 to DQ63
U8
U17
RS
RS
RS
DM8/DQS17
DQS8
DQS
DQ
/CS DM
DQS
DQ
/CS DM
8
CB0 to CB7
U9
U18
3.3Ω
A0 to A12 (U1 to U18)
BA0, BA1 (U1 to U18)
/RAS (U1 to U18)
/CAS (U1 to U18)
/WE (U1 to U18)
* U1 to U18: 512M bits DDR SDRAM
U20: 2k bits EEPROM
RS: 22Ω
A0 to A12
BA0, BA1
/RAS
3.3Ω
3.3Ω
3.3Ω
3.3Ω
VDD
VREF
VSS
U1 to U18
/CAS
/WE
U1 to U18
U1 to U18
VDDID
open
CKE0
CKE1
CKE (U1, U3, U6, U8, U9, U11, U13, U14, U16)
CKE (U2, U4, U5, U7, U10, U12, U15, U17, U18)
Clock wiring
Serial PD
SCL
Clock input DDR SDRAMS
SCL
SDA
SDA
CK0, /CK0
CK1, /CK1
CK2, /CK2
6DRAM loads
6DRAM loads
6DRAM loads
U20
A0
A1
A2
Note: Wire per Clock loading table/Wiring diagrams.
SA0 SA1 SA2
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
Data Sheet E0408E30 (Ver. 3.0)
8
EBD11ED8ADFB-5
Logical Clock Net Structure
6DRAM loads
5DRAM loads
DRAM1
DRAM1
DRAM2
DRAM3
DRAM2
DRAM3
R = 120Ω
R = 120Ω
R = 120Ω
R = 120Ω
CLK
DIMM
connector
DIMM
connector
DRAM4
DRAM5
Capacitance
DRAM5
/CLK
DRAM6
DRAM1
DRAM6
DRAM1
4DRAM loads
3DRAM loads
DRAM2
Capacitance
DRAM3
R = 120Ω
Capacitance
DIMM
connector
DIMM
connector
Capacitance
DRAM5
Capacitance
DRAM5
DRAM6
DRAM1
Capacitance
Capacitance
2DRAM loads
1DRAM loads
Capacitance
Capacitance
Capacitance
DRAM3
R = 120Ω
DIMM
connector
DIMM
connector
Capacitance
DRAM5
Capacitance
Capacitance
Capacitance
Data Sheet E0408E30 (Ver. 3.0)
9
EBD11ED8ADFB-5
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +3.6
–0.5 to +3.6
50
VDD
IOS
PD
V
mA
W
18
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
1
Tstg
Note: 1. DDR SDRAM component specification.
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)
Parameter
Symbol
VDD,VDDQ
VSS
min.
typ.
2.6
0
max.
2.7
0
Unit
V
Notes
1
Supply voltage
2.5
0
V
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
VREF
0.49 × VDDQ
VREF – 0.04
VREF + 0.15
–0.3
0.50 × VDDQ 0.51 × VDDQ
V
VTT
VREF
—
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
V
VIH (DC)
VIL (DC)
V
2
3
—
V
Input voltage level,
VIN (DC)
VIX (DC)
VID (DC)
–0.3
—
VDDQ + 0.3
V
V
V
4
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
0.5 × VDDQ − 0.2V 0.5 × VDDQ
0.36
0.5 × VDDQ + 0.2V
VDDQ + 0.6
—
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0408E30 (Ver. 3.0)
10
EBD11ED8ADFB-5
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.6V ± 0.1V, VSS = 0V)
Parameter
Symbol
IDD0
Grade
max.
Unit
mA
Test condition
Notes
1, 2, 9
-5B
-5C
2205
2070
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACTV-PRE)
CKE ≥ VIH, BL = 4,
Operating current
(ACTV-READ-PRE)
-5B
-5C
2655
2520
IDD1
mA
CL = 3,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current
Floating idle standby current
IDD2P
IDD2F
54
mA
mA
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4
630
4, 5
CKE ≥ VIH, /CS ≥ VIH
Quiet idle standby current
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
360
mA
mA
mA
mA
mA
mA
mA
mA
4, 10
DQ, DQS, DM = VREF
Active power down
standby current
540
CKE ≤ VIL
3
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 3
CKE ≥ VIH, BL = 2,
CL = 3
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Active standby current
1260
3240
3240
5940
72
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Self refresh current
IDD6
Operating current
(4 banks interleaving)
-5B
-5C
5670
5400
IDD7A
BL = 4
1, 5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
Parameter
Symbol
ILI
min.
–36
max.
36
Unit
µA
Test condition
Note
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDD ≥ VOUT ≥ VSS
VOUT = 1.95V
ILO
–10
10
µA
IOH
IOL
–15.2
15.2
—
mA
mA
1
1
—
VOUT = 0.35V
Note: 1. DDR SDRAM component specification.
Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)
Parameter
Symbol
CI1
Pins
max.
Unit
pF
Note
Address, /RAS, /CAS, /WE,
/CS, CKE
CK, /CK
Input capacitance
Input capacitance
Data and DQS input/output
capacitance
60
50
20
CI2
pF
CO
DQ, DQS, CB
pF
Data Sheet E0408E30 (Ver. 3.0)
11
EBD11ED8ADFB-5
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
(DDR SDRAM Component Specification)
-5B
min.
5
-5C
min.
5
Parameter
Symbol
tCK
max.
8
max.
8
Unit
ns
Notes
10
Clock cycle time
CK high-level width
CK low-level width
tCH
0.45
0.55
0.55
0.45
0.55
0.55
tCK
tCK
tCL
0.45
0.45
min
(tCH, tCL)
min
(tCH, tCL)
CK half period
tHP
—
—
tCK
DQ output access time from CK, /CK
DQS output access time from CK, /CK
DQS to DQ skew
tAC
–0.7
0.7
0.6
0.4
—
–0.7
0.7
0.6
0.4
—
ns
ns
ns
ns
ns
2, 11
2, 11
3
tDQSCK
tDQSQ
tQH
–0.6
–0.6
—
—
DQ/DQS output hold time from DQS
Data hold skew factor
tHP – tQHS
—
tHP – tQHS
—
tQHS
0.5
0.5
Data-out high-impedance time from CK,
tHZ
tLZ
—
0.7
0.7
—
0.7
0.7
ns
ns
5, 11
6, 11
/CK
Data-out low-impedance time from CK,
/CK
–0.7
–0.7
Read preamble
tRPRE
tRPST
tDS
0.9
0.4
0.4
0.4
1.75
0
1.1
0.6
—
0.9
0.4
0.4
0.4
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
8
8
7
tDH
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
ns
—
—
ns
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
9
Write command to first DQS latching
transition
tDQSS
0.72
1.28
0.72
1.28
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
tDSS
tDSH
tDQSH
tDQSL
tIS
0.2
0.2
0.35
0.35
0.6
0.6
2.2
2
—
0.2
0.2
0.35
0.35
0.6
0.6
2.2
2
—
tCK
tCK
tCK
tCK
ns
—
—
—
—
DQS input low pulse width
—
—
Address and control input setup time
Address and control input hold time
Address and control input pulse width
—
—
8
8
7
tIH
—
—
ns
tIPW
—
—
ns
Mode register set command cycle time tMRD
—
—
tCK
ns
Active to Precharge command period
tRAS
40
70000
40
70000
Active to Active/Auto refresh command
tRC
55
70
—
—
60
70
—
—
ns
ns
period
Auto refresh to Active/Auto refresh
command period
tRFC
Active to Read/Write delay
Precharge to active command period
Active to Autoprecharge delay
Active to active command period
Write recovery time
tRCD
tRP
15
—
—
—
—
—
18
—
—
—
—
—
ns
ns
ns
ns
ns
15
18
tRAP
tRRD
tWR
tRCD min.
tRCD min.
10
10
15
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
tCK
13
Data Sheet E0408E30 (Ver. 3.0)
12
EBD11ED8ADFB-5
-5B
min.
2
-5C
min.
2
Parameter
Symbol
tWTR
tREF
max.
—
max.
—
Unit
tCK
µs
Notes
Internal write to Read command delay
Average periodic refresh interval
—
7.8
—
7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,
tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)
tDAL = 7 clocks
Data Sheet E0408E30 (Ver. 3.0)
13
EBD11ED8ADFB-5
Timing Parameter Measured in Clock Cycle for unbuffered DIMM
Number of clock cycle
tCK
5ns
Parameter
Symbol
tWPD
tRPD
min.
4 + BL/2
BL/2
2 + BL/2
3
max.
—
Unit
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
Burst stop command to write command delay
Burst stop command to DQ High-Z
tCK
tCK
—
tCK
tCK
tCK
tWRD
tBSTW
tBSTZ
—
—
3
3
Read command to write command delay
(to output all data)
Pre-charge command to High-Z
Write command to data in latency
Write recovery
tRWD
3 + BL/2
—
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tHZP
3
3
tWCD
tWR
1
1
3
—
0
DM to data in latency
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
0
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
2
—
—
—
1
15
200
1
Power down exit to command input
1
—
Data Sheet E0408E30 (Ver. 3.0)
14
EBD11ED8ADFB-5
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9
and the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This
column address becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0, BA1 (input pin)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
L
Bank 2
H
H
Bank 3
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ, CB (input and output pins)
Data are input to and output from these pins.
DQS (input and output pin)
DQS provide the read data strobes (as output) and the write data strobes (as input).
Data Sheet E0408E30 (Ver. 3.0)
15
EBD11ED8ADFB-5
DM (input pins)
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF
VDD (power supply pins)
2.6V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
2.6V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDD5108ADTA-5 datasheet (E0383E).
Data Sheet E0408E30 (Ver. 3.0)
16
EBD11ED8ADFB-5
Physical Outline
Unit: mm
133.35 ± 0.15
128.95
4.00 max
(DATUM -A-)
(64.48)
Component area
(Front)
1
92
B
A
1.27 ± 0.10
64.77
49.53
2 – φ 2.50 ± 0.10
93
184
Component area
(Back)
R 2.00
3.00 min
Detail A
Detail B
1.27 typ
(DATUM -A-)
6.62
2.175
R 0.90
6.35
1.80 ± 0.10
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.
ECA-TS2-0040-01
Data Sheet E0408E30 (Ver. 3.0)
17
EBD11ED8ADFB-5
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0408E30 (Ver. 3.0)
18
EBD11ED8ADFB-5
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0408E30 (Ver. 3.0)
19
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