EBD21RD4ADNA [ELPIDA]
2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks); 注册2GB DDR SDRAM DIMM （ 256M字X72位， 2级）
| 型号： | EBD21RD4ADNA |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| 文件： | 总19页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
2GB Registered DDR SDRAM DIMM
EBD21RD4ADNA (256M words × 72 bits, 2 Ranks)
Description
Features
The EBD21RD4ADNA is a 256M words × 72 bits, 2
ranks Double Data Rate (DDR) SDRAM Module,
mounting 36 pieces of DDR SDRAM sealed in TCP
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2-bit prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each TCP
on the module board.
• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
• 1 piece of PLL clock driver, 1 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0433E10 (Ver. 1.0)
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003
EBD21RD4ADNA
Ordering Information
Data rate
Mbps (max.)
Component JEDEC speed bin*1
(CL-tRCD-tRP)
Contact
pad
Part number
Package
Mounted devices
EBD21RD4ADNA-6B
EBD21RD4ADNA-7A
EBD21RD4ADNA-7B
333
266
266
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
184-pin
DIMM
512M bits DDR
SDRAM TCP*2
Gold
Notes: 1. Module /CAS latency = component CL + 1
2. Please refer to 512Mb DDR TSOP product datasheet (E0384E) for electrical characteristics.
Pin Configurations
Front side
1 pin
52 pin53 pin 92 pin
93 pin
144 pin 145 pin 184 pin
Back side
Pin No.
1
Pin name
VREF
DQ0
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Pin name
Pin No.
Pin name
VSS
Pin No.
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
Pin name
VSS
DQS8
A0
93
2
94
DQ4
DM8/DQS17
A10
3
VSS
CB2
95
DQ5
4
DQ1
VSS
96
VDD
CB6
5
DQS0
DQ2
CB3
97
DM0/DQS9
DQ6
VDD
6
BA1
98
CB7
7
VDD
DQ3
DQ32
VDD
DQ33
DQS4
DQ34
VSS
99
DQ7
VSS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VSS
DQ36
DQ37
VDD
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
/RESET
VSS
NC
NC
DM4/DQS13
DQ38
DQ39
VSS
DQ8
VDD
DQ9
BA0
DQ12
DQ13
DM1/DQS10
VDD
DQS1
VDD
NC
DQ35
DQ40
VDD
/WE
DQ44
/RAS
NC
DQ14
DQ15
CKE1
VDD
DQ45
VDD
VSS
DQ41
/CAS
VSS
DQ10
DQ11
CKE0
VDD
DQ16
DQ17
DQS2
VSS
/CS0
/CS1
DQS5
DQ42
DQ43
VDD
NC
NC
DM5/DQS14
VSS
DQ20
A12
DQ46
DQ47
NC
VSS
DQ21
A11
DQ48
DQ49
VSS
VDD
A9
DM2/DQS11
VDD
DQ52
DQ53
DQ18
Preliminary Data Sheet E0433E10 (Ver. 1.0)
2
EBD21RD4ADNA
Pin No.
29
Pin name
A7
Pin No.
75
Pin name
NC
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Pin name
DQ22
A8
Pin No.
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin name
NC
30
VDD
DQ19
A5
76
NC
VDD
31
77
VDD
DQ23
VSS
DM6/DQS15
DQ54
DQ55
VDD
32
78
DQS6
DQ50
DQ51
VSS
33
DQ24
VSS
DQ25
DQS3
A4
79
A6
34
80
DQ28
DQ29
VDD
35
81
NC
36
82
VDDID
DQ56
DQ57
VDD
DQ60
DQ61
VSS
37
83
DM3/DQS12
A3
38
VDD
DQ26
DQ27
A2
84
39
85
DQ30
VSS
DM7/DQS16
DQ62
DQ63
VDD
40
86
DQS7
DQ58
DQ59
VSS
41
87
DQ31
CB4
42
VSS
A1
88
43
89
CB5
SA0
44
CB0
CB1
VDD
90
NC
VDD
SA1
45
91
SDA
CK0
SA2
46
92
SCL
/CK0
VDDSPD
Preliminary Data Sheet E0433E10 (Ver. 1.0)
3
EBD21RD4ADNA
Pin Description
Pin name
Function
Address input
Row address
A0 to A12
A0 to A12
Column address
A0 to A9, A11, A12
BA0, BA1
Bank select address
Data input/output
DQ0 to DQ63
CB0 to CB7
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/RAS
/CAS
/WE
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0
Clock input
/CK0
Differential clock input
Input and output data strobe
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
SDA
SA0 to SA2
VDD
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDDSPD
VREF
VSS
VDDID
/RESET
NC
VDD identification flag
Reset pin (forces register inputs low)
No connection
Preliminary Data Sheet E0433E10 (Ver. 1.0)
4
EBD21RD4ADNA
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
device
256 byte
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0
0
0
0
07H
0DH
0CH
02H
48H
00H
04H
SDRAM DDR
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
12
2
72 bits
0 (+)
Module data width continuation
Voltage interface level of this assembly 0
SSTL 2.5V
DDR SDRAM cycle time, CL = X
-6B
9
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
60H
75H
70H
CL = 2.5*3
-7A, -7B
0
0
SDRAM access from clock (tAC)
-6B
10
0.70ns*3
-7A, -7B
0
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
75H
02H
0.75ns*3
ECC
11
12
DIMM configuration type
7.8 µs
Self refresh
Refresh rate/type
1
0
0
0
0
0
1
0
82H
13
14
Primary SDRAM width
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
04H
04H
× 4
× 4
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
Burst length supported
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH
04H
0CH
01H
02H
2, 4, 8
SDRAM device attributes: Number of
banks on SDRAM device
4
SDRAM device attributes:
/CAS latency
2, 2.5
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0
1
21
22
SDRAM module attributes
0
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
26H
C0H
Registered
0.2V
SDRAM device attributes: General
Minimum clock cycle time at CLX - 0.5
-6B, -7A
23
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
75H
A0H
CL = 2*3
-7B
Maximum data access time (tAC) from
clock at CLX - 0.5
-6B
24
0
1
1
1
0
0
0
0
70H
0.70ns*3
0.75ns*3
-7A, -7B
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H
00H
25
26
Minimum clock cycle time at CLX - 1
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
Preliminary Data Sheet E0433E10 (Ver. 1.0)
5
EBD21RD4ADNA
Byte No. Function described
Minimum row precharge time (tRP)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
18ns
27
28
29
30
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H
50H
-6B
-7A, -7B
20ns
Minimum row active to row active
delay (tRRD)
-6B
0
0
1
1
0
0
0
0
30H
12ns
-7A, -7B
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
3CH
48H
50H
15ns
18ns
20ns
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
(tRAS)
-6B
0
0
1
0
1
0
1
0
2AH
42ns
-7A, -7B
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
2DH
01H
45ns
2 banks
1GB
31
32
Module rank density
Address and command setup time
before clock (tIS)
-6B
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
75H
90H
75H
90H
45H
0.75ns*3
0.9ns*3
-7A, -7B
Address and command hold time after
clock (tIH)
-6B
33
0.75ns*3
0.9ns*3
-7A, -7B
Data input setup time before clock
(tDS)
-6B
34
35
0.45ns*3
-7A, -7B
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
50H
45H
0.5ns*3
Data input hold time after clock (tDH)
-6B
0.45ns*3
-7A, -7B
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
50H
00H
0.5ns*3
36 to 40
41
Superset information
Future use
Active command period (tRC)
-6B
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
3CH
41H
60ns*3
65ns*3
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
42
0
1
0
0
1
0
0
0
48H
72ns*3
-7A, -7B
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
4BH
30H
75ns*3
12ns*3
43
44
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
2DH
32H
55H
450ps*3
500ps*3
550ps*3
-7A, -7B
Data hold skew (tQHS)
-6B
45
-7A, -7B
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
75H
00H
00H
750ps*3
Future use
Initial
46 to 61
62
Superset information
SPD revision
Preliminary Data Sheet E0433E10 (Ver. 1.0)
6
EBD21RD4ADNA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
212
Checksum for bytes 0 to 62
63
1
1
0
1
0
1
0
0
D4H
-6B
-7A
1
1
0
0
1
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
1
0
1
1
0
0
8BH
B6H
7FH
7FH
FEH
00H
139
182
-7B
64
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
65
66
Elpida Memory
67 to 71
*2 (ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
75
76
77
78
79
80
81
82
83
84
85
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
45H
42H
44H
32H
31H
52H
44H
34H
41H
44H
4EH
41H
2DH
E
B
D
2
1
R
D
4
A
D
N
A
—
Module part number
-6B
86
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
36H
37H
41H
6
7
A
-7A, -7B
Module part number
-7A
87
-6B, -7B
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
42H
20H
30H
20H
B
88 to 90
91
Module part number
Revision code
Revision code
(Space)
Initial
(Space)
92
Year code
(HEX)
93
Manufacturing date
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
××
××
Week code
(HEX)
94
Manufacturing date
2
95 to 98
Module serial number
*
99 to 127 Manufacturer specific data
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High“.
2. Bytes 95 through 98 are assembly serial number.
3. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
7
EBD21RD4ADNA
Block Diagram
VSS
/RCS1
/RCS0
RS
RS
DQS0
DM0/DQS9
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
DQ0 to DQ3
DQS1
DQ4 to DQ7
DM1/DQS10
D0
D18
D9
D27
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ8 to DQ11
DQS2
DQ12 to DQ15
DM2/DQS11
D1
D19
D10
D28
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ16 to DQ19
DQS3
DQ20 to DQ23
DM3/DQS12
D2
D20
D11
D29
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ24 to DQ27
DQS4
DQ28 to DQ31
DM4/DQS13
D3
D21
D12
D30
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ32 to DQ35
DQS5
DQ36 to DQ39
DM5/DQS14
D4
D22
D13
D31
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ40 to DQ43
DQS6
DQ44 to DQ47
DM6/DQS15
D5
D23
D14
D32
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ48 to DQ51
DQS7
DQ52 to DQ55
DM7/DQS16
D6
D24
D15
D33
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ56 to DQ59
DQS8
DQ60 to DQ63
DM8/DQS17
D7
D25
D16
D34
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
CB0 to CB3
CB4 to CB7
D8
D26
D17
D35
R
S
S
S
S
S
S
S
S
/CS0
/CS1
/RCS0 -> /CS: SDRAMs D0 to D17
* D0 to D35: 512M bits DDR SDRAM TCP
U0: 2k bits EEPROM
RS: 22Ω (DQ, DQS)
PLL: CDCV857
Register: SSTV32852
R
R
R
R
R
R
R
/RCS1 -> /CS: SDRAMs D18 to D35
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35
/RRAS -> /RAS: SDRAMs D0 to D35
/RCAS -> /CAS: SDRAMs D0 to D35
RCKE0 -> CKE: SDRAMs D0 to D17
RCKE1 -> CKE: SDRAMs D18 to D35
/RWE -> /WE: SDRAMs D0 to D35
R
E
G
I
S
T
E
R
BA0 to BA1
A0 to A12
/RAS
Serial PD
/CAS
SCL
SCL
A0
SDA
SDA
CKE0
U0
CKE1
A1
A2
R
S
/WE
PCK
/PCK
/RESET
SA0 SA1 SA2
Notes:
VDD
D0 to D35
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
VREF
VSS
D0 to D35
D0 to D35
VDDID
open
CK0, /CK0
PLL*
Note: Wire per Clock loading table/Wiring diagrams.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
8
EBD21RD4ADNA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
SDRAM
stack
PLL
120Ω
OUT1
SDRAM
stack
120Ω
CK0
IN
/CK0
240Ω
OUT'N'
Register
120Ω
C
Feedback
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0 ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
9
EBD21RD4ADNA
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +3.6
–1.0 to +3.6
50
V
VDD
IOS
PT
V
mA
W
°C
°C
18
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
1
Tstg
Note:1. DDR SDRAM component specification
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)
Parameter
Symbol
VDD,VDDQ
VSS
min.
typ.
2.5
0
max.
2.7
0
Unit
V
Notes
1
Supply voltage
2.3
0
V
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
VREF
0.49 × VDDQ
VREF – 0.04
VREF + 0.15
–0.3
0.50 × VDDQ 0.51 × VDDQ
V
VTT
VREF
—
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
V
VIH (DC)
VIL (DC)
V
2
3
—
V
Input voltage level,
CK and /CK inputs
VIN (DC)
VIX (DC)
VID (DC)
–0.3
—
VDDQ + 0.3
V
V
V
4
Input differential cross point
voltage, CK and /CK inputs
0.5 × VDDQ − 0.2V 0.5 × VDDQ
0.36
0.5 × VDDQ + 0.2V
VDDQ + 0.6
Input differential voltage,
CK and /CK inputs
—
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
10
EBD21RD4ADNA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
mA
Test condition
Notes
1, 2, 9
-6B
-7A, -7B
4160
3700
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACTV-PRE) IDD0
Operating current
IDD1
-6B
-7A, -7B
-6B
-7A, -7B
4880
4330
395
385
CKE ≥ VIH, BL = 4,
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2, 5
4
(ACTV-READ-PRE)
CL = 3.5, tRC = tRC (min.)
Idle power down standby current IDD2P
CKE ≤ VIL
Floating idle
IDD2F
-6B
-7A, -7B
1370
1180
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 5
Standby current
Quiet idle
Standby current
-6B
-7A, -7B
1010
1000
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
IDD2Q
4, 10
3
Active power down standby
-6B
-7A, -7B
1010
1000
IDD3P
current
CKE ≤ VIL
-6B
-7A, -7B
2630
2260
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
Active standby current
IDD3N
IDD4R
IDD4W
IDD5
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Operating current
(Burst read operation)
-6B
-7A, -7B
5600
4870
CKE ≥ VIH, BL = 2,
CL = 3.5
Operating current
(Burst write operation)
-6B
-7A, -7B
5600
4870
CKE ≥ VIH, BL = 2,
CL = 3.5
-6B
-7A, -7B
-6B
-7A, -7B
7220
6670
430
420
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Auto refresh current
Self refresh current
IDD6
Operating current
(4 banks interleaving)
-6B
-7A, -7B
10280
8650
IDD7A
BL = 4
5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM, DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once per one every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
11
EBD21RD4ADNA
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
Parameter
Symbol
ILI
min.
–2
max.
2
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
VOUT = 1.95V
ILO
–5
5
µA
IOH
IOL
–15.2
15.2
—
—
mA
mA
VOUT = 0.35V
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V 0.2V)
Parameter
Symbol
CI1
Pins
max.
20
Unit
pF
Notes
Address, /RAS, /CAS, /WE,
/CS, CKE
Input capacitance
Input capacitance
1, 3
CI2
CK, /CK
20
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB, DM
20
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
min.
max.
12
min.
max
12
min.
max.
12
Parameter
Symbol
tCK
Unit Notes
Clock cycle time
(CL = 2)
7.5
7.5
10
ns
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min
(tCH, tCL)
min
(tCH, tCL)
min
(tCH, tCL)
CK half period
tHP
—
—
—
tCK
ns
DQ output access time from CK, /CK tAC
DQS output access time from CK,
/CK
–0.7
0.7
0.6
0.45
–0.75
–0.75
—
0.75
0.75
0.5
–0.75
–0.75
—
0.75
0.75
0.5
2, 11
2, 11
3
tDQSCK –0.6
ns
DQS to DQ skew
tDQSQ
—
ns
ns
ns
DQ/DQS output hold time from DQS tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
Data-out high-impedance time from
CK, /CK
tHZ
tLZ
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
ns
ns
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
–0.7
–0.75
–0.75
Read preamble
tRPRE
tRPST
tDS
0.9
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.45
0.45
1.75
8
8
7
tDH
—
—
—
ns
tDIPW
—
—
—
ns
tWPRES 0
—
—
—
ns
tWPRE 0.25
—
0.25
—
0.25
—
tCK
Preliminary Data Sheet E0433E10 (Ver. 1.0)
12
EBD21RD4ADNA
-6B
-7A
min.
0.4
-7B
min.
0.4
min.
max.
0.6
max
0.6
max.
0.6
Parameter
Symbol
Unit Notes
Write postamble
tWPST 0.4
tCK
tCK
9
Write command to first DQS latching
transition
tDQSS
tDSS
0.75
1.25
0.75
1.25
0.75
1.25
DQS falling edge to CK setup time
0.2
0.2
—
—
—
0.2
—
—
—
—
0.2
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge hold time from CK tDSH
0.2
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH 0.35
0.35
0.35
0.35
0.35
tDQSL
0.35
0.75
Address and control input setup time tIS
—
0.9
—
0.9
—
ns
8
Address and control input hold time tIH
Address and control input pulse width tIPW
0.75
2.2
—
—
0.9
2.2
—
—
0.9
2.2
—
—
ns
ns
8
7
Mode register set command cycle
time
tMRD
2
—
2
—
2
—
tCK
Active to Precharge command period tRAS
42
60
120000 45
120000 45
120000 ns
Active to Active/Auto refresh
tRC
—
—
65
75
—
—
65
75
—
—
ns
ns
command period
Auto refresh to Active/Auto refresh
command period
tRFC
72
Active to Read/Write delay
tRCD
18
—
—
—
—
—
20
—
—
—
—
—
20
—
—
—
—
—
ns
ns
ns
ns
ns
Precharge to active command period tRP
18
20
20
Active to Autoprecharge delay
Active to active command period
Write recovery time
tRAP
tRCD min.
tRCD min.
tRCD min.
tRRD
tWR
12
15
15
15
15
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
tCK 13
Internal write to Read command
delay
tWTR
tREF
1
—
1
—
1
—
tCK
µs
Average periodic refresh interval
—
7.8
—
7.8
—
7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
13
EBD21RD4ADNA
12. VDD is assumed to be 2.5V 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle
tCK
6ns
7.5ns
Parameter
Symbol
min.
min.
min.
min.
Unit
tCK
tCK
tCK
Write to pre-charge command delay (same bank) tWPD
Read to pre-charge command delay (same bank) tRPD
4 + BL/2
BL/2
3 + BL/2
BL/2
Write to read command delay (to input all data)
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
2 + BL/2
2 + BL/2
Burst stop command to write command delay
(CL = 3)
—
3
—
2
tCK
tCK
tCK
tCK
(CL = 3.5)
3
Burst stop command to DQ High-Z
(CL = 3)
—
3.5
—
3
3
(CL = 3.5)
3.5
3.5
3.5
Read command to write command delay
(to output all data)
tRWD
—
—
2 + BL/2
tCK
(CL = 3)
(CL = 3.5)
tRWD
tHZP
3 + BL/2
—
3 + BL/2
3
tCK
tCK
Pre-charge command to High-Z
(CL = 3)
—
3
(CL = 3.5)
tHZP
tWCD
tWR
3.5
2
3.5
3.5
2
3.5
tCK
tCK
tCK
Write command to data in latency
Write recovery
2
1
Register set command to active or register set
command
tMRD
2
2
tCK
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
tSNR
12
200
1
10
200
1
tCK
tCK
tCK
tCK
tSRD
tPDEN
tPDEX
1
1
Power down exit to command input
1
1
Preliminary Data Sheet E0433E10 (Ver. 1.0)
14
EBD21RD4ADNA
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11, AY12) is loaded via theA0 to the
A9, the A11 and the A12 at the cross point of the CK rising edge and the VREF level in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0, BA1 (input pin)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
L
Bank 2
H
H
Bank 3
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ, CB (input and output pins)
Data are input to and output from these pins.
DQS (input and output pin)
DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0433E10 (Ver. 1.0)
15
EBD21RD4ADNA
VDD (power supply pins)
2.5V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
2.5V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
/RESET (input pin)
LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
Detailed Operation Part and Timing Waveforms
Refer to the EDD5104ADTA, EDD5108ADTA, EDD5116ADTA datasheet (E0384E). DM pins of component device
fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Preliminary Data Sheet E0433E10 (Ver. 1.0)
16
EBD21RD4ADNA
Physical Outline
Unit: mm
4.80
133.35 ± 0.15
128.95
(DATUM -A-)
(64.48)
Component area
(Front)
1
92
B
A
1.27 ± 0.10
64.77
49.53
2 – φ 2.50 ± 0.10
93
184
Component area
(Back)
R 2.00
3.00 min
Detail A
Detail B
1.27 typ
(DATUM -A-)
6.62
2.175
R 0.90
6.35
1.00 ± 0.05
1.80 ± 0.10
Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.
ECA-TS2-0058-01
Preliminary Data Sheet E0433E10 (Ver. 1.0)
17
EBD21RD4ADNA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0433E10 (Ver. 1.0)
18
EBD21RD4ADNA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0433E10 (Ver. 1.0)
19
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