EBD51RC4AAFA-7A-E [ELPIDA]
DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184;
| 型号： | EBD51RC4AAFA-7A-E |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | DDR DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总17页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AAFA (64M words × 72 bits, 1 Bank)
Description
Features
The EBD51RC4AAFA is a 64M words × 72 bits × 1
bank Double Data Rate (DDR) SDRAM Module,
mounting 18 pieces of 256Mbits DDR SDRAM sealed
• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
in TSOP package.
Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2-bit
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 3, 3.5
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0335E10 (Ver. 1.0)
Date Published January 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003
EBD51RC4AAFA
Ordering Information
Component
Data rate
Mbps (max.)
JEDEC speed bin*1
(CL-tRCD-tRP)
Contact
pad
Part number
Package
Mounted devices
EBD51RC4AAFA-7A
EBD51RC4AAFA-7B
266
266
DDR266A (2-3-3)
184-pin DIMM
Gold
M2S56D20ATP-75A
M2S56D20ATP-75A, -75
DDR266B (2.5-3-3)
Note: 1. Module /CAS latency = component CL + 1
Pin Configurations
Front side
1 pin
52 pin53 pin 92 pin
93 pin
144 pin 145 pin 184 pin
Back side
Pin No.
1
Pin name
VREF
DQ0
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin name
Pin No.
Pin name
VSS
Pin No.
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
Pin name
VSS
DQS8
A0
93
2
94
DQ4
DM8/DQS17
A10
3
VSS
CB2
95
DQ5
4
DQ1
VSS
96
VDDQ
DM0/DQS9
DQ6
CB6
5
DQS0
DQ2
CB3
97
VDDQ
CB7
6
BA1
98
7
VDD
DQ3
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
99
DQ7
VSS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
VSS
DQ36
DQ37
VDD
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
/RESET
VSS
NC
NC
DM4/DQS13
DQ38
DQ39
VSS
DQ8
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ9
BA0
DQS1
VDDQ
NC
DQ35
DQ40
VDDQ
/WE
DQ44
/RAS
NC
DQ14
DQ15
NC
DQ45
VDDQ
/CS0
VSS
DQ41
/CAS
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
VDDQ
NC
NC
DQS5
DQ42
DQ43
VDD
NC
DM5/DQS14
VSS
DQ20
A12
DQ46
DQ47
NC
VSS
DQ21
A11
DQ48
DQ49
VSS
VDDQ
DQ52
DQ53
NC
A9
DM2/DQS11
VDD
DQ18
A7
NC
DQ22
Preliminary Data Sheet E0335E10 (Ver. 1.0)
2
EBD51RC4AAFA
Pin No.
30
Pin name
VDDQ
DQ19
A5
Pin No.
76
Pin name
NC
Pin No.
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Pin name
A8
Pin No.
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Pin name
VDD
31
77
VDDQ
DQS6
DQ50
DQ51
VSS
DQ23
VSS
DM6/DQS15
DQ54
32
78
33
DQ24
VSS
79
A6
DQ55
34
80
DQ28
DQ29
VDDQ
DM3/DQS12
A3
VDDQ
NC
35
DQ25
DQS3
A4
81
36
82
VDDID
DQ56
DQ57
VDD
DQ60
37
83
DQ61
38
VDD
DQ26
DQ27
A2
84
VSS
39
85
DQ30
VSS
DM7/DQS16
DQ62
40
86
DQS7
DQ58
DQ59
VSS
41
87
DQ31
CB4
DQ63
42
VSS
88
VDDQ
SA0
43
A1
89
CB5
44
CB0
90
NC
VDDQ
CK0
SA1
45
CB1
91
SDA
SA2
46
VDD
92
SCL
/CK0
VDDSPD
Preliminary Data Sheet E0335E10 (Ver. 1.0)
3
EBD51RC4AAFA
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A12
A0 to A12
A0 to A9, A11
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/RAS
/CAS
/WE
/CS0
Chip select
CKE0
Clock enable
CK0
Clock input
/CK0
Differential clock input
Input and output data strobe
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
DQS0 to DQS8
DM0 to DM8/DQS9 to DQS17
SCL
SDA
SA0 to SA2
VDD
Power for internal circuit
Power for DQ circuit
VDDQ
VDDSPD
VREF
VSS
Power for serial EEPROM
Input reference voltage
Ground
VDDID
/RESET
NC
VDD identification flag
Reset pin (forces register inputs low)
No connection
Preliminary Data Sheet E0335E10 (Ver. 1.0)
4
EBD51RC4AAFA
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
256 byte
device
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
07H
0DH
0BH
01H
48H
00H
04H
SDRAM DDR
Number of row address
Number of column address
Number of DIMM banks
Module data width
13
11
1
72 bits
0 (+)
Module data width continuation
Voltage interface level of this assembly 0
SSTL 2.5V
DDR SDRAM cycle time, CL = X
-7A
9
0
1
1
1
0
0
0
0
70H
CL = 2.5*3
-7B
0
0
0
1
1
0
1
1
0
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
75H
75H
02H
10
11
SDRAM access from clock (tAC)
DIMM configuration type
0.75ns*3
ECC
7.8 µs
Self refresh
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
13
14
Primary SDRAM width
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
04H
04H
× 4
Error checking SDRAM width
× 4
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH
04H
0CH
01H
02H
2, 4, 8
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
4
2/2.5
0
1
21
22
SDRAM module attributes
0
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
26H
C0H
Registered
± 0.2V
SDRAM device attributes: General
Minimum clock cycle time at
CLX - 0.5
-7A
23
0
1
1
1
0
1
0
1
75H
CL = 2*3
-7B
1
0
0
1
1
1
0
1
0
0
0
1
0
0
0
1
A0H
75H
Maximum data access time (tAC) from
clock at CLX - 0.5
24
25
0.75ns*3
Minimum clock cycle time at
CLX - 1
0
0
0
0
0
0
0
0
00H
Maximum data access time (tAC) from
26
27
28
29
30
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
00H
50H
3CH
50H
2DH
clock at CLX - 1
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
20ns
15ns
20ns
45ns
Preliminary Data Sheet E0335E10 (Ver. 1.0)
5
EBD51RC4AAFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
1 bank
512MB
31
32
33
34
Module bank density
1
1
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
80H
90H
90H
50H
Address and command setup time
before clock (tIS)
Address and command hold time after
clock (tIH)
Data input setup time before clock
(tDS)
Data input hold time after clock (tDH)
0.9ns*3
0.9ns*3
0.5ns*3
35
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
50H
00H
41H
0.5ns*3
36 to 40
41
Superset information
Future use
65ns*3
Active command period (tRC)
Auto refresh to active/
42
0
1
0
0
1
0
1
1
4BH
75ns*3
Auto refresh command cycle (tRFC)
43
SDRAM tCK cycle max. (tCK max.)
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
30H
32H
75H
00H
00H
12ns*3
44
Dout to DQS skew
500ps*3
750ps*3
Future use
Initial
45
Data hold skew (tQHS)
Superset information
SPD revision
46 to 61
62
Checksum for bytes 0 to 62
-7A
-7B
63
0
0
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
03H
33H
7FH
3
51
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
66
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FEH
00H
Elpida Memory
67 to 71
(ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
45H
42H
44H
35H
31H
52H
43H
34H
41H
41H
46H
41H
2DH
37H
E
B
D
5
1
R
C
4
A
A
F
A
—
7
Module part number
-7A
87
0
1
0
0
0
0
0
1
41H
A
-7B
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
42H
20H
30H
20H
B
88 to 90
91
Module part number
Revision code
Revision code
(Space)
Initial
(Space)
92
Year code
(BCD)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Preliminary Data Sheet E0335E10 (Ver. 1.0)
6
EBD51RC4AAFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
××
Comments
Week code
(BCD)
94
Manufacturing date
×
×
×
×
×
×
×
×
2
95 to 98
Module serial number
*
99 to 127 Manufacturer specific data
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”.
2. Bytes 95 through 98 are assembly serial number.
3. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
7
EBD51RC4AAFA
Block Diagram
VSS
/RCS0
RS
RS
DQS0
DM0/DQS9
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
DQ0 to DQ3
DQS1
DQ4 to DQ7
DM1/DQS10
D0
D9
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ8 to DQ11
DQS2
DQ12 to DQ15
DM2/DQS11
D1
D10
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ16 to DQ19
DQS3
DQ20 to DQ23
DM3/DQS12
D2
D11
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ24 to DQ27
DQS4
DQ28 to DQ31
DM4/DQS13
D3
D12
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ32 to DQ35
DQS5
DQ36 to DQ39
DM5/DQS14
D4
D13
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ40 to DQ43
DQS6
DQ44 to DQ47
DM6/DQS15
D5
D14
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ48 to DQ51
DQS7
DQ52 to DQ55
DM7/DQS16
D6
D15
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
RS
RS
DQ56 to DQ59
DQS8
DQ60 to DQ63
DM8/DQS17
D7
D16
DQS
DQ
/CS DM
DQS
DQ
/CS DM
RS
RS
CB0 to CB3
CB4 to CB7
D8
D17
R
S
/CS0
/RCS0 -> /CS: SDRAMs D0 to D17
R
* D0 to D17: 256M bits DDR SDRAM
U0: 2k bits EEPROM
RS: 22Ω
PLL: CDCV857
Register: SSTV16857
R
S
R
S
R
S
R
S
R
S
R
S
BA0 to BA1
A0 to A12
/RAS
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17
/RRAS -> /RAS: SDRAMs D0 to D17
E
G
I
S
T
E
R
/CAS
/RCAS -> /CAS: SDRAMs D0 to D17
CKE0
RCKE0A -> CKE: SDRAMs D0 to D17
Serial PD
/WE
/RWE -> /WE: SDRAMs D0 to D17
/RESET
SCL
SCL
SDA
SDA
PCK
/PCK
U0
VDDQ
VDD
D0 to D17
D0 to D17
D0 to D17
D0 to D17
A0
A1
A2
VREF
VSS
SA0 SA1 SA2
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
VDDID
open
CK0, /CK0
PLL*
Note: Wire per Clock loading table/Wiring diagrams.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
8
EBD51RC4AAFA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
SDRAM
stack
PLL
120Ω
OUT1
SDRAM
stack
120Ω
CK0
IN
240Ω
Register1
/CK0
(Typically two registers per DIMM)
OUT'N'
120Ω
C
Feedback
Register2
240Ω
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0 ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
9
EBD51RC4AAFA
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +3.6
–1.0 to +3.6
50
V
VDD, VDDQ
IOUT
PT
V
mA
W
°C
°C
18
Operating temperature
Storage temperature
Topr
0 to +70
–55 to +125
1
Tstg
Note: 1. DDR SDRAM component specification.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)
Parameter
Symbol
min.
Typ
2.5
0
max.
2.7
0
Unit
V
Notes
1, 2
Supply voltage
VDD, VDDQ 2.3
VSS
0
V
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
VREF
0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ
V
1
VTT
VREF – 0.04 VREF
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
1
VIH (DC)
VIL (DC)
VIN (DC)
VREF + 0.15
–0.3
—
—
—
V
1, 3
1, 4
5
V
Input signal voltage
–0.3
V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
—
VDDQ + 0.6
V
6
Notes: 1. All parameters are referred to VSS, when measured.
2. VDDQ must be lower than or equal to VDD.
3. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
4. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
5. VIN (DC) specifies the allowable dc execution of each differential input.
6. VID (DC) specifies the input differential voltage required for switching.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
10
EBD51RC4AAFA
DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit
mA
Test condition
Notes
1, 2, 5
-7A
-7B
2194
2096
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACTV-PRE) IDD0
CKE ≥ VIH, BL = 2,
Operating current
IDD1
-7A
-7B
3184
2996
CL = 3.5,
mA
1, 2, 5
(ACTV-READ-PRE)
tRC = tRC (min.)
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
718
656
1114
1016
844
746
1294
1196
4444
4256
4084
3896
4084
3986
448
440
Idle power down standby current IDD2P
mA
mA
mA
mA
mA
mA
mA
mA
mA
CKE ≤ VIL
4
Floating idle standby current
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
CKE ≥ VIH, /CS ≥ VIH
CKE ≤ VIL
4
Active power down standby
current
3
CKE ≥ VIH, /CS ≥ VIH,
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 3.5
CKE ≥ VIH, BL = 2,
CL = 3.5
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Active standby current
3
Operating current
(Burst read operation)
Operating current
(Burst write operation)
1, 2, 5, 6
1, 2, 5, 6
Auto refresh current
Input ≥ VDD – 0.2V
Input ≤ 0.2V.
Self refresh current
IDD6
Random read current
(4 banks interleaving)
-7A
-7B
6326
6146
IDD7
BL = 4
5, 6, 8
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. The IDD data on this table are measured with regard to tCK = min. in general.
8. 4 banks active. Only one bank is running at tRC = tRC (min.)
DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
Parameter
Symbol
ILI
min.
–10
max.
10
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDD ≥ VOUT ≥ VSS
VOUT = VTT + 0.84V
VOUT = VTT – 0.84V
ILO
–10
10
µA
IOH
IOL
–16.8
16.8
—
mA
mA
—
Preliminary Data Sheet E0335E10 (Ver. 1.0)
11
EBD51RC4AAFA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
10
Unit
pF
Notes
1, 3
Address, /RAS, /CAS, /WE,
/CS, CKE
Input capacitance
Input capacitance
CI2
CK, /CK
20
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
15
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-7A
-7B
Parameter
Symbol
tCK
min.
max
15
min.
max
15
Unit
ns
Notes
Clock cycle time
(CL = 2)
7.5
10
(CL = 2.5)
tCK
tCH
tCL
7.5
15
7.5
15
ns
CK high-level width
CK low-level width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min
(tCH, tCL)
min
(tCH, tCL)
CK half period
tHP
tAC
—
—
tCK
ns
DQ output access time from
CK, /CK
–0.75
0.75
–0.75
0.75
DQS output access time from CK, /CK tDQSCK
–0.75
—
0.75
0.5
—
–0.75
—
0.75
0.5
—
ns
ns
ns
DQS to DQ skew
tDQSQ
tQH
DQ/DQS output hold time from DQS
tHP – 0.75
tHP – 0.75
Data-out high-impedance time from CK,
/CK
tHZ
tLZ
–0.75
–0.75
0.75
0.75
–0.75
–0.75
0.75
0.75
ns
ns
1
1
Data-out low-impedance time from CK,
/CK
Read preamble
tRPRE
tRPST
tDS
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
tDH
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
ns
—
—
ns
3
2
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
tDSS
tDSH
tDQSH
tDQSL
tIS
0.2
0.2
0.35
0.35
0.9
0.9
15
—
0.2
0.2
0.35
0.35
0.9
0.9
15
—
tCK
tCK
tCK
tCK
ns
—
—
—
—
DQS input low pulse width
—
—
Address and control input setup time
Address and control input hold time
—
—
6
6
tIH
—
—
ns
Mode register set command cycle time tMRD
—
—
ns
Active to Precharge command period
tRAS
45
120000
45
120000
ns
Preliminary Data Sheet E0335E10 (Ver. 1.0)
12
EBD51RC4AAFA
-7A
-7B
Parameter
Symbol
tRC
min.
max
—
min.
max
—
Unit
ns
Notes
Active to Active/Auto refresh command
period
Auto refresh to Active/Auto refresh
command period
65
75
65
75
tRFC
—
—
ns
Active to Read/Write delay
Precharge to active command period
Active to active command period
Write recovery time
tRCD
tRP
20
20
15
15
—
—
—
—
20
20
15
15
—
—
—
—
ns
ns
ns
ns
tRRD
tWR
Auto precharge write recovery and
precharge time
Internal write to Read command delay tWTR
tDAL
35
—
—
35
—
—
ns
1
1
tCK
ns
Exit self refresh to non-read command tXSNR
75
200
75
200
Exit self refresh to read command
Exit power down to any non-read
command
tXSRD
tXPNR
tCK
1
1
tCK
Exit precharge power down to read
command
Average periodic refresh interval
tXPRD
tREF
1
1
tCK
µs
5
4
—
7.8
—
7.8
Notes: 1 tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These
parameters are not referenced to a specific voltage level, but specify when the device output is no longer
driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be
transitioning from High-Z to logic Low. If a previous write was in progress, DQS could be High, Low, or
transitioning from High to Low at this time, depending on tDQSS.
4. A maximum of eight auto refresh commands can be posted to any given DDR SDRAM device.
5. tXPRD should be 200 tCK in the condition of the unstable CK operation during the power down mode.
6. For command/address and CK and /CK slew rate ≥ 1.0V/ns.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
13
EBD51RC4AAFA
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs
and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs
and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred
to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK
and the /CK.
/S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored.
However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of
the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is
loaded via the A0 to the A9, the A11 at the cross point of the CK rising edge and the VREF level in a read or a write
command cycle. This column address becomes the starting address of a burst operation.
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write
command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low
when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High
when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is
disabled.
BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2
and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If
BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected.
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are
entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CK cycle (= ICKEPW) at least, that is, if CKE changes at the cross point of the CK
rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with
proper hold time tIH.
Pin Functions (2)
DQ, CB (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input).
VDD and VDDQ (power supply pins): 2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output
buffer.)
VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM).
VSS (power supply pin): Ground is connected.
/RESET (input pin): LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
Detailed Operation Part and Timing Waveforms
Refer to M2S56D20/30/40ATP datasheet. DM pins of component device fixed to VSS level on the module board.
DIMM /CAS latency = Device CL + 1 for registered type.
Preliminary Data Sheet E0335E10 (Ver. 1.0)
14
EBD51RC4AAFA
Physical Outline
Unit: mm
128.95
4.00 max
(DATUM -A-)
(64.48)
Component area
(Front)
1
92
B
A
1.27 ± 0.10
64.77
49.53
133.35 ± 0.15
2 – φ 2.50 ± 0.10
93
184
Component area
(Back)
3.00 min
R 2.00
Detail A
Detail B
1.27 typ
(DATUM -A-)
6.62
2.175
R 0.90
6.35
1.80 ± 0.10
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.
ECA-TS2-0050-01
Preliminary Data Sheet E0335E10 (Ver. 1.0)
15
EBD51RC4AAFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0335E10 (Ver. 1.0)
16
EBD51RC4AAFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0335E10 (Ver. 1.0)
17
相关型号：
©2020 ICPDF网 联系我们和版权申明