EBE10EE8ACWA-8G-E [ELPIDA]
1GB Unbuffered DDR2 SDRAM DIMM; 1GB无缓冲DDR2 SDRAM DIMM
| 型号： | EBE10EE8ACWA-8G-E |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 1GB Unbuffered DDR2 SDRAM DIMM |
| 文件： | 总30页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
1GB Unbuffered DDR2 SDRAM DIMM
EBE10EE8ACWA (128M words × 72 bits, 1 Rank)
Specifications
Features
• Density: 1GB
• Double-data-rate architecture; two data transfers per
clock cycle
• Organization
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
128M words × 72 bits, 1 rank
• Mounting 9 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• Package: 240-pin socket type dual in line memory
module (DIMM)
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
PCB height: 30.0mm
Lead pitch: 1.0mm
• Differential clock inputs (CK and /CK)
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Eight internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Interface: SSTL_18
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Precharge: auto precharge option for each burst
• /DQS can be disabled for single-ended Data Strobe
access
operation
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Document No. E1214E10 (Ver. 1.0)
Date Published December 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007
EBE10EE8ACWA
Ordering Information
Component
JEDEC speed bin
Mbps (max.) (CL-tRCD-tRP)
Data rate
Contact
pad
Part number
Package
Mounted devices
EBE10EE8ACWA-8E-E 800
EBE10EE8ACWA-8G-E
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
EDE1108ACBG-8E-E
EDE1108ACBG-8E-E
240-pin DIMM
(lead-free)
Gold
EDE1108ACBG-8E-E
EDE1108ACBG-6E-E
EBE10EE8ACWA-6E-E 667
DDR2-667 (5-5-5)
Pin Configurations
Front side
1 pin
64 pin65 pin
120 pin
121 pin
184 pin 185 pin
240 pin
Back side
Pin No.
1
Pin name
VREF
VSS
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Pin name
A4
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
Pin name
VSS
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
Pin name
VDD
A3
2
VDD
A2
DQ4
DQ5
VSS
3
DQ0
A1
4
DQ1
VDD
VSS
VSS
VDD
NC
VDD
CK0
/CK0
VDD
A0
5
VSS
DM0
NC
6
/DQS0
DQS0
VSS
7
VSS
8
DQ6
DQ7
VSS
9
DQ2
VDD
A10
VDD
BA1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ3
VSS
BA0
DQ12
DQ13
VSS
VDD
/RAS
/CS0
VDD
ODT0
A13
DQ8
VDD
/WE
DQ9
VSS
/CAS
VDD
NC
DM1
NC
/DQS1
DQS1
VSS
VSS
NC
CK1
VDD
VSS
DQ36
DQ37
VSS
DM4
NC
NC
VDD
VSS
DQ32
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
/CK1
VSS
NC
VSS
DQ14
DQ15
VSS
DQ10
DQ11
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
VSS
DQ38
DQ39
DM2
Data Sheet E1214E10 (Ver. 1.0)
2
EBE10EE8ACWA
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin name
/DQS2
DQS2
VSS
Pin No.
87
Pin name
DQ35
VSS
Pin No.
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pin name
NC
Pin No.
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin name
VSS
88
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
DQ44
DQ45
VSS
89
DQ40
DQ41
VSS
DQ18
DQ19
VSS
90
91
DM5
NC
92
/DQS5
DQS5
VSS
DQ24
DQ25
VSS
93
VSS
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
/DQS3
DQS3
VSS
96
97
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8
NC
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
SA2
/CK2
VSS
CB0
NC
CB1
VSS
DM6
NC
VSS
/DQS6
DQS6
VSS
/DQS8
DQS8
VSS
VSS
VSS
CB6
CB7
VSS
VDD
NC
DQ54
DQ55
VSS
DQ50
DQ51
VSS
CB2
CB3
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VDD
CKE0
VDD
BA2
VDD
NC
DM7
NC
/DQS7
DQS7
VSS
NC
VSS
NC
VDD
A12
DQ62
DQ63
VSS
VDD
A11
DQ58
DQ59
VSS
A9
A7
VDD
A8
VDDSPD
SA0
VDD
A5
SDA
SCL
A6
SA1
Data Sheet E1214E10 (Ver. 1.0)
3
EBE10EE8ACWA
Pin Description
Pin name
Function
Address input
Row address
Column address
A0 to A13
A0 to A13
A0 to A9
A10 (AP)
Auto precharge
BA0, BA1, BA2
Bank select address
Data input/output
DQ0 to DQ63
CB0 to CB7
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
/RAS
/CAS
/WE
/CS0
Chip select
CKE0
Clock enable
CK0 to CK2
Clock input
/CK0 to /CK2
Differential clock input
Input and output data strobe
Input mask
DQS0 to DQS8, /DQS0 to /DQS8
DM0 to DM8
SCL
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
ODT0
ODT control
NC
No connection
Data Sheet E1214E10 (Ver. 1.0)
4
EBE10EE8ACWA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
128 bytes
256 bytes
Total number of bytes in serial PD
device
2
3
4
5
6
7
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
08H
0EH
0AH
60H
48H
00H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
10
1
72
0
Module data width continuation
Voltage interface level of this
assembly
8
9
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
05H
25H
SSTL 1.8V
2.5ns*1
DDR SDRAM cycle time, CL = X
-8E (CL = 5)
-8G (CL = 6)
-6E (CL = 5)
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
25H
30H
2.5ns*1
3.0ns*1
SDRAM access from clock (tAC)
-8E, -8G
10
0
1
0
0
0
0
0
0
40H
0.4ns*1
-6E
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
45H
02H
82H
08H
08H
00H
0.45ns*1
ECC
7.8µs
× 8
11
12
13
14
15
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
× 8
0
SDRAM device attributes:
Burst length supported
16
17
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0CH
08H
4,8
8
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes: /CAS
18
latency
0
0
1
1
1
0
0
0
38H
3, 4, 5
-8E, -6E
-8G
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
70H
01H
02H
00H
4, 5, 6
19
20
21
DIMM Mechanical Characteristics
DIMM type information
SDRAM module attributes
4.00mm max.
Unbuffered
Normal
Weak Driver
50Ω ODT Support
22
23
SDRAM device attributes: General
0
0
0
0
0
0
1
1
03H
Minimum clock cycle time at
CL = X − 1
-8E, -6E (CL = 4)
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
1
3DH
30H
50H
45H
50H
3DH
3.75ns*1
3.0ns*1
0.5ns*1
0.45ns*1
5.0ns*1
3.75ns*1
-8G (CL = 5)
Maximum data access time (tAC)
from clock at CL = X − 1
-8E, -6E (CL = 4)
24
25
-8G (CL = 5)
Minimum clock cycle time at
CL = X − 2
-8E, -6E (CL = 3)
-8G (CL = 4)
Data Sheet E1214E10 (Ver. 1.0)
5
EBE10EE8ACWA
Byte No. Function described
Maximum data access time (tAC)
from clock at CL = X − 2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
26
0
1
1
0
0
0
0
0
60H
0.6ns*1
-8E, -6E (CL = 3)
-8G (CL = 4)
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
50H
32H
3CH
1EH
0.5ns*1
12.5ns
15ns
Minimum row precharge time (tRP)
-8E
27
-8G, -6E
Minimum row active to row active
delay (tRRD)
28
29
7.5ns
Minimum /RAS to /CAS delay (tRCD)
-8E
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
1
1
32H
3CH
2DH
01H
12.5ns
15ns
-8G, -6E
Minimum active to precharge time
(tRAS)
30
31
45ns
Module rank density
1G bytes
Address and command setup time
before clock (tIS)
-8E, -8G
32
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
17H
20H
25H
27H
05H
0.17ns*1
0.20ns*1
0.25ns*1
0.27ns*1
0.05ns*1
-6E
Address and command hold time
after clock (tIH)
-8E, -8G
33
-6E
Data input setup time before clock
(tDS)
-8E, -8G
34
35
-6E
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
10H
12H
0.10ns*1
0.12ns*1
Data input hold time after clock (tDH)
-8E, -8G
-6E
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
17H
3CH
0.17ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
1EH
1EH
00H
7.5ns*1
7.5ns*1
TBD
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe
characteristics
Extension of Byte 41 and 42
-8E
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
0
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
36H
06H
39H
3CH
7FH
80H
14H
18H
1EH
-8G, -6E
Active command period (tRC)
-8E
41
57.5ns*1
60ns*1
-8G, -6E
Auto refresh to active/
Auto refresh command cycle (tRFC)
42
43
44
127.5ns*1
8ns*1
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-8E, -8G
0.20ns*1
0.24ns*1
0.30ns*1
-6E
Data hold skew (tQHS)
-8E, -8G
45
46
-6E
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
22H
00H
0.34ns*1
PLL relock time
Undefined
Data Sheet E1214E10 (Ver. 1.0)
6
EBE10EE8ACWA
Byte No. Function described
47 to 61
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
00H
12H
62
63
SPD Revision
Rev. 1.2
Checksum for bytes 0 to 62
-8E
0
0
0
0
1
0
1
0
0AH
-8G
-6E
1
0
1
0
1
1
0
0
1
0
1
1
1
0
0
0
EEH
24H
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
0
1
1
1
1
1
1
1
7FH
66
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
Module part number
1
0
×
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
×
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
×
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
×
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
×
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
×
1
0
1
0
0
1
1
0
0
0
1
0
1
1
0
×
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
×
1
0
1
1
0
1
1
0
1
1
1
1
1
FEH
00H
××
Elpida Memory
67 to 71
72
(ASCII-8bit code)
73
45H
42H
45H
31H
30H
45H
45H
38H
41H
43H
57H
41H
2DH
E
B
E
1
74
75
76
77
0
78
E
E
8
79
80
81
A
C
W
A
—
82
83
84
85
Module part number
-8E, -8G
86
87
0
0
0
0
0
1
1
1
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
38H
36H
45H
8
6
E
-6E
Module part number
-8E, -6E
-8G
0
0
0
0
0
0
×
1
0
1
0
0
0
×
0
1
0
1
1
1
×
0
0
0
0
1
0
×
0
1
0
0
0
0
×
1
1
1
0
0
0
×
1
0
0
0
0
0
×
1
1
1
0
0
0
×
47H
2DH
45H
20H
30H
20H
××
G
88
89
90
91
92
93
Module part number
Module part number
Module part number
Revision code
—
E
(Space)
Initial
Revision code
(Space)
Manufacturing date
Year code (BCD)
Week code
(BCD)
94
Manufacturing date
×
×
×
×
×
×
×
×
××
95 to 98
Module serial number
99 to 127 Manufacture specific data
Note 1:
These specifications are defined based on component specification, not module.
Data Sheet E1214E10 (Ver. 1.0)
7
EBE10EE8ACWA
Block Diagram
/CS0
R
S1
R
S1
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
R
R
S1
S1
S1
R
R
S1
/CS DQS /DQS
/CS DQS /DQS
DM
DM
8
8
8
8
R
S1
8
8
8
R
D0
D4
S1
DQ0
to DQ7
DQ0
to DQ7
DQ0 to DQ7
DQ32 to DQ39
R
R
S1
R
S1
S1
S1
/DQS1
DQS1
/DQS5
DQS5
S1
R
R
R
S1
R
R
/CS DQS /DQS
/CS DQS /DQS
DM1
DM
DM5
DM
S1
S1
DQ0
to DQ7
DQ0
to DQ7
D1
DQ8 to DQ15
DQ40 to DQ47
D5
R
R
S1
R
S1
/DQS2
DQS2
/DQS6
DQS6
S1
R
S1
R
R
R
R
S1
/CS DQS /DQS
S1
/DQS
/CS DQS
DM2
DM
DM6
DM
S1
S1
DQ0
to DQ7
DQ0
to DQ7
D6
D2
DQ48 to DQ55
DQ16 to DQ23
R
R
S1
R
S1
/DQS3
DQS3
/DQS7
DQS7
S1
R
S1
R
/CS DQS /DQS
S1
R
R
/CS DQS /DQS
S1
DM
DM3
DM
DM7
8
S1
R
S1
D3
DQ0
to DQ7
DQ0
to DQ7
D7
DQ56 to DQ63
DQ24 to DQ31
R
S1
R
/DQS8
S2
S2
S2
S2
S2
BA0 to BA2
A0 to A13
/RAS
BA0 to BA2: SDRAMs (D0 to D8)
A0 to A13: SDRAMs (D0 to D8)
R
S1
R
R
R
R
DQS8
R
R
S1
/CS DQS /DQS
/RAS: SDRAMs (D0 to D8)
/CAS: SDRAMs (D0 to D8)
DM8
DM
8
S1
DQ0
to DQ7
D8
CB0 to CB7
/CAS
/WE
CKE0
ODT0
/WE: SDRAMs (D0 to D8)
CKE: SDRAMs (D0 to D8)
ODT:SDRAMs (D0 to D8)
Serial PD
SCL
SDA
SDA
SCL
SA0
SA1
SA2
VDDSPD
VREF
SPD
A0
A1
A2
U0
SDRAMs (D0 to D8)
WP
SDRAMs (D0 to D8)
VDD
VSS
SDRAMs (D0 to D8)
Notes :
1. DQ wiring maybe changed within a byte.
* D0 to D7 : 1G bits DDR2 SDRAM
U0 : 2k bits EEPROM
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be meintained as shown.
Rs1 : 22
Ω
Ω
3. Refer to the appropriate clock wiring topology
under the DIMM wiring details section of this document.
Rs2 : 10
Data Sheet E1214E10 (Ver. 1.0)
8
EBE10EE8ACWA
Logical Clock Net Structure
3DRAM loads
R = 200Ω
C1
C1
DRAM
DRAM
DIMM
connector
R = 200Ω
DRAM
C1
R = 200Ω
*C1: 1pF
Data Sheet E1214E10 (Ver. 1.0)
9
EBE10EE8ACWA
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Notes
1
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +2.3
–0.5 to +2.3
50
VDD
IOS
PD
V
mA
W
1
9
Operating case temperature
Storage temperature
TC
0 to +95
–55 to +100
°C
°C
1, 2
1
Tstg
Notes: 1. DDR2 SDRAM component specification.
2. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of
EMRS (2) bit A7 is required.
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TC = 0°C to +85°C) (DDR2 SDRAM Component Specification)
Parameter
Symbol
VDD, VDDQ
VSS
min.
typ.
1.8
0
max.
1.9
0
Unit
V
Notes
4
Supply voltage
1.7
0
V
VDDSPD
VREF
1.7
—
3.6
V
Input reference voltage
Termination voltage
DC input logic high
DC input low
0.49 × VDDQ
VREF − 0.04
VREF + 0.125
−0.3
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
3
VTT
VREF
VREF + 0.04
VDDQ + 0.3
VREF – 0.125
V
VIH (DC)
VIL (DC)
VIH (AC)
VIL (AC)
V
V
AC input logic high
AC input low
VREF + 0.200
V
VREF – 0.200
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ must be equal to VDD.
Data Sheet E1214E10 (Ver. 1.0)
10
EBE10EE8ACWA
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
Parameter
Pins
Specification
Unit
V
Command, Address,
CKE, ODT
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
0.5
0.5
V
Maximum overshoot area above VDD
DDR2-800
0.66
0.8
V-ns
V-ns
V-ns
DDR2-667
Maximum undershoot area below VSS
DDR2-800
0.66
DDR2-667
0.8
V-ns
V
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
Maximum undershoot area below VSS
Maximum peak amplitude allowed for overshoot
CK, /CK
0.5
0.5
V
0.23
0.23
0.5
V-ns
V-ns
V
DQ, DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS,
Maximum peak amplitude allowed for undershoot
0.5
V
RDQS, /RDQS,
DM, UDM, LDM
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
0.23
0.23
V-ns
V-ns
Maximum amplitude
Overshoot area
VDD, VDDQ
Volts (V)
VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Data Sheet E1214E10 (Ver. 1.0)
11
EBE10EE8ACWA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol Grade
max.
Unit
mA
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-PRE)
-8E, -8G
765
720
IDD0
IDD1
-6E
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(ACT-READ-PRE)
-8E, -8G
-6E
900
855
mA
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge power-down
standby current
IDD2P
IDD2Q
IDD2N
90
mA
mA
mA
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
-8E, -8G
-6E
315
270
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-8E, -8G
-6E
360
315
Idle standby current
all banks open;
Fast PDN Exit
tCK = tCK (IDD);
MRS(12) = 0
CKE is L;
IDD3P-F
IDD3P-S
315
180
mA
mA
Active power-down
standby current
Other control and address bus
inputs are STABLE;
Slow PDN Exit
MRS(12) = 1
Data bus inputs are FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-8E, -8G
-6E
810
720
Active standby current
IDD3N
IDD4R
mA
mA
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Operating current
-8E, -8G
-6E
1440
1260
(Burst read operating)
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
Operating current
-8E, -8G
-6E
1440
1260
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4W
mA
(Burst write operating)
Data Sheet E1214E10 (Ver. 1.0)
12
EBE10EE8ACWA
Parameter
Symbol Grade
max.
Unit
mA
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-8E, -8G
-6E
2610
2520
Auto-refresh current
IDD5
IDD6
Self Refresh Mode;
CK and /CK at 0V;
CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Self-refresh current
90
mA
mA
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Operating current
(Bank interleaving)
-8E, -8G
-6E
2610
2475
IDD7
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
Data Sheet E1214E10 (Ver. 1.0)
13
EBE10EE8ACWA
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2-800
DDR2-667
Parameter
5-5-5
5
6-6-6
6
5-5-5
5
Unit
tCK
ns
CL (IDD)
tRCD (IDD)
tRC (IDD)
12.5
57.5
7.5
15
15
60
60
ns
tRRD (IDD)
tFAW (IDD)
tCK (IDD)
7.5
35
7.5
37.5
3
ns
35
ns
2.5
2.5
45
ns
tRAS (min.)(IDD)
tRAS (max.)(IDD)
tRP (IDD)
45
45
ns
70000
12.5
127.5
70000
15
70000
15
ns
ns
tRFC (IDD)
127.5
127.5
ns
Data Sheet E1214E10 (Ver. 1.0)
14
EBE10EE8ACWA
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
ILI
Value
Unit
µA
Notes
Input leakage current
Output leakage current
2
5
VDD ≥ VIN ≥ VSS
VDDQ ≥ VOUT ≥ VSS
ILO
µA
Minimum required output pull-up under AC
test load
VOH
VOL
VTT + 0.603
V
V
5
5
Maximum required output pull-down under
AC test load
VTT − 0.603
Output timing measurement reference level VOTR
0.5 × VDDQ
+13.4
V
1
Output minimum sink DC current
Output minimum source DC current
IOL
mA
mA
3, 4, 5
2, 4, 5
IOH
−13.4
Notes: 1. The VDDQ of the device under test is referenced.
2. VDDQ = 1.7V; VOUT = 1.42V.
3. VDDQ = 1.7V; VOUT = 0.28V.
4. The DC value of VREF applied to the receiving device is expected to be set to VTT.
5. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit
V
Notes
1, 2
2
AC differential input voltage
AC differential cross point voltage
AC differential cross point voltage
VID (AC)
VIX (AC)
VOX (AC)
0.5
VDDQ + 0.6
0.5 × VDDQ − 0.175
0.5 × VDDQ − 0.125
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
V
3
Notes: 1. VID (AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true
input signal (such as CK, DQS, RDQS) and VCP is the complementary input signal (such as /CK, /DQS,
/RDQS). The minimum value is equal to VIH (AC) − VIL (AC).
2. The typical value of VIX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX (AC)
is expected to track variations in VDDQ. VIX (AC) indicates the voltage at which differential input signals
must cross.
3. The typical value of VOX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and
VOX (AC) is expected to track variations in VDDQ. VOX (AC) indicates the voltage at which differential
output signals must cross.
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
Differential Signal Levels*1, 2
Data Sheet E1214E10 (Ver. 1.0)
15
EBE10EE8ACWA
ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
∆VM
min.
60
typ.
75
max.
90
Unit
Ω
Note
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω
Deviation of VM with respect to VDDQ/2
1
1
1
1
120
40
150
50
180
60
Ω
Ω
−6
+6
%
Note: 1. Test condition for Rtt measurements.
Measurement Definition for Rtt (eff)
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I(VIL (AC)) respectively.
VIH (AC), and VDDQ values defined in SSTL_18.
VIH(AC)−VIL(AC)
Rtt(eff ) =
I(VIH(AC))−I(VIL(AC))
Measurement Definition for ∆VM
Measure voltage (VM) at test pin (midpoint) with no load.
2×VM
∆VM =
−1 ×100
VDDQ
OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
min.
12.6
0
typ.
18
max.
23.4
4
Unit
Ω
Notes
1, 5
Output impedance
Pull-up and pull-down mismatch
Output slew rate
Ω
1, 2
1.5
5
V/ns
3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and
voltage.
3. Slew rate measured from VIL(AC) to VIH(AC).
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate
as measured from AC to AC. This is guaranteed by design and characterization.
5. DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed
from default settings.
Data Sheet E1214E10 (Ver. 1.0)
16
EBE10EE8ACWA
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
CCK
Pins
min.
1.0
max.
2.0
Unit
pF
Notes
1
CLK input pin capacitance
CK, /CK
Input capacitance
-8E, -8G
/RAS, /CAS,
/WE, /CS,
CKE, ODT,
Address
CIN
1.0
1.0
1.75
2.0
pF
pF
1
1
-6E
DQ, DQS, /DQS, UDQS,
/UDQS,
LDQS, /LDQS, RDQS,
/RDQS, DM, UDM, LDM, CB
Input/output pin
capacitance
CI/O
2.5
3.5
pF
2
Notes: 1. Matching within 0.25pF.
2. Matching within 0.50pF.
Data Sheet E1214E10 (Ver. 1.0)
17
EBE10EE8ACWA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
Parameter
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
Symbol
tRCD
tRP
min.
12.5
12.5
57.5
max.
min.
15
max.
min.
15
max.
Unit Notes
Active to read or write command
delay
ns
ns
ns
Precharge command period
15
15
Active to active/auto-refresh
command time
tRC
60
60
DQ output access time from CK,
/CK
tAC
−400
+400
+350
0.52
0.52
−400
−350
0.48
0.48
+400
+350
0.52
0.52
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
ps
10
10
13
13
DQS output access time from CK,
/CK
tDQSCK −350
tCK
(avg)
CK high-level width
CK low-level width
tCH (avg) 0.48
tCK
(avg)
tCL(avg) 0.48
Min.
Min.
Min.
CK half period
tHP
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
ps
ps
6, 13
13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
2500
8000
3000
8000
(CL = 5)
(CL = 4)
(CL = 3)
tCK (avg) 2500
tCK (avg) 3750
tCK (avg) 5000
8000
8000
8000
3000
3750
5000
8000
8000
8000
3000
3750
5000
8000
8000
8000
ps
ps
ps
13
13
13
tDH
(base)
DQ and DM input hold time
DQ and DM input setup time
125
125
50
175
100
0.6
ps
ps
5
4
tDS
(base)
50
Control and Address input pulse
width for each input
tCK
(avg)
tIPW
tDIPW
tHZ
0.6
0.6
0.35
DQ and DM input pulse width for
each input
tCK
(avg)
0.35
0.35
Data-out high-impedance time from
CK,/CK
tAC max.
tAC max.
tAC max. ps
10
10
10
DQS, /DQS low-impedance time
from CK,/CK
tLZ
(DQS)
tAC min. tAC max. tAC min. tAC max. tAC min. tAC max. ps
DQ low-impedance time from
CK,/CK
2
2
2
tLZ (DQ)
tAC max.
tAC max.
tAC max. ps
× tAC min.
× tAC min
× tAC min
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
tQHS
tQH
200
300
200
300
240
340
ps
ps
ps
DQ hold skew factor
7
8
DQ/DQS output hold time from
DQS
tHP –
tQHS
tHP –
tQHS
tHP –
tQHS
DQS latching rising transitions to
associated clock edges
tCK
(avg)
tDQSS
tDQSH
tDQSL
−0.25
0.35
0.35
0.2
+0.25
−0.25
0.35
0.35
0.2
+0.25
−0.25
0.35
0.35
0.2
+0.25
tCK
(avg)
DQS input high pulse width
DQS input low pulse width
tCK
(avg)
tCK
(avg)
DQS falling edge to CK setup time tDSS
Data Sheet E1214E10 (Ver. 1.0)
18
EBE10EE8ACWA
-8E
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
Parameter
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
Symbol
tDSH
min.
0.2
max.
min.
0.2
max.
min.
0.2
max.
Unit Notes
DQS falling edge hold time from
CK
tCK
(avg)
Mode register set command cycle
time
tMRD
2
2
2
nCK
tCK
(avg)
Write postamble
Write preamble
tWPST
tWPRE
0.4
0.35
0.6
0.4
0.6
0.4
0.6
tCK
(avg)
0.35
250
175
0.35
275
200
Address and control input hold time tIH (base) 250
ps
5
4
Address and control input setup
tIS (base) 175
time
ps
tCK
(avg)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
1.1
0.9
0.4
1.1
0.9
0.4
1.1
11
12
tCK
(avg)
0.6
0.6
0.6
Active to precharge command
Active to auto-precharge delay
tRAS
tRAP
45
70000
45
70000
45
70000
ns
ns
tRCD min.
tRCD min.
tRCD min.
Active bank A to active bank B
command period
tRRD
7.5
7.5
7.5
ns
Four active window period
/CAS to /CAS command delay
Write recovery time
tFAW
tCCD
tWR
35
2
35
2
37.5
2
ns
nCK
ns
15
15
15
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
Auto precharge write recovery +
precharge time
tDAL
nCK 1, 9
Internal write to read command
delay
tWTR
tRTP
7.5
7.5
7.5
ns
Internal read to precharge
command delay
7.5
7.5
7.5
ns
Exit self-refresh to a non-read
command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
tRFC + 10
ns
Exit self-refresh to a read
command
200
2
200
2
200
2
nCK
nCK
Exit precharge power down to any
non-read command
Exit active power down to read
command
tXARD
2
2
2
nCK 3
Exit active power down to read
command
tXARDS 8 − AL
8 − AL
7 − AL
nCK 2, 3
(slow exit/low power mode)
CKE minimum pulse width (high
and low pulse width)
tCKE
3
0
0
3
0
0
3
0
0
nCK
ns
Output impedance test driver delay tOIT
MRS command to ODT update
delay
12
12
12
12
12
12
tMOD
ns
Auto-refresh to active/auto-refresh
command time
tRFC
127.5
127.5
127.5
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
tREFI
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
(+85°C < TC ≤ +95°C)
Minimum time clocks remains ON
after CKE asynchronously drops
low
tIS +
tIS +
tCK(avg)
+ tIH
tIS +
tCK(avg)
+ tIH
tDELAY tCK(avg)
ns
+ tIH
Data Sheet E1214E10 (Ver. 1.0)
19
EBE10EE8ACWA
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not
an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing
tQH.
The value to be used for tQH calculation is determined by the following equation;
tHP = min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock high time;
tCL(abs) is the minimum of the actual instantaneous clock low time;
7. tQHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the
input is transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are independent of each other, due to data pin skew, output pattern effects,
and p-channel to n-channel variation of the output drivers.
8. tQH = tHP – tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification
value under the max column.
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye
will be.}
Examples:
a. If the system provides tHP of 1315ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975ps
(min.)
b. If the system provides tHP of 1420ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080ps
(min.)
9. RU stands for round up. WR refers to the tWR parameter stored in the MRS.
10. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps and
tERR(6-10per) max. = +293ps, then tDQSCK min.(derated) = tDQSCK min. − tERR(6-10per) max. =
−400ps − 293ps = −693ps and tDQSCK max.(derated) = tDQSCK max. − tERR(6-10per) min. = 400ps +
272ps = +672ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ) min.(derated) = −900ps − 293ps =
−1193ps and tLZ(DQ) max.(derated)= 450ps + 272ps = +722ps.
11. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per) min. = −72ps and
tJIT(per) max. = +93ps, then tRPRE min.(derated) = tRPRE min. + tJIT(per) min. = 0.9 × tCK(avg) − 72ps
= +2178ps and tRPRE max.(derated) = tRPRE max. + tJIT(per) max. = 1.1 × tCK(avg) + 93ps = +2843ps.
Data Sheet E1214E10 (Ver. 1.0)
20
EBE10EE8ACWA
12. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty) min. = −72ps and
tJIT(duty) max. = +93ps, then tRPST min.(derated) = tRPST min. + tJIT(duty) min. = 0.4 × tCK(avg) −
72ps = +928ps and tRPST max.(derated) = tRPST max. + tJIT(duty) max. = 0.6 × tCK(avg) + 93ps =
+1592ps.
13. Refer to the Clock Jitter table.
Data Sheet E1214E10 (Ver. 1.0)
21
EBE10EE8ACWA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter
Symbol
tAOND
tAON
min.
max.
Unit
tCK
ps
Notes
1, 3
ODT turn-on delay
2
2
ODT turn-on
tAC (min)
tAC (max) + 700
ODT turn-on (power down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min) + 2000
2tCK + tAC(max) + 1000
ps
2.5
2.5
tCK
ps
5
ODT turn-off
tAC(min)
tAC(max) + 600
2, 4, 5
ODT turn-off (power down mode)
ODT to power down entry latency
ODT power down exit latency
tAOFPD
tANPD
tAXPD
tAC(min) + 2000
2.5tCK + tAC(max) + 1000
ps
3
8
3
8
tCK
tCK
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
2. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
3. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
4. When the device is operated with input clock jitter, this parameter needs to be derated by
{−tJIT(duty) max. − tERR(6-10per) max. } and { −tJIT(duty) min. − tERR(6-10per) min. } of the actual input
clock.(output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps,
tERR(6-10per) max. = +293ps, tJIT(duty) min. = −106ps and tJIT(duty) max. = +94ps, then
tAOF min.(derated) = tAOF min. + { −tJIT(duty) max. − tERR(6-10per) max. } = −450ps + { −94ps − 293ps}
= −837ps and tAOF max.(derated) = tAOF max. + { −tJIT(duty) min. − tERR(6-10per) min. } = 1050ps +
{ 106ps + 272ps} = +1428ps.
5. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 × nCK assumes a tCH(avg), average input
clock high pulse width of 0.5 relative to tCK(avg). tAOF min. and tAOF max. should each be derated by
the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF min. should be derated by
subtracting 0.02 × tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52,
the tAOF max. should be derated by adding 0.02 × tCK(avg) to it. Therefore, we have;
tAOF min.(derated) = tAC min. − [0.5 − Min.(0.5, tCH(avg) min.)] × tCK(avg)
tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH(avg) max.) − 0.5] × tCK(avg)
or
tAOF min.(derated) = Min.(tAC min., tAC min. − [0.5 − tCH(avg) min.] × tCK(avg))
tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH(avg) max. − 0.5] × tCK(avg))
where tCH(avg) min. and tCH(avg) max. are the minimum and maximum of tCH(avg) actually measured
at the DRAM input balls.
Data Sheet E1214E10 (Ver. 1.0)
22
EBE10EE8ACWA
AC Input Test Conditions (DDR2 SDRAM Component Specification)
Parameter
Symbol
Value
0.5 × VDDQ
1.0
Unit
V
Notes
1
Input reference voltage
VREF
Input signal maximum peak to peak swing
Input signal minimum slew rate
VSWING (max.)
SLEW
V
1
1.0
V/ns
2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL (AC) level applied to
the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH (AC) (min.) for
rising edges and the range from VREF to VIL (AC) (max.) for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL (AC) to VIH (AC) on the positive
transitions and VIH (AC) to VIL (AC) on the negative transitions.
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VSWING(max.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
∆TF
VREF
∆TR
−
VIL (AC)(max.)
VIH (AC) min.
−
VREF
Falling slew =
Rising slew =
∆TF
∆TR
AC Input Test Signal Wave forms
Measurement point
DQ
VTT
RT =25 Ω
Output Load
Data Sheet E1214E10 (Ver. 1.0)
23
EBE10EE8ACWA
Clock Jitter [DDR2-800, 667]
-8E, -8G
800
-6E
Frequency (Mbps)
Parameter
667
Symbol
min.
max.
8000
100
min.
3000
−125
max.
8000
125
Unit
ps
Notes
Average clock period
Clock period jitter
tCK (avg)
tJIT (per)
2500
−100
1
5
ps
Clock period jitter during
DLL locking period
tJIT
(per, lck)
−80
80
−100
100
250
200
ps
ps
ps
5
6
6
Cycle to cycle period jitter
tJIT (cc)
200
160
Cycle to cycle clock period jitter
during DLL locking period
tJIT (cc, lck)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
tERR (2per) −150
tERR (3per) −175
tERR (4per) −200
tERR (5per) −200
150
175
200
200
−175
−225
−250
−250
175
225
250
250
ps
ps
ps
ps
7
7
7
7
Cumulative error across
n=6,7,8,9,10 cycles
tERR
(6-10per)
−300
300
450
−350
−450
350
450
ps
ps
7
7
Cumulative error across
n=11, 12,…49,50 cycles
tERR
(11-50per)
−450
Average high pulse width
Average low pulse width
Duty cycle jitter
tCH (avg)
tCL (avg)
tJIT (duty)
0.48
0.48
−100
0.52
0.52
100
0.48
0.48
−125
0.52
0.52
125
tCK (avg)
tCK (avg)
ps
2
3
4
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window.
N
tCK(avg) =
tCKj
N
∑
j =1
N = 200
2. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
N
tCH(avg) =
tCHj (N ×tCK(avg))
∑
j =1
N = 200
3. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
N
tCL(avg) =
tCLj (N × tCK(avg))
∑
j =1
N = 200
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of
any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).
tJIT (duty) is not subject to production test.
tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where:
tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200}
tJIT (CL) = {tCLj − tCL (avg) where j = 1 to 200}
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).
tJIT (per) = Min./Max. of { tCKj − tCK (avg) where j = 1 to 200}
tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same
definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not
subject to production test.
Data Sheet E1214E10 (Ver. 1.0)
24
EBE10EE8ACWA
6. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles:
tJIT (cc) = Max. of |tCKj+1 − tCKj|
tJIT (cc) is defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same
definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not
subject to production test.
7. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
tERR (nper) is not subject to production test.
n
tERR(nper) =
tCKj − n×tCK(avg))
∑
j =1
2 ≤ n ≤ 50 for tERR (nper)
8. These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing hold at all times.
(minimum and maximum of spec values are to be used for calculations in the table below.)
Parameter
Symbol
min.
max.
Unit
Absolute clock period
tCK (abs) tCK (avg) min. + tJIT (per) min. tCK (avg) max. + tJIT (per) max. ps
Absolute clock high pulse
width
tCH (avg) min. × tCK (avg) min. tCH (avg) max. × tCK (avg) max.
tCH (abs)
tCL (abs)
ps
ps
+ tJIT (duty) min.
tCL (avg) min. × tCK (avg) min. tCL (avg) max. × tCK (avg) max.
+ tJIT (duty) min. + tJIT (duty) max.
+ tJIT (duty) max.
Absolute clock low pulse
width
Example: For DDR2-667, tCH(abs) min. = ( 0.48 × 3000 ps ) - 125ps = 1315ps
Data Sheet E1214E10 (Ver. 1.0)
25
EBE10EE8ACWA
Pin Functions
CK, /CK (input pin)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A13 (input pins)
Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address
becomes the starting address of a burst operation.
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0, BA1, BA2 (input pin)
BA0, BA1 and BA2 are bank select signals (BA). The memory array is divided into 8 banks: bank 0 to bank 7. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
BA2
L
Bank 0
Bank 1
H
L
L
L
Bank 2
H
H
L
L
Bank 3
H
L
L
Bank 4
H
H
H
H
Bank 5
H
L
L
Bank 6
H
H
Bank 7
H
Remark: H: VIH. L: VIL.
Data Sheet E1214E10 (Ver. 1.0)
26
EBE10EE8ACWA
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ and CB (input and output pins)
Data are input to and output from these pins.
DQS and /DQS (input and output pin)
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
DM (input pins)
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.
VDD (power supply pins)
1.8V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
1.8V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDE1108ACBG, EDE1116ACBG datasheet (E1173E).
Data Sheet E1214E10 (Ver. 1.0)
27
EBE10EE8ACWA
Physical Outline
Unit: mm
3.18 max
0.5 min
(DATUM -A-)
3.00
Component area
(Front)
1
120
B
A
1.27 ± 0.10
63.00
55.00
133.35
121
240
(Back)
FULL R
Detail A
Detail B
(DATUM -A-)
FULL R
1.00
4.00
2.50
5.00
1.50 ± 0.10
0.80 ± 0.05
ECA-TS2-0126-02
Data Sheet E1214E10 (Ver. 1.0)
28
EBE10EE8ACWA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E1214E10 (Ver. 1.0)
29
EBE10EE8ACWA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL2, H2S, NH3,
SO2, and NO .
x
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1214E10 (Ver. 1.0)
30
相关型号：
©2020 ICPDF网 联系我们和版权申明