EBE82FF4A1RR 概述
8GB Fully Buffered DIMM 8GB全缓冲DIMM
EBE82FF4A1RR 数据手册
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PDF下载PRELIMINARY DATA SHEET
8GB Fully Buffered DIMM
EBE82FF4A1RR
Specifications
Features
• Density: 8GB
• JEDEC standard Raw Card AA Design
• Organization
• Industry Standard Advanced Memory Buffer (AMB)
1024M words × 72 bits, 4 ranks
• High-speed differential point-to-point link interface at
1.5V (JEDEC spec)
• Mounting 36 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
• Various features/modes:
DDP: 2 pieces of 1Gb chips sealed in one package
• Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
PCB height: 30.35mm
Lead pitch: 1.00mm
Interface for a thermal sensor and status indicator
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
• Channel error detection and reporting
• Automatic DDR2 SDRAM bus and channel
calibration
• Power supply
• SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V +0.075V/ −0.045V
• Data rate: 800Mbps/667Mbps (max.)
Note: Warranty void if removed DIMM heat
spreader.
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Performance
FB-DIMM
DDR2 SDRAM
System clock
frequency
Peak channel
throughput
Speed grade
PC2-6400F
PC2-5300F
FB-DIMM link data rate
4.8Gbps
Speed Grade
DDR data rate
800Mbps
200MHz
167MHz
9.6GByte/s
8.0GByte/s
DDR2-800 (5-5-5)
DDR2-667 (5-5-5)
4.0Gbps
667Mbps
Document No. E1339E20 (Ver. 2.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
EBE82FF4A1RR
Ordering Information
DIMM speed
grade
Component JEDEC
speed bin (CL-tRCD-tRP)
Part number
Mounted devices*1
Mounted AMB*2
IDT Rev. L4
EBE82FF4A1RR-8E-E
EBE82FF4A1RR-6E-E
PC2-6400F
PC2-5300F
DDR2-800 (5-5-5)
DDR2-667 (5-5-5)
2G bits DDR2 SDRAM
Notes: 1. Please refer to 1Gb DDR2 datasheet (E0975E) for electrical characteristics.
2. Please refer to the following documents for detailed operation part and timing waveforms.
Advanced Memory Buffer (AMB) specification
FB-DIMM Architecture and Protocol specification
Part Number
Environment code
E: Lead Free
Elpida Memory
(RoHS compliant)
Type
B: Module
DRAM Speed Grade
8E: DDR2-800 (5-5-5)
6E: DDR2-667 (5-5-5)
Product Family
E: DDR2
Density / Rank
82: 8GB/4-rank
AMB Device Information
R: IDT, Rev.L4
Module Type
F: Fully Buffered
Module Outline
R: 240-pin DIMM (DDP)
Mono Density
F: 2Gbit
Die Rev. (Mono)
Power Supply, Interface
A: 1.8V, SSTL_1.8
Mono Organization
4: x4
Preliminary Data Sheet E1339E20 (Ver. 2.0)
2
EBE82FF4A1RR
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol
Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large
memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing,
refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for
handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other
DIMMs on the FB-DIMM channel.
The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface.
FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is
288 devices per channel and total memory capacity scales with DRAM bit density.
The AMB is the buffer that isolates the DRAMs from the channel.
Advanced Memory Buffer Functionality
The AMB will perform the following FB-DIMM channel functions.
• Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB
DIMM position.
• Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames.
• If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
• Detects errors on the channel and reports them to the host memory controller.
• Support the FB-DIMM configuration register set as defined in the register chapters.
• Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM.
• Provides a read buffer FIFO and a write buffer FIFO.
• Supports an SMBus protocol interface for access to the AMB configuration registers.
• Provides logic to support MemBIST and IBIST design for test functions.
• Provides a register interface for the thermal sensor and status indicator.
• Functions as a repeater to extend the maximum length of FB-DIMM links.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
3
EBE82FF4A1RR
Advanced Memory Buffer Block Diagram
Southbound
Data in
Southbound
10×2
Data out
10×2
Reference
clock
Data merge
PLL
RE-time
Re-synch
1×2
Demux
PISO
/RESET
Reset
control
10×12
10×12
Link init SM
and control
and CSRs
Init
patterns
Thermal
sensor
Mux
4
DRAM clock
4
IBIST-RX
LAI logic
DRAM Command
IBIST-TX
failover
DRAM clock
Command
decoder &
CRC check
24
DRAM
address and
Command
out
command copy1
Mux
Mux
24
DRAM
address and
command copy2
DRAM
interface
DDR state controller
and CSRs
Core
controller
and CSRs
A2 for the ECC DRAMs
A6 for the ECC DRAMs
Write data
FIFO
Data out
Data in
4
DRAM chip select
External MemBIST
DDR calibration
72+18×2
DRAM
data and strobes
Sync & idle
pattern
generator
Data CRC
generator and
Read FIFO
NB LAI Buffer
IBIST-TX
IBIST-RX
LAI
controller
Link init SM
and control
and CSRs
Mux
SMBus
failover
SMBus
14×6×2
14×12
controller
PISO
Demux
Re-synch
RE-time
Data merge
Northbound
Data Out
Northbound
14×2
14×2
Data In
Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
4
EBE82FF4A1RR
Interfaces
Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,
one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or
an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on an FB-DIMM.
Memory Interface
NB FBD
NB FBD
in Link
out Link
SB FBD
in Link
SB FBD
out Link
AMB
SMB
Block Diagram AMB Interfaces
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8
DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven
to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the
next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the
direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives
the data to the next DIMM until the host is reached.
Host
Nourthbound
Southbound
AMB
AMB
AMB
AMB
n/c
n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Preliminary Data Sheet E1339E20 (Ver. 2.0)
5
EBE82FF4A1RR
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces
The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential
point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data
from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards
this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or
status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs.
Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary
differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound
on 14 secondary differential pairs.
DDR2 Channel
The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports four
ranks of eight banks with 15 row/column request, 64 data, and eight check-bit signals. There are two copies of
address and command signals excluding chip select, to support DIMM routing and electrical requirements. Four
transfer bursts are driven on the data and check-bit lines at 800MHz. Propagation delays between read data/check-
bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using
write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides
four copies of the command clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each
DRAM nibble.
SMBus Slave interface
The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM
link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at
100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other
parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down.
The SMBus address straps located on the DIMM connector are used by the unique ID.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
6
EBE82FF4A1RR
Block Diagram
VSS
/CS1
/CS3
/CS0
/CS2
DQS0
/DQS0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DM /CS DQS /DQS
DQ0
4
4
4
4
4
4
4
4
4
DQ0
to DQ3
DQ0 to DQ3
D0
D36
D18
D54
to DQ3
to DQ3
to DQ3
DQS9
/DQS9
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
DQ4 to DQ7
D1
D37
D19
D55
to DQ3
to DQ3
to DQ3
to DQ3
DQS1
/DQS1
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
4
4
4
4
4
4
D2
D38
D20
D56
DQ8 to DQ11
to DQ3
to DQ3
to DQ3
to DQ3
DQS10
/DQS10
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM CS DQS /DQS
DQ0
4
DQ12 to DQ15
D3
D39
D21
D57
to DQ3
to DQ3
to DQ3
to DQ3
DQS2
/DQS2
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
DQ16 to DQ19
D4
D40
D22
D58
to DQ3
to DQ3
to DQ3
to DQ3
DQS11
/DQS11
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
D5
D41
D23
D59
DQ20 to DQ23
to DQ3
to DQ3
to DQ3
to DQ3
DQS3
/DQS3
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
4
4
4
4
D6
D42
D24
D60
DQ24 to DQ27
to DQ3
to DQ3
to DQ3
to DQ3
DQS12
/DQS12
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
DQ28 to DQ31
D7
D43
D25
D61
to DQ3
to DQ3
to DQ3
to DQ3
DQS8
/DQS8
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
4
CB0 to CB3
D8
D44
D26
D62
to DQ3
to DQ3
to DQ3
to DQ3
Block Diagram (1)
Preliminary Data Sheet E1339E20 (Ver. 2.0)
7
EBE82FF4A1RR
VSS
/CS1
/CS3
/CS0
/CS2
DQS4
/DQS4
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
4
4
4
4
4
4
4
4
4
DQ32 to DQ35
D9
D45
D27
D63
to DQ3
to DQ3
to DQ3
to DQ3
DQS13
/DQS13
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DQ36 to DQ39
D10
D46
D28
D64
to DQ3
to DQ3
to DQ3
to DQ3
DQS5
/DQS5
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DQ40 to DQ43
D11
D47
D29
D65
to DQ3
to DQ3
to DQ3
to DQ3
DQS14
/DQS14
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM CS DQS /DQS
DQ0
4
4
4
4
4
4
4
4
DQ44 to DQ47
D12
D48
D30
D66
to DQ3
to DQ3
to DQ3
to DQ3
DQS6
/DQS6
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DQ48 to DQ51
D13
D49
D31
D67
to DQ3
to DQ3
to DQ3
to DQ3
DQS15
/DQS15
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
DQ52 to DQ55
D14
D50
D32
D68
to DQ3
to DQ3
to DQ3
to DQ3
DQS7
/DQS7
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DQ56 to DQ59
D15
D51
D33
D69
to DQ3
to DQ3
to DQ3
to DQ3
DQS16
/DQS16
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DQ60 to DQ63
D16
D52
D34
D70
to DQ3
to DQ3
to DQ3
to DQ3
DQS17
/DQS17
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
DM /CS DQS /DQS
DQ0
CB4 to CB7
D17
D53
D35
D71
to DQ3
to DQ3
to DQ3
to DQ3
Serial PD
PN0 to PN13
/PN0 to /PN13
PS0 to PS9
SN0 to SN13
/SN0 to /SN13
SS0 to SS9
Terminators
AMB
VTT
SCL
SDA
SCL
SDA
U0
VCC
/PS0 to /PS9
/SS0 to /SS9
WP A0 A1 A2
SA0 SA1 SA2
SPD, AMB
VDDSPD
DQ0 to DQ63
CB0 to CB7
DQS0 to DQS17
/DQS0 to /DQS17
/CS0 -> /CS (D36 to D53)
/CS1 -> /CS (D54 to D71)
/CS2 -> /CS (D0 to D17)
/CS3 -> /CS (D18 to D35)
CKE0 -> CKE (D0 to D17,D36 to D53)
CKE1 -> CKE (D18 to D35,D54 to D71)
ODT -> ODT (D36 to D71)
BA0 to BA2 (all SDRAMs)
A0 to A13 (all SDRAMs)
ECCA2,ECCA6 -> NC
/RAS (all SDRAMs)
/CAS (all SDRAMs)
/WE (all SDRAMs)
A
M
B
D0 to D71, AMB
VDD
D0 to D71
VREF
VSS
SCL
SDA
SA1 to SA2
SA0
D0 to D71, SPD, AMB
* D0 to D71 : 1G bits DDR2 SDRAM
U0 : 256 bytes EEPROM
/RESET
Notes:
1. DQ wiring may be changed within a nibble.
SCK/ /SCK
2. There are two physical copies of each address/command/control excluding CS.
3. There are four physical copies of each clock.
CK/ /CK (all SDRAMs)
4. ECCA2 and ECCA6 does not use(NC).
5. ODT pin(D0-D35) is connected to VSS.
All address/command/control/clock
VTT
Block Diagram (2)
Preliminary Data Sheet E1339E20 (Ver. 2.0)
8
EBE82FF4A1RR
Pin Configurations
Front side
1 pin
68 pin69 pin
120 pin
240 pin
121 pin
188 pin 189 pin
Back side
Front side
Back side
No. Name No. Name No.
Name No.
Name
No.
Name No.
Name No.
Name No.
Name
NC
1
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VTT
VID1
36 VSS
37 PN5
38 /PN5
39 VSS
71
72
73
74
/PS0
VSS
PS1
/PS1
VSS
PS2
/PS2
VSS
PS3
/PS3
VSS
PS4
/PS4
VSS
VSS
NC
106 NC
107 VSS
121 VDD
122 VDD
123 VDD
124 VSS
125 VDD
126 VDD
127 VDD
128 VSS
129 VCC
130 VCC
131 VSS
132 VCC
133 VCC
134 VSS
135 VTT
136 VID0
156 VSS
157 SN5
158 /SN5
159 VSS
160 SN13
191 /SS0 226
2
192 VSS
193 SS1
227
228
VSS
SCK
/SCK
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VTT
3
108 VDD
109 VDD
110 VSS
111 VDD
112 VDD
113 VDD
114 VSS
115 VDD
116 VDD
117 VTT
118 SA2
119 SDA
120 SCL
4
194 /SS1 229
5
40 PN13 75
41 /PN13 76
195 VSS
230
231
6
161 /SN13 196 SS2
7
42 VSS
43 VSS
44 NC
45 NC
46 VSS
47 VSS
77
78
79
80
81
82
162 VSS
163 VSS
164 NC
197 /SS2 232
8
198 VSS
199 SS3
233
234
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
165 NC
200 /SS3 235
166 VSS
167 VSS
168 SN12
201 VSS
202 SS4
236
237
48 PN12 83
49 /PN12 84
203 /SS4 238
VDDSPD
SA0
169 /SN12 204 VSS
239
240
50 VSS
51 PN6
85
86
87
88
89
90
91
92
93
94
95
96
97
170 VSS
171 SN6
205 VSS
206 NC
SA1
/RESET 52 /PN6
NC
137 M_TEST 172 /SN6
207 NC
VSS
NC
53 VSS
54 PN7
55 /PN7
56 VSS
57 PN8
58 /PN8
59 VSS
60 PN9
61 /PN9
62 VSS
VSS
VSS
PS9
/PS9
VSS
PS5
/PS5
VSS
PS6
/PS6
VSS
PS7
138 VSS
139 NC
173 VSS
174 SN7
175 /SN7
176 VSS
177 SN8
178 /SN8
179 VSS
180 SN9
181 /SN9
182 VSS
183 SN10
208 VSS
209 VSS
210 SS9
211 /SS9
212 VSS
213 SS5
214 /SS5
215 VSS
216 SS6
217 /SS6
218 VSS
NC
140 NC
VSS
PN0
/PN0
VSS
PN1
/PN1
VSS
PN2
/PN2
VSS
PN3
/PN3
VSS
PN4
/PN4
141 VSS
142 SN0
143 /SN0
144 VSS
145 SN1
146 /SN1
147 VSS
148 SN2
149 /SN2
150 VSS
151 SN3
152 /SN3
153 VSS
154 SN4
155 /SN4
63 PN10 98
64 /PN10 99
184 /SN10 219 SS7
65 VSS
100 /PS7
185 VSS
186 SN11
220 /SS7
221 VSS
66 PN11 101 VSS
67 /PN11 102 PS8
187 /SN11 222 SS8
68 VSS
69 VSS
70 PS0
103 /PS8
104 VSS
105 NC
188 VSS
189 VSS
190 SS0
223 /SS8
224 VSS
225 NC
Preliminary Data Sheet E1339E20 (Ver. 2.0)
9
EBE82FF4A1RR
Pin Description
Pin name
Pin Type
Input
Function
SCK, /SCK
System clock input
PN0 to PN13, /PN0 to /PN13
Output
Input
Primary northbound data
Primary southbound data
Secondary northbound data
Secondary southbound data
Serial presence detect (SPD) clock input
SPD data and AMB SMBus address/data
SPD address inputs
PS0 to PS9, /PS0 to /PS9
SN0 to SN13, /SN0 to /SN13
Input
SS0 to SS9, /SS0 to /SS9
Output
Input
SCL
SDA
Input / Output
Input
SA0 to SA2*1
VID0 to VID1*2
/RESET
M_TEST*3
NC
Input
Voltage ID
Input
AMB reset signal
Input
VREF margin test input
No connection
VCC
Power supply
Power supply
Power supply
Power supply
AMB core power and AMB channel interface power (1.5V)
DRAM power and AMB DRAM I/O power (1.8V)
DRAM address, Command and clock termination voltage (VDD/2)
SPD power (3.3V)
VDD
VTT
VDDSPD
VSS
Ground
Notes: 1. They are also used to select the DIMM number in the AMB.
2. These pins must be unconnected.
3. Don’t connect in a system.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
10
EBE82FF4A1RR
Electrical Specifications
• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
VIN/VOUT
VCC
Value
Unit
Note
Voltage on any pin relative to VSS
AMB core power voltage relative to VSS
–0.3 to +1.75
–0.3 to +1.75
–0.5 to +2.30
–0.5 to +2.30
–55 to +100
V
V
DRAM interface power voltage relative to VSS VDD
V
Termination voltage relative to VSS
Storage temperature
VTT
Tstg
V
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Conditions
Parameter
Symbol
Value
0 to +95
110
Unit
°C
Note
1
SDRAM component case temperature
AMB component case temperature
TC_DRAM
TC_AMB
°C
Note: 1. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of
EMRS (2) bit A7 is required.
DC Operating Conditions
Parameter
Symbol
VCC
min.
1.455
1.7
typ.
1.50
1.8
max.
Unit
V
Note
AMB supply voltage
1.575
DDR2 SDRAM supply voltage VDD
1.9
V
Input termination voltage
EEPROM supply voltage
SPD input high voltage
SPD input low voltage
RESET input high voltage
RESET input low voltage
Leakage current (RESET)
Leakage current (link)
VTT
0.48 × VDD 0.50 × VDD
0.52 × VDD
V
VDDSPD
VIH (DC)
VIL (DC)
VIH (DC)
VIL (DC)
IL
3.0
2.1
—
3.3
—
—
—
—
—
—
3.6
V
VDDSPD
V
1
1
2
2
2
3
0.8
—
0.5
90
5
V
1.0
—
V
V
–90
–5
µA
µA
IL
Notes: 1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal /RESET.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface
specification.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
11
EBE82FF4A1RR
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
Symbol
min.
—
typ.
—
max.
4
Units
clks
Note
tEI
propagate
EI Assertion pass-thru timing
EI deassertion pass-thru timing
EI assertion duration
Resample pass-thru time
Resynch pass-thru time
Bit lock Interval
tEID
tEI
—
—
bit lock
—
clks
100
—
—
clks
1.075
2.075
—
—
ns
—
—
ns
tBitLock
—
119
154
frames
frames
Frame lock Interval
tFrameLock
—
—
Note: 1. The EI stands for ″Electrical Idle″.
Power Specification Parameter and Test Conditions
-8E
800
-6E
Frequency (Mbps)
Parameter
667
Symbol
Power Supply max.
max.
1.70
Unit
Conditions
Note
L0 state, idle (0 BW)
@1.5V
@1.8V
Total
1.90
3.01
7.85
2.80
2.99
9.24
3.60
5.27
14.84
2.80
A
Primary channel enabled,
Idle Current, single
or last DIMM
Idd_Idle_0
Secondary channel disabled
2.81
7.15
2.60
2.80
8.56
3.20
5.16
13.98
2.60
A
CKE high. Command and address lines stable.
DRAM clock active.
W
A
@1.5V
@1.8V
Total
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Idle Current, first
DIMM
Idd_Idle_1
A
W
A
@1.5V
@1.8V
Total
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
Active Power
Idd_Active_1
A
W
A
L0 state
@1.5V
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Active Power, data
pass through
@1.8V
Total
3.00
9.26
2.80
8.56
A
Idd_Active_2
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
W
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
@1.5V
@1.8V
Total
2.70
2.64
8.41
2.50
2.62
8.06
A
Idd_Training
(for AMB
spec. Not in
SPD)
Training
A
CKE high, Command and address lines stable.
DRAM clock active.
W
Preliminary Data Sheet E1339E20 (Ver. 2.0)
12
EBE82FF4A1RR
Reference Clock Input Specifications*1
Parameter
Symbol
min.
190
max.
Units
Notes
2, 3, 4
Reference clock frequency@ 4.8 Gb/s
(nominal 200MHz)
fRefclk-4.8
fRefclk-4.0
200.1
MHz
MHz
Reference clock frequency@ 4.0 Gb/s
(nominal 166.67MHz)
158.33
166.75
1.15
2, 3, 4
Single-ended maximum voltage
Single-ended minimum voltage
Differential voltage high
Differential voltage low
Absolute crossing point
VCross variation
Vmax
V
5, 7
5, 8
6
Vmin
−0.3
V
VRefclk-diff-ih
VRefclk-diff-il
VCross
150
mV
mV
mV
mV
mV
−150
550
140
225
6
250
0.6
5, 9, 10
5, 9, 11
12
VCross-delta
VSCK-cm-acp-p
AC common mode
ERRefclk-diff-Rise,
ERRefclk-diff-Fall
Rising and falling edge rates
4.0
20
V/ns
%
6, 13
6, 14
% Mismatch between rise and fall edge
rates
ERRefclk-Match
Duty cycle of reference clock
Ringback voltage threshold
Allowed time before ringback
Clock leakage current
TRefclk-Dutycycle
VRB-diff
40
60
%
6
−100
100
mV
ps
6, 15
6, 15
16, 17
17
TStable
500
−10
0.5
II_CK
10
µA
pF
Clock input capacitance
CI_CK
2.0
Difference between
RefClk and RefClk#
input capacitance
Clock input capacitance delta
Transport delay
CI_CK (∆)
−0.25
0.25
5
pF
ns
TD
18, 19
NSAMPLE
TREF-JITTER-RMS
1012
periods 20
Reference clock jitter (rms), filtered
3.0
30
ps
ps
21, 22
Reference clock jitter (peak-to-peak) due
to spectrum clocking effects
TREF-SSCp-p
Reference clock jitter difference between TREF-JITTER-
adjacent AMB DELTA
0.75
ps
23
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times
the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FB-
DIMM channel and so on.
3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency.
4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only
required for those data rates that are supported by the device under test.
5. Measurement taken from single-ended waveform.
6. Measurement taken from differential waveform.
7. Defined as the maximum instantaneous voltage including overshoot.
8. Defined as the minimum instantaneous voltage including undershoot.
9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+
equals the falling edge of REFCLK-.
10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing. Refers to all crossing points for this measurement.
11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the
maximum allowed variance in for any particular system.
12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock
frequency).
Preliminary Data Sheet E1339E20 (Ver. 2.0)
13
EBE82FF4A1RR
13. Measured from −150mV to + 150mV on the differential waveform. The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential 0V crossing.
14. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is
measured using a ± 75mV window centered on the median cross point where REFCLK+ rising meets
REFCLK- falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope uses
for the edge rate calculations. The rising edge rate of REFCLK+ should be compared to the falling edge
rate of REFCLK-. The maximum allowed difference should not exceed 20% of the slowest edge
15. Tstable is the time the differential clock must maintain a minimum ±150mV differential voltage after rising
/falling edges before it is allowed to droop back into the ±100mV differential range.
16.Measured with a single-ended input voltage of 1V.
17. Applies to RefClk and RefClk#.
18. This parameter is not a direct clock output parameter but it indirectly determines the clock output
parameter TREF-JITTER.
19. The net transport delay is the difference in time of flight between associated data and clock paths. The
data path is defined from the reference clock source, through the TX, to data arrival at the data sampling
point in the RX. The clock path is defined from the reference clock source to clock arrival at the same
sampling point. The path delays are caused by copper trace routes, on-chip routing, on-chip buffering,
etc. They include the time-of-flight of interpolators or other clock adjustment mechanisms. They do not
include the phase delays caused by finite PLL loop bandwidth because these delays are modeled by the
PLL transfer functions.
20. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that
the jitter will be measured over a smaller, yet statistically significant, sample size and the total jitter at
NSAMPLE samples extrapolated from an estimate of the sigma of the random jitter components.
21. Measured with SSC enabled on reference clock generator.
22. As “measured” after the phase jitter filter. This number is separate from the receiver jitter budget that is
defined by the TRX-Total-MIN parameters.
23. This maximum value is below the noise floor of some test equipment.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
14
EBE82FF4A1RR
Differential Transmitter Output Specifications*1
Parameter
Symbol
min.
max.
1300
Unit
mV
Comments
Differential peak-to-peak
output voltage for large
voltage swing
VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- |
Measured as note 2
VTX-DIFFp-p_L
900
Differential peak-to-peak
output voltage for regular
voltage swing
VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- |
VTX-DIFFp-p_R
VTX-DIFFp-p_S
800
520
mV
mV
Measured as note 2
Differential peak-to-peak
output voltage for small
voltage swing
VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- |
Measured as note 2
Defined as:
VTX-CM = DC (avg) of |VTX-D+
+ VTX-D-|/2
DC common code
output voltage for large
voltage swing
VTX-CM_L
375
280
mV
Measured as note 2
Defined as:
VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2
Measured as note 2. See also note 3
DC common code
output voltage for small
voltage swing
VTX-CM_S
135
mV
dB
dB
De-emphasized differential
output voltage ratio for
-3.5dB de-emphasis
VTX-DE-3.5-Ratio
VTX-DE-6.0-Ratio
2, 4, 5
2, 4, 5
−3.0
−5.0
−4.0
−7.0
De-emphasized differential
output voltage ratio for
-6dB de-emphasis
VTX-CM-AC =
AC peak-to-peak common
mode output voltage for large VTX-CM-ACp-p L
swing
Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+
+ VTX-D-|/2
90
80
70
mV
mV
mV
Measured as note 2. See also note 6
VTX-CM-AC =
AC peak-to-peak common
mode output voltage for
regular swing
Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+
+ VTX-D-|/2
VTX-CM-ACp-p R
Measured as note 2. See also note 6
VTX-CM-AC =
AC peak-to-peak common
mode output voltage for small VTX-CM-ACp-p S
swing
Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+
+ VTX-D-|/2
Measured as note 2. See also note 6
Maximum single-ended
voltage in EI condition,
DC + AC
VTX-IDLE-SE
50
20
mV
mV
mV
7, 8
7, 8, 9
8
Maximum single-ended
voltage in EI condition,
DC only
VTX-IDLE-SE-DC
VTX-IDLE-DIFFp-p
Maximum peak-to-peak
differential voltage in EI
condition
40
Single-ended voltage
(w.r.t.VSS) on D+/D-
VTX-SE
−75
750
mV
UI
2, 10
Minimum TX eye width
TTX-Eye-MIN
TTX-DJ-DD
TTX-PULSE
0.7
2, 11, 12
2, 11, 12, 13
14
Maximum TX deterministic
jitter
0.2
UI
Instantaneous pulse width
0.85
30
UI
Differential TX output rise/fall TTX-RISE,
time
Given by 20%-80% voltage levels.
Measured as note 2
90
20
ps
TTX-FALL
Mismatch between rise and
fall times
TTX-RF-MISMATCH
ps
Measured over 0.1GHz to 2.4GHz.
See also note 15
Differential return loss
RLTX-DIFF
RLTX-CM
8
6
dB
dB
Measured over 0.1GHz to 2.4GHz.
See also note 15
Common mode return loss
Preliminary Data Sheet E1339E20 (Ver. 2.0)
15
EBE82FF4A1RR
Parameter
Symbol
RTX
min.
41
max.
55
Unit
Comments
16
Transmitter termination
resistance
Ω
RTX-Match-DC =
2×|RTX-D+ − RTX-D-| / (RTX-D+
+ RTX-D-)
D+/D- TX resistance
difference
RTX-Match-DC
4
%
Bounds are applied separately to high
and low output voltage states
Lane-to-lane skew at TX
Lane-to-lane skew at TX
LTX-SKEW 1
LTX-SKEW 2
100 + 3UI ps
100 + 2UI ps
17, 19
18, 19
Maximum TX Drift
(resync mode)
TTX-DRIFT-RESYNC
240
ps
ps
20
Maximum TX Drift
(resample mode only)
TTX-DRIFT-
RESAMPLE
120
20
21
Bit Error Ratio
BER
10-12
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. Specified at the package pins into a timing and voltage compliance test load. Common-mode
measurements to be performed using a 101010 pattern.
3. The transmitter designer should not artificially elevate the common mode in order to meet this
specification.
4. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by
the VTX-DIFFp-p of the first bit after a transition.
5. De-emphasis shall be disabled in the calibration state.
6. Includes all sources of AC common mode noise.
7. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as
the Electrical Idle condition.
8. Specified at the package pins into a voltage compliance test load. Transmitters must meet both single-
ended and differential output EI specifications.
9. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset
between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between
adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered.
10. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2)
11. This number does not include the effects of SSC or reference clock jitter.
12. These timing specifications apply to resync mode only.
13. Defined as the dual-dirac deterministic jitter.
14. Pulse width measured at 0 V differential.
15. One of the components that contribute to the deterioration of the return loss is the ESD structure which
needs to be carefully designed.
16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not
exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin.
17. Lane to Lane skew at the Transmitter pins for an end component.
18. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane
skew at the Receiver pins of the incoming PORT).
19. This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship
after initialization.
20. Measured from the reference clock edge to the center of the output eye. This specification must be met
across specified voltage and temperature ranges for a single component. Drift rate of change is
significantly below the tracking capability of the receiver.
21. BER per differential lane.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
16
EBE82FF4A1RR
Differential Receiver Input Specifications*1
Parameter
Symbol
min.
170
max.
1300
Unit
mV
Comments
Differential peak-to-peak input
voltage
VRX-DIFFp-p = 2×|VRX-D+ -VRX-D-|
Measured as note 2
VRX-DIFFp-p
Maximum single-ended voltage
for EI condition (AC + DC)
VRX-IDLE-SE
65
mV
mV
mV
mV
mV
3, 4, 5, 6
3, 4, 5, 6, 7
4, 5, 6
5
Maximum single-ended voltage
for EI condition (DC only)
VRX-IDLE-SE-DC
VRX-IDLE-DIFFp-p
VRX-SE
35
Maximum peak-to-peak differential
voltage for EI condition
65
Single-ended voltage (w.r.t. VSS)
on D+/D-
−300
900
Single-pulse peak differential input
voltage
VRX-DIFF-PULSE
85
5, 8
Amplitude ratio between adjacent
symbols,
1100mV < VRX-DIFFp-p<= 1300mV
VRX-DIFF-ADJ
RATIO- HI
3.0
4.0
5, 9
5, 9
Amplitude ratio between adjacent
symbols,
VRX-DIFFp-p <= 1100mV
VRX-DIFF-ADJ
RATIO
Maximum RX inherent timing error TRX-TJ-MAX
0.4
0.3
UI
UI
5, 10, 11
Maximum RX inherent
TRX-DJ-DD
5, 10, 11, 12
deterministic timing error
Single-pulse width at zero-voltage
TRX-PW-ZC
0.55
0.2
50
UI
UI
ps
5, 8
crossing
Single-pulse width at minimum-
TRX-PW-ML
5, 8
level crossing
TRX-RISE,
Differential RX input rise/fall time
TRX-FALL
Given by 20%-80% voltage levels.
Defined as:
VRX-CM = DC (avg) of |VRX-D+
+ VRX-D-|/2
Measured as note 2.
See also note 13
Common mode of the input voltage VRX-CM
120
400
mV
mV
VRX-CM-AC =
Max |VRX-D+ + VRX-D-|/2 –
Min |VRX-D+ + VRX-D-|/2
Measured as note 2
AC peak-to-peak common mode of
VRX-CM-ACp-p
270
45
input voltage
Ratio of VRX-CM-ACp-p to
VRX-CM-EH-Ratio
%
14
minimum VRX-DIFFp-p
Measured over 0.1GHz to 2.4GHz.
See also note 15
Differential return loss
RLRX-DIFF
9
dB
Measured over 0.1GHz to 2.4GHz.
See also note 15
Common mode return loss
RX termination resistance
RLRX-CM
RRX
6
dB
41
55
4
Ω
16
RRX-Match-DC =
2×|RRX-D+ − RRX-D-| / (RRX-D+
+ RRX-D-)
D+/D- RX resistance difference
RRX-Match-DC
LRX-PCB-SKEW
%
Lane-to-lane PCB skew at the
receiver that must be tolerated.
See also note 17
Lane-to-lane PCB skew at Rx
Minimum RX Drift Tolerance
6
UI
TRX-DRIFT
FTRK
400
0.2
ps
18
Minimum data tracking 3dB
bandwidth
MHz
19
TEI-ENTRY -
DETECT
Electrical idle entry detect time
60
ns
ns
20
21
Electrical idle exit detect time
Bit Error Ratio
TEI-EXIT -DETECT
BER
30
10-12
Preliminary Data Sheet E1339E20 (Ver. 2.0)
17
EBE82FF4A1RR
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the
pad will be lower than at the pin.
3. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as
the Electrical Idle condition. Worst-case margins are determined by comparing EI levels with common
mode levels during normal operation for the case with transmitter using small voltage swing.
4. Multiple lanes need to detect the EI condition before the device can act upon the EI detection.
5. Specified at the package pins into a timing and voltage compliance test setup.
6. Receiver designers may implement either single-ended or differential EI detection. Receivers must meet
the specification that corresponds to the implemented detection circuit.
7. This specification, considered with VTX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset
between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between
adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered.
8. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must
comply with both the single-pulse mask and the cumulative eye mask.
9. The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference
in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and
subsequent symbols.
10. This number does not include the effects of SSC or reference clock jitter.
11. This number includes setup and hold of the RX sampling flop.
12. Defined as the dual-dirac deterministic timing error.
13. Allows for 15mV DC offset between transmit and receive devices.
14. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-to-
peak common mode specification. For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-to-
peak common mode is the lesser of (200mV × 0.45 = 90mV) and VRX-CM-ACp-p.
15. One of the components that contribute to the deterioration of the return loss is the ESD structure which
needs to be carefully designed.
16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not
exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin.
17. This number represents the lane-to-lane skew between TX and RX pins and does not include the
transmitter output skew from the component driving the signal to the receiver. This is one component of
the end-to-end channel skew in the AMB specification.
18. Measured from the reference clock edge to the center of the input eye. This specification must be met
across specified voltage and temperature ranges for a single component. Drift rate of change is
significantly below the tracking capability of the receiver.
19. This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2MHz
is 0.05UI.
20. The specified time includes the time required to forward the EI entry condition.
21. BER per differential lane.
Preliminary Data Sheet E1339E20 (Ver. 2.0)
18
EBE82FF4A1RR
Serial PD Matrix for FB-DIMM
Byte No. Function described
Byte value
116
Hex value
92H
0
1
2
3
4
5
6
7
8
9
10
Number of serial PD bytes written / SPD device size / CRC coverage
SPD revision
Revision 1.1
11H
Key byte / DRAM device type
Voltage levels of this assembly
SDRAM addressing
DDR2 SDRAM FB-DIMM 09H
VDD = 1.8V, VCC = 1.5V 12H
14-row, 11-column, 8-bank 49H
Module physical attributes
Module Type / Thickness
Module organization
8.2mm
24H
07H
20H
00H
01H
04H
FB-DIMM
4 ranks / 4bits
Fine timebase (FTB) dividend / divisor
Medium timebase dividend
Medium timebase divisor
1
4
SDRAM minimum cycle time (tCK (min.))
-8E
11
2.50ns
0AH
-6E
3.00ns
8ns
0CH
20H
33H
12
13
SDRAM maximum cycle time (tCK (max.))
SDRAM /CAS latencies supported
CL = 3, 4, 5
SDRAM minimum /CAS latencies time (tCAS)
-8E
14
12.5ns
32H
3CH
52H
-6E
15ns
SDRAM write recovery times supported
-8E
15
WR = 2 to 6
-6E
WR = 2 to 5
15ns
42H
3CH
72H
50H
16
17
18
SDRAM write recovery time (tWR)
SDRAM write latencies supported
SDRAM additive latencies supported
WL = 2 to 8
AL = 0 to 4
SDRAM minimum /RAS to /CAS delay (tRCD)
-8E
19
12.5ns
32H
-6E
15ns
3CH
1EH
20
21
SDRAM minimum row active to row active delay (tRRD)
7.5ns
SDRAM minimum row precharge time (tRP)
-8E
12.5ns
15ns
32H
-6E
3CH
00H
B4H
22
23
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time (tRAS)
45ns
SDRAM minimum auto-refresh to active /auto-refresh time (tRC)
-8E
24
57.5ns
E6H
-6E
60ns
F0H
FEH
01H
1EH
1EH
03H
07H
01H
25
26
27
28
29
30
31
SDRAM minimum refresh recovery time delay (tRFC), LSB
SDRAM minimum refresh recovery time delay (tRFC), MSB
SDRAM Internal write to read command delay (tWTR)
SDRAM Internal read to precharge command delay (tRTP)
SDRAM burst lengths supported
127.5ns
127.5ns
7.5ns
7.5ns
BL = 4, 8
ODT = 50, 75, 150Ω
Supported
SDRAM terminations supported
SDRAM drivers supported
SDRAM average refresh interval (tREFI) / double refresh mode bit /
high temperature self-refresh rate support indication
32
7.8µs Double/HT refresh C2H
Preliminary Data Sheet E1339E20 (Ver. 2.0)
19
EBE82FF4A1RR
Byte No. Function described
Byte value
Hex value
51H
××
33
Tcasemax (TC (max.)) delta / DT4R4W delta
95°C/ 0.40°C
3
34
Psi T-A SDRAM at still air
SDRAM DT0
*
3
*
35
××
3
*
36
SDRAM DT2Q
××
3
*
37
SDRAM DT2P
××
3
*
38
SDRAM DT3N
××
3
*
39
SDRAM DT4R / mode bit
SDRAM DT5B
××
3
*
40
××
3
*
41
SDRAM DT7
××
42 to 74
75
Reserved
00H
01H
00H
00H
00H
22H
00H
××
AMB QR control setting
FBD ODT CTRL ranks 0 and 1, RD and WRT
FBD ODT CTRL ranks 2 and 3, RD
FBD ODT definition for ranks 2 and 3
FBD ODT definition for ranks 0 and 1
Reserved
QR = Enable
76
77
78
Disable
79
150/150Ω
80
81 to 93
94 to 97
98
AMB personality bytes
Reserved
00H
××
AMB case temperature maximum (Tcase (max.))
Category byte
99
DDP/FDHS
12H
00H
××
100
Reserved
101 to 116 AMB personality bytes
117
118
119
120
121
Module ID: manufacturer’s JEDEC ID code
Elpida Memory
Elpida Memory
02H
FEH
××
Module ID: manufacturer’s JEDEC ID code
Module ID: manufacturing location
Module ID: manufacturing date
Year code (BCD)
Date code (BCD)
××
Module ID: manufacturing date
××
122 to 125 Module ID: module serial number
126 to 127 Cyclical redundancy code
128 to 145 Module part number
××
××
EBE82FF4A1RR
Initial
××
146
147
148
149
150
151
Module revision code
30H
20H
02H
FEH
××
Module revision code
(Space)
SDRAM manufacturer’s JEDEC ID code
SDRAM manufacturer’s JEDEC ID code
Informal AMB content revision tag (MSB)
Informal AMB content revision tag (LSB)
Elpida Memory
Elpida Memory
××
152 to 175 Manufacturer's specific data
176 to 255 Open for customer use
00H
00H
Remark IDD: DRAM current, ICC: AMB current
Notes: 1. Based on DDR2 SDRAM component specification.
2. Refer to JESD51-3 “Low effective thermal conductivity Test board for leaded surface mount packages”
under JESD51-2 standard.
3. DT parameter is derived as following: DTx = IDDx × VDD × Psi T-A, where IDDx definition is based on
JEDEC DDR2 SDRAM component specification and at VDD=1.9V, it is the datasheet (worst case) value,
and Psi T-A is the programmed value of Psi T-A (value in SPD Byte 33).
Preliminary Data Sheet E1339E20 (Ver. 2.0)
20
EBE82FF4A1RR
Physical Outline
Unit: mm
8.20 max.
Front side
Full DIMM heat spreader
5.20 max.
3.00 max.
74.675
D6
(DATUM -A-)
D3
D4
D1
D37
D15
D51
D12 D13
D48 D49
D10
D46
D39 D40
D42
AMB
D2
D5
D38 D41
D11 D14
D45 D47 D50
D16
D52
D0
D36
D9
D7
D43
1
120
1.27 ± 0.10
1.25
R0.75
B
A
67.00
51.00
5.175
133.35
Back side
120
121
240
D34
D70
D20
D56
D23
D59
D29 D32
D65 D68
D18
D54
D27
D63
D25
D61
D8
D44
D17
D53
D22
D58
D30
D66
D31
D67
D19
D55
D21
D57
D24
D60
D28
D64
D33
D69
D26
D62
D35
D71
FULL R
2.50
Detail A
Detail B
(DATUM -A-)
FULL R
1.00
2.50
0.40 min.
5.00
0.80 ± 0.05
1.50 ± 0.10
Tie bar keep out zone
ECA-TS2-0244-01
Preliminary Data Sheet E1339E20 (Ver. 2.0)
21
EBE82FF4A1RR
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E1339E20 (Ver. 2.0)
22
EBE82FF4A1RR
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL2, H2S, NH3,
SO2, and NO .
x
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1339E20 (Ver. 2.0)
23
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