EDE5108GBSA-5A-E_技术文档

PRELIMINARY DATA SHEET

512M bits DDR-II SDRAM

EDE5104GBSA (128M words × 4 bits)

EDE5108GBSA (64M words × 8 bits)

EDE5116GBSA (32M words × 16 bits)

Features

Description

The EDE5104GB is a 512M bits DDR-II SDRAM

• 1.8V power supply

organized as 33,554,432 words × 4 bits × 4 banks.

• Double-data-rate architecture: two data transfers per

clock cycle

The EDE5108GB is a 512M bits DDR-II SDRAM

organized as 16,777,216 words × 8 bits × 4 banks.

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

It packaged in 64-ball µBGA package.

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

The EDE5116GB is a 512M bits DDR-II SDRAM

organized as 8,388,608 words × 16 bits × 4 banks.

• Differential clock inputs (CK and /CK)

It is packaged in 84-ball µBGA package.

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• µBGA package is lead free solder (Sn-Ag-Cu)

Document No. E0249E30 (Ver. 3.0)

Date Published August 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2002

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Ordering Information

Mask

version

Organization

(words × bits)

Internal

Banks

Data rate

(Mbps)

Part number

/CAS latency Package

4, 5

3, 4, 5

EDE5104GBSA-5A-E

EDE5104GBSA-4A-E

533

400

B

128M × 4

64M × 8

4

64-ball µBGA

EDE5108GBSA-5A-E

EDE5108GBSA-4A-E

533

400

4, 5

3, 4, 5

EDE5116GBSA-5A-E

EDE5116GBSA-4A-E

533

400

4, 5

3, 4, 5

32M × 16

84-ball µBGA

Part Number

E D E 51 04 G B SA - 4A - E

Elpida Memory

Type

D: Monolithic Device

Lead Free

Product Code

E: DDR-II

Speed

Density / Bank

5A: 533Mbps

4A: 400Mbps

51: 512M /4 banks

Bit Organization

04: x4

08: x8

Package

SA: µBGA

16: x16

Die Rev.

Voltage, Interface

G: 1.8V, SSTL_18

Preliminary Data Sheet E0249E30 (Ver. 3.0)

2

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Pin Configurations

/xxx indicates active low signal.

64-ball µBGA

84-ball µBGA

(×8, ×4 organization)

(×16 organization)

1

2

3

7

8

9

1

2

3

7

8

9

A

B

C

D

E

A

B

C

D

E

NC

VDD

NC

VSS

VSSQ /UDQS VDDQ

DQ14 VSSQ UDM

VDDQ

DQ12 VSSQ DQ11

VDD NC VSS

UDQS VSSQ DQ15

VDDQ DQ8 VDDQ

DQ10 VSSQ DQ13

DQ9 VDDQ

NU/ /RDQS

(NC)*

VSSQ /LDQS VDDQ

VDD

VSS

VSSQ /DQS VDDQ

F

G

H

J

F

G

H

J

DQ6

(NC)*

DQ7

DQS VSSQ

(NC)*

DM/RDQS

VSSQ

DQ6 VSSQ LDM

VDDQ DQ1 VDDQ

DQ4 VSSQ DQ3

VDDL VREF VSS

LDQS VSSQ DQ7

VDDQ DQ0 VDDQ

DQ2 VSSQ DQ5

(DM)*

VDDQ

DQ1 VDDQ

VSSQ DQ3

VREF VSS

CKE /WE

VDDQ DQ0 VDDQ

DQ4

(NC)*

DQ5

(NC)*

DQ2 VSSQ

VSSDL CK

VDD

ODT

VDDL

VDD

ODT

K

L

K

L

/RAS

/CAS

A2

/CK

/CS

A0

/RAS

/CAS

A2

/CK

/CS

A0

CKE /WE

NC

BA0

A10

BA1

A1

NC

BA0

A10

BA1

A1

M

N

P

R

M

N

P

R

VDD

VSS

VDD

VSS

VDD

A3

A7

A5

A9

NC

A6

A11

NC

A4

A8

VSS

VDD

A3

A7

A5

A9

NC

A6

A11

NC

A4

A8

NC

A12

A13

A12

(Top view)

Note: ( )* marked pins are for ×4 organization.

Pin name

Function

Pin name

ODT

Function

A0 to A13

BA0, BA1

DQ0 to DQ15

Address inputs

Bank select

ODT control

VDD

Supply voltage for internal circuit

Ground for internal circuit

Data input/output

VSS

DQS, /DQS

UDQS, /UDQS

LDQS, /LDQS

Differential data strobe

VDDQ

Supply voltage for DQ circuit

RDQS, /RDQS

/CS

Differential data strobe for read

Chip select

VSSQ

VREF

VDDL

VSSDL

NC*¹

Ground for DQ circuit

Reference supply voltage

Supply voltage for DLL circuit

Ground for DLL circuit

No connection

/RAS, /CAS, /WE

CKE

Command input

Clock enable

CK, /CK

Differential Clock input

Write Data mask

DM, UDM, LDM

NU*²

Not usable

Notes: 1. Not internally connected with die.

2. Don’t use other than reserved functions.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

3

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electrical Specifications.................................................................................................................................5

Block Diagram .............................................................................................................................................10

Pin Function.................................................................................................................................................11

Command Operation ...................................................................................................................................13

Simplified State Diagram.............................................................................................................................20

Operation of DDR-II SDRAM.......................................................................................................................21

Package Drawing ........................................................................................................................................54

Recommended Soldering Conditions..........................................................................................................54

Preliminary Data Sheet E0249E30 (Ver. 3.0)

4

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Electrical Specifications

• All voltages are referenced to VSS (GND)

• Execute power-up and Initialization sequence before proper device operation is achieved.

Absolute Maximum Ratings

Parameter

Symbol

VDD

VDDQ

VIN

Rating

Unit

V

Note

Power supply voltage

Power supply voltage for output

Input voltage

–0.5 to +2.3

0 to +70

–55 to +150

1.0

1

V

Output voltage

VOUT

TA

V

Operating temperature (ambient)

Storage temperature

Power dissipation

°C

W

mA

TSTG

PD

Short circuit output current

IOUT

50

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (SSTL_18)

• There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

Parameter

Symbol

VDD

min.

Typ.

1.8

max.

1.9

Unit

V

Notes

Supply voltage

1.7

4

Supply voltage for output

Input reference voltage

Termination voltage

DC input logic high

DC input low

VDDQ

VREF

1.7

1.8

1.9

V

4

0.49 × VDDQ

VREF – 0.04

VREF + 0.125

–0.3

0.50 × VDDQ 0.51 × VDDQ

V

1, 2

3

VTT

VREF

VREF + 0.04

VDDQ + 0.3V

VREF – 0.125

V

VIH (dc)

VIL (dc)

VIH (ac)

VIL (ac)

V

AC input logic high

AC input low

VREF + 0.250

V

VREF – 0.250

V

Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected

to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed ±2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and

VDDL tied together.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

5

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

max.

Parameter

Symbol

IDD0

Grade

× 4, × 8

× 16

Unit

mA

Test condition

one bank; tRC = tRC (min.) ; tCK = tCK (min.) ; DQ,

DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock

cycle

Operating current

(ACT-PRE)

TBD

one bank; Burst = 4; tRC = tRC (min.) ;

CL = 4; tCK = tCK (min.) ; IOUT = 0mA;

address and control inputs changing once per clock

cycle

Operating current

(ACT-READ-PRE)

IDD1

TBD

mA

Precharge power-down

standby current

all banks idle; power-down mode; CKE = VIL (max.);

tCK = tCK (min.)

IDD2P

IDD2N

TBD

mA

/CS = VIH (min.); all banks idle; CKE = VIH (min.);

tCK = tCK (min.) ; address and control inputs

changing once per clock cycle

Idle standby current

one bank active; power-down mode; CKE = VIL

(max.);

tCK = tCK (min.)

Active power-down

standby current

IDD3P

TBD

mA

one bank; active;/CS = VIH (min.);

CKE = VIH (min.); tRC = tRAS max; tCK = tCK

(min.); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing

once per clock cycle

Active standby current IDD3N

one bank; Burst = 4; burst; address and control

inputs changing once per clock cycle; DQ and DQS

outputs changing twice per clock cycle; CL = 4; tCK

= tCK (min.) ; IOUT = 0mA

Operating current

IDD4R

TBD

mA

(Burst read operating)

one bank; Burst = 4; writes; continuous burst;

address and control inputs changing once per clock

cycle; DQ and DQS inputs changing twice per clock

cycle; CL = 4;

Operating current

IDD4W

(Burst write operating)

tCK = tCK (min.)

Auto-refresh current

Self-refresh current

IDD5

IDD6

TBD

mA

tRC = tRFC (min.)

Self Refresh Mode; CKE = 0.2V

Four bank interleaving READs (BL4) with auto

precharge, tRC = tRC (min.); Address and control

inputs change during Active, READ, or WRITE

commands.

Operating current

(Bank interleaving)

IDD7

TBD

mA

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

VOH

Unit

V

Notes

5

Minimum required output pull-up under AC

test load

VTT + 0.603

VTT – 0.603

Maximum required output pull-down under

AC test load

VOL

V

5

Output timing measurement reference level VOTR

0.5 × VDDQ

+13.4

V

1

Output minimum sink DC current

Output minimum source DC current

IOL

mA

3, 4, 5

2, 4, 5

IOH

–13.4

Note: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.7V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

5. After OCD calibration to 18Ω at TA = 25°C, VDD = VDDQ = 1.8V.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

6

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V)

Notes

1

Parameter

Symbol Pins

min.

1.5

Typ

2.0

max.

2.5

Unit

pF

CLK input pin capacitance

CCK

CK

/RAS, /CAS,

/WE, /CS,

Input pin capacitance

CIN

1.5

2.0

2.5

pF

1

CKE. ODT,

Address

DQ, DQS, /DQS,

UDQS, /UDQS,

LDQS, /LDQS,

/RDQS, /RDQS,

DM, UDM, LDM

Input/output pin capacitance

CI/O

3.0

3.5

4.0

pF

2

Notes: 1. Matching within 0.25pF.

2. Matching within 0.50pF.

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

-5A

-4A

Frequency (Mbps)

533

400

Parameter

Symbol

tAC

min.

–500

max.

+500

+450

0.55

min.

–600

–500

0.45

max.

+600

+500

0.55

Unit

ps

Notes

DQ output access time from CK, /CK

DQS output access time from CK, /CK tDQSCK –450

ps

CK high-level width

CK low-level width

tCH

tCL

0.45

tCK

min.

(tCL, tCH)

min.

(tCL, tCH)

CK half period

tHP

ps

Clock cycle time

tCK

tDH

tDS

3750

350

8000

5000

400

8000

ps

DQ and DM input hold time

DQ and DM input setup time

350

400

Control and Address input pulse width

for each input

tIPW

tDIPW

tHZ

0.6

tCK

ps

DQ and DM input pulse width for each

input

0.35

Data-out high-impedance time from

CK,/CK

tAC max.

Data-out low-impedance time from

CK,/CK

tLZ

tAC min.

ps

DQS-DQ skew for DQS and associated

DQ signals

tDQSQ

300

400

350

450

ps

DQ hold skew factor

tQHS

tQH

ps

DQ/DQS output hold time from DQS

tHP – tQHS

WL – 0.25

tHP – tQHS

WL – 0.25

Write command to first DQS latching

transition

tDQSS

WL + 0.25

tCK

DQS input high pulse width

tDQSH

tDQSL

tDSS

0.35

0.2

2

0.35

0.2

2

tCK

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

tDSH

Mode register set command cycle time tMRD

Write preamble setup time

Write postamble

tWPRES

0

tWPST

tWPRE

0.4

0.25

0.6

0.4

0.25

0.6

Write preamble

Preliminary Data Sheet E0249E30 (Ver. 3.0)

7

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

-5A

533

min.

500

0.9

-4A

400

min.

600

0.9

Frequency (Mbps)

Parameter

Symbol

tIH

max.

Unit

ps

Notes

Address and control input hold time

ddress and A control input setup time

Read preamble

tIS

ps

tRPRE

tRPST

tRAS

1.1

0.6

1.1

0.6

tCK

ns

Read postamble

0.4

Active to precharge command

45

Active to active/auto refresh command

time

tRC

60

65

ns

Active to read or write command delay tRCD

15

20

ns

Precharge command period

Active to auto-precharge delay

tRP

15

20

tRAP

tRCD min.

Active bank A to active bank B

command period

tRRD

7.5

10

ns

(EDE5104GB, EDE5108GB)

(EDE5116GB)

tRRD

tWR

10

15

10

15

ns

Write recovery time

Auto precharge write recovery +

precharge time

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

tDAL

tCK

1

Internal write to read command delay

Exit self refresh to any command

tWTR

tXSC

7.5

10

ns

200

tCK

Exit power down to any non-read

command

tXPNR

tXPRD

tXARD

2

tCK

Exit precharge power down to read

command

6 – AL

2

6 – AL

2

3

Exit active power down to read

command

Exit active power down to read

command

tXARDS 6 – AL

6 – AL

tCK

3

(slow exit/low power mode)

Output impedance test driver delay

tOIT

0

12

0

12

ns

µs

Auto refresh to active/auto refresh

command time

tRFC

tREFI

105

Average periodic refresh interval

7.8

Notes: 1. For each of the terms above, if not already an integer, round to the next highest integer.

2. AL: Additive Latency.

3. MRS A12 bit define which active power down exit timing to be applied.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

8

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

AC Electrical Characteristics and Operating Conditions

Parameter

Symbol

tAOND

tAON

min

max

Unit Notes

tCK

ODT turn-on delay

ODT turn-on

2

tAC(min)

tAC(min) + 2000

2.5

tAC(max) + 1000

2tCK + tAC(max) + 1000

2.5

ps

1

ODT turn-on (power - down mode)

ODT turn-off delay

ODT turn-off

tAONPD

tAOFD

tAOF

ps

tCK

ps

tAC(min)

tAC(min) + 2000

tAC(max) + 600

2

ODT turn-off (power - down mode)

tAOFPD

2.5tCK + tAC(max) + 1000

ns

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

Test Conditions

tCK

VDD

CLK

VREF

VSS

VSWING

VX

/CLK

tCL

tCH

VDD

VIH

VREF

VSS

VIL

∆t

SLEW = (VIH (ac) – VIL (ac))/∆t

Measurement point

DQ

VTT

RT =25 Ω

Preliminary Data Sheet E0249E30 (Ver. 3.0)

9

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Block Diagram

CK

/CK

CKE

Bank 3

Bank 2

Bank 1

A0 to A13, BA0, BA1

Row

address

buffer

and

Memory cell array

Bank 0

refresh

counter

Mode

register

Sense amp.

Column decoder

Column

address

buffer

and

/CS

/RAS

/CAS

/WE

burst

counter

Data control circuit

Latch circuit

DQS, /DQS

RDQS, /RDQS

CK, /CK

DLL

Input & Output buffer

ODT

DM

DQ

Preliminary Data Sheet E0249E30 (Ver. 3.0)

10

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Pin Function

CK, /CK (input pins)

CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of crossing).

/CS (input pin)

All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with

multiple banks. /CS is considered part of the command code.

/RAS, /CAS, /WE (input pins)

/RAS, /CAS and /WE (along with /CS) define the command being entered.

A0 to A13 (input pins)

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the respective bank.

[Address Pins Table]

Address (A0 to A13)

Notes

1

Part number

EDE5104GB

EDE5108GB

EDE5116GB

Row address

AX0 to AX13

AX0 to AX12

Column address

AY0 to AY9, AY11

AY0 to AY9

Notes: 1. A13 pin is NC for ×16 organization.

A10 (AP) (input pin)

A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low)

or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address

inputs also provide the op-code during mode register set commands.

BA0, BA1 (input pins)

BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also

determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

[Bank Select Signal Table]

BA0

L

BA1

L

Bank 0

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self

refresh.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

11

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

DM, UDM and LDM (input pins)

DM is an input mask signal for write data. In 32M × 16 products, UDM and LDM control upper byte (DQ8 to DQ15)

and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled High coincident with that input data during

a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches

the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by

EMRS.

DQ (input/output pins)

Bi-directional data bus.

DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins)

Output with read data, input with write data for source synchronous operation. In 32M × 16 products, UDQS, /UDQS

and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data,

centered in write data. Used to capture write data. /DQS can be disabled by EMRS.

RDQS, /RDQS (output pins)

Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins

exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS.

ODT (input pins)

ODT (On Die Termination control) is a registered High signal that enables termination resistance internal to the DDR

II SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for × 4, × 8

configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM

signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.

VDD, VSS, VDDQ, VSSQ (power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

VDDL and VSSDL (power supply)

VDDL and VSSDL are power supply pins for DLL circuits.

VREF (Power supply)

SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ

Preliminary Data Sheet E0249E30 (Ver. 3.0)

12

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Command Operation

Command Truth Table

The DDR-II SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Previous Current

BA1,

A13 to

A11

A0 to

A10 A9

Function

Symbol cycle

cycle

H

L

/CS /RAS /CAS /WE BA0

Notes

Mode register set

MRS

H

L

H

L

H

×

L

×

L

H

×

L

×

H

L

H

×

L

BA0 = 0 and MRS OP Code

BA0 = 1 and EMRS OP Code

1

Extended mode register set EMRS

L

1

Auto (CBR) refresh

Self refresh entry

Self refresh exit

REF

H

×

L

H

×

1

SELF

SELFX

PRE

×

1

H

×

1

Single bank precharge

Precharge all banks

Bank activate

H

L

BA

×

1, 2

1

PALL

ACT

L

H

L

BA

×

Row Address

Column L

Column H

Column L

Column H

1, 2

Write

WRIT

WRITA

READ

READA

NOP

Column 1, 2, 3

Write with auto precharge

Read

L

H

×

Read with auto precharge

No operation

×

1

Device deselect

DESL

PDEN

PDEX

×

1

Power down mode entry

Power down mode exit

L

×

1, 4, 5

H

×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. All DDR-II commands are defined by states of /CS, /RAS, /CAS, /WE, and CKE at the rising edge of the

clock.

2. Bank Select (BA0, BA1), determine which bank is to be operated upon.

3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in

Burst Read command [READ] or ″Writes interrupted by a Write″ in Burst Write command [WRIT].

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is

therefore limited by the refresh requirements of the device. One clock delay is required for mode entry and

exit.

5. The state of ODT does not affect the states described in this table. The ODT function is not available

during Self Refresh.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

13

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

CKE Truth Table

CKE

Command

Current

Cycle

BA1,BA0,

/CS /RAS /CAS /WE A13 to A0 Notes

Current state

Self refresh

Function

INVALID

H

L

×

1

2

Exit self refresh with device

deselect

H

Exit self refresh with no

operation

L

H

L

H

×

2

Illegal

L

H

L

H

L

×

H

Command

Address

Maintain self refresh

INVALID

×

Power down

×

1

2

Power down mode exit

H

Command

except NOP

ILLEGAL

L

H

L

Address

2

Maintain power down mode

L

×

All banks idle Device deselect

Refer to the current state truth

H

3

H

L

H

L

×

Command

Address

table

Power down

×

Register command begin power

down next cycle

L

Command

Address

3

4

Entry self refresh

L

H

×

Refer to operations in the

current state truth table

Any state other

than listed

above

H

×

Power down entry

ILLEGAL

H

L

×

5

×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The

minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit.

3. The inputs (BA1, BA0, A13 to A0) depend on the command that is issued. See the Command Truth Table

for more information.

4. The Auto Refresh, Self Refresh mode, and the Mode Register Set modes can only be entered from the all

banks idle state.

5. Must be a legal command as defined in the Command Truth Table.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

14

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current state

/CS /RAS /CAS /WE Address

Command Operation

Notes

Idle

H

L

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

H

L

×

H

L

H

L

×

DESL

NOP

Nop or Power down

H

L

×

Nop or Power down

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

Row activating

Precharge

L

BA, A10 (AP)

A10 (AP)

PRE

L

PALL

REF

Precharge all banks

Auto refresh

Self refresh

L

H

L

×

2

L

×

SELF

MRS

L

BA, MRS-OPCODE

Mode register accessing

Extended mode register accessing

Nop

L

BA, EMRS-OPCODE EMRS

Bank(s) active

×

DESL

NOP

H

L

H

L

×

Nop

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

Begin Read

Begin Write

L

Begin Write

H

L

ILLEGAL

1

L

BA, A10 (AP)

A10 (AP)

PRE

Precharge

L

PALL

REF

Precharge all banks

ILLEGAL

L

H

L

×

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

ILLEGAL

L

BA, EMRS-OPCODE EMRS

ILLEGAL

Read

×

DESL

NOP

Continue burst to end -> Row active

Burst interrupt

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1, 4

1

L

ILLEGAL

1

H

L

ILLEGAL

1

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

1

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

ILLEGAL

L

BA, EMRS-OPCODE EMRS

ILLEGAL

Preliminary Data Sheet E0249E30 (Ver. 3.0)

15

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Current state

Write

/CS /RAS /CAS /WE Address

Command

DESL

Operation

Note

Continue burst to end

-> Write recovering

H

L

×

Continue burst to end

-> Write recovering

H

NOP

L

H

L

H

L

H

L

×

H

L

H

L

H

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

1

Burst interrupt

ILLEGAL

1, 4

1

L

H

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

1

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

ILLEGAL

L

BA, MRS-OPCODE MRS

BA, EMRS-OPCODE EMRS

ILLEGAL

L

ILLEGAL

Read with

×

H

L

×

DESL

NOP

Continue burst to end -> Precharging

ILLEGAL

auto precharge

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

ILLEGAL

L

BA, MRS-OPCODE MRS

BA, EMRS-OPCODE EMRS

ILLEGAL

L

ILLEGAL

Write with auto

Precharge

Continue burst to end

->Write recovering with auto precharge

H

L

×

DESL

NOP

Continue burst to end

->Write recovering with auto precharge

H

L

H

L

H

L

H

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

L

H

L

BA, A10 (AP)

A10 (AP)

PRE

L

PALL

REF

L

H

L

×

L

×

SELF

L

BA, MRS-OPCODE MRS

BA, EMRS-OPCODE EMRS

L

Preliminary Data Sheet E0249E30 (Ver. 3.0)

16

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Current state

Precharging

/CS /RAS /CAS /WE Address

Command

DESL

NOP

Operation

Note

H

L

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

H

L

×

H

L

H

L

×

Nop -> Enter idle after tRP

H

L

×

Nop -> Enter idle after tRP

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

Nop -> Enter idle after tRP

L

PALL

REF

Nop -> Enter idle after tRP

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Row activating

×

Nop -> Enter bank active after tRCD

H

L

H

L

×

Nop -> Enter bank active after tRCD

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Write recovering

×

Nop -> Enter bank active after tWR

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

New write

L

New write

H

L

ILLEGAL

1

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Preliminary Data Sheet E0249E30 (Ver. 3.0)

17

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Current state

/CS /RAS /CAS /WE Address

Command

DESL

Operation

Note

Write recovering

with

H

×

Nop -> Enter bank active after tWR

auto precharge

L

H

L

H

L

H

L

H

L

×

H

L

H

L

H

L

×

NOP

Nop -> Enter bank active after tWR

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Refresh

×

Nop -> Enter idle after tRFC

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Mode register

accessing

H

×

DESL

Nop -> Enter idle after tMRD

L

H

L

H

L

H

L

H

L

×

NOP

Nop -> Enter idle after tMRD

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Preliminary Data Sheet E0249E30 (Ver. 3.0)

18

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Current state

/CS

H

L

/RAS /CAS /WE Address

Command

DESL

NOP

Operation

Note

Extended Mode

register accessing

×

H

L

×

H

L

H

L

×

Nop -> Enter idle after tMRD

ILLEGAL

H

L

×

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

L

ILLEGAL

L

ILLEGAL

L

ILLEGAL

L

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. This command may be issued for other banks, depending on the state of the banks.

2. All banks must be in "IDLE".

3. All AC timing specs must be met.

4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

19

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Simplified State Diagram

CKEL

SELFX

INITALIZATION

AUTO REFRESH

tRFC

SELF REFRESH

CKEL

MRS

PDEN

MRS

EMRS

PRECHARGE

POWER

IDLE

CKEH

tMRD

DOWN

ACTIVATING

tRCD

RL + BL/2 + tRTP

READA

WL + BL/2 + tWR

WRITA

tRP

PRECHARGE

WRIT

PRE

READ

WRITE

READ

CKEL

PDEN

CKEH

ACTIVE

POWER

DOWN

BANK ACTIVE

Automatic sequence

Command sequence

Simplified State Diagram

Preliminary Data Sheet E0249E30 (Ver. 3.0)

20

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Operation of DDR-II SDRAM

Read and write accesses to the DDR-II SDRAM are burst oriented; accesses start at a selected location and

continue for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of

an Active command, which is then followed by a Read or Write command. The address bits registered coincident

with the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A13

select the row). The address bits registered coincident with the Read or Write command are used to select the

starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior

to normal operation, the DDR-II SDRAM must be initialized. The following sections provide detailed information

covering device initialization; register definition, command descriptions and device operation.

Power On and Initialization

DDR-II SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to

VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause

permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally

coincident with VTT. By attempting to maintain CKE Low, the DQ and DQS outputs are in the High-Z state during

power-up. After all power supply, reference voltages, and the clocks are stable, the DDR-II SDRAM requires a 200µs

delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be

brought high. Issuing the NOP command during tRFC period, a Precharge ALL command must be applied. Next a

mode register set command must be issued for the extended mode register, to enable the DLL. Then a mode

register set command must be issued for the mode register, to reset the DLL and to program the operating

parameters. 200 clock cycles are required between the DLL reset and any read command. Precharge ALL command

should be applied, placing the device in the “all banks idle” state.

Once in the idle state, two Auto Refresh cycles must be performed. Additionally, a mode register set command for

the mode register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL)

must be performed. Finally, OCD impedance adjustment should be performed. At least, ERMS OCD Default

command must be issued. Following these cycles, the DDR-II SDRAM is ready for normal operation. Failure to

follow these steps may lead to unpredictable start-up modes.

Power-Up and Initialization Sequence

The following sequence is required for Power-up and Initialization.

1. Apply power and attempt to maintain CKE and ODT at a low state (all other inputs may be undefined.)

Apply VDD before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and VREF.

2. Start clock and maintain stable condition for a minimum of 200µs.

3. The minimum of 200µs after stable power and clock(CK, /CK), apply NOP and take CKE High.

4. Wait tRFC then issue precharge commands for all banks of the device.

5. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide Low to A0, High to BA0 and

Low to all of the rest address pins, A1 to A11 and BA1)

6. Issue a mode register set command for DLL reset. The additional 200 cycles of clock input is required to

lock the DLL. (To issue DLL reset command, provide High to A8 and Low to BA0)

7. Issue precharge commands for all banks of the device.

8. Issue 2 or more auto-refresh commands.

9. Issue a mode register set command with low to A8 to initialize device operation.

10.Carry out OCD impedance adjustment (Follow “OCD Flow Chart” in the chapter of Off-Chip Driver (OCD)

Impedance Adjustment). At least, EMRS OCD Default Command (A9=A8=A7=1) must be issued. Whenever

issue extended mode register set command for OCD, keep previous setting of A0 to A6, A0 to A13 and BA1

CK

/CK

CKE

Command

Any

command

REF

MRS

EMRS

PALL

tRFC

PALL

EMRS

MRS

REF

NOP

tRP

tRFC

tMRD

Follow OCD

Flowchart

tOIT

tRP

tMRD

DLL reset

DLL enable

OCD drive(1)

OCD calibration mode

exit

200 cycles (min)

Power up and Initialization Sequence

Preliminary Data Sheet E0249E30 (Ver. 3.0)

21

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Programming the Mode Register

For application flexibility, burst type, /CAS latency, DLL reset function are user defined variables and must be

programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive /CAS latency,

and variable data-output impedance adjustment are also user defined variables and must be programmed with an

Extended Mode Register Set (EMRS) command. Re-executing the MRS and EMRS Commands can alter contents

of the MRS and EMRS. Even though the user chooses to modify only a subset of the MRS or EMRS variables, all

variables must be redefined when the MRS or EMRS commands are issued.

After initial power up, the both MRS and EMRS Commands must be issued before read or write cycles may begin.

All four banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set

Command can be issued. Either MRS or EMRS Commands are activated by the low signals of /CS, /RAS, /CAS and

/WE at the positive edge of the clock. When the bank address 0 (BA0) is low, the DDR-II SDRAM enables the MRS

command. When the bank address 0 (BA0) is high, the DDR-II SDRAM enables the EMRS command. The address

input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new

command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and Reset DLL do

not affect array contents, which means reinitialization including those can be executed any time after power-up

without affecting array contents.

DDR-II SDRAM Mode Register Set [MRS]

The mode register stores the data for controlling the various operating modes of DDR-II SDRAM. It controls /CAS

latency, burst sequence, test mode, DLL reset and various vendor specific options to make DDR-II SDRAM useful

for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE

and BA0, while controlling the state of address pins A0 to A13. The DDR-II SDRAM should be in all bank precharge

with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is

required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharge

state. The mode register is divided into various fields depending on functionality. Burst address sequence type is

defined by A3, and, /CAS latency is defined by A4 to A6. The DDR-II doesn’t support half clock latency mode. A7 is

used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. A9 to A11 are used

for define Write Recovery time in clocks using for Auto Precharge. Users are required to set the appropriate values

according to tWR spec and operating frequency of the systems.

A12 is used for Active Power Down exit timing selection. If Slow exit is set, DLL is turned off during Active Power

Down, then Asynchronous ODT timings and tXARDS timing for exit should be used. Refer to the table for specific

codes.

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address field

0*

0

0* 0*

WR

DLL TM /CAS latency BT

Burst length

Mode register

Burst length

A8

0

DLL reset

No

A7

Mode

Normal

Test

A3

Burst type

A2

0

A1

1

A0

0

BL

4

0

1

0

1

Sequential

Interleave

1

Yes

0

1

8

BA1

0

MRS mode

MRS

BA0

0

WR for Auto Precharge

A11 A10 A9

/CAS latency

0

EMRS(1)

1

WR

A6

0

A5

0

A4

0

Latency

Reserved

1

EMRS(2): Reserved

EMRS(3): Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

2

1

0

1

Reserved

3

0

1

0

Reserved

4

0

1

3

A12 Active power down exit timing

Reserved

1

0

4

0

1

Fast exit (use tXARD timing)

Slow exit (use tXARDS timing)

1

0

1

5

1

0

Reserved

1

*BA1, A12 and A13 are reserved for future use and must be programmed to 0 when setting the mode register.

Mode Register Set (MRS)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

22

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

DDR-II SDRAM Extended Mode Register Set [EMRS]

The extended mode register stores the data for enabling or disabling the DLL, output driver strength and additive

latency. The default value of the extended mode register is not defined, therefore the extended mode register must

be written after power-up for proper operation. The extended mode register is written by asserting low on /CS, /RAS,

/CAS, /WE and High on BA0, while controlling the states of address pins A0 to A13. The DDR-II SDRAM should be

in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set

command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode

register contents can be changed using the same command and clock cycle requirements during normal operation

as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength data-output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is

used for /DQS enable and A11 is used for RDQS enable. A12 is used for Qoff (output buffers disable).

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self

refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address field

0*¹

1

0*¹

/DQS OCD program ODT Additive latency ODT D.I.C DLL

Extended mode register

Qoff

RDQS

A10 /DQS enable

0

1

Enable

Disable

A11 RDQS enable

A0

0

DLL enable

Enable

0

1

Disable

Enable

1

Disable

ODT

A6

A2

BA0

0

(nominal Rtt)

BA1

MRS mode

MRS

0

1

0

1

0

1

0

1

ODT Disabled

75

Additive latency

1

EMRS(1)

A5

0

A4

0

A3

0

Latency

0

EMRS(2): Reserved

EMRS(3): Reserved

150

0

1

Reserved

0

1

Driver impedance adjustment*²

0

1

0

2

Operation

A9

0

A8

0

A7

0

1

3

OCD calibration mode exit

Drive(1)

1

0

4

0

1

0

1

Reserved

0

1

0

Drive(0)

1

0

1

0

Adjust mode

1

OCD calibration Default

Driver strength control

Output Driver

Impedance Control

Normal

Driver

Qoff

A12

0

A1

0

Size

100%

60%

Output buffers enabled

Output buffers disabled

1

Weak

*1: BA1 and A13 are reserved for future use, and must be programmed to 0 when setting the extended mode register.

*2: Refer to the chapter "Off-chip Driver (OCD) impedance Adjustment" for detailed information

Extended Mode Register Set (EMRS)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

23

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

[Pin Function Matrix for RDQS, /RDQS, /DQS]

RDQS enable

(A11)

/DQS enable

(A10)

DM/ RDQS

/RDQS

/DQS

0(disable)

1(enable)

0(enable)

1(disable)

0(enable)

1(disable)

DM

High - Z

/RDQS

High - Z

/DQS

DM

High - Z

/DQS

RDQS

High - Z

Off-Chip Driver (OCD) Impedance Adjustment

DDR-II SDRAM supports driver calibration feature and the “OCD Flow Chart ” is an example of sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be

carefully controlled depending on system environment.

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

EMRS: Drive(0)

DQ & DQS High ; /DQS Low

DQ & DQS Low ; /DQS High

ALL OK

Test

Need calibration

EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

OCD Flow Chart

Preliminary Data Sheet E0249E30 (Ver. 3.0)

24

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Extended Mode Register Set for OCD Impedance Adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out

by DDR-II SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive(1) mode, all

DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive(0) mode, all DQ, DQS

(and RDQS) signals are driven low and all /DQS signals are driven high.

In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver

characteristics follow approximate nominal V/I curve for 18Ω output drivers, but are not guaranteed. If tighter control

is required, which is controlled within 18Ω ± 3Ω driver impedance range, OCD must be used.

[OCD Mode Set Program]

A9

0

A8

0

A7

0

Operation

OCD calibration mode exit

Drive (1) DQ, DQS, (RDQS) High and /DQS Low

Drive (0) DQ, DQS, (RDQS) Low and /DQS High

Adjust mode

0

1

0

1

0

1

0

1

OCD calibration default

OCD Impedance Adjustment

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst

code to DDR-II SDRAM as in table X. For this operation, burst length has to be set to BL = 4 via MRS command

before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in table X means

all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR-II

SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR-II SDRAM will be adjusted to the

same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further

increment or decrement code has no effect. The default setting may be any step within the 16 step range.

[OCD Adjustment Program]

4bits burst data inputs to all DQs

Operation

DT0

0

DT1

0

DT2

0

DT3

0

Pull-up driver strength

NOP

Pull-down driver strength

NOP

0

1

Increase by 1 step

Decrease by 1 step

NOP

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

1

0

NOP

0

1

0

1

Increase by 1 step

Decrease by 1 step

Increase by 1 step

Decrease by 1 step

Reserved

0

1

0

1

0

1

0

1

0

Other combinations

For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the following

timing diagram. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS

addressing mode (ie.sequentialorinterleave).

Preliminary Data Sheet E0249E30 (Ver. 3.0)

25

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the “Output

Impedance Control Register Set Cycle”. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not

affected by MRS addressing mode (i.e. sequential or interleave).

/CK

CK

Command

EMRS

NOP

EMRS

NOP

WL

tWR

DQS, /DQS

tDS tDH

DT0

DQ_in

DT1

DT2

DT3

OCD adjust mode

OCD calibration mode exit

Output Impedance Control Register Set Cycle

Drive Mode

Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR-II SDRAM Driver impedance before

OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all

output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance

Measurement/Verify Cycle”.

/CK

CK

Command

EMRS

NOP

EMRS

High-Z

DQS, /DQS

DQs High for drive (1)

DQs Low for drive (0)

DQ

tOIT

Enter drivemode

OCD Calibration mode exit

Output Impedance Measurement/Verify Cycle

Preliminary Data Sheet E0249E30 (Ver. 3.0)

26

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

ODT(On Die Termination)

On Die Termination (ODT), is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS,

/DQS, RDQS, /RDQS, and DM signal for × 4 × 8 configurations via the ODT control pin. For × 16 configuration ODT

is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal via the ODT control pin. The ODT

feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to

independently turn on/off termination resistance for any or all DRAM devices.

The ODT function is turned off and not supported in self refresh mode.

VDDQ

sw1

sw2

Rval1

Rval2

DRAM

input

buffer

Input

Rval1

Rval2

sw1

sw2

VSSQ

Switch sw1 or sw2 is enabled by ODT pin.

Selection between sw1 or sw2 is determined by Rtt (nomial) in EMRS

Termination included on all DQs, DM, DQS, /DQS, RDQS and /RDQS pins.

Target Rtt ( ) = (Rval1) / 2 or (Rval2) / 2

Functional Representation of ODT

Preliminary Data Sheet E0249E30 (Ver. 3.0)

27

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

DC Electrical Characteristics and Operating Conditions

Parameter

Symbol

Rtt1(eff)

Rtt2(eff)

Rtt(mis)

min

60

Typ

75

max

90

Unit

Ω

Notes

Rtt effective impedance value for EMRS (A6, A2) = 0,1 ; 75 Ω

Rtt effective impedance value for EMRS (A6, A2) = 1,0 ; 150 Ω

Rtt mismatch tolerance between any pull-up and pull-down pair

1

120

−3.75

150

180

+3.75

Ω

%

Test Condition For Rtt Measurements ^*1

Measurement Definition for Rtt(eff)

Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC))

respectively.

VIH(AC) − VIL(AC)

Rtt(eff) =

I(VIH(AC)) − I(VIL(AC))

Measurement Definition for Rtt(mis)

Measure voltage (Vm) at test pin (midpoint) with no load.

2 × Vm

VDDQ

× 100%

Rtt(mis) =

− 1

Notes: 1. VIH(AC), and VDDQ values defined in SSTL_18.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

28

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

/CK

CK

CKE

ODT

tIS

tAOFD

tAOND

Internal

Term Res.

Rtt

tAON min.

tAOF min.

tAON max.

tAOF max.

ODT Timing for Active and Standby Mode

T0

T1

T2

T3

T4

T5

T6

/CK

CK

CKE

ODT

tIS

tAOFPD max.

tAOFPD min.

Internal

Term Res.

Rtt

tAONPD min.

tAONPD max.

ODT Timing for Power down Mode

Preliminary Data Sheet E0249E30 (Ver. 3.0)

29

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

ODT Control of Reads

At a minimum, ODT must be latched High by CK at (Read Latency – 3tCK) after the READ command and remain

High until (Read Latency + BL/2 – 2tCK) after the READ command (where Read Latency = AL + CL). The controller

is also required to activate it´s own termination with a turn on time the same as the DRAM and keeping it on until

valid data is no longer on the system bus.

T0

T1

T2

T3

T4

T5

T6

/CK

CK

Controller

Term Res.

Rtt (Controller)

Command

(to slot1)

READ

NOP

ODT

(to slot2)

at DRAM in slot1

READ

NOP

Command

DQS

RL

out0 out1 out2 out3

DQ

at DRAM in slot2

ODT

tAOFD

tAOND

DRAM

Term Res.

Rtt (DRAM)

Read Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency = 3tCK ; tAOND = 2tCK ; tAOFD = 2.5tCK)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

30

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

/CK

CK

Controller

Term Res.

Rtt (Controller)

Command

(to slot1)

READ

NOP

ODT

(to slot2)

at DRAM in slot1

READ

NOP

Command

DQS

RL

out0 out1 out2 out3

DQ

at DRAM in slot2

ODT

tAOFD

tAOND

DRAM

Term Res.

Rtt (DRAM)

Read Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency = 4tCK ; tAOND = 2tCK ; tAOFD = 2.5tCK)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

31

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

At a minimum, ODT must be latched High by CK at (Write Latency – 3 tCK) after the WRIT command and remain

high until (Write Latency + BL/2 – 2tCK) after the WRIT command(Where Write Latency = Read Latency – 1tCK).

During writes, no ODT is required at the controller.

T0

T1

T2

T3

T4

T5

T6

/CK

CK

Controller

Term Res.

Command

(to slot1)

WRIT

NOP

ODT

(to slot2)

at DRAM in slot1

Command

WRIT

NOP

DQS

RL

in0

in1

in2

in3

DQ

at DRAM in slot2

ODT

tAOFD

tAOND

DRAM

Term Res.

Rtt (DRAM)

Write Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency = 3tCK ; tAOND = 2tCK ; tAOFD = 2.5tCK)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

32

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

/CK

CK

Controller

Term Res.

Command

(to slot1)

WRIT

NOP

ODT

(to slot2)

at DRAM in slot1

Command

WRIT

NOP

DQS

RL

in0

in1

in2

in3

DQ

at DRAM in slot2

ODT

tAOFD

tAOND

DRAM

Term Res.

Rtt (DRAM)

Write Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency = 4tCK ; tAOND = 2tCK ; tAOFD = 2.5tCK)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

33

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Bank Activate Command [ACT]

The bank activate command is issued by holding /CAS and /WE High with /CS and /RAS Low at the rising edge of

the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through

A13 is used to determine which row to activate in the selected bank. The Bank activate command must be applied

before any read or write operation can be executed. Immediately after the bank active command, the DDR-II

SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank

that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to

delay when the R/W command is internally issued to the device. The additive latency value must be chosen to

assure tRCD (min.) is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been

activated it must be precharged before another bank activate command can be applied to the same bank. The bank

active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between

successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC),

which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the

different bank is determined by (tRRD).

T0

T1

T2

T3

Tn

Tn+1

Tn+2

PRE

Tn+3

/CK

CK

Posted

READ

Posted

READ

Command

ACT

PRE

ACT

tRCD(min.)

Address

ROW: 0

COL: 0

ROW: 1

tCCD

COL: 1

ROW: 0

Bank0 Read begins

Additive latency (AL)

tRCD =1

tRRD

tRAS

tRP

tRC

Bank0

Active

Bank1

Active

Bank0

Precharge

Bank1

Precharge Active

Bank0

Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

34

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS High,

/CS and /CAS Low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access

cycle is a read operation (/WE high) or a write operation (/WE low).

The DDR-II SDRAM provides a fast column access operation. A single read or write Command will initiate a serial

read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific

segments of the page length. For example, the 32M bits × 4 I/O × 4 Banks chip has a page length of 2048 bits

(defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary

segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the

column address supplied to the device during the read or write Command (CA0 to CA9, CA11). The second, third

and fourth access will also occur within this group segment, however, the burst order is a function of the starting

address, and the burst sequence.

A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is

defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Posted /CAS

Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR-II

SDRAM. In this operation, the DDR-II SDRAM allows a /CAS read or write command to be issued immediately after

the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is

held for the time of the additive latency (AL) before it is issued inside the device. The Read Latency (RL) is

controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before

the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined

as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency

(RL=AL+CL).

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

/CK

CK

Command

DQS, /DQS

DQ

READ

NOP

ACT

WRIT

WL = RL n–1 = 4

AL = 2

CL = 3

> tRCD

=

RL = AL + CL = 5

out0 out1 out2 out3

in0 in1 in2 in3

> tRAC

=

Read followed by a write to the same bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

/CK

CK

AL = 0

READ

NOP

WRIT

NOP

Command

DQS, /DQS

DQ

ACT

CL = 3

WL = RL n–1 = 2

> tRCD

=

RL = AL + CL = 3

out0 out1 out2 out3

in0 in1 in2 in3

> tRAC

=

Read followed by a write to the same bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

Preliminary Data Sheet E0249E30 (Ver. 3.0)

35

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. DDR-II SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave

address ordering is supported, however, sequential address ordering is nibble based for ease of implementation.

The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS,

which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported.

Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or Write by Write at

the boundary of Burst 4. Therefore the burst stop command is not supported on DDR-II SDRAM devices.

[Burst Length and Sequence]

Burst length

Starting address (A2, A1, A0) Sequential addressing (decimal)

Interleave addressing (decimal)

0, 1, 2, 3

000

001

010

011

000

001

010

011

100

101

110

111

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

4

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

Note: Page length is a function of I/O organization and column addressing

32M bits × 4 organization (CA0 to CA9, CA11); Page Length = 2048 bits

16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits

8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits

Preliminary Data Sheet E0249E30 (Ver. 3.0)

36

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Burst Read Command [READ]

The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start

of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency

(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.

The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out

appears on the DQ pin in phase with the DQS signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set

(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set

(EMRS).

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

READ

NOP

Command

<tDQSCK

=

DQS, /DQS

CL = 3

RL = 3

DQ

out0 out1 out2 out3

Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

READ

NOP

Command

<tDQSCK

=

DQS, /DQS

CL = 3

RL = 3

DQ

out0 out1 out2 out3 out4 out5 out6 out7

Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))

Preliminary Data Sheet E0249E30 (Ver. 3.0)

37

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

NOP

Command

<tDQSCK

=

DQS, /DQS

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

DQ

Burst Read Operation (RL = 5, BL = 4 (AL = 2, CL = 3))

T0

T1

T3

T4

T5

T6

T7

T8

T9

/CK

CK

Posted

READ

Posted

WRIT

NOP

Command

tRTW (Read to Write = 4 clocks)

DQS, /DQS

RL = 5

WL = RL - 1 = 4

out0 out1 out2 out3

in0

in1

in2

in3

DQ

Burst Read followed by Burst Write (RL = 5, WL = RL-1 = 4, BL = 4)

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-

around-time, which is 4 clocks.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

Posted

READ

NOP

Command

DQS, /DQS

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3 out4 out5 out6

DQ

Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3) )

Preliminary Data Sheet E0249E30 (Ver. 3.0)

38

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Enabling a read command at every other clock supports the seamless burst read operation. This operation is

allowed regardless of same or different banks as long as the banks are activated.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

/CK

CK

NOP

Command

READ NOP READ

A

B

DQS, /DQS

RL = 4

out0 out1 out2 out3 out0 out1 out2out3out4 out5 out6 out7

DQ

Burst interrupt is only

allowed at this timing.

Burst Read Interrupt by Read

Preliminary Data Sheet E0249E30 (Ver. 3.0)

39

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Burst Write Command [WRIT]

The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of

the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read

latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble)

one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge

of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent

burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst

has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst

write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery

time (tWR).

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

WRIT

NOP

PRE

NOP

Command

ACT

Completion of

the Burst Write

<tDQSS

=

DQS, /DQS

DQ

>tWR

>tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T11

/CK

CK

WRIT

NOP

ACT

Command

PRE

Completion of

the Burst Write

<tDQSS

=

DQS, /DQS

DQ

>tWR

>tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

in4

in5

in6

in7

Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))

Preliminary Data Sheet E0249E30 (Ver. 3.0)

40

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

Posted

WRIT

NOP

PRE

Command

Completion of

the Burst Write

<tDQSS

=

DQS, /DQS

DQ

>tWR

WL = RL −1 = 4

=

in0

in1

in2

in3

Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

/CK

CK

Write to Read = CL + 1 + tWTR (2) = 6

NOP

Posted

READ

NOP

Command

DQS, /DQS

DQ

AL = 2

CL = 3

WL = RL –1 = 4

RL = 5

>tWTR

=

in0

in1

in2

in3

out0 out1

Burst Write followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3))

The minimum number of clock from the burst write command to the burst read command is CL + 1 + a write to-read-

turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit

write data from the input buffer into sense amplifiers in the array.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

WRIT

Posted

WRIT

Command

NOP

DQS, /DQS

WL = RL − 1 = 4

in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7

DQ

Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4)

Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed

regardless of same or different banks as long as the banks are activated.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

41

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

/CK

CK

NOP

Command

WRIT NOP WRIT

DQS, /DQS

WL = 3

in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7

DQ

Burst interrupt is only

allowed at this timing.

Write interrupt by Write (WL = 3, BL = 8)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

42

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Write data mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR-II SDRAMs, Consistent with the

implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in

a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used

during read cycles.

T1

in

T2

T3

in

T4

in

T5

T6

DQS

/DQS

DQ

DM

in

Write mask latency = 0

Data Mask Timing

[tDQSS(min.)]

/CK

CK

tWR

WRIT

Command

NOP

tDQSS

DQS, /DQS

DQ

in0

in2 in3

DM

tDQSS

[tDQSS(max.)]

DQS, /DQS

DQ

in0

in2 in3

DM

Data Mask Function, WL = 3, AL = 0 shown

Preliminary Data Sheet E0249E30 (Ver. 3.0)

43

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Precharge Command [PRE]

The precharge command is used to precharge or close a bank that has been activated. The precharge command is

triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge

command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,

BA0 and BA1 are used to define which bank to precharge when the command is issued.

[Bank Selection for Precharge by Address Bits]

A10

L

BA0

L

BA1

L

Precharged Bank(s)

Bank 0 only

L

H

L

Bank 1 only

L

H

Bank 2 only

L

H

Bank 3 only

H

×

All banks 0 to 3

Remark: H: VIH, L: VIL, ×: VIH or VIL

Burst Read Operation Followed by Precharge

Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks

For the earliest possible precharge, the precharge command may be issued on the rising edge that is

“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the

same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

NOP

AL + 2 clocks

PRE

NOP

ACT

NOP

Command

DQS, /DQS

> t

RP

=

AL = 1

CL = 3

RL = 4

out0 out1 out2 out3

CL = 3

DQ

> t

RAS

=

Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

ACT

NOP

AL + 2 clocks

PRE

NOP

Command

DQS, /DQS

> t

RP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> t

RAS

=

Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))

Preliminary Data Sheet E0249E30 (Ver. 3.0)

44

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

/CK

CK

Posted

READ

NOP

PRE

NOP

ACT

Command

AL + BL/2 Clocks

DQS, /DQS

DQ

> t

RP

=

CL = 4

AL = 2

RL = 6

out0 out1 out2 out3 out4 out5 out6 out7

> t

RAS(min.)

=

Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4, BL=8))

Preliminary Data Sheet E0249E30 (Ver. 3.0)

45

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Burst Write followed by Precharge

Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge

command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the

burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR-II

SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

WRIT

NOP

PRE

Command

> tWR

=

DQS, /DQS

WL = 3

in0

in1

in2

in3

DQ

Completion of

the Burst Write

Burst Write followed by Precharge (WL = (RL-1) =3)

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

Posted

WRIT

NOP

PRE

Command

> tWR

=

DQS, /DQS

DQ

WL = 4

in0

in1

in2

in3

Completion of

the Burst Write

Burst Write followed by Precharge (WL = (RL-1) = 4)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

46

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T11

/CK

CK

WRIT

NOP

ACT

Command

PRE

Completion of

the Burst Write

<tDQSS

=

DQS, /DQS

DQ

>tWR

>tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

in4

in5

in6

in7

Burst Write followed by Precharge (WL = (RL-1) = 4,BL= 8)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

47

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge

command or the auto-precharge function. When a read or a write command is given to the DDR-II SDRAM, the

/CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin

precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write

Command is issued, then normal read or write burst operation is executed and the bank remains active at the

completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-

precharge function is engaged. During auto-precharge, a read Command will execute as normal with the exception

that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end

of the read burst.

Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally

delays the Precharge operation until the array restore operation has been completed so that the auto precharge

command may be issued with any read or write command.

Burst Read with Auto Precharge [READA]

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR-II

SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with

AP command when the condition that. When tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the

start point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command)

may be issued to the same bank if the following two conditions are satisfied simultaneously.

(1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

A10 = 1

Posted

READ

NOP

Command

ACT

> tRAS(min.)

=

DQS, /DQS

> tRP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> tRC

=

Auto precharge begins

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))

Preliminary Data Sheet E0249E30 (Ver. 3.0)

48

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

A10 = 1

Posted

READ

NOP

ACT

NOP

Command

> tRAS(min.)

=

DQS, /DQS

> tRP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> tRC

=

Auto precharge begins

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

/CK

CK

A10 = 1

NOP

Command

READ

ACT

tRAS (min.)

DQS, /DQS

AL = 2

CL = 3

RL = 5

tRP

out0 out1 out2 out3 out4 out5 out6 out7

DQ

tRC

Auto Precharge begins.

Burst Read with Auto Precharge Followed by an Activation to the Same Bank

(RL = 5, BL = 8 (AL = 2, CL = 3)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

49

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Burst Write with Auto-Precharge [WRITA]

If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR-II

SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time

(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following two conditions are satisfied.

(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T12

/CK

CK

A10 = 1

Posted

WRIT

NOP

Command

ACT

DQS, /DQS

> tWR

> tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

DQ

> tRC

=

Auto Precharge Begins

Completion of the Burst Write

Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)

T0

T3

T4

T5

T6

T7

T8

T9

T10

/CK

CK

A10 = 1

Posted

WRIT

NOP

Command

NOP

ACT

DQS, /DQS

> tWR

=

WL = RL –1 = 4

> tRP

=

in0

in1

in2

in3

DQ

> tRC

=

Auto Precharge Begins

Completion of the Burst Write

Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

50

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

T0 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

/CK

CK

A10 = 1

NOP

Command

WRIT

ACT

DQS, /DQS

tWR

tRP

WL = RL - 1 = 4

in0 in1 in2 in3 in4 in5 in6 in7

DQ

tRC

Auto Precharge begins.

Burst Write with Auto Precharge Followed by an Activation to the Same Bank

(WL = 4, BL = 8, tWR = 2, tRP = 3)

Preliminary Data Sheet E0249E30 (Ver. 3.0)

51

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Refresh Requirements

DDR-II SDRAM requires a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two

ways: by an explicit Automatic Refresh command, or by an internally timed event in Self Refresh mode. Dividing the

number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline

to controllers for distributed refresh timing.

Automatic Refresh Command (/CAS Before /RAS Refresh) [REF]

When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the Automatic

Refresh mode (CBR). All banks of the DDR-II SDRAM must be precharged and idle for a minimum of the Precharge

time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device,

supplies the bank address during the refresh cycle. No control of the external address bus is required once this

cycle has started.

When the refresh cycle has completed, all banks of the DDR-II SDRAM will be in the precharged (idle) state. A

delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh

Command must be greater than or equal to the Auto Refresh cycle time (tRFC).

The DDR-II SDRAM requires Automatic Refresh cycles at an average periodic interval of tREFI (maximum). A

maximum of eight Automatic Refresh commands can be posted to any given DDR-II SDRAM, and the maximum

absolute interval between any Auto Refresh command and the next Auto Refresh command is 8 × tREFI.

T0

T1

T2

T3

T15

T7

T8

/CK

CK

High

> tRP

> tRFC

=

CKE

=

Any

Command

PRE

NOP

CBR

NOP

Command

Automatic Refresh Command

Self Refresh Command [SELF]

The DDR-II SDRAM device has a built-in timer to accommodate Self Refresh operation. The self refresh command

is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Once the

Command is registered, CKE must be held low to keep the device in self refresh mode. When the SDRAM has

entered self refresh mode all of the external control signals, except CKE, are disabled. The clock is internally

disabled during self refresh operation to save power. The user may halt the external clock while the device is in Self

Refresh mode, however, the clock must be restarted before the device can exit self refresh operation. Once the

clock is cycling, the exit command will be registered asynchronously by bringing CKE high. After CKE is brought

high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the self refresh

exit command. The purpose of this circuit is to filter out noise glitches on the CKE input that may cause the DDR-II

SDRAM to erroneously exit self refresh operation. Once the self refresh command is registered, a delay equal or

longer than the tXSC must be satisfied before any command can be issued to the device. CKE must remain high

for the entire Self Refresh exit period (tXSC) and commands must be gated off with /CS held High. Alternatively,

NOP commands may be registered on each positive clock edge during the self refresh exit interval. (Self Refresh

Command)

T0

T1

T2

T3

Tm

Tn

Tn+1

/CK

CK

> tXSC

=

CKE

Any

Command

SELF

NOP

: VIH or VIL

Self Refresh Command

Preliminary Data Sheet E0249E30 (Ver. 3.0)

52

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Power-Down [PDEN]

Power-down is entered when CKE is registered (no accesses can be in progress). If power-down occurs when all

banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active

in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output

buffers, excluding CK, /CK and CKE. In power down mode, CKE Low and a stable clock signal must be maintained

at the inputs of the DDR-II SDRAM, and all other input signals are “VIH or VIL”. Power-down duration is limited by

the refresh requirements of the device.

The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESL). A valid,

executable command may be applied after satisfied tXPRD or tXARD for read command exiting form precharge

power-down or active power-down respectively ,and after satisfied tXPNR for non-read command.

/CK

CK

tIS

CKE

VALID

NOP

VALID

Command

tXPRD, tXPNR

tXARD

power down

mode

No column

access in progress

Exit

Enter power down mode

(Burst read or write operation

must not be in progress)

: VIH or VIL

Power Down

Burst Interruption

Interruption of a burst read or write cycle is prohibited.

No Operation Command [NOP]

The no operation command should be used in cases when the DDR-II SDRAM is in an idle or a wait state. The

purpose of the no operation command is to prevent the DDR-II SDRAM from registering any unwanted commands

between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at

the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

Deselect Command [DESL]

The deselect command performs the same function as a no operation command. Deselect Command occurs when

/CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

53

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Package Drawing

64-ball FBGA(µBGA) (TBD)

Solder ball: Lead free (Sn-Ag-Cu)

80-ball FBGA(µBGA) (TBD)

Solder ball: Lead free (Sn-Ag-Cu)

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDE51XXGBSA.

Type of Surface Mount Device

EDE51XXGBSA: 64-ball µBGA, 80-ball µBGA < Lead free (Sn-Ag-Cu) >

Preliminary Data Sheet E0249E30 (Ver. 3.0)

54

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V^DDor GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Preliminary Data Sheet E0249E30 (Ver. 3.0)

55

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

µBGA is a registered trademark of Tessera, Inc.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0249E30 (Ver. 3.0)

56


型号：	EDE5108GBSA-5A-E
厂家：	ELPIDA MEMORY
描述：	512M bits DDR-II SDRAM 位512M DDR- II SDRAM 存储内存集成电路动态存储器双倍数据速率时钟
文件：	总56页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDE5108GBSA-5A-E [ELPIDA]

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