EDJ2104BDBG-GN-F [ELPIDA]
Differential clock inputs; 差分时钟输入型号: | EDJ2104BDBG-GN-F |
厂家: | ELPIDA MEMORY |
描述: | Differential clock inputs |
文件: | 总30页 (文件大小:447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
COVER
DATA SHEET
2G bits DDR3 SDRAM
EDJ2104BDBG (512M words × 4 bits)
EDJ2108BDBG (256M words × 8 bits)
Specifications
Features
• Density: 2G bits
• Organization
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
— 64M words × 4 bits × 8 banks (EDJ2104BDBG)
— 32M words × 8 bits × 8 banks (EDJ2108BDBG)
• Package
— 78-ball FBGA (EDJ2104BDBG, EDJ2108BDBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD = 1.5V 0.075V
• Data rate
— 1866Mbps/1600Mbps/1333Mbps/1066Mbps/
800Mbps (max)
• 1KB page size
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
— Row address: A0 to A14
• Data mask (DM) for write data
— Column address: A0 to A9, A11 (EDJ2104BDBG)
A0 to A9 (EDJ2108BDBG)
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
• Eight internal banks for concurrent operation
• Interface: SSTL_15
— Dynamic ODT
— Asynchronous ODT
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
• Multi Purpose Register (MPR) for pre-defined pattern
read out
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range:
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13
• /CAS Write Latency (CWL): 5, 6, 7, 8, 9
• Precharge: auto precharge option for each burst
access
— Normal/extended
• Programmable Output driver impedance control
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Document. No. E1772E40 (Ver. 4.0)
Date Published December 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2011-2012
EDJ2104BDBG, EDJ2108BDBG
Ordering Information
Die
revision
Organization
(words × bits)
Internal
banks
JEDEC speed bin
(CL-tRCD-tRP)
Part number
Package
EDJ2104BDBG-JS-F
EDJ2104BDBG-GN-F
EDJ2104BDBG-DJ-F
EDJ2104BDBG-AE-F
EDJ2104BDBG-8C-F
DDR3-1866M (13-13-13)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-800E (6-6-6)
78-ball FBGA
D
D
512M × 4
256M × 8
8
8
EDJ2108BDBG-JS-F
EDJ2108BDBG-GN-F
EDJ2108BDBG-DJ-F
EDJ2108BDBG-AE-F
EDJ2108BDBG-8C-F
DDR3-1866M (13-13-13)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-800E (6-6-6)
78-ball FBGA
Part Number
E D J 21 04 B D BG - JS- F
Elpida Memory
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Type
D: Packaged Device
Speed
Product Family
J: DDR3
JS: DDR3-1866M (13-13-13)
GN: DDR3-1600K (11-11-11)
DJ: DDR3-1333H (9-9-9)
AE: DDR3-1066F (7-7-7)
8C: DDR3-800E (6-6-6)
Density / Bank
21: 2Gb / 8-bank
Organization
04: x4
Package
BG: FBGA
08: x8
Power Supply, Interface
B: 1.5V, SSTL_15
Die Rev.
Detailed Information
For detailed electrical specification and further information, please refer to the DDR3 SDRAM General Functionality
and Electrical Condition data sheet (E1926E).
Data Sheet E1772E40 (Ver. 4.0)
2
EDJ2104BDBG, EDJ2108BDBG
Pin Configurations
Pin Configurations (×4/×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
1
2
3
7
8
9
A
B
A
B
VSS
VDD
NC
NC
VSS
VDD
VSS
VDD
NC
NU/(/TDQS) VSS
VDD
VSS VSSQ DQ0
DM VSSQ VDDQ
VSS VSSQ DQ0
VDDQ
DM/TDQS VSSQ VDDQ
C
D
C
D
VDDQ
VSSQ
DQ2 DQS
NC /DQS
DQ1
VDD
NC
DQ3 VSSQ
VSSQ
NC VDDQ
NC
VDD CKE
DQ2 DQS
DQ1
VDD
DQ7
DQ3 VSSQ
VSSQ
VSS
VSSQ DQ6 /DQS
VSS
DQ5
E
F
G
H
J
E
F
G
H
J
DQ4
VREFDQ VDDQ NC
NC VSS /RAS
ODT VDD /CAS
VREFDQ VDDQ
VDDQ
NC
CK
/CK
VSS
NC
VSS /RAS
CK
/CK
VSS
ODT VDD /CAS
VDD CKE
A10(AP)
A10(AP)
NC
/CS
/WE
ZQ
NC
NC
/CS
/WE
ZQ
NC
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
K
L
K
L
A12(/BC) BA1
VDD
VSS
VDD
VSS
A12(/BC) BA1
VDD
VSS
VDD
VSS
A5
A2
A1
A4
A6
A8
A5
A2
A1
A4
A6
A8
M
N
M
N
A7
A9
A11
A14
A7
A9
A11
A14
/RESET A13
/RESET A13
(Top view)
(Top view)
Pin name
Function
Pin name
Function
Address inputs
A0 to A14*3
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*3
Active low asynchronous reset
BA0 to BA2*3
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*3
Bank select
VDD
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Data input/output
Differential data strobe
Termination data strobe
Chip select
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*1
NU*2
Reference voltage for DQ
Reference voltage for CA
Reference pin for ZQ calibration
No connection
/RAS, /CAS, /WE*3
CKE*3
Command input
Clock enable
CK, /CK
Differential clock input
Write data mask
ODT control
DM
ODT*3
Not usable
Notes: 1. Not internally connected with die.
2. Don't connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1772E40 (Ver. 4.0)
3
EDJ2104BDBG, EDJ2108BDBG
CONTENTS
Specifications ........................................................................................................................................ 1
Features ................................................................................................................................................ 1
Ordering Information ............................................................................................................................. 2
Part Number .......................................................................................................................................... 2
Detailed Information .............................................................................................................................. 2
Pin Configurations ................................................................................................................................. 3
1. Electrical Conditions ...................................................................................................................... 5
1.1
1.2
1.3
1.4
Absolute Maximum Ratings ..............................................................................................................5
Operating Temperature Condition ....................................................................................................5
Recommended DC Operating Conditions ........................................................................................6
IDD and IDDQ Measurement Conditions ..........................................................................................7
2. Electrical Specifications ............................................................................................................... 18
2.1
2.2
2.3
DC Characteristics ..........................................................................................................................18
Pin Capacitance ..............................................................................................................................20
Standard Speed Bins ......................................................................................................................22
3. Package Drawing ......................................................................................................................... 27
3.1 78-ball FBGA ..................................................................................................................................27
4. Recommended Soldering Conditions .......................................................................................... 28
Data Sheet E1772E40 (Ver. 4.0)
4
EDJ2104BDBG, EDJ2108BDBG
1. Electrical Conditions
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
1.1 Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings
Parameter
Symbol
VDD
Rating
Unit
V
Notes
Power supply voltage
Power supply voltage for output
Input voltage
−0.4 to +1.975
−0.4 to +1.975
−0.4 to +1.975
−0.4 to +1.975
−0.4 to 0.6 × VDD
−0.4 to 0.6 × VDDQ
−55 to +100
1.0
1, 3
1, 3
1
VDDQ
VIN
V
V
Output voltage
VOUT
VREFCA
VREFDQ
Tstg
V
1
Reference voltage
Reference voltage for DQ
Storage temperature
Power dissipation
V
3
V
3
°C
W
mA
1, 2
1
PD
Short circuit output current
IOUT
50
1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 × VDDQ, When
VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
1.2 Operating Temperature Condition
Table 2: Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Notes
Operating case temperature
TC
0 to +95
°C
1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During
operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case
temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double
refresh requirement may not apply for some devices.)
b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual
Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto
Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Data Sheet E1772E40 (Ver. 4.0)
5
EDJ2104BDBG, EDJ2108BDBG
1.3 Recommended DC Operating Conditions
Table 3: Recommended DC Operating Conditions (TC = 0°C to +85°C)
Parameter
Symbol
VDD
min
typ
1.5
1.5
max
Unit
V
Notes
1, 2
Supply voltage
Supply voltage for DQ
1.425
1.425
1.575
1.575
VDDQ
V
1, 2
Notes: 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Data Sheet E1772E40 (Ver. 4.0)
6
EDJ2104BDBG, EDJ2108BDBG
1.4 IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined.
The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD
and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3
SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of
the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Note:IDDQ values cannot be directly used to calculate I/O power of the DDR3 SDRAM. They can be used to support
correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O
power to actual channel I/O power supported by IDDQ measurement.
For IDD and IDDQ measurements, the following definitions apply:
• L and 0: VIN ≤ VIL(AC)max
• H and 1: VIN ≥ VIH(AC)min
• MID-LEVEL: defined as inputs are VREF = VDDQ / 2
• FLOATING: don't care or floating around VREF.
• Timings used for IDD and IDDQ measurement-loop patterns are provided in Timings used for IDD and IDDQ
Measurement-Loop Patterns table.
• Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions
table.
Note:The IDD and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
• Detailed IDD and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table
through IDD7 Measurement-Loop Pattern table.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting.
RON = RZQ/7 (34Ω in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40Ω in MR1);
RTT_WR = RZQ/2 (120Ω in MR2);
TDQS Feature disabled in MR1
• Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L}
• Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H}
Data Sheet E1772E40 (Ver. 4.0)
7
EDJ2104BDBG, EDJ2108BDBG
IDD
IDDQ
VDD
VDDQ
/RESET
CK, /CK
DDR3
RTT = 25Ω
DQS, /DQS,
DQ, DM,
TDQS, /TDQS
SDRAM
CKE
/CS
/RAS, /CAS, /WE
Address, BA
ODT
VDDQ/2
ZQ
VSSQ
VSS
Figure 2: Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific
memory channel
environment
IDDQ
Test load
Channel
I/O power
simulation
IDDQ
measurement
IDDQ
simulation
Correlation
Correction
Channel I/O power
number
Figure 3: Correlation from Simulated Channel I/O Power to Actual Channel I/O Power
Supported by IDDQ Measurement
Data Sheet E1772E40 (Ver. 4.0)
8
EDJ2104BDBG, EDJ2108BDBG
1.4.1
Timings Used for IDD and IDDQ Measurement-Loop Patterns
Table 4: Timings Used for IDD and IDDQ Measurement-Loop Patterns
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
CL
6-6-6
6
7-7-7
7
9-9-9
9
11-11-11
11
Unit
nCK
ns
tCK(min)
2.5
6
1.875
7
1.5
9
1.25
11
nRCD(min)
nRC(min)
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
21
15
6
27
20
7
33
24
9
39
nRAS(min)
nRP(min)
28
11
nFAW (1KB)
nFAW (2KB, 4KB)
nRRD (1KB)
nRRD (2KB, 4KB)
nRFC (1Gb)
nRFC (2Gb)
nRFC (4Gb)
nRFC (8Gb)
16
20
4
20
27
4
20
30
4
24
32
5
4
6
5
6
44
64
104
140
59
86
139
187
74
107
174
234
88
128
208
280
DDR3-1866
Parameter
CL
13-13-13
13
Unit
nCK
ns
tCK(min)
1.07
13
nRCD(min)
nRC(min)
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
45
nRAS(min)
nRP(min)
32
13
nFAW (1KB)
nFAW (2KB, 4KB)
nRRD (1KB)
nRRD (2KB, 4KB)
nRFC (1Gb)
nRFC (2Gb)
nRFC (4Gb)
nRFC (8Gb)
26
33
5
6
103
150
243
328
Data Sheet E1772E40 (Ver. 4.0)
9
EDJ2104BDBG, EDJ2108BDBG
1.4.2
Basic IDD and IDDQ Measurement Conditions
Table 5: Basic IDD and IDDQ Measurement Conditions
Parameter
Symbol
Description
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Table 4; BL: 8*1; AL: 0; /CS: H
between ACT and PRE; Command, address, bank address inputs: partially toggling
according to Table 6; Data I/O: MID-LEVEL; DM: stable at 0;
Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 6);
Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; Pattern details: see
Table 6
Operating one bank
active precharge
current
IDD0
CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 4; BL: 8*1, *6; AL:
0; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data
I/O: partially toggling according to Table 7;
Operating one bank
active-read-precharge
current
IDD1
DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table 7); Output buffer and RTT: enabled in MR*2; ODT Signal: stable at 0;
Pattern details: see Table 7
CKE: H; External clock: on; tCK, CL: see Table 4 BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 8;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in mode registers*2; ODT signal: stable at 0; pattern details: see
Table 8
Precharge standby
current
IDD2N
CKE: H; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in MR*2; ODT signal: toggling according to Table 9; pattern details:
see Table 9
Precharge standby
ODT current
IDD2NT
Precharge standby
ODT IDDQ current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD
current
CKE: L; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM:
stable at 0; bank activity: all banks closed; output buffer and RTT: EMR*2; ODT
signal: stable at 0; precharge power down mode: slow exit*3
IDDQ2NT
IDD2P0
Precharge power-down
current slow exit
CKE: L; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; precharge power down mode: fast exit*3
CKE: H; External clock: On; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0
Precharge power-down
current fast exit
IDD2P1
IDD2Q
Precharge quiet
standby current
CKE: H; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 8;
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: all banks open; output buffer and RTT: enabled in MR*2;
ODT signal: stable at 0; pattern details: see Table 8
CKE: L; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks open; output buffer and RTT:
enabled in MR*2; ODT signal: stable at 0
Active standby current
IDD3N
IDD3P
Active power-down
current
CKE: H; External clock: on; tCK, CL: see Table 4; BL: 8*1, *6; AL: 0; /CS: H between
RD; Command, address, bank address Inputs: partially toggling according to
Table 10; data I/O: seamless read
Operating burst read
current
data burst with different data between one burst and the next one according to
Table 10; DM: stable at 0;
IDD4R
bank activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
(see Table 10); Output buffer and RTT: enabled in MR*2; ODT signal: stable at 0;
pattern details: see Table 10
Operating burst read
IDDQ current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD
current
IDDQ4R
Data Sheet E1772E40 (Ver. 4.0)
10
EDJ2104BDBG, EDJ2108BDBG
Table 5: Basic IDD and IDDQ Measurement Conditions (cont’d)
Parameter
Symbol
Description
CKE: H; External clock: on; tCK, CL: see Table 4; BL: 8*1; AL: 0; /CS: H between WR;
command, address, bank address inputs: partially toggling according to Table 11;
data I/O: seamless write data burst with different data between one burst and the next
one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank
activity: all banks open,
Operating burst write current IDD4W
WR commands cycling through banks: 0,0,1,1,2,2,.. (see Table 11); Output buffer
and RTT: enabled in MR*2; ODT signal: stable
at H; pattern details: see Table 11
CKE: H; External clock: on; tCK, CL, nRFC: see Table 4; BL: 8*1; AL: 0; /CS: H
between REF;
Command, address, bank address Inputs: partially toggling according to Table 12;
data I/O: MID-LEVEL; DM: stable at 0;
Burst refresh current
IDD5B
IDD6
bank activity: REF command every nRFC (Table 12); output buffer and RTT: enabled
in MR*2; ODT signal: stable at 0; pattern
details: see Table 12
TC: 0 to 85°C; ASR: disabled*4; SRT:
Normal*5; CKE: L; External clock: off; CK and /CK: L; CL: see Table 4; BL: 8*1;
AL: 0; /CS, command, address, bank address, data I/O: MID-LEVEL; DM: stable
at 0; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR*2;
ODT signal: MID-LEVEL
Self-refresh current: normal
temperature range
TC: 0 to 95°C; ASR: Disabled*4; SRT: Extended*5; CKE: L; External clock: off; CK
and /CK: L; CL: Table 4; BL: 8*1; AL: 0; /CS, command, address, bank address, data
I/O: MID-LEVEL;
Self-refresh current: extended
temperature range
IDD6ET
IDD6TC
DM: stable at 0; bank activity: Extended temperature self-refresh operation; output
buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
TC: 0 to 95°C; ASR: Enabled*4; SRT: Normal*5; CKE: L; External clock: off;
CK and /CK: L; CL: Table 4; BL: 8*1; AL: 0; /CS, command, address, bank address,
data I/O: MID-LEVEL; DM: stable at 0; bank activity: Auto self-refresh operation;
output buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
Auto self-refresh current
(Optional)
CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 4;
BL: 8*1, *6; AL: CL-1; /CS: H between ACT and RDA; Command, address, bank
address Inputs: partially toggling according to Table 13; data I/O: read data bursts
with different data between one burst and the next one according to Table 13; DM:
stable at 0; bank activity: two times interleaved cycling through banks (0, 1, …7) with
different addressing, see Table 13; output buffer and RTT: enabled in MR*2; ODT
signal: stable at 0; pattern details: see Table 13
Operating bank interleave
read current
IDD7
IDD8
/RESET: low; External clock: off; CK and /CK: low; CKE: FLOATING; /CS, command,
address, bank address, Data IO: FLOATING; ODT signal: FLOATING
RESET low current reading is valid once power is stable and /RESET has been low
for at least 1ms.
RESET low current
Notes: 1. Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].
2. MR: Mode Register
Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1];
RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0].
3. Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit.
4. Auto self-refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature.
5. Self-refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range.
6. Read burst type: nibble sequential, set MR0 bit A3 = 0
Data Sheet E1772E40 (Ver. 4.0)
11
EDJ2104BDBG, EDJ2108BDBG
Table 6: IDD0 Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7
A3
A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
ACT
D, D
/D, /D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1, 2
3, 4
…
Repeat pattern 1…4 until nRAS − 1, truncate if necessary
PRE
Repeat pattern 1...4 until nRC − 1, truncate if necessary
nRAS
…
0
0
1
0
0
0
0
0
0
0
0
1 × nRC
+ 0
ACT
D, D
/D, /D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
1 × nRC
+1, 2
1 × nRC
+ 3, 4
Toggling Static H
…
Repeat pattern nRC + 1,...,4 until 1 × nRC + nRAS − 1, truncate if necessary
PRE
Repeat nRC + 1,...,4 until 2 × nRC − 1, truncate if necessary
1 × nRC
+ nRAS
0
0
1
0
0
0
0
0
0
F
0
…
1
2
3
4
5
6
7
2 × nRC Repeat Sub-Loop 0, use BA= 1 instead
4 × nRC Repeat Sub-Loop 0, use BA= 2 instead
6 × nRC Repeat Sub-Loop 0, use BA= 3 instead
8 × nRC Repeat Sub-Loop 0, use BA= 4 instead
10 × nRC Repeat Sub-Loop 0, use BA= 5 instead
12 × nRC Repeat Sub-Loop 0, use BA= 6 instead
14 × nRC Repeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
12
EDJ2104BDBG, EDJ2108BDBG
Table 7: IDD1 Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7 A3 A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
ACT
D, D
/D, /D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
1, 2
3, 4
…
Repeat pattern 1...4 until nRCD − 1, truncate if necessary
RD
Repeat pattern 1...4 until nRAS − 1, truncate if necessary
PRE
Repeat pattern 1...4 until nRC − 1, truncate if necessary
nRCD
…
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
00000000
nRAS
…
0
0
1
0
0
0
0
⎯
1 × nRC
+ 0
ACT
D, D
/D, /D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
⎯
⎯
⎯
0
1 × nRC
+ 1, 2
1 × nRC
+ 3, 4
Toggling Static H
…
Repeat pattern nRC + 1,..., 4 until nRC + nRCD − 1, truncate if necessary
RD
Repeat pattern nRC + 1,..., 4 until nRC +nRAS − 1, truncate if necessary
PRE
Repeat pattern nRC + 1,..., 4 until 2 × nRC − 1, truncate if necessary
1 × nRC
+ nRCD
0
1
0
1
0
0
0
0
0
F
0
0
00110011
…
1 × nRC
+ nRAS
0
0
1
0
0
0
0
0
0
F
⎯
…
1
2
3
4
5
6
7
2 × nRC Repeat Sub-Loop 0, use BA= 1 instead
4 × nRC Repeat Sub-Loop 0, use BA= 2 instead
6 × nRC Repeat Sub-Loop 0, use BA= 3 instead
8 × nRC Repeat Sub-Loop 0, use BA= 4 instead
10 × nRC Repeat Sub-Loop 0, use BA= 5 instead
12 × nRC Repeat Sub-Loop 0, use BA= 6 instead
14 × nRC Repeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
13
EDJ2104BDBG, EDJ2108BDBG
Table 8: IDD2N and IDD3N Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7
A3
A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
1
D
0
1
2
/D
/D
3
4 to 7
8 to 11
Repeat Sub-Loop 0, use BA= 1 instead
Repeat Sub-Loop 0, use BA= 2 instead
Toggling Static H 2
3
4
5
6
7
12 to 15 Repeat Sub-Loop 0, use BA= 3 instead
16 to 19 Repeat Sub-Loop 0, use BA= 4 instead
20 to 23 Repeat Sub-Loop 0, use BA= 5 instead
24 to 27 Repeat Sub-Loop 0, use BA= 6 instead
28 to 31 Repeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Table 9: IDD2NT and IDDQ2NT Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7
A3
A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
1
D
0
2
/D
/D
3
1
4 to 7
8 to 11
Repeat Sub-Loop 0, but ODT = 0 and BA= 1
Repeat Sub-Loop 0, but ODT = 1 and BA= 2
Toggling Static H 2
3
4
5
6
7
12 to 15 Repeat Sub-Loop 0, but ODT = 1 and BA= 3
16 to 19 Repeat Sub-Loop 0, but ODT = 0 and BA= 4
20 to 23 Repeat Sub-Loop 0, but ODT = 0 and BA= 5
24 to 27 Repeat Sub-Loop 0, but ODT = 1 and BA= 6
28 to 31 Repeat Sub-Loop 0, but ODT = 1 and BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
14
EDJ2104BDBG, EDJ2108BDBG
Table 10: IDD4R and IDDQ4R Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7 A3 A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
1
⎯
2,3
/D, /D
RD
D
⎯
0
4
00110011
5
⎯
⎯
6,7
/D, /D
Toggling Static H 1
8 to 15
Repeat Sub-Loop 0, but BA= 1
2
3
4
5
6
7
16 to 23 Repeat Sub-Loop 0, but BA= 2
24 to 31 Repeat Sub-Loop 0, but BA= 3
32 to 39 Repeat Sub-Loop 0, but BA= 4
40 to 47 Repeat Sub-Loop 0, but BA= 5
48 to 55 Repeat Sub-Loop 0, but BA= 6
56 to 63 Repeat Sub-Loop 0, but BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
15
EDJ2104BDBG, EDJ2108BDBG
Table 11: IDD4W Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7 A3 A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
1
⎯
2,3
/D, /D
WR
D
⎯
0
4
00110011
5
⎯
⎯
6,7
/D, /D
Toggling Static H 1
8 to 15
Repeat Sub-Loop 0, but BA= 1
2
3
4
5
6
7
16 to 23 Repeat Sub-Loop 0, but BA= 2
24 to 31 Repeat Sub-Loop 0, but BA= 3
32 to 39 Repeat Sub-Loop 0, but BA= 4
40 to 47 Repeat Sub-Loop 0, but BA= 5
48 to 55 Repeat Sub-Loop 0, but BA= 6
56 to 63 Repeat Sub-Loop 0, but BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise MID-LEVEL.
2. Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Table 12: IDD5B Measurement-Loop Pattern
CK,
/CK
Sub
Cycle
Com-
A11
A7 A3 A0
CKE
-Loop number mand /CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
REF
D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
⎯
⎯
⎯
0
1, 2
3,4
/D, /D
5 to 8
9 to 12
Repeat cycles 1...4, but BA= 1
Repeat cycles 1...4, but BA= 2
13 to 16 Repeat cycles 1...4, but BA= 3
17 to 20 Repeat cycles 1...4, but BA= 4
21 to 24 Repeat cycles 1...4, but BA= 5
25 to 28 Repeat cycles 1...4, but BA= 6
29 to 32 Repeat cycles 1...4, but BA= 7
33 to
Toggling Static H
1
2
Repeat Sub-Loop 1, until nRFC − 1. Truncate, if necessary.
nRFC − 1
Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
16
EDJ2104BDBG, EDJ2108BDBG
Table 13: IDD7 Measurement-Loop Pattern
CK,
/CK
Sub
-Loop number
Cycle
Com-
mand
A11
A7 A3 A0
CKE
/CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2
0
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
⎯
1
00000000
0
2
⎯
…
Repeat above D Command until nRRD − 1
nRRD
ACT
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
F
F
F
0
0
0
⎯
nRRD + 1 RDA
00110011
1
nRRD + 2
…
D
⎯
Repeat above D Command until 2 × nRRD − 1
2
3
2 × nRRD Repeat Sub-Loop 0, but BA= 2
3 × nRRD Repeat Sub-Loop 1, but BA= 3
D
1
0
0
0
0
3
0
0
0
F
0
⎯
4
5
6
4 × nRRD
Assert and repeat above D Command until nFAW − 1, if necessary
Repeat Sub-Loop 0, but BA= 4
nFAW
nFAW
Repeat Sub-Loop 1, but BA= 5
Repeat Sub-Loop 0, but BA= 6
Repeat Sub-Loop 1, but BA= 7
+ nRRD
nFAW
7
8
9
+ 2 × nRRD
nFAW
+ 3 × nRRD
D
1
0
0
0
0
7
0
0
0
F
0
0
⎯
⎯
nFAW
+ 4 × nRRD
Assert and repeat above D Command until 2 × nFAW − 1, if necessary
2 × nFAW
+ 0
ACT
0
0
1
1
0
0
0
0
0
F
2 × nFAW
+ 1
Toggling Static H
RDA
D
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
F
F
0
0
00110011
10
11
⎯
2 × nFAW
+ 2
Repeat above D Command until 2 × nFAW + nRRD − 1
2 × nFAW
+ nRRD
ACT
0
0
1
1
0
1
0
0
0
0
0
⎯
2 × nFAW
+ nRRD + 1
RDA
D
0
1
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
00000000
⎯
2 × nFAW
+ nRRD + 2
Repeat above D Command until 2 × nFAW + 2 × nRRD − 1
2 × nFAW
+2 × nRRD
2 × nFAW
+ 3 × nRRD
12
13
Repeat Sub-Loop 10, but BA= 2
Repeat Sub-Loop 11, but BA= 3
D
1
0
0
0
0
3
0
0
0
0
0
⎯
2 × nFAW
+ 4 × nRRD
14
15
16
Assert and repeat above D Command until 3 × nFAW − 1, if necessary
3 × nFAW Repeat Sub-Loop 10, but BA= 4
3 × nFAW
Repeat Sub-Loop 11, but BA= 5
+nRRD
3 × nFAW
17
18
19
Repeat Sub-Loop 10, but BA= 6
+ 2 × nRRD
3 × nFAW
Repeat Sub-Loop 11, but BA= 7
+ 3 × nRRD
D
1
0
0
0
0
7
0
0
0
0
0
⎯
3 × nFAW
+ 4 × nRRD
Assert and repeat above D Command until 4 × nFAW − 1, if necessary
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
3. BA: BA0 to BA2.
4. Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1772E40 (Ver. 4.0)
17
EDJ2104BDBG, EDJ2108BDBG
2. Electrical Specifications
2.1 DC Characteristics
Table 14: DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
Data rate
(Mbps)
× 4
× 8
Parameter
Symbol
max
max
Unit
Notes
800
40
45
50
55
60
40
45
50
55
60
1066
1333
1600
1866
Operating current
(ACT-PRE)
IDD0
mA
800
50
55
60
65
70
50
55
60
65
70
1066
1333
1600
1866
Operating current
(ACT-RD-PRE)
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
800
16
18
18
20
22
16
18
18
20
22
1066
1333
1600
1866
IDD2P1
IDD2P0
Fast PD Exit
Slow PD Exit
Precharge power-down
standby current
800
12
12
12
12
12
12
12
12
12
12
1066
1333
1600
1866
800
25
27
30
33
35
25
27
30
33
35
1066
1333
1600
1866
Precharge standby current IDD2N
800
25
27
30
33
35
25
27
30
33
35
1066
1333
1600
1866
Precharge standby
IDD2NT
ODT current
800
25
27
30
33
35
25
27
30
33
35
1066
1333
1600
1866
Precharge quiet standby
IDD2Q
current
800
25
27
27
30
30
25
27
27
30
30
1066
1333
1600
1866
Active power-down current
IDD3P
(Always fast exit)
800
35
37
40
43
45
35
37
40
43
45
1066
1333
1600
1866
Active standby current
IDD3N
Data Sheet E1772E40 (Ver. 4.0)
18
EDJ2104BDBG, EDJ2108BDBG
Table 14: DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)(cont’d)
Data rate
(Mbps)
× 4
× 8
Parameter
Symbol
max
max
Unit
Notes
800
75
80
1066
1333
1600
1866
85
90
Operating current
(Burst read operating)
IDD4R
95
100
110
120
mA
105
110
800
80
85
1066
1333
1600
1866
90
95
Operating current
(Burst write operating)
IDD4W
IDD5B
100
110
120
105
115
125
mA
mA
800
170
170
170
175
175
170
170
170
175
175
1066
1333
1600
1866
Burst refresh current
800
135
145
165
175
185
140
150
170
180
190
1066
1333
1600
1866
All bank interleave read
current
IDD7
IDD8
mA
mA
RESET low current
12
12
Table 15: Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
Parameter
Symbol
max
Unit
Notes
Self-refresh current
normal temperature range
IDD6
12
mA
Self-refresh current
extended temperature range
IDD6ET
IDD6TC
18
mA
mA
Auto self-refresh current
(Optional)
⎯
Data Sheet E1772E40 (Ver. 4.0)
19
EDJ2104BDBG, EDJ2108BDBG
2.2 Pin Capacitance
Table 16: Pin Capacitance [DDR3-800 to 1600] (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V)
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes
Input/outputcapacitance CIO
1.4
3.0
1.4
2.7
1.4
2.5
1.4
2.3
pF
pF
pF
1, 2
2
Input capacitance,
CCK
0.8
0
1.6
0.8
0
1.6
0.8
0
1.4
0.8
0
1.4
CK and /CK
Input capacitance delta,
CK and /CK
CDCK
0.15
0.15
0.15
0.15
2, 3
Input/outputcapacitance
delta,
DQS and /DQS
CDDQS
CI
0
0.2
1.4
0
0.2
0
0.15
1.3
0
0.15
1.3
pF
pF
2, 4
2, 5
Input capacitance,
(control, address,
command, input-only
pins)
0.75
0.75
1.35
0.75
0.75
Input capacitance delta,
(All control input-only
pins)
CDI_CTRL −0.5
0.3
0.5
−0.5
−0.5
0.3
0.5
−0.4
−0.4
0.2
0.4
−0.4
−0.4
0.2
0.4
pF
pF
2, 6, 7
2, 8, 9
Input capacitance delta,
(All addres/command
input-only pins)
CDI_ADD_
−0.5
CMD
Input/outputcapacitance
delta, DQ,DM, DQS,
/DQS, TDQS, /TDQS
CDIO
CZQ
−0.5
0.3
3
−0.5
0.3
3
−0.5
0.3
3
−0.5
0.3
3
pF
pF
2, 10
2, 11
Input/outputcapacitance
of ZQ pin
⎯
⎯
⎯
⎯
Table 17: Pin Capacitance [DDR3-1866] (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V)
DDR3-1866
Parameter
Symbol
Min
Max
Units
Notes
Input/output capacitance
CIO
1.4
2.2
pF
1, 2
Input capacitance,
CK and /CK
CCK
0.8
0
1.3
pF
pF
pF
2
Input capacitance delta, CK and /CK CDCK
0.15
0.15
2, 3
2, 4
Input/output capacitance delta,
CDDQS
0
DQS and /DQS
Input capacitance,
(control, address, command, input- CI
only pins)
0.75
1.2
pF
2, 5
Input capacitance delta,
(All control input-only pins)
CDI_CTRL
−0.4
0.2
0.4
pF
pF
2, 6, 7
2, 8, 9
Input capacitance delta, (All
addres/command input-only pins)
CDI_ADD_CMD −0.4
Input/output capacitance delta,
DQ,DM, DQS, /DQS, TDQS, /TDQS
CDIO
−0.5
0.3
3
pF
pF
2, 10
2, 11
Input/output capacitance of ZQ pin CZQ
⎯
Notes: 1. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS.
2. VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, /RESET and ODT as
necessary). VDD = VDDQ = 1.5V, VBIAS=VDD/2 and ondie termination off.
3. Absolute value of CCK-C/CK.
4. Absolute value of CIO(DQS)-CIO(/DQS).
Data Sheet E1772E40 (Ver. 4.0)
20
EDJ2104BDBG, EDJ2108BDBG
5. CI applies to ODT, /CS, CKE, A0-A15, BA0-BA2, /RAS, /CAS and /WE.
6. CDI_CTRL applies to ODT, /CS and CKE.
7. CDI_CTRL = CI(CTRL) − 0.5 × (CI(CK)+CI(/CK)).
8. CDI_ADD_CMD applies to A0-A15, BA0-BA2, /RAS, /CAS and /WE.
9. CDI_ADD_CMD = CI(ADD_CMD) − 0.5 × (CI(CK)+CI(/CK)).
10. CDIO=CIO(DQ,DM) − 0.5 × (CIO(DQS)+CIO(/DQS)).
11. Maximum external load capacitance on ZQ pin: 5pF.
Data Sheet E1772E40 (Ver. 4.0)
21
EDJ2104BDBG, EDJ2108BDBG
2.3 Standard Speed Bins
Table 18: DDR3-800 Speed Bins
Speed Bin
DDR3-800E
6-6-6
min
15
CL-tRCD-tRP
Symbol
/CAS write latency
max
20
Unit
ns
Notes
tAA
10
tRCD
15
⎯
ns
10
tRP
15
⎯
ns
10
tRC
52.5
37.5
3.0
⎯
ns
10
tRAS
9 × tREFI
3.3
ns
9
tCK(avg) @CL=5
tCK(avg) @CL=6
Supported CL settings
Supported CWL settings
CWL = 5
CWL = 5
ns
1, 2, 3, 11
1, 2, 3, 11
2.5
3.3
ns
5, 6
nCK
nCK
5
Table 19: DDR3-1066 Speed Bins
Speed Bin
DDR3-1066F
7-7-7
CL-tRCD-tRP
Symbol
/CAS write latency
min
max
Unit
ns
Notes
tAA
13.125
13.125
13.125
50.625
37.5
20
10
tRCD
⎯
ns
10
tRP
⎯
ns
10
tRC
⎯
ns
10
tRAS
9 × tREFI
3.3
ns
9
tCK(avg) @CL=5
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
3.0
ns
1, 2, 3, 4, 5, 11
Reserved
2.5
Reserved
3.3
ns
4
tCK(avg) @CL=6
tCK(avg) @CL=7
tCK(avg) @CL=8
ns
1, 2, 3, 5
Reserved
Reserved
1.875
Reserved
Reserved
< 2.5
ns
4
ns
4
ns
1, 2, 3, 4
4
Reserved
1.875
Reserved
< 2.5
ns
ns
1, 2, 3
Supported CL settings
Supported CWL settings
5, 6, 7, 8
5, 6
nCK
nCK
Data Sheet E1772E40 (Ver. 4.0)
22
EDJ2104BDBG, EDJ2108BDBG
Table 20: DDR3-1333 Speed Bins
Speed Bin
DDR3-1333H
9-9-9
CL-tRCD-tRP
Symbol
/CAS write latency
min
max
Unit
Notes
13.5
tAA
20
ns
10
(13.125)
13.5
tRCD
tRP
⎯
⎯
⎯
ns
ns
ns
10
10
10
(13.125)
13.5
(13.125)
49.5
tRC
(49.125)
tRAS
36
9 × tREFI
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
9
tCK(avg) @CL=5
CWL = 5
CWL = 6, 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6
CWL= 7
3.0
1, 2, 3, 4, 6, 11
Reserved
2.5
Reserved
3.3
4
tCK(avg) @CL=6
tCK(avg) @CL=7
tCK(avg) @CL=8
1, 2, 3, 6
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
< 2.5
4
4
4
1, 2, 3, 4, 6
Reserved
Reserved
1.875
Reserved
Reserved
< 2.5
4
4
1, 2, 3, 6
Reserved
Reserved
1.5
Reserved
Reserved
< 1.875
Reserved
< 1.875
4
tCK(avg) @CL=9
tCK(avg) @CL=10
4
1, 2, 3, 4
4
CWL = 5, 6
CWL= 7
Reserved
1.5
1, 2, 3
Supported CL settings
Supported CWL settings
5, 6, 7, 8, 9, 10
5, 6, 7
Data Sheet E1772E40 (Ver. 4.0)
23
EDJ2104BDBG, EDJ2108BDBG
Table 21: DDR3-1600 Speed Bins
Speed Bin
DDR3-1600K
11-11-11
min
CL-tRCD-tRP
Symbol
/CAS write latency
max
Unit
Notes
13.75
tAA
20
ns
10
(13.125)
13.75
tRCD
tRP
⎯
⎯
⎯
ns
ns
ns
10
10
10
(13.125)
13.75
(13.125)
48.75
tRC
(48.125)
tRAS
35
9 × tREFI
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
9
tCK(avg) @CL=5
CWL = 5
CWL = 6, 7, 8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
CWL= 7
3.0
1, 2, 3, 4, 7, 11
Reserved
2.5
Reserved
3.3
4
tCK(avg) @CL=6
tCK(avg) @CL=7
1, 2, 3, 7
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
< 2.5
4
4
4
1, 2, 3, 4, 7
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
< 2.5
4
4
tCK(avg) @CL=8
4
1, 2, 3, 7
Reserved
Reserved
Reserved
1.5
Reserved
Reserved
Reserved
< 1.875
4
4
tCK(avg) @CL=9
tCK(avg) @CL=10
tCK(avg) @CL=11
4
1, 2, 3, 4, 7
CWL= 8
Reserved
Reserved
1.5
Reserved
Reserved
< 1.875
4
CWL = 5, 6
CWL= 7
4
1, 2, 3, 7
CWL= 8
Reserved
Reserved
1.25
Reserved
Reserved
< 1.5
4
CWL = 5, 6, 7
CWL= 8
4
1, 2, 3
Supported CL settings
Supported CWL settings
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Data Sheet E1772E40 (Ver. 4.0)
24
EDJ2104BDBG, EDJ2108BDBG
Table 22: DDR3-1866 Speed Bins
Speed Bin
DDR3-1866M
13-13-13
min
CL-tRCD-tRP
Symbol
/CAS write latency
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
Notes
tAA
13.91
20.0
tRCD
13.91
⎯
tRP
13.91
⎯
tRC
47.91
⎯
tRAS
34.0
9 × tREFI
3.3
9
tCK(avg) @CL=5
CWL = 5
3.0
1, 2, 3, 8
CWL = 6, 7, 8, 9
CWL = 5
Reserved
2.5
Reserved
3.3
4
tCK(avg) @CL=6
tCK(avg) @CL=7
tCK(avg) @CL=8
1, 2, 3, 8
CWL = 6
Reserved
Reserved
Reserved
1.875
Reserved
Reserved
Reserved
2.5
4
CWL = 7, 8, 9
CWL = 5
4
4
CWL = 6
1, 2, 3, 8
CWL = 7, 8, 9
CWL = 5
Reserved
Reserved
1.875
Reserved
Reserved
2.5
4
4
CWL = 6
1, 2, 3, 8
CWL = 7
Reserved
Reserved
Reserved
1.5
Reserved
Reserved
Reserved
1.875
4
CWL = 8, 9
CWL = 5, 6
CWL= 7
4
tCK(avg) @CL=9
4
1, 2, 3, 8
CWL= 8
Reserved
Reserved
Reserved
1.5
Reserved
Reserved
Reserved
1.875
4
CWL= 9
4
tCK(avg) @CL=10
tCK(avg) @CL=11
CWL = 5, 6
CWL= 7
4
1, 2, 3, 8
CWL= 8
Reserved
Reserved
1.25
Reserved
Reserved
1.5
4
CWL = 5, 6, 7
CWL= 8
4
1, 2, 3, 8
CWL= 9
Reserved
Reserved
Reserved
Reserved
1.07
Reserved
Reserved
Reserved
Reserved
1.25
4
tCK(avg) @CL=12
tCK(avg) @CL=13
CWL = 5, 6, 7, 8
CWL= 9
4
4
CWL = 5, 6, 7, 8
CWL= 9
4
4
Supported CL settings
Supported CWL settings
5, 6, 7, 8, 9, 10, 11, 13
5, 6, 7, 8, 9
1, 2, 3, 8
Data Sheet E1772E40 (Ver. 4.0)
25
EDJ2104BDBG, EDJ2108BDBG
Notes: 1. The CL setting and CWL setting result in tCK(avg)min and tCK(avg)max requirements. When making a selection of
tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(avg)min limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
tCK(avg) value (3.0, 2.5, 1.875, 1.5, or 1.25ns) when calculating CL(nCK) = tAA(ns) / tCK(avg)(ns), rounding up to the
next ‘Supported CL’.
3. tCK(avg)max limits: Calculate tCK(avg) + tAA(max)/CL selected and round the resulting tCK(avg) down to the next valid
speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK(avg)max corresponding to CL selected.
4. Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1066
Speed Bins which are not subject to production tests but verified by design/characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1333
Speed Bins which is not subject to production tests but verified by design/characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1600
Speed Bins which is not subject to production tests but verified by design/characterization.
8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1866
Speed Bins which is not subject to production tests but verified by design/characterization.
9. tREFI depends on operating case temperature (TC).
10. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min) must be 13.125 ns or lower. SPD
settings must be programmed to match.
11. DDR3-800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
Data Sheet E1772E40 (Ver. 4.0)
26
EDJ2104BDBG, EDJ2108BDBG
3. Package Drawing
3.1 78-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
7.50 ± 0.10
0.20 S B
INDEX MARK
0.20 S A
0.20 S
1.20 max.
S
0.35 ± 0.05
0.10 S
M S A B
φ0.15
78-φ0.45 ± 0.05
B
A
INDEX MARK
1.6 0.8
6.4
ECA-TS2-0306-01
Data Sheet E1772E40 (Ver. 4.0)
27
EDJ2104BDBG, EDJ2108BDBG
4. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the 2G bits DDR3 SDRAM.
Type of Surface Mount Device
EDJ2104BDBG, EDJ2108BDBG: 78-ball FBGA < Lead free (Sn-Ag-Cu) >
Data Sheet E1772E40 (Ver. 4.0)
28
EDJ2104BDBG, EDJ2108BDBG
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E1772E40 (Ver. 4.0)
29
EDJ2104BDBG, EDJ2108BDBG
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other
such application in which especially high quality and reliability is demanded or where its failure or
malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to
contact Elpida Memory's sales office before using this product for such applications.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL2, H2S, NH3,
SO2, and NO .
x
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E1007
Data Sheet E1772E40 (Ver. 4.0)
30
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