EDK1216CFBJ-75-F [ELPIDA]
128M bits DDR Mobile RAM™; 128M DDR位移动RAM
| 型号： | EDK1216CFBJ-75-F |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 128M bits DDR Mobile RAM™ |
| 文件： | 总56页 (文件大小：708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
128M bits DDR Mobile RAM
EDK1216CFBJ (8M words × 16 bits)
Specifications
Pin Configurations
• Density: 128M bits
• Organization
/xxx indicates active low signal.
60-ball FBGA
2M words × 16 bits × 4 banks
1
2
3
4
5
6
7
8
9
10
• Package: 60-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.7V to 1.95V
• Clock frequency: 133MHz (max.)
• 1KB page size
A
B
C
D
E
VSS DQ15 VSSQ
VDDQ DQ13 DQ14
VSSQ DQ11 DQ12
VDDQ DQ9 DQ10
VSSQ UDQS DQ8
VDDQ DQ0
VDD
DQ1
DQ3
DQ5
DQ2 VSSQ
DQ4 VDDQ
DQ6 VSSQ
Row address: A0 to A11
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
DQ7 LDQS VDDQ
• Burst lengths (BL): 2, 4, 8, 16
• Burst type (BT):
Sequential (2, 4, 8, 16)
Interleave (2, 4, 8, 16)
• /CAS Latency (CL): 3
F
G
H
UDM
CK
VSS
CKE
A9
NC
/CK
NC
A8
VDD
NC
/WE
/CS
LDM
/CAS /RAS
BA1
A1
A11
A7
BA0
A0
J
• Precharge: auto precharge option for each burst
A6
A10
A2
access
K
VSS
A4
A5
A3
VDD
• Driver strength: normal, 1/2, 1/4, 1/8
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
• Operating ambient temperature range
TA =−25°C to +85°C
(Top View)
Address input
A0 to A11
BA0, BA1
DQ0 to DQ15
UDQS, LDQS
/CS
Bank select address
Data-input/output
Input and output data strobe
Chip select
/RAS
/CAS
/WE
UDM, LDM
CK
/CK
CKE
VDD
Row address strobe
Column address strobe
Write enable
Write data mask
Clock input
Features
• Low power consumption
• Partial Array Self-Refresh (PASR)
Differential clock input
Clock enable
• Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
VSS
• Double-data-rate architecture; two data transfers per
VDDQ
VSSQ
NC
one clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Burst termination by burst stop command and
Precharge command
Document No. E1194E20 (Ver. 2.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2009
EDK1216CFBJ
Ordering Information
Organization
(words × bits)
Internal
banks
Clock frequency Data rate
Part number
MHz (max.)
Mbps (max.)
/CAS latency
Package
EDK1216CFBJ-75-F
8M × 16
4
133
266
3
60-ball FBGA
Part Number
E D K 12 16 C F BJ - 75 - F
Elpida Memory
Type
Environment Code
F: Lead Free (RoHS compliant)
and Halogen Free
D: Monolithic Device
Speed
75: 133MHz
Product Family
K: DDR Mobile RAM
Density/Page size
12: 128Mb/1KB
Package
BJ: FBGA
Organization
16: x16
Power Supply, Interface
C: VDD = 1.8V, VDDQ = 1.8V, LVCMOS
Die Rev.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
2
EDK1216CFBJ
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram.............................................................................................................................19
Operation of the DDR Mobile RAM .............................................................................................................20
Timing Waveforms.......................................................................................................................................44
Package Drawing ........................................................................................................................................53
Recommended Soldering Conditions..........................................................................................................54
Preliminary Data Sheet E1194E20 (Ver. 2.0)
3
EDK1216CFBJ
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
VT
Rating
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +2.45
–0.5 to +2.45
50
VDD
IOS
PD
V
mA
W
1.0
Operating ambient temperature
Storage temperature
TA
–25 to +85
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = −25°C to +85°C)
Parameter
Pins
Symbol
min.
1.70
typ.
1.8
max.
1.95
Unit
V
Notes
VDD,
VDDQ
Supply voltage
VSS,
0
0
0
V
V
V
VSSQ
DC input voltage level
CK, /CK
VIN (DC)
–0.3
—
VDDQ + 0.3
0.6 × VDDQ
AC Input differential cross
point voltage
VIX
0.4 × VDDQ
0.5 × VDDQ
5
DC input differential voltage
AC input differential voltage
DC input high voltage
DC input low voltage
VID (DC)
VID (AC)
0.4 × VDDQ
0.6 × VDDQ
—
—
—
—
—
—
VDDQ + 0.6
VDDQ + 0.6
VDDQ + 0.3
0.3 × VDDQ
VDDQ + 0.3
0.2 × VDDQ
V
V
V
V
V
V
4
4
VIHD (DC) 0.7× VDDQ
VILD (DC) –0.3
VIHD (AC) 0.8× VDDQ
VILD (AC) –0.3
1, 2
DQ, DM, DQS,
address, bank
select address,
command signals
AC input high voltage
AC input low voltage
Notes: 1. VIH (max.) = 2.45V (pulse width ≤ 5ns).
2. VIL (min.) = –0.5V (pulse width ≤ 5ns).
3. All voltage referred to VSS and VSSQ must be same potential.
4. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and the input
level on /CK.
5. The value of VIX is expected to be 0.5 × VDDQ and must track variations in the DC level of the same.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
4
EDK1216CFBJ
DC Characteristics 1 (TA = –25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol Grade
max.
Unit
Test condition
Notes
tRC ≥ tRC (min.), CKE ≥ VIH (min.),
tCK = tCK (min.)
Address and Command input signals are
changed one time during 2tCK. Data input
signals are stable
Operating current
IDD0
40
mA
Standby current in power down
IDD2P
0.8
0.6
mA
mA
CKE ≤ VIL (max.), tCK = tCK (min.)
CKE ≤ VIL (max.), tCK = ∞
Standby current in power down
(input signal stable)
IDD2PS
CKE ≥ VIH (min.), tCK = tCK (min.),
/CS ≥ VIH (min.),
Standby current in non power down IDD2N
4.0
mA
Input signals are changed one time during
2tCK.
CKE ≥ VIH (min.), tCK = ∞,
Standby current in non power down
IDD2NS
2.0
3.0
2.0
mA
mA
mA
Address and Command Input signals are
(input signal stable)
stable. DQ and DQS are Don't care.
Active standby current in power
down
IDD3P
CKE ≤ VIL (max.), tCK = tCK (min.)
CKE ≤ VIL (max.), tCK = ∞
Active standby current in power
down
IDD3PS
IDD3N
(input signal stable)
CKE ≥ VIH (min.), tCK = tCK (min.),
/CS ≥ VIH (min.),
Input signals are changed one time during
2tCK.
Active standby current in non power
down
10
mA
mA
CKE ≥ VIH (min.), tCK = ∞,
Active standby current in non power
down (input signal stable)
IDD3NS
7.0
Address and Command Input signals are
stable. DQ and DQS are Don't care.
Burst length = 4, tCK ≥ tCK (min.),
IOUT = 0mA, One bank active, 50 % data
changing each burst
Burst operating current
Refresh current
IDD4
IDD5
80
70
mA
mA
1
2
tRFC ≥ tRFC (min.)
Advanced Data Retention Current
(TA = –25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
IDD6
Grade
typ.
—
max.
140
Unit
Condition
Notes
Advanced data retention current
(Self-refresh current)
PASR="000" (Full)
PASR="001" (2BK)
PASR="010" (1BK)
PASR="000" (Full)
PASR="001" (2BK)
PASR="010" (1BK)
µA
−25°C ≤ TA ≤ +45°C
CKE ≤ 0.2V
—
—
—
—
—
120
110
210
160
140
µA
µA
µA
µA
µA
IDD6
+45°C < TA ≤ +85°C
CKE ≤ 0.2V
Preliminary Data Sheet E1194E20 (Ver. 2.0)
5
EDK1216CFBJ
Notes: 1. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured on condition that addresses are changed only one time during
tCK (min.).
2. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
ILI
min.
–2.0
max.
2.0
Unit
µA
Test condition
Notes
Input leakage current
0 ≤ VIN ≤ VDDQ
0 ≤ VOUT ≤ VDDQ,
DQ = disable
Output leakage current
ILO
–1.5
1.5
µA
Output high voltage
Output low voltage
VOH
VOL
0.9 × VDDQ
—
V
V
IOH = − 0.1mA
—
0.1 × VDDQ
IOL = 0.1 mA
Pin Capacitance (TA = +25°C, VDD and VDDQ = 1.7V to 1.95V)
Parameter
Symbol
CI1
Pins
min.
1.5
1.5
—
typ.
—
—
—
—
—
—
max.
3.5
Unit
pF
pF
pF
pF
pF
pF
Notes
Input capacitance
CK, /CK
1
CI2
All other input-only pins
CK, /CK
3.0
1
Delta input capacitance
Cdi1
Cdi2
CI/O
Cdio
0.25
0.5
1
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
—
1
Input/output capacitance
2.0
—
4.5
1, 2
1
Delta input/output capacitance
0.5
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
TA = +25°C.
2. DOUT circuits are disabled.
AC Characteristics (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
tCK
min.
max.
100
0.55
0.55
—
Unit
ns
Notes
Clock cycle time
7.5
CK high-level width
tCH
0.45
tCK
tCK
tCK
ns
CK low-level width
tCL
0.45
CK half period
tHP
min. ( tCH, tCL)
DQ output access time from CK, /CK
DQS-in cycle time
tAC
2.5
6.0
1.1
6.0
6.0
—
2, 8
tDSC
tDQSCK
tHZ
0.9
tCK
ns
DQS output access time from CK, /CK
DQ-out high-impedance time from CK, /CK
DQ-out low-impedance time from CK, /CK
DQS to DQ skew
2.5
2, 8
5, 8
6, 8
3
—
ns
tLZ
1.0
ns
tDQSQ
tQH
—
0.6
—
ns
DQ/DQS output hold time from DQS
Data hold skew factor
tHP − tQHS
—
ns
4
tQHS
tDS
0.75
—
ns
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Read preamble
0.8
ns
3
3
tDH
0.8
—
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPRE
tWPST
1.8
—
ns
0.9
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
Write preamble setup time
Write preamble
0
0.25
0.4
—
tCK
tCK
Write postamble
0.6
7
Preliminary Data Sheet E1194E20 (Ver. 2.0)
6
EDK1216CFBJ
Parameter
Symbol
tDQSS
tDSS
tDSH
tDQSH
tDQSL
tIS
min.
0.75
0.2
0.2
0.4
0.4
1.3
1.3
2.6
2
max.
1.25
—
Unit
tCK
tCK
tCK
tCK
tCK
ns
Notes
Write command to first DQS latching transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
—
0.6
0.6
—
DQS input low pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command period
3
3
3
tIH
—
ns
tIPW
—
ns
tMRD
tRAS
tRC
—
tCK
ns
45
120000
—
75
ns
Auto refresh to Active/Auto refresh command period tRFC
97.5
22.5
22.5
15
—
ns
Active to Read/Write delay
tRCD
tRP
—
ns
Precharge to active command period
Active to active command period
Column address to column address delay
Write recovery time
—
ns
tRRD
tCCD
tWR
—
ns
1
tCK
ns
15
—
—
—
—
64
Autoprecharge write recovery and precharge time
Self-Refresh Exit Period
tDAL
tSREX
tWTR
tREF
—
9
120
1
ns
Internal Write to Read command delay
Refresh period
tCK
ms
—
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ and tLZ are specified with 20pF bus loading condition.
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and
minimum 1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next
higher integer.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
7
EDK1216CFBJ
Test Conditions
Parameter
Symbol
Value
Unit
V
Note
Input high voltage
VIH (AC)
VIL (AC)
VID (AC)
0.8 × VDDQ
0.2 × VDDQ
1.4
1
1
1
Input low voltage
V
Input differential voltage, CK and /CK inputs
V
Input differential cross point voltage,
CK and /CK inputs
VIX (AC)
VDDQ/2 with VDD=VDDQ
V
Input signal slew rate
SLEW
CL
1
V/ns
pF
1
Output load
20
Note: 1. VDD = VDDQ
tCK
tCH
tCL
VIH
VIL
/CK
CK
VID
VIX
tLZ
tAC
T
(VIH − VIL)
slew rate =
T
DQOUT
Q1
Q2
VDDQ/2
(DQOUT)
Test Condition (Wave form and Timing Reference)
DQ
CL
Output Load
Preliminary Data Sheet E1194E20 (Ver. 2.0)
8
EDK1216CFBJ
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
7.5ns
Parameter
Symbol
tWPD
tRPD
min.
max.
Unit
tCK
tCK
tCK
Notes
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
3 + BL/2
BL/2
tWRD
2 + BL/2
Burst stop command to write command delay
tBSTW
tBSTZ
3
3
tCK
tCK
(CL = 3)
Burst stop command to DQ high-Z
(CL = 3)
Read command to write command delay
(to output all data)
tRWD
tHZP
3 + BL/2
3
tCK
tCK
(CL = 3)
Pre-charge command to high-Z
(CL = 3)
Write command to data in latency
Write recovery
tWCD
tWR
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
2
DM to data in latency
tDMD
tMRD
tSREX
tRFC
0
Mode register set command cycle time
Self-refresh exit to non-column command
Auto refresh period
2
16
13
2
Power down entry
tPDEN
tPDEX
tCKE
1
2
2
Power down exit to command input
CKE minimum pulse width
1
1
Notes: 1. The device will be into power down mode at the second CK rising edge after CKE to be low level with
NOP or DESL command.
2. If PDEN command is issued but CKE stay in low level just for one clock (=tCKE min.) then CKE return to
high level, the device will not be into power down mode.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
9
EDK1216CFBJ
Block Diagram
CK
/CK
CKE
Bank 3
Bank 2
Bank 1
Address, BA0, BA1
Row
address
buffer
and
Memory cell array
Bank 0
refresh
counter
Mode
register
Sense amp.
Column decoder
Column
address
buffer
and
/CS
/RAS
/CAS
/WE
burst
counter
Data control circuit
Latch circuit
DQS
DM
Input & Output buffer
DQ
Preliminary Data Sheet E1194E20 (Ver. 2.0)
10
EDK1216CFBJ
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the
cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS
and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other
input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A11 (input pins)
Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address is loaded at the cross point of the CK rising edge
and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This column address
becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A11)
Organization
Part number
Row address
AX0 to AX11
Column address
AY0 to AY8
EDK1216CFBJ
× 16 bits
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled.
BA0 and BA1 (input pins)
BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.
(See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
CKE (input pin)
CKE controls power down mode, self-refresh function with other command inputs.
The CKE minimum pulse width should be 1 tCK.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
11
EDK1216CFBJ
DQ0 to DQ15 (input/output pins)
Data are input to and output from these pins.
UDQS and LDQS (input and output pin): DQS provides the read data strobes (as output) and the write data
strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence
Table).
UDM and LDM (input pin)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VDDQ/2.
When DM = high, the data input at the same timing are masked while the internal burst counter will be counting up.
Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
[DQS and DM Correspondence Table]
Part number
Organization
DQS
Data mask
LDM
DQs
EDK1216CFBJ
× 16 bits
LDQS
UDQS
DQ0 to DQ7
DQ8 to DQ15
UDM
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers. VDD and VDDQ must have same voltage range (1.7V to 1.95V).
Preliminary Data Sheet E1194E20 (Ver. 2.0)
12
EDK1216CFBJ
Command Operation
Command Truth Table
The DDR Mobile RAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Command
Symbol
DESL
NOP
n – 1
H
n
/CS /RAS /CAS /WE BA1 BA0 AP
Address
Ignore command
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
×
H
H
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
V
V
V
V
V
V
×
×
×
L
×
×
×
V
V
V
V
V
V
×
×
×
L
L
×
×
×
L
H
L
H
V
L
H
×
×
L
L
×
×
×
V
V
V
V
V
×
×
×
×
V
V
No operation
H
Burst stop command
Column address and read command
Read with auto-precharge
Column address and write command
Write with auto-precharge
Row address strobe and bank active
Precharge select bank
Precharge all bank
BST
H
READ
READA
WRIT
WRITA
ACT
H
H
H
L
H
L
H
L
H
L
L
H
H
H
H
L
H
L
PRE
H
L
PALL
REF
H
L
L
Refresh
H
L
H
H
L
SELF
MRS
H
L
L
Mode register set
H
H
H
L
L
EMRS
H
L
L
L
H
Remark: H: VIH. L: VIL. ×: Don’t Care V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is high at the cross point of the CK rising edge and the VDDQ/2 level, all input signals are neglected and
internal state is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VDDQ/2 level, address and data
input are neglected and internal state is held.
Burst stop command [BST]
This command stops a current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
all output buffers become high-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
13
EDK1216CFBJ
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register, to defines
how it works. The both mode registers are set through the address pins (the A0 to the A11, BA0 to BA1) in the
mode register set cycle. For details, refer to "Mode register and extended mode register set".
Preliminary Data Sheet E1194E20 (Ver. 2.0)
14
EDK1216CFBJ
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR Mobile RAM.
Current state
Precharging*1
/CS
H
L
/RAS /CAS /WE
Address
Command
DESL
Operation
NOP
×
×
×
×
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
L
×
BST
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
NOP
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
L
L
H
H
L
H
L
L
L
PRE, PALL
L
L
×
ILLEGAL
NOP
Idle*2
H
L
×
×
×
×
DESL
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
L
×
BST
NOP
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
READ/READA
WRIT/WRITA
ACT
ILLEGAL*11
ILLEGAL*11
Activating
NOP
L
L
L
H
H
H
L
L
L
PRE, PALL
Refresh/
L
L
H
L
L
×
L
L
×
H
L
×
REF, SELF
MRS
Self-refresh*12
MODE
Mode register set*12
Refresh
×
×
DESL
NOP
(auto-refresh)*3
L
H
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
L
H
H
L
H
L
×
NOP
BST
NOP
×
ILLEGAL
×
×
×
H
L
×
ILLEGAL
×
×
ILLEGAL
Activating*4
×
×
×
DESL
NOP
H
H
H
H
L
H
H
L
×
NOP
NOP
×
BST
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE, PALL
L
×
×
H
L
×
Active*5
×
×
×
DESL
NOP
H
H
H
H
L
H
H
L
×
NOP
NOP
×
BST
NOP
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
Starting read operation
Starting write operation
ILLEGAL*11
Pre-charge
ILLEGAL
L
H
H
L
H
L
L
PRE, PALL
L
×
Preliminary Data Sheet E1194E20 (Ver. 2.0)
15
EDK1216CFBJ
Current state
Read*6
/CS
H
/RAS /CAS /WE
Address
Command
DESL
NOP
Operation
NOP
×
×
×
H
L
×
×
×
L
H
H
H
H
NOP
L
BST
Burst stop
Interrupting burst read
operation to
L
H
L
H
BA, CA, A10
READ/READA
start new read
L
L
H
L
L
L
BA, CA, A10
BA, RA
WRIT/WRITA
ACT
ILLEGAL*13
ILLEGAL*11
H
H
Interrupting burst read
operation to start pre-
charge
L
L
H
L
BA, A10
PRE, PALL
L
L
L
×
×
×
×
ILLEGAL
Read with auto-pre-
charge*7
H
×
×
DESL
NOP
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*11
ILLEGAL*11
ILLEGAL
NOP
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE, PALL
L
×
×
×
×
×
Write*8
×
×
×
DESL
NOP
BST
H
H
H
H
H
L
NOP
Burst Stop
Interrupting burst write
operation to
L
H
L
H
BA, CA, A10
BA, CA, A10
READ/READA
start read operation.
Interrupting burst write
operation to
L
H
L
L
WRIT/WRITA
start new write
operation.
L
L
L
L
H
H
H
L
BA, RA
ACT
ILLEGAL*11
Interrupting write operation
to start pre-charge.
BA, A10
PRE, PALL
L
H
L
L
L
L
L
×
×
ILLEGAL
Write recovering*9
×
×
×
×
DESL
NOP
H
H
H
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
H
BA, CA, A10
READ/READA
Starting read operation.
Starting new write
operation.
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL*11
ILLEGAL*11
ILLEGAL
PRE/PALL
×
Preliminary Data Sheet E1194E20 (Ver. 2.0)
16
EDK1216CFBJ
Current state
/CS
H
/RAS /CAS /WE
Address
Command
DESL
Operation
NOP
Write with auto- pre-
×
×
×
×
charge*10
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*11
ILLEGAL*11
ILLEGAL
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRIT A
ACT
L
H
H
L
H
L
L
PRE, PALL
L
×
Remark: H: VIH. L: VIL. ×: Don’t Care
Notes: 1. The DDR Mobile RAM is in "Precharging" state for tRP after precharge command is issued.
2. The DDR Mobile RAM reaches "IDLE" state tRP after precharge command is issued.
3. The DDR Mobile RAM is in "Refresh" state for tRFC after auto-refresh command is issued.
4. The DDR Mobile RAM is in "Activating" state for tRCD after ACT command is issued.
5. The DDR Mobile RAM is in "Active" state after "Activating" is completed.
6. The DDR Mobile RAM is in "READ" state until burst data have been output and DQ output circuits are
turned off.
7. The DDR Mobile RAM is in "READ with auto-precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR Mobile RAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR Mobile RAM is in "Write recovering" for tWR after the last data are input.
10. The DDR Mobile RAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
17
EDK1216CFBJ
CKE Truth Table
CKE
n – 1
H
Current state
Command
n
/CS
L
/RAS /CAS /WE
Address
Notes
Idle
Idle
Auto-refresh command (REF)
Self-refresh entry (SELF)
H
L
L
L
H
H
H
×
×
×
×
×
×
×
×
×
2
2
H
L
L
L
H
L
L
H
×
H
×
Idle/Active
Power down entry (PDEN)
Self refresh exit (SELFX)
Power down exit (PDEX)
H
L
H
L
L
H
H
H
H
H
×
H
×
H
×
Self refresh
Power down
L
H
L
L
H
×
H
×
H
×
L
H
Notes: 1. H: VIH . L: VIL × : Don’t Care .
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 clock cycle at least.
Auto-refresh command [REF]
This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start. Precharge has been
completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-
refresh command.
The average refresh cycle is 15.6µs. To allow for improved efficiency in scheduling, some flexibility in the absolute
refresh interval (64ms) is provided. A maximum of eight auto-refresh commands can be posted to the DDR Mobile
RAM or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is
8 × tREF.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 2 clocks) after the cycle when [PDEN] is issued, the DDR Mobile RAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held low. No internal refresh operation occurs during the power down mode.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state.
Power down exit [PDEX]
The DDR Mobile RAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
18
EDK1216CFBJ
Simplified State Diagram
SELF
REFRESH
EXTENDED
MODE
REGISTER
SET
SR ENTRY
SR EXIT
MRS
REFRESH
MODE
REGISTER
SET
AUTO
REFRESH
IDLE
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
POWER
DOWN
ACTIVE
CKE_
CKE
BST
WRITE
ROW
ACTIVE
BST
READ
WRITE
WRITE
WITH
AP
READ
WITH
AP
READ
WRITE
READ
READ
READ
WITH AP
WRITE
WITH AP
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
Automatic sequence
Manual input
Preliminary Data Sheet E1194E20 (Ver. 2.0)
19
EDK1216CFBJ
Operation of the DDR Mobile RAM
Initialization
The DDR Mobile RAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 200µs or longer pause must precede any signal toggling.
VDD should be turned on simultaneously or before VDDQ.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed.
(4) The mode register must be programmed and the extended mode register should be programmed. After the
mode register set cycle or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be
satisfied.
Remarks:
1
The sequence of Auto refresh, mode register programming and extended mode register programming above may
be transposed.
2
CKE must be held high until the Precharge command is issued to ensure data-bus high-Z.
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A11 and BA0 and BA1 pins by the mode register set
command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode
register are set by inputting signal via the A0 to the A11 and BA0 and BA1 pins during mode register set cycles.
BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a
write operation, the mode register must be set.
Mode register
The mode register has four fields;
Reserved
: A11 through A7
: A6 through A4
: A3
/CAS latency
Wrap type
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have elapsed.
/CAS Latency
/CAS latency must be set to 3.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become high-Z. The burst length is programmable as 2, 4, 8 and 16.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each wrap
type.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
20
EDK1216CFBJ
Extended Mode Register
The extended mode register has three fields;
Reserved
Driver Strength
: A11 through A7, A4, A3
: A6 through A5
Partial Array Self Refresh
: A2 through A0
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.
Note: EMRS has default value at power up. [A9 : A0] = [00 0000 0000].
Driver Strength
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.
Advanced Temperature Compensated Self Refresh (ATCSR)
The DDR Mobile RAM automatically changes the self-refresh cycle by on die temperature sensor. No extended
mode register program is required. Manual TCSR (Temperature Compensated Self-Refresh) is not implemented.
Partial Array Self Refresh
Memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data
outside the defined area will not be retained during self-refresh.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
21
EDK1216CFBJ
Power-Down Mode and CKE Control
DDR Mobile RAM will be into power-down mode at the second CK rising edge after CKE to be low level with NOP or
DESL command at first CK rising edge after CKE signal to be low.
CK
/CK
CKE
Valid*1
Valid*1
NOP
NOP
Valid*2
Valid*2
NOP
Command
Address
Power-down mode
Notes: 1. Valid*1 can be either Activate command or Precharge command, When Valid*1 is Activate command,
power-down mode will be active power-down mode, while it will be precharge power down mode,
if Valid*1 will be Precharge command.
2. Valid*2 can be any command as long as all of specified AC parameters are satisfied.
Power-Down Entry and Exit
However, if the CKE has one clock cycle high and on clock cycle low just as below, even DDR Mobile RAM will not
enter power-down mode, this command flow does not hurt any data and can be done.
CK
/CK
CKE
Command
PRE
NOP
NOP
ACT
Note: Assume PRE and ACT command is closing and activating same bank.
CKE Control
Preliminary Data Sheet E1194E20 (Ver. 2.0)
22
EDK1216CFBJ
Mode Register Definition
BA1 BA0 A11 A10 A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
BL
A0
0
0
0
0
0
LTMODE
WT
Mode Register Set
Bits2-0
000
WT = 0
WT = 1
R
2
R
2
001
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
010
4
4
R
R
R
3
Burst length
011
100
101
110
111
8
8
16
R
R
R
16
R
R
R
Latency
mode
R
R
R
R
0
1
Sequential
Interleave
Wrap type
BA1 BA0 A11 A10 A9
A8
A7
0
A6
A5
A4
0
A3
0
A2
A1
A0
1
0
0
0
0
DS
PASR
Extended Mode Register Set
Bits2-0 Refresh Array
0
000
001
010
011
100
101
110
111
All banks
Bank A & Bank B (BA1=0)
Bank A (BA0=BA1=0)
Partial Array
Self Refresh
R
R
R
R
R
Bits6-5 Strength
00
01
10
11
Normal
1/2 strength
1/4 strength
1/8 strength
Driver Strength
Remark R : Reserved
Preliminary Data Sheet E1194E20 (Ver. 2.0)
23
EDK1216CFBJ
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
Starting Ad. Addressing(decimal)
A0
0
Sequence Interleave
A1
0
A0 Sequence
Interleave
0, 1, 2,
1, 0, 3,
2, 3, 0,
3, 2, 1,
0,
1,
1
0
0,
1,
1
0
0
1
0
1
0, 1, 2,
1, 2, 3,
2, 3, 0,
3
0
1
2
3
2
1
0
1
0
1
1
3,
0, 1,
Burst length = 8
Starting Ad.
Addressing(decimal)
A2 A1 A0 Sequence
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0, 1, 2, 3, 4, 5, 6,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7, 0,
3, 4, 5, 6, 7, 0, 1,
4, 5, 6, 7, 0, 1, 2,
5, 6, 7, 0, 1, 2, 3,
6, 7, 0, 1, 2, 3, 4,
7, 0, 1, 2, 3, 4, 5,
7
0
1
2
3
4
5
6
0, 1, 2, 3, 4, 5, 6,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7, 4,
3, 2, 1, 0, 7, 6, 5,
4, 5, 6, 7, 0, 1, 2,
5, 4, 7, 6, 1, 0, 3,
6, 7, 4, 5, 2, 3, 0,
7, 6, 5, 4, 3, 2, 1,
7
6
5
4
3
2
1
0
Burst length = 16
Starting Ad.
Addressing(decimal)
A3 A2 A1 A0 Sequence
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
Interleave
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14
2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13
3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11
5, 4, 7, 6, 1, 0, 3, 2, 13, 12, 15, 14, 9, 8, 11, 10
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0,
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1,
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2,
5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3,
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4,
7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5,
8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6,
9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7,
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8,
0
1
2
3
4
5
6
7
8
9
6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8,
7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9,
8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6,
9, 8, 11, 10, 13, 12, 15, 14, 1, 0, 3, 2, 5, 4, 7,
10, 11, 8, 9, 14, 15, 12, 13, 2, 3, 0, 1, 6, 7, 4,
9
8
7
6
5
4
3
2
1
0
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11, 10, 9, 8, 15, 14, 13, 12, 3, 2, 1, 0, 7, 6, 5,
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2,
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 13, 12, 15, 14, 9, 8, 11, 10, 5, 4, 7, 6, 1, 0, 3,
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0,
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
Preliminary Data Sheet E1194E20 (Ver. 2.0)
24
EDK1216CFBJ
Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, 8 or 16. The starting address of the burst read is defined by the column address, the bank
select address which is loaded via the A0 to A11 and BA0 and BA1 pins in the cycle when the read command is
issued. The data output timing is characterized by CL and tAC. The read burst start (CL-1) × tCK + tAC (ns) after
the clock rising edge where the read command is latched. The DDR Mobile RAM outputs the data strobe through
DQS pins simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS pins are driven
low from high-Z state. This low period of DQS is referred as read preamble. The burst data are output coincidentally
at both the rising and falling edge of the data strobe. The DQ pins become high-Z in the next cycle after the burst
read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become high-Z. This
low period of DQS is referred as read postamble.
CK
/CK
tRCD
Command
Address
NOP
ACT
Row
NOP
READ
NOP
Column
tRPRE
out0 out1
BL = 2
tRPST
out0 out1 out2 out3
BL = 4
BL = 8
DQS
DQ
out0 out1 out2 out3 out4 out5 out6 out7
out out
14 15
out0 out1 out2 out3 out4 out5 out6 out7
BL = 16
CL = 3
BL: Burst length
Read Operation (Burst Length)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
25
EDK1216CFBJ
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
NOP
Command
tRPRE
tRPST
VTT
VTT
DQS
DQ
tAC,tDQSCK
out0 out1 out2 out3
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
8 or 16. The latency from write command to data input is fixed to 1. The starting address of the burst write is
defined by the column address, the bank select address which is loaded via the A0 to A11, BA0 to BA1 pins in the
cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well
during burst operation. tWPRE prior to the first rising edge of DQS, DQS must be set to low. tWPST after the last
falling edge of DQS, the DQS pins can be changed to high-Z. The leading low period of DQS is referred as write
preamble. The last low period of DQS is referred as write postamble.
Example
CK
/CK
tRCD
Command
Address
NOP
ACT
Row
NOP
WRIT
NOP
Column
tWPRE
tWPRES
in0 in1
BL = 2
tWPST
in0 in1 in2 in3
DQS
DQ
BL = 4
BL = 8
in0 in1 in2 in3 in4 in5 in6 in7
in
in
in0 in1 in2 in3 in4 in5 in6 in7
14 15
BL = 16
BL: Burst length
Write Operation
Preliminary Data Sheet E1194E20 (Ver. 2.0)
26
EDK1216CFBJ
Burst Stop
Burst stop command during burst operation
The burst stop (BST) command stops the burst read and sets all output buffers to high-Z. tBSTZ (= CL) cycles after
a BST command issued, all DQ and DQS pins become high-Z.
The BST command is also supported for the burst write operation. No data will be written in subsequent cycles.
Note that bank address is not referred when this command is executed.
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
Command
BST
NOP
tBSTZ
DQS
DQ
out0 out1
CL: /CAS latency
Burst Stop during a Read Operation
Preliminary Data Sheet E1194E20 (Ver. 2.0)
27
EDK1216CFBJ
Auto-Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts BL/2 (= tRPD)
clocks after READA command input. tRAS lock out mechanism for READA allows a read command with auto
precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min)
specification. A column command to the other active bank can be issued the next cycle after the last data output.
Read with auto-precharge command does not limit row commands execution for other bank.
CK
/CK
tRP (min)
tRAS (min)
tRCD (min)
BL/2 (= tRPD)
ACT
READA
NOP
ACT
Command
DQS
tAC,tDQSCK
DQ
out0 out1 out2 out3
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started (WL) + BL/2 + tWR (= tWPD) clocks after WRITA command issued.
A column command to the other banks can be issued the next cycle after the internal precharge command issued.
Write with auto-precharge command does not limit row commands execution for other bank.
CK
/CK
tRAS (min)
tRP
tRCD (min)
ACT
NOP
WRITA
NOP
ACT
Command
WL + BL/2 + tWR (= tWPD)
DM
DQS
DQ
in1 in2 in3 in4
BL = 4
Note: Internal auto-precharge starts at the timing indicated by " ".
Burst Write (BL = 4)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
28
EDK1216CFBJ
The Concurrent Auto Precharge
The DDR Mobile RAM supports the concurrent auto precharge feature, a read with auto-precharge or a write with
auto-precharge, can be followed by any command to the other banks, as long as that command does not interrupt
the read or write data transfer, and all other related limitations apply (e.g. contention between READ data and
WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge, to a
command to a different bank, is summarized below.
To command (different bank, non-
interrupting command)
Minimum delay
From command
Read w/AP
(Concurrent AP supported)
Units
tCK
tCK
tCK
tCK
tCK
tCK
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
BL/2
CL (rounded up)+ (BL/2)
1
Write w/AP
1 + (BL/2) + tWTR
BL/2
1
Preliminary Data Sheet E1194E20 (Ver. 2.0)
29
EDK1216CFBJ
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
1. Same
Same
Different
Any
ACTIVE
2. Same
—
3. Different
ACTIVE
IDLE
t0
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
NOP
ACT
Row
NOP
READ
READ
Column A Column B
Address
BA
out out out out out out
A0 A1 B0 B1 B2 B3
DQ
Column = A Column = B
Read Read
Column = A
Dout
Column = B
Dout
DQS
Bank0
Active
CL = 3
BL = 4
Bank0
READ to READ Command Interval (same ROW address in the same bank)*
Note: n ≥ 3
Preliminary Data Sheet E1194E20 (Ver. 2.0)
30
EDK1216CFBJ
t0
t1
t2
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
READ
READ
NOP
ACT
NOP
ACT
NOP
Row0
Row1
Column A Column B
Address
BA
out out out out out out
A0 A1 B0 B1 B2 B3
DQ
Column = A Column = B
Read Read
Bank0
Dout
Bank3
Dout
DQS
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
CL = 3
BL = 4
READ to READ Command Interval (different bank)*
Note: n ≥ 3
Preliminary Data Sheet E1194E20 (Ver. 2.0)
31
EDK1216CFBJ
A Write command to the consecutive Write command Interval
Destination row of the consecutive write
command
Bank
address
Row address State
Operation
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive write command can be issued.
1. Same
Same
Different
Any
ACTIVE
2. Same
—
3. Different
ACTIVE
IDLE
t0
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
NOP
ACT
Row
NOP
WRIT
WRIT
Column A Column B
Address
BA
DQ
inA0 inA1 inB0 inB1 inB2 inB3
Column = A
Write
Column = B
Write
DQS
Bank0
Active
BL = 4
Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
32
EDK1216CFBJ
t0
t1
t2
tn
tn+1
tn+2
tn+3
tn+4
tn+5
CK
/CK
Command
NOP
ACT
NOP
ACT
NOP
WRIT
WRIT
Row0
Row1
Column A Column B
Address
BA
DQ
inA0 inA1 inB0 inB1 inB2 inB3
Bank0
Write
Bank3
Write
DQS
Bank0
Active
Bank3
Active
BL = 4
Bank0, 3
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
33
EDK1216CFBJ
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write
command
Bank
address
Row address State
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
1. Same
Same
Different
Any
ACTIVE
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
2. Same
—
3. Different
ACTIVE
IDLE
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
READ
BST
NOP
tBSTW (≥ tBSTZ)
WRIT
NOP
DM
tBSTZ (= CL)
DQ
out0 out1
in0 in1 in2 in3
High-Z
DQS
OUTPUT
INPUT
BL = 4
CL = 3
READ to WRITE Command Interval
Preliminary Data Sheet E1194E20 (Ver. 2.0)
34
EDK1216CFBJ
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
Row address State
address
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
1. Same
2. Same
3. Different
Same
Different
Any
ACTIVE
—
ACTIVE
IDLE
t0
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
tn + 4
CK
/CK
Command
WRIT
NOP
READ
NOP
tWRD (min)
tWTR*
DM
out2
DQ
out0 out1
in0
in1
in2
in3
DQS
INPUT
OUTPUT
BL = 4
CL = 3
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
Preliminary Data Sheet E1194E20 (Ver. 2.0)
35
EDK1216CFBJ
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
Row address State
address
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
1. Same
2. Same
3. Different
Same
Different
Any
ACTIVE
—
—*1
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
ACTIVE
IDLE
—*1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
READ
NOP
DM
High-Z
High-Z
DQ
in0 in1 in2
out0 out1 out2 out3
DQS
BL = 4
CL = 3
Data masked
[WRITE to READ delay = 1 clock cycle]
Preliminary Data Sheet E1194E20 (Ver. 2.0)
36
EDK1216CFBJ
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
DM
High-Z
High-Z
DQ
in0 in1 in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4
CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
tWTR*
DM
DQ
in0 in1 in2
in3
out0 out1 out2 out3
DQS
BL = 4
CL = 3
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
Preliminary Data Sheet E1194E20 (Ver. 2.0)
37
EDK1216CFBJ
A Write command to the Bust stop command interval: To interrupt the write operation
WRITE to BST Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
DM
WRIT
BST
NOP
DQ
in0 in1
DQS
BL = 4 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 1 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
NOP
BST
NOP
DM
DQ
in0 in1 in2
in3
DQS
Data will be written
Following data will not be written.
BL = 8 or longer
[WRITE to BST delay = 2 clock cycle]
Preliminary Data Sheet E1194E20 (Ver. 2.0)
38
EDK1216CFBJ
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
DM
WRIT
NOP
BST
NOP
DQ
in0 in1 in2
in3
in4
in5
DQS
BL = 8 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 3 clock cycle]
Preliminary Data Sheet E1194E20 (Ver. 2.0)
39
EDK1216CFBJ
A Read command to the consecutive Precharge command interval
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
Operation
The PRE and PALL command can interrupt a read operation.
1.
2.
Same
To complete a burst read operation, tRPD is required between the read and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a read command.
No interval timing is required between the read and the precharge command.
Different
READ to PRECHARGE Command Interval (same bank) : To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
PRE/
PALL
Command
DQ
NOP
READ
NOP
NOP
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP
(= CL) after the precharge command.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
DQ
NOP
READ PRE/PALL
NOP
High-Z
High-Z
out0 out1
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
40
EDK1216CFBJ
A Write command to the consecutive Precharge command interval
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
Operation
The PRE and PALL command can interrupt a write operation.
1.
2.
Same
To complete a burst write operation, tWPD is required between the write and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a write command.
No interval timing is required between the write and the precharge command.
Different
WRITE to PRECHARGE Command Interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
t0
t1
t2
t3
t4
tn
tn + 1
tn + 2
CK
/CK
Command
PRE/PALL
WRIT
NOP
tWPD
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
t0
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
CK
/CK
Command
PRE/PALL
WRIT
NOP
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data
input
Data
masked
BL = 4
WRITE to PRECHARGE Command Interval (same bank) (BL = 4, DM to mask data)
Preliminary Data Sheet E1194E20 (Ver. 2.0)
41
EDK1216CFBJ
Bank active command interval
Destination row of the consecutive ACT
command
Bank
address
Row address
State
Operation
Two successive ACT commands can be issued at tRC interval. In between two
1. Same
2. Different
Any
Any
ACTIVE
successive ACT operations, precharge command should be executed.
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
tRRD after an ACT command, the next ACT command can be issued.
ACTIVE
IDLE
CK
/CK
Command
A
C
T
ACT
NOP
PRE
NOP
ACT
NOP
Address
BA
ROW: 0
ROW: 1
ROW: 0
Bank0
Active
Bank3
Active
Bank0
Precharge
Bank0
Active
tRRD
tRC
Bank Active to Bank Active
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK
/CK
Command
MRS
NOP
ACT
NOP
Address
CODE
BS and ROW
Mode Register Set
Bank3
Active
tMRD
Preliminary Data Sheet E1194E20 (Ver. 2.0)
42
EDK1216CFBJ
DM Control
DM can mask input data. By setting DM to low, data can be written. UDM and LDM can mask the upper and lower
byte of input data, respectively. When DM is set to high, the corresponding data is not written, and the previous data
is held. The latency between DM input and enabling/disabling mask function is 0.
t1
t2
t3
t4
t5
t6
DQS
Mask
Mask
DQ
DM
Write mask latency = 0
DM Control
Preliminary Data Sheet E1194E20 (Ver. 2.0)
43
EDK1216CFBJ
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
tIS
tIH
tIH
Command
(/RAS, /CAS,
/WE, /CS)
tIS
Address
= Don't care
Read Timing Definition (1)
CK
/CK
Command
READ
tHZ (max.)
tHZ (min.)
High-Z
tLZ (max.)
tLZ (min.)
High-Z
High-Z
DQ
(Output)
tLZ (max.)
tLZ (min.)
High-Z
DQS
CL = 3
BL = 2
Preliminary Data Sheet E1194E20 (Ver. 2.0)
44
EDK1216CFBJ
Read Timing Definition (2)
/CK
CK
tDQSCK
tAC (min.)
DQS
tAC (min.)
tDSC
Fastest DQ
(Output)
tQH
tDQSQ
Slowest DQ
(Output)
Data valid
window
tDQSCK
tAC (max.)
DQS
tDQSQ
Fastest DQ
(Output)
tQH
tQHS
tAC (max.)
Slowest DQ
(Output)
Data valid
window
BL = 4
= Invalid
Write Timing Definition
tCK
/CK
CK
tDQSS
tDSS
tDSH
tDSS
tDSC
tWPRES
DQS
tDQSL
tDQSH
tWPST
tWPRE
DQ
(Din)
tDIPW
tDIPW
tDS
tDH
tDH
DM
tDS
tDIPW
BL = 4
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
45
EDK1216CFBJ
Power on Sequence*
CK
/CK
Clock cycle is necessary
VIH
CKE
/CS
tMRD
tMRD
2 refresh cycles are necessary
/RAS
/CAS
/WE
BA0
BA1
A10
Address key
Address key
Address
DM
DQ
High-Z
tRP
tRFC
tRFC
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
Extended
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
is necessary
= Don't care
Note: The sequence of auto refresh, mode register programming and extended mode register programming above
may be transposed.
Preliminary Data Sheet E1194E20 (Ver. 2.0)
46
EDK1216CFBJ
Read Cycle
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRP
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
tIS tIH
tIS tIH
/RAS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CAS
tIS tIH
/WE
BA
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
A10
tIS tIH
tIS tIH
tIS tIH
Address
DM
tRPST
tRPRE
tDSC
High-Z
DQS (output)
High-Z
DQ (output)
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
CL = 3
BL = 4
Bank0 Access
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
47
EDK1216CFBJ
Write Cycle
tCK
tCH
tCL
CK
/CK
tRC
VIH
CKE
/CS
tRP
tRAS
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/RAS
/CAS
/WE
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS
tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
BA
tIS tIH
A10
tIS tIH
tIS tIH
tIS tIH
Address
tDQSS
tDQSL
tWPST
tDH
DQS
(input)
tDQSH
tDS
tDS
tDS
DM
tDH
DQ (input)
tDH
tWR
CL = 2
BL = 4
Bank0 Access
Bankk 00
Actiivvee
Bank 0
Write
Bank 0
Precharge
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
48
EDK1216CFBJ
Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
DM
code
code
C: b
R: b
valid
High-Z
High-Z
DQS
DQ
b
tMRD
tRP
Bank 3
Read
Bank 3
Precharge
Mode
register
set
Bank 3
Active
CL = 3
BL = 4
Precharge
If needed
= Don't care
Read/Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 Tn
Tn+1 Tn+2 Tn+3 Tn+4
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:b''
C:a R:b
C:b
DM
DQS
DQ
a
b
b’’
Read
Write
tWRD
Read
tRWD
Bank 0
Active
Bank 0 Bank 3
Read Active
Bank 3
Write
Bank 3
Read
Read cycle
CL = 3
BL = 4
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
49
EDK1216CFBJ
Auto Refresh Cycle
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ
High-Z
High-Z
b
tRP
tRFC
Precharge
If needed
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 3
BL = 4
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
50
EDK1216CFBJ
Self-Refresh Cycle
/CK
CK
tIS
tIH
CKE = low
CKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ
tRP
tSREX
Bank 0
Active
Bank 0
Read
Self refresh
exit
Precharge
If needed
Self
refresh
entry
BL = 4
= Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
51
EDK1216CFBJ
Power Down Entry and Exit
/CK
CK
t
t
IS
IH
CKE = low
CKE
tCKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
R: c
DM
DQS
DQ
tRP
tPDEX
Power Bank 0
tPDEN
Precharge
If needed
Power down
entry
Bank 0
Read
down
exit
Active
BL = 4
=
Don't care
Preliminary Data Sheet E1194E20 (Ver. 2.0)
52
EDK1216CFBJ
Package Drawing
60-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
5.5 ± 0.1
0.2 S A
INDEX MARK
0.2 S B
0.2
S
+0.12
−0.08
0.88
S
0.25 ± 0.05
0.08
S
M
φ0.05
S A B
60-φ0.3 ± 0.05
A
B
INDEX MARK
1.25
0.5
4.5
ECA-TS2-0230-02
Preliminary Data Sheet E1194E20 (Ver. 2.0)
53
EDK1216CFBJ
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDK1216CFBJ.
Type of Surface Mount Device
EDK1216CFBJ: 60-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E1194E20 (Ver. 2.0)
54
EDK1216CFBJ
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E1194E20 (Ver. 2.0)
55
EDK1216CFBJ
Mobile RAM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL2, H2S, NH3,
SO2, and NO .
x
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1194E20 (Ver. 2.0)
56
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