EHB0010A1MA-7E-E [ELPIDA]
Memory Circuit, Flash+SDRAM, 4MX16, CMOS, PBGA151, ROHS COMPLIANT, FBGA-151;
| 型号： | EHB0010A1MA-7E-E |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | Memory Circuit, Flash+SDRAM, 4MX16, CMOS, PBGA151, ROHS COMPLIANT, FBGA-151 动态存储器 内存集成电路 |
| 文件： | 总113页 (文件大小：901K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
64Mb Flash Memory +
512Mb DDR SDRAM MCP
EHB0010A1MA
Description
DDR SDRAM Specifications
The EHB0010A1MA is a MCP (Multi Chip Package);
organized the SpansionTM 64M bits flash memory
(S99PL064J0039) and the Elpida 512M bits DDR
SDRAM in one package.
• Density: 512M bits
• Organization
⎯ × 32 bits: 4M words × 32 bits × 4 banks
• Power supply:
D-VDD, D-VDDQ = 1.8V +0.15V/–0.1V
Each flash memory and DDR SDRAM device operates
separately.
• Data rate: 266Mbps (max.)
• 2KB page size
⎯ Row address: A0 to A12
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Package: 151-ball FBGA
• Operating ambient temperature range
⎯ TA =−20°C to +85°C
Flash Memory Specifications
• Density: 64M bits
• Organization
⎯ × 16 bits: 4M words × 16 bits
• Power supply: F-VDD = 2.7V to 3.6V
• Access time
⎯ Address access: 70ns (max.)
⎯ Page access: 30ns (max.)
• Power supply current (for F-VDD at 10MHz)
⎯ Read: 45mA (typ.)
• Driver strength: full/half/quarter
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period: 7.8μs
⎯ Write: 15mA (typ.)
⎯ Standby mode: 0.2μA (typ.)
⎯ Program/erase: 17mA (typ.)
• Cycling endurance: 100k cycle/sector
• Data retention: 10 years
• FlexBank Architecture: four separate banks, with up
to two simultaneous operations per device
⎯ Bank A: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
⎯ Bank B: 24 Mbit (32 Kw x 48)
⎯ Bank C: 24 Mbit (32 Kw x 48)
⎯ Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
• Secured Silicon Sector region
⎯ Up to 128 words accessible through a command
sequence
⎯ Up to 64 factory-locked words
⎯ Up to 64 customer-lockable words
• Both top and bottom boot blocks in one device
Document No. E0950E30 (Ver. 3.0)
Date Published February 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007
EHB0010A1MA
Ordering Information
Flash memory
DDR SDRAM
Part number
(words × bits) Access time
70ns (address access)
30ns (page access)
(words × bits )
16M × 32
Data rate
266Mbps
/CAS latency Package
EHB0010A1MA-7E-E
4M × 16
3
151-ball FBGA
Part Number
E H B 0010 A 1 MA - 7E- E
Elpida Memory
Environment code
E: Lead Free
(RoHS compliant)
Type
H: MCP
Speed
7E: 133MHz (3-4-3)
Product Code
Package
MA: Stacked FBGA
B: DDR SDRAM
+ Flash memory
Die Rev.
Internal Code
Voltage, Interface
A: DDR SDRAM 1.8V power supply,
Flash memory 3.0V power supply
Data Sheet E0950E30 (Ver. 3.0)
2
EHB0010A1MA
CONTENTS
Description.....................................................................................................................................................1
Flash Memory Specifications.........................................................................................................................1
DDR SDRAM Specifications..........................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Block Diagram ...............................................................................................................................................4
Pin Configurations .........................................................................................................................................5
Pin Descriptions.............................................................................................................................................6
Note for MCP Datasheet ...............................................................................................................................6
512M bits DDR SDRAM Parts....................................................................................................7
DDR SDRAM Electrical Specifications..........................................................................................................8
Block Diagram .............................................................................................................................................14
Pin Function.................................................................................................................................................15
Command Operation ...................................................................................................................................17
Simplified State Diagram.............................................................................................................................23
Operation of the DDR SDRAM....................................................................................................................24
Timing Waveforms.......................................................................................................................................47
64M bits NOR Flash Memory Parts.........................................................................................56
Block Diagram .............................................................................................................................................57
Device Bus Operations................................................................................................................................59
Sector Protection.........................................................................................................................................71
Persistent Sector Protection........................................................................................................................72
Password Protection Mode..........................................................................................................................73
Common Flash Memory Interface (CFI)......................................................................................................78
Command Definitions ..................................................................................................................................81
Command Definitions Tables ......................................................................................................................87
Write Operation Status ................................................................................................................................90
Absolute Maximum Ratings.........................................................................................................................95
Operating Ranges .......................................................................................................................................95
DC Characteristics.......................................................................................................................................96
AC Characteristic.........................................................................................................................................97
Timing Diagrams .......................................................................................................................................103
Pin Capacitance ........................................................................................................................................109
Package Drawing ......................................................................................................................................110
Recommended Soldering Conditions........................................................................................................111
Data Sheet E0950E30 (Ver. 3.0)
3
EHB0010A1MA
Block Diagram
F-VDD
F-A0 to F-A21
F-VSS
64M (x16) bits Flash memory
F-RY(/BY)
F-/CE, F-/OE, F-/WE,
F-/WP(ACC), F-/RESET
F-DQ0 to F-DQ15
D-/CS
D-VDD, D-VDDQ
D-VSS, D-VSSQ
D-A0 to D-A12
D-BA0, D-BA1
D-DM0 to D-DM3
D-/CAS, D-/RAS,D-/WE
D-CKE, D-CK,D-/CK
512M (x32) bits DDR SDRAM
D-DQ0 to D-DQ31
D-DQS0 to D-DQS3
Data Sheet E0950E30 (Ver. 3.0)
4
EHB0010A1MA
Pin Configurations
/xxx indicate active low signal.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
A
B
C
D
D-VDD D-DM0 D-VSS D-VDDQ D-VDDQ D-VSS D-VSS D-VDD D-VDDQ D-VDDQ D-VSS D-DM2 D-VSS
NC
NC
D-DQS1 D-DQS0 D-DQ2 D-DQ4 D-DQ7 D-DQ0 D-VSS D-DQ20 D-DQ23 D-DQ19 D-DQ21 D-DQS2 D-DQS3 D-VDD
D-DQ9 D-DQ12 D-DQ3 D-DQ5 D-DQ6 D-DQ1 D-VSS D-DQ22 D-DQ18 D-DQ17 D-DQ16 D-DQ30 D-DQ31 D-DM3
D-VSS
D-DM1
D-DQ10 D-DQ15 D-VSS
D-DQ13 D-DQ8
D-DQ27 D-DQ24 D-VSS
D-DQ29 D-DQ25 D-VSS
D-VSS
D-VSS
E
F
G
H
J
D-DQ14 D-DQ11
D-VDDQ D-VDDQ
F-VDD F-VDD
D-DQ28 D-DQ26 D-VSS
D-VDD D-VDDQ D-VDDQ
D-BA0 D-BA1 D-VDDQ
D-/RAS D-/WE D-/CS
D-/CAS D-CKE D-VSS
D-VSS
D-VDDQ
F-VSS
F-RY/(/BY) F-/WE
F-DQ15 F-/OE
F-DQ11 F-/CE
F-VSS
F-DQ12
F-DQ8
F-A20
K
L
D-A6
D-A8
D-A12 D-CK
M
N
F-A6
F-A0
F-A9
D-A9
D-/CK
D-A7
F-A17
D-A2
D-A4
D-A11
F-A1
P
R
F-A21 F-A10
F-
F-A14 F-A15
F-A3
F-A2
F-DQ3 F-DQ5
D-A3
D-A10
D-A0
D-A5 D-VDD
D-VSS D-VDD
F-A18
/WP(ACC)
F-
/RESET
F-A7
F-A19
F-A8
F-A11
F-A16
F-DQ1 F-DQ7 F-DQ0 F-DQ2 F-DQ4
D-A1
F-A12
F-A13
T
NC
F-VSS
F-VDD F-DQ14 F-A5
F-A4 F-DQ13 F-DQ9 F-DQ10 F-DQ6 F-VSS F-VDD
NC
(Top view)
Data Sheet E0950E30 (Ver. 3.0)
5
EHB0010A1MA
Pin Descriptions
Pin
Description
F-A0 to F-A21
D-A0 to D-A12
D-BA0, D-BA1
F-/CE
Address input (Flash memory)
Address input (DDR SDRAM)
Bank select address (DDR SDRAM)
Chip enable input (Flash memory)
Chip select (DDR SDRAM)
D-/CS
D-/RAS
Row address strobe (DDR SDRAM)
Column address strobe (DDR SDRAM)
Write enable (Flash memory)
D-/CAS
F-/WE
D-/WE
Write enable (DDR SDRAM)
D-DM0 to D-DM3
D-CKE
Write data mask (DDR SDRAM)
Clock enable (DDR SDRAM)
D-CK, D-/CK
F-/OE
Differential lock input (DDR SDRAM)
Output enable input (Flash memory)
Hardware reset input (Flash memory)
Write protect acceleration input (Flash memory)
Ready/busy output and open drain(Flash memory)
Data-input/output (Flash memory)
Data-input/output (DDR SDRAM)
Input and output data strobe (DDR SDRAM)
Power supply (Flash memory)
F-/RESET
F-/WP(ACC) *1
F-RY(/BY) *2
F-DQ0 to F-DQ15
D-DQ0 to D-DQ31
D-DQS0 to D-DQS3
F-VDD
D-VDD
Power for internal circuit (DDR SDRAM)
Power for DQ circuit (DDR SDRAM)
Ground (Flash memory)
D-VDDQ
F-VSS
D-VSS
NC*3
Ground for internal circuit (DDR SDRAM)
No connection
Notes: 1. When F-/WP(ACC)= VIL, the highest and lowest two 4K-word sectors are write protected regardless of
other sector protection configurations. When F-/WP(ACC)= VIH, these sector are unprotected unless the
DYB or PPB is programmed. When F-/WP(ACC)= 12V, program and erase operations are accelerated.
2. When F-RY(/BY) = VIH, the device is ready to accept read operations and commands. When F-RY(/BY) =
VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset
operation.
3. Not internally connected.
Note for MCP Datasheet
After this chapter, pin names appear in the DDR SDRAM parts and the NOR Flash Memory parts represent pin
names with prefix “D-” or “F-“, respectively.
e.g. VDD in the DDR SDRAM parts represents D-VDD.
VDDQ in the DDR SDRAM parts represents D-VDDQ.
VCC in the Flash Memory parts represents F-VDD.
VSS in the Flash Memory parts represents F-VSS.
Data Sheet E0950E30 (Ver. 3.0)
6
EHB0010A1MA
512M bits DDR SDRAM Parts
Data Sheet E0950E30 (Ver. 3.0)
7
EHB0010A1MA
DDR SDRAM Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VT
Rating
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +2.3
–0.5 to +2.3
50
VDD
IOS
PD
V
mA
W
1.0
Operating ambient temperature
Storage temperature
TA
–20 to +85
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = −20°C to +85°C)
Parameter
Pins
Symbol
min
1.7
typ.
1.8
max
1.95
Unit
V
Notes
1
VDD,
VDDQ
Supply voltage
VSS
0
0
0
V
V
V
V
Input high voltage
Input low voltage
All other input VIH
0.8 × VDDQ
–0.3
—
—
—
VDDQ + 0.3
0.2 × VDDQ
VDDQ + 0.3
2
3
pins
VIL
DC input voltage level
CK, /CK
VIN (DC)
–0.3
AC Input differential cross
point voltage
VIX
0.4 × VDDQ
0.5 × VDDQ 0.6 × VDDQ
V
6
DC input differential voltage
AC input differential voltage
DC input high voltage
DC input low voltage
VID (DC)
VID (AC)
0.4 × VDDQ
0.6 × VDDQ
0.7× VDDQ
–0.3
—
—
—
—
—
—
VDDQ + 0.6
VDDQ + 0.6
VDDQ + 0.3
0.3 × VDDQ
VDDQ + 0.3
0.2 × VDDQ
V
V
V
V
V
V
5
5
DQ, DM, DQS VIHD (DC)
VILD (DC)
AC input high voltage
AC input low voltage
VIHD (AC)
0.8× VDDQ
–0.3
VILD (AC)
Notes: 1. VDDQ must be equal to VDD.
2. VIH (max.) = 2.3V (pulse width ≤ 5ns).
3. VIL (min.) = –0.5V (pulse width ≤ 5ns).
4. All voltage referred to VSS.
5. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and the input
level on /CK.
6. The value of VIX is expected to be 0.5 × VDDQ and must track variations in the DC level of the same.
Data Sheet E0950E30 (Ver. 3.0)
8
EHB0010A1MA
DC Characteristics 1 (TA = –20°C to +85°C, VDD and VDDQ = 1.8V +0.15V/–0.1V, VSS = 0V)
×32
max.
Parameter
Symbol
IDD1
Grade
Unit
mA
Test condition
Notes
1
Burst length = 2
tRC ≥ tRC (min.), IO = 0mA,
One bank active
Operating current
80
CKE ≤ VIL (max.),
tCK = tCK (min.)
Standby current in power down
IDD2P
3.0
2.8
mA
mA
Standby current in power down
(input signal stable)
IDD2PS
CKE ≤ VIL (max.), tCK = ∞
CKE ≥ VIH (min.),
tCK = tCK (min.),
/CS ≥ VIH (min.),
Standby current in non power down
IDD2N
6.0
mA
Input signals are changed one time
during 2tCK.
CKE ≥ VIH (min.), tCK = ∞,
Input signals are stable.
Standby current in non power down
(input signal stable)
IDD2NS
4.0
5.0
4.0
mA
mA
mA
CKE ≤ VIL (max.),
tCK = tCK (min.)
Active standby current in power down IDD3P
Active standby current in power down
IDD3PS
CKE ≤ VIL (max.), tCK = ∞
(input signal stable)
CKE ≥ VIH (min.),
tCK = tCK (min.),
/CS ≥ VIH (min.),
Input signals are changed one time
during 2 tCK.
Active standby current in non power
down
IDD3N
10
mA
Active standby current in non power
down
(input signal stable)
CKE ≥ VIH (min.), tCK = ∞,
Input signals are stable.
IDD3NS
IDD4
7.0
mA
mA
Burst length = 4
tCK ≥ tCK (min.),
Burst operating current
120
2
3
IOUT = 0mA, All banks active
Refresh current
IDD5
IDD6
90
mA
mA
tRFC ≥ tRFC (min.)
CKE ≤ 0.2V
Self-refresh current
3.5
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD1 is measured on condition that addresses are changed only one time during
tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured on condition that addresses are changed only one time during
tCK (min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
Data Sheet E0950E30 (Ver. 3.0)
9
EHB0010A1MA
DC Characteristics 2 (TA = −20°C to +85°C, VDD and VDDQ = 1.8V +0.15V/–0.1V, VSS = 0V)
Parameter
Symbol
ILI
min.
–2.0
max.
2.0
Unit
µA
Test condition
Notes
Input leakage current
0 ≤ VIN ≤ VDDQ
0 ≤ VOUT ≤ VDDQ,
DQ = disable
Output leakage current
ILO
–1.5
1.5
µA
Output high voltage
Output low voltage
VOH
VOL
0.9 × VDDQ
—
V
V
IOH = − 0.1mA
—
0.1 × VDDQ
IOL = 0.1 mA
Pin Capacitance (TA = +25°C, VDD and VDDQ = 1.8V +0.15V/–0.1V)
Parameter
Symbol
CI1
Pins
min.
2.0
2.0
—
typ.
—
—
—
—
—
—
max.
4.5
Unit
pF
pF
pF
pF
pF
pF
Notes
Input capacitance
CK, /CK
1
CI2
All other input pins
CK, /CK
4.5
1
Delta input capacitance
Cdi1
Cdi2
CI/O
Cdio
0.25
0.5
1
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
—
1
Data input/output capacitance
Delta input/output capacitance
3.5
—
6.0
1, 2,
1
0.5
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V,
TA = +25°C.
2. DOUT circuits are disabled.
AC Characteristics (Reference)
(TA = −20°C to +85°C, VDD and VDDQ = 1.8V +0.15V/–0.1V, VSS = 0V)
Parameter
Symbol
tCK
min.
max.
—
Unit
ns
Notes
Clock cycle time
7.5
CK high-level width
tCH
0.45
0.55
0.55
—
tCK
tCK
tCK
ns
CK low-level width
tCL
0.45
CK half period
tHP
min. ( tCH, tCL)
DQ output access time from CK, /CK
DQS-in cycle time
tAC
2
6.0
1.1
6.0
6.0
6.0
6.0
6.0
0.65
—
2, 8
tDSC
tDQSCK
tHZ
0.9
tCK
ns
DQS output access time from CK, /CK
DQ-out high-impedance time from CK, /CK
DQ-out low-impedance time from CK, /CK
DQS-out high-impedance time from CK, /CK
DQS-out low-impedance time from CK, /CK
DQS to DQ skew
2
2, 8
5, 8
6, 8
5, 8
6, 8
3
1
ns
tLZ
1
ns
tDQSHZ
tDQSLZ
tDQSQ
tQH
1.5
ns
1.5
ns
—
ns
DQ/DQS output hold time from DQS
Data hold skew factor
tHP − tQHS
ns
4
tQHS
tDS
—
0.75
—
ns
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Read preamble
0.8
0.8
1.75
0.9
0.4
0
ns
3
3
tDH
—
ns
tDIPW
tRPRE
tRPST
tWPRES
tWPRE
tWPST
—
ns
1.1
0.6
—
tCK
tCK
ns
Read postamble
Write preamble setup time
Write preamble
0.25
0.4
—
tCK
tCK
Write postamble
0.6
7
Data Sheet E0950E30 (Ver. 3.0)
10
EHB0010A1MA
Parameter
Symbol
tDQSS
tDSS
tDSH
tDQSH
tDQSL
tIS
min.
0.75
0.2
0.2
0.35
0.35
1.3
1.3
3.0
2
max.
1.25
—
Unit
tCK
tCK
tCK
tCK
tCK
ns
Notes
Write command to first DQS latching transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
—
—
DQS input low pulse width
—
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command period
—
3
3
3
tIH
—
ns
tIPW
—
ns
tMRD
tRAS
tRC
—
tCK
ns
45
120000
—
75
ns
Auto refresh to Active/Auto refresh command
period
tRFC
108
—
ns
Active to Read/Write delay
Precharge to active command period
Active to active command period
Write recovery time
tRCD
tRP
30
—
—
—
—
—
—
—
7.8
ns
ns
ns
ns
ns
ns
tCK
µs
22.5
tRRD
tWR
15
15
Autoprecharge write recovery and precharge time tDAL
tWR + tRP
Self-Refresh Exit Period
tSREX
120
1
Internal Write to Read command delay
Average periodic refresh interval
tWTR
tREF
—
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ and tDQSHZ are defined as DOUT transition delay from low-Z to high-Z at the end of read burst
operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific
DOUT voltage level, but specify when the device output stops driving.
6. tLZ and tDQSLZ are defined as DOUT transition delay from high-Z to low-Z at the beginning of read
operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device
output begins driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ, tLZ, tDQSHZ and tDQSLZ are specified with 15pF bus loading condition.
Data Sheet E0950E30 (Ver. 3.0)
11
EHB0010A1MA
Test Conditions
Parameter
Symbol
Value
1.6
Unit
V
Note
Input high voltage
VIH (AC)
VIL (AC)
VID (AC)
Input low voltage
0.2
V
Input differential voltage, CK and /CK inputs
1.4
V
Input differential cross point voltage,
CK and /CK inputs
VIX (AC)
VDDQ/2 with VDD=VDDQ
V
Input signal slew rate
Output load
SLEW
CL
1
V/ns
pF
15
tCK
tCH
tCL
VIH (=1.6V)
VIL (=0.2V)
/CK
CK
VID
VIX
tLZ
tAC
T
(VIH − VIL)
slew rate =
T
DQOUT
Q1
Q2
VDDQ/2
(DQOUT)
Test Condition (Wave form and Timing Reference)
DQ
CL
Output Load
Data Sheet E0950E30 (Ver. 3.0)
12
EHB0010A1MA
Timing Parameter Measured in Clock Cycle
Number of clock cycle
7.5ns
tCK
Parameter
Symbol
min.
max.
⎯
Unit
tCK
tCK
tCK
Write to pre-charge command delay (same bank) tWPD
Read to pre-charge command delay (same bank) tRPD
3 + BL/2
BL/2
⎯
Write to read command delay (to input all data)
tWRD
2 + BL/2
⎯
Burst stop command to write command delay
(CL = 3)
tBSTW
3
3
⎯
⎯
tCK
tCK
Burst stop command to DQ high-Z
(CL = 3)
tBSTZ
tRWD
tHZP
Read command to write command delay
(to output all data)
(CL = 3)
3 + BL/2
3
⎯
⎯
tCK
tCK
Pre-charge command to high-Z
(CL = 3)
Write command to data in latency
Write recovery
tWCD
tWR
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
2
DM to data in latency
tDMD
tMRD
tSREX
tRFC
0
Mode register set command cycle time
Self-refresh exit to non-column command
Auto refresh period
2
16
15
1
Power down entry
tPDEN
tPDEX
tCKE
Power down exit to command input
CKE minimum pulse width
1
2
Data Sheet E0950E30 (Ver. 3.0)
13
EHB0010A1MA
Block Diagram
CK
/CK
CKE
Bank 3
Bank 2
Bank 1
Address, BA0, BA1
Row
address
buffer
and
Memory cell array
Bank 0
refresh
counter
Mode
register
Sense amp.
Column decoder
Column
address
buffer
and
/CS
/RAS
/CAS
/WE
burst
counter
Data control circuit
Latch circuit
DQS
DM
Input & Output buffer
DQ
Data Sheet E0950E30 (Ver. 3.0)
14
EHB0010A1MA
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the
cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS
and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other
input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address is loaded via the A0 to the A8 at the cross point
of the CK rising edge and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This
column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Organization
Page size
2KB
Row address
AX0 to AX12
Column address
AY0 to AY8
× 32 bits
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled.
BA0 and BA1 (input pins)
BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.
(See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0950E30 (Ver. 3.0)
15
EHB0010A1MA
CKE (input pin)
CKE controls power down mode, self-refresh function with other command inputs.
The CKE level must be kept for 1 clock at least, that is, if CKE changes at the cross point of the CK rising edge and
the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ0 to DQ31 (input/output pins)
Data are input to and output from these pins.
DQS0 to DQS3 (input and output pin): DQS provides the read data strobes (as output) and the write data strobes
(as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
DM0 to DM3 (input pin)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VDDQ/2.
When DM = high, the data input at the same timing are masked while the internal burst counter will be counting up.
Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
[DQS and DM Correspondence Table]
Organization
DQS
Data mask
DM0
DQs
× 32 bits
DQS0
DQS1
DQS2
DQS3
DQ0 to DQ7
DQ8 to DQ15
DQ16 to DQ23
DQ24 to DQ31
DM1
DM2
DM3
VDD, VSS, VDDQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ is power supply pin for the output buffers. VDD
must be equal to VDDQ.
Data Sheet E0950E30 (Ver. 3.0)
16
EHB0010A1MA
Command Operation
Command Truth Table
The DDR SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All
other combinations than those in the table below are illegal.
CKE
Command
Symbol
DESL
NOP
n – 1
H
n
/CS /RAS /CAS /WE BA1 BA0 AP
Address
Ignore command
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
×
×
×
×
×
×
×
V
V
V
V
V
V
×
×
×
L
L
×
×
×
L
H
L
H
V
L
H
×
×
L
L
×
No operation
H
H
H
H
H
H
H
L
H
H
L
H
L
×
×
Burst stop command
Column address and read command
Read with auto-precharge
Column address and write command
Write with auto-precharge
Row address strobe and bank active
Precharge select bank
Precharge all bank
BST
H
×
×
READ
READA
WRIT
WRITA
ACT
H
H
H
L
V
V
V
V
V
V
×
V
V
V
V
V
×
H
L
H
L
H
L
L
H
H
H
H
L
H
L
PRE
H
L
PALL
REF
H
L
L
×
Refresh
H
L
H
H
L
×
×
SELF
MRS
H
L
L
×
×
Mode register set
H
H
H
L
L
L
V
V
EMRS
H
L
L
L
H
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is high at the cross point of the CK rising edge and the VDDQ/2 level, all input signals are neglected and
internal state is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VDDQ/2 level, address and data
input are neglected and internal state is held.
Burst stop command [BST]
This command stops a current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
all output buffers become high-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Data Sheet E0950E30 (Ver. 3.0)
17
EHB0010A1MA
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 (See Bank Select Signal Table) and determines
the row address (Address Pins Table in “Pin Function”).
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins in the mode register set cycle. For details, refer to
"Mode register and extended mode register set".
Data Sheet E0950E30 (Ver. 3.0)
18
EHB0010A1MA
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state
Precharging*1
/CS
H
L
/RAS /CAS /WE Address
Command
Operation
Next state
Idle
Idle
—
×
×
×
×
DESL
NOP
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
L
×
BST
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
NOP
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
—
L
L
—
L
H
H
L
H
L
—
L
L
PRE, PALL
Idle
—
L
L
×
ILLEGAL
NOP
Idle*2
H
L
×
×
×
×
DESL
Idle
Idle
Idle
—
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
L
×
BST
NOP
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
READ/READA
WRIT/WRITA
ACT
ILLEGAL*11
ILLEGAL*11
Activating
NOP
L
L
—
L
H
H
H
L
Active
Idle
L
L
PRE, PALL
Refresh/
Idle /
Self-refresh
L
L
H
L
L
×
L
L
×
H
L
×
×
REF, SELF
MRS
Self-refresh*12
MODE
Mode register set*12
Idle
Refresh
×
DESL
NOP
Idle
(auto-refresh)*3
L
H
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
H
H
L
H
H
L
H
L
×
NOP
BST
NOP
Idle
—
×
ILLEGAL
ILLEGAL
ILLEGAL
NOP
×
×
—
×
×
×
—
Activating*4
×
×
×
×
DESL
Active
Active
—
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL*11
ILLEGAL
NOP
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
—
L
BA, CA, A10
—
H
H
L
H
L
BA, RA
—
L
BA, A10
PRE, PALL
—
L
×
×
—
Active*5
×
×
×
×
DESL
Active
Active
Active
H
H
H
H
H
L
H
L
×
NOP
NOP
×
BST
NOP
H
BA, CA, A10
READ/READA
Starting read operation Read/READA
Write
Starting write operation recovering/
precharging
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
L
L
L
L
H
H
L
H
L
×
BA, RA
BA, A10
×
ACT
ILLEGAL*11
Pre-charge
ILLEGAL
—
PRE, PALL
Idle
—
Data Sheet E0950E30 (Ver. 3.0)
19
EHB0010A1MA
Current state
Read*6
/CS
H
/RAS /CAS /WE Address
Command
DESL
NOP
Operation
NOP
Next state
Active
×
×
×
×
×
×
L
H
H
H
H
H
L
NOP
Active
L
BST
Burst stop
Active
Interrupting burst read
operation to
L
H
L
H
BA, CA, A10
READ/READA
Active
start new read
L
L
H
L
L
L
BA, CA, A10
BA, RA
WRIT/WRITA
ACT
ILLEGAL*13
ILLEGAL*11
—
—
H
H
Interrupting burst read
operation to start pre-
charge
L
L
H
L
BA, A10
PRE, PALL
Precharging
L
L
L
×
×
×
×
ILLEGAL
—
Read with auto-pre-
charge*7
H
×
×
DESL
NOP
Precharging
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
Precharging
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*11
ILLEGAL*11
ILLEGAL
—
—
—
—
—
—
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
L
PRE, PALL
L
×
Write
recovering
Write*8
H
×
×
×
×
DESL
NOP
Write
recovering
L
L
H
H
H
H
H
L
×
×
NOP
BST
NOP
Burst Stop
—
Interrupting burst write
operation to
start read operation.
L
L
H
H
L
L
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
Read/ReadA
Interrupting burst write
operation to
start new write
operation.
BA, CA, A10
Write/WriteA
L
L
L
L
H
H
H
L
BA, RA
ACT
ILLEGAL*11
—
Interrupting write
operation to start pre-
charge.
BA, A10
PRE, PALL
Idle
L
H
L
L
L
L
L
×
×
ILLEGAL
NOP
—
Write recovering*9
×
×
×
×
DESL
Active
Active
—
H
H
H
H
H
L
H
L
×
NOP
NOP
×
BST
ILLEGAL
H
BA, CA, A10
READ/READA
Starting read operation. Read/ReadA
Starting new write
Write/WriteA
operation.
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
L
L
L
L
H
H
L
H
L
×
BA, RA
BA, A10
×
ACT
ILLEGAL*11
ILLEGAL*11
ILLEGAL
—
—
—
PRE/PALL
Data Sheet E0950E30 (Ver. 3.0)
20
EHB0010A1MA
Current state
/CS
H
/RAS /CAS /WE Address
Command
DESL
Operation
NOP
Next state
Write with auto-
pre-charge*10
×
×
×
×
Precharging
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
×
NOP
NOP
Precharging
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*11
ILLEGAL*11
ILLEGAL
—
—
—
—
—
—
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRIT A
ACT
L
H
H
L
H
L
L
PRE, PALL
L
×
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
5. The DDR SDRAM is in "Active" state after "Activating" is completed.
6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
Data Sheet E0950E30 (Ver. 3.0)
21
EHB0010A1MA
CKE Truth Table
CKE
n – 1
H
Current state
Command
n
/CS
L
/RAS /CAS /WE
Address
Notes
Idle
Idle
Auto-refresh command (REF)
Self-refresh entry (SELF)
H
L
L
L
H
H
H
×
×
×
×
×
×
×
×
×
2
2
H
L
L
L
H
L
L
H
×
H
×
Active/Idle
Power down entry (PDEN)
Self refresh exit (SELFX)
Power down exit (PDEX)
H
L
H
L
L
H
H
H
H
H
×
H
×
H
×
Self refresh
Power down
L
H
L
L
H
×
H
×
H
×
L
H
Notes: 1. H: VIH. L: VIL × : VIHor VIL.
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 clock cycle at least.
Auto-refresh command [REF]
This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start. Precharge has been
completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-
refresh command.
The average refresh cycle is 7.8μs. To allow for improved efficiency in scheduling, some flexibility in the absolute
refresh interval (64ms) is provided. A maximum of eight auto-refresh commands can be posted to the DDR SDRAM
or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is
8 × tREF.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN after the cycle when [PDEN] is issued, the DDR SDRAM enters into power-down mode. In power down
mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while
CKE is held low. No internal refresh operation occurs during the power down mode.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. tSREX after [SELFX], non-column commands can be
executed
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Data Sheet E0950E30 (Ver. 3.0)
22
EHB0010A1MA
Simplified State Diagram
SELF
REFRESH
EXTENDED
MODE
REGISTER
SET
SR ENTRY
SR EXIT
MRS
REFRESH
MODE
REGISTER
SET
AUTO
REFRESH
IDLE
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
POWER
DOWN
ACTIVE
CKE_
CKE
BST
WRITE
ROW
ACTIVE
BST
READ
WRITE
WRITE
WITH
AP
READ
WITH
AP
READ
WRITE
READ
READ
READ
WITH AP
WRITE
WITH AP
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
Automatic sequence
Manual input
Data Sheet E0950E30 (Ver. 3.0)
23
EHB0010A1MA
Operation of the DDR SDRAM
Initialization
The DDR SDRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 200μs or longer pause must precede any signal toggling.
VDD should be turned on before VDDQ
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed.
(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle
or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be satisfied.
Remarks:
1
The sequence of Auto refresh, mode register programming and extended mode register programming above may
be transposed.
2
3
CKE must be held high.
DM is don't care.
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0 and BA1 pins by the mode register set
command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode
register are set by inputting signal via the A0 to the A12 and BA0 and BA1 pins during mode register set cycles.
BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a
write operation, the mode register must be set.
Mode register
The mode register has four fields;
Options
: A12 through A7
: A6 through A4
: A3
/CAS latency
Wrap type
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have elapsed.
/CAS Latency
/CAS latency must be set to 3.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become high-Z. The burst length is programmable as 2, 4 and 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each wrap
type.
Data Sheet E0950E30 (Ver. 3.0)
24
EHB0010A1MA
Extended Mode Register
The extended mode register has four fields;
Options
: A12 through A7, A4 through A0
: A6 through A5
Driver Strength
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.
Driver Strength
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.
Data Sheet E0950E30 (Ver. 3.0)
25
EHB0010A1MA
Mode Register Definition
BA0 BA1
A12
0
A11 A10 A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
BL
A0
0
0
0
0
0
LTMODE
WT
Mode Register Set
Bits2-0
000
001
010
011
100
101
110
111
WT = 0
WT = 1
R
2
R
2
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
4
4
R
R
R
3
Burst length
8
8
R
R
R
R
R
R
R
R
Latency
mode
R
R
R
R
0
1
Sequential
Interleave
Wrap type
BA0 BA1
A12
0
A11 A10
A9
0
A8
A7
0
A6
A5
A4
A3
0
A2
A1
A0
0
0
1
0
0
0
DS
0
0
0
Extended Mode Register Set
Bits6-5 Strength
00
01
10
11
Normal
1/2 strength
1/4 strength
R
Driver Strength
Remark R : Reserved
Data Sheet E0950E30 (Ver. 3.0)
26
EHB0010A1MA
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
Starting Ad. Addressing(decimal)
A0
0
Sequence Interleave
A1
0
A0 Sequence
Interleave
0, 1,
1, 0,
0, 1,
1, 0,
0
1
0
1
0, 1, 2, 3,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
1
0
1, 2, 3, 0,
2, 3, 0, 1,
1
1
3,
0, 1, 2,
Burst length = 8
Starting Ad.
Addressing(decimal)
A2 A1 A0 Sequence
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7, 0,
2, 3, 4, 5, 6, 7, 0, 1,
3, 4, 5, 6, 7, 0, 1, 2,
4, 5, 6, 7, 0, 1, 2, 3,
5, 6, 7, 0, 1, 2, 3, 4,
6, 7, 0, 1, 2, 3, 4, 5,
7, 0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7, 6,
2, 3, 0, 1, 6, 7, 4, 5,
3, 2, 1, 0, 7, 6, 5, 4,
4, 5, 6, 7, 0, 1, 2, 3,
5, 4, 7, 6, 1, 0, 3, 2,
6, 7, 4, 5, 2, 3, 0, 1,
7, 6, 5, 4, 3, 2, 1, 0,
Data Sheet E0950E30 (Ver. 3.0)
27
EHB0010A1MA
Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4 or 8. The starting address of the burst read is defined by the column address, the bank select
address (See “Pin Function”) in the cycle when the read command is issued. The data output timing is characterized
by CL and tAC. The read burst start (CL-1) × tCK + tAC (ns) after the clock rising edge where the read command is
latched. The DDR SDRAM outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to the
first rising edge of the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is referred
as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe.
The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST from the last falling
edge of the data strobe, the DQS pins become high-Z. This low period of DQS is referred as read postamble.
CK
/CK
tRCD
Command
Address
NOP
ACT
Row
NOP
READ
NOP
Column
tRPRE
out0 out1
BL = 2
tRPST
DQS
DQ
out0 out1 out2 out3
BL = 4
BL = 8
out0 out1 out2 out3 out4 out5 out6 out7
CL = 3
BL: Burst length
Read Operation (Burst Length)
Data Sheet E0950E30 (Ver. 3.0)
28
EHB0010A1MA
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
NOP
Command
tRPRE
tRPST
VTT
VTT
DQS
DQ
tAC,tDQSCK
out0 out1 out2 out3
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued.
DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first
rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be
changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is
referred as write postamble.
CK
/CK
tRCD
Command
Address
NOP
ACT
Row
NOP
WRIT
NOP
Column
tWPRE
tWPRES
in0 in1
BL = 2
tWPST
DQS
DQ
in0 in1 in2 in3
BL = 4
BL = 8
in0 in1 in2 in3 in4 in5 in6 in7
BL: Burst length
Write Operation
Data Sheet E0950E30 (Ver. 3.0)
29
EHB0010A1MA
Burst Stop
Burst stop command during burst operation
The burst stop (BST) command is used to stop data in Read or Write burst operation.
The BST command stops the burst read and sets all output buffers to high-Z. tBSTZ (= CL) cycles after a BST
command issued, all DQ and DQS pins become high-Z.
The BST command is also supported for the burst write operation. No data will be written in the same cycle at the
BST command, and in subsequent cycles.
Note that bank address is not referred when this command is executed.
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
Command
BST
NOP
tBSTZ
DQS
DQ
out0 out1
CL: /CAS latency
Burst Stop during a Read Operation
Data Sheet E0950E30 (Ver. 3.0)
30
EHB0010A1MA
Auto-Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts BL/2 clocks after
READA command input. tRAS lock out mechanism for READA allows a read command with auto precharge to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column
command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge
command does not limit row commands execution for other bank.
CK
/CK
tRP (min)
tRAS (min)
tRCD (min)
BL/2
ACT
READA
NOP
ACT
Command
DQS
tAC,tDQSCK
DQ
out0 out1 out2 out3
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started BL/2 + 3 clocks after WRITA command issued.
A column command to the other banks can be issued the next cycle after the internal precharge command issued.
Write with auto-precharge command does not limit row commands execution for other bank.
CK
/CK
tRAS (min)
tRP
tRCD (min)
ACT
NOP
WRITA
NOP
ACT
Command
BL/2 + 3
DM
DQS
DQ
in1 in2 in3 in4
BL = 4
Note: Internal auto-precharge starts at the timing indicated by " ".
Burst Write (BL = 4)
Data Sheet E0950E30 (Ver. 3.0)
31
EHB0010A1MA
The Concurrent Auto Precharge
The DDR SDRAM supports the concurrent auto precharge feature, a read with auto-precharge or a write with auto-
precharge, can be followed by any command to the other banks, as long as that command does not interrupt the
read or write data transfer, and all other related limitations apply (e.g. contention between READ data and WRITE
data must be avoided.) The minimum delay from a read or write command with auto precharge, to a command to a
different bank, is summarized below.
To command (different bank, non-
interrupting command)
Minimum delay
(Concurrent AP supported)
From command
Read w/AP
Units
tCK
tCK
tCK
tCK
tCK
tCK
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
BL/2
CL (rounded up)+ (BL/2)
1
Write w/AP
1 + (BL/2) + tWTR
BL/2
1
Data Sheet E0950E30 (Ver. 3.0)
32
EHB0010A1MA
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
1. Same
Same
Different
Any
ACTIVE
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
2. Same
—
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
3. Different
ACTIVE
IDLE
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
t0
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
NOP
ACT
Row
NOP
READ
READ
Column A Column B
Address
BA
out out out out out out
A0 A1 B0 B1 B2 B3
DQ
Column = A Column = B
Read Read
Column = A
Dout
Column = B
Dout
DQS
Bank0
Active
CL = 3
BL = 4
Bank0
READ to READ Command Interval (same ROW address in the same bank)*
Note: n ≥ 4
Data Sheet E0950E30 (Ver. 3.0)
33
EHB0010A1MA
t0
t1
t2
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
READ
READ
NOP
ACT
NOP
ACT
NOP
Row0
Row1
Column A Column B
Address
BA
out out out out out out
A0 A1 B0 B1 B2 B3
DQ
Column = A Column = B
Read Read
Bank0
Dout
Bank3
Dout
DQS
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
CL = 3
BL = 4
READ to READ Command Interval (different bank)*
Note: n ≥ 4
Data Sheet E0950E30 (Ver. 3.0)
34
EHB0010A1MA
A Write command to the consecutive Write command Interval
Destination row of the consecutive write
command
Bank
address
Row address State
Operation
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
1. Same
Same
Different
Any
ACTIVE
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
2. Same
—
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
3. Different
ACTIVE
IDLE
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive write command can be issued.
t0
tn
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
CK
/CK
Command
NOP
ACT
Row
NOP
WRIT
WRIT
Column A Column B
Address
BA
DQ
inA0 inA1 inB0 inB1 inB2 inB3
Column = A
Write
Column = B
Write
DQS
Bank0
Active
BL = 4
Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
Data Sheet E0950E30 (Ver. 3.0)
35
EHB0010A1MA
t0
t1
t2
tn
tn+1
tn+2
tn+3
tn+4
tn+5
CK
/CK
Command
NOP
ACT
NOP
ACT
NOP
WRIT
WRIT
Row0
Row1
Column A Column B
Address
BA
DQ
inA0 inA1 inB0 inB1 inB2 inB3
Bank0
Write
Bank3
Write
DQS
Bank0
Active
Bank3
Active
BL = 4
Bank0, 3
WRITE to WRITE Command Interval (different bank)
Data Sheet E0950E30 (Ver. 3.0)
36
EHB0010A1MA
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write
command
Bank
address
Row address State
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
1. Same
Same
Different
Any
ACTIVE
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
2. Same
—
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
3. Different
ACTIVE
IDLE
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
READ
BST
NOP
tBSTW (≥ tBSTZ)
WRIT
NOP
DM
tBSTZ (= CL)
DQ
out0 out1
in0 in1 in2 in3
High-Z
DQS
OUTPUT
INPUT
BL = 4
CL = 3
READ to WRITE Command Interval
Data Sheet E0950E30 (Ver. 3.0)
37
EHB0010A1MA
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
Row address State
address
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD after the write command.
1. Same
2. Same
3. Different
Same
Different
Any
ACTIVE
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
—
To complete a burst operation, the consecutive read command should be
performed tWRD after the write command.
ACTIVE
IDLE
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
tWRD (min)
tWTR*
DM
out2
DQ
out0 out1
in0
in1
in2
in3
DQS
INPUT
OUTPUT
BL = 4
CL = 3
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
Data Sheet E0950E30 (Ver. 3.0)
38
EHB0010A1MA
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
Row address State
address
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*1
1. Same
2. Same
3. Different
Same
Different
Any
ACTIVE
—
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*1
ACTIVE
IDLE
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
READ
NOP
DM
High-Z
High-Z
DQ
in0 in1 in2
out0 out1 out2 out3
DQS
BL = 4
CL = 3
Data masked
[WRITE to READ delay = 1 clock cycle]
Data Sheet E0950E30 (Ver. 3.0)
39
EHB0010A1MA
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
DM
High-Z
High-Z
DQ
in0 in1 in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4
CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
NOP
tWTR*
DM
DQ
in0 in1 in2
in3
out0 out1 out2 out3
DQS
BL = 4
CL = 3
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
Data Sheet E0950E30 (Ver. 3.0)
40
EHB0010A1MA
A Write command to the Bust stop command interval: To interrupt the write operation
WRITE to BST Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
DM
WRIT
BST
NOP
DQ
in0 in1
DQS
BL = 4 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 1 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
NOP
BST
NOP
DM
DQ
in0 in1 in2
in3
DQS
Data will be written
Following data will not be written.
BL = 8 or longer
[WRITE to BST delay = 2 clock cycle]
Data Sheet E0950E30 (Ver. 3.0)
41
EHB0010A1MA
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
DM
WRIT
NOP
BST
NOP
DQ
in0 in1 in2
in3
in4
in5
DQS
BL = 8 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 3 clock cycle]
Data Sheet E0950E30 (Ver. 3.0)
42
EHB0010A1MA
A Read command to the consecutive Precharge command interval (same bank): To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
PRE/
PALL
Command
DQ
NOP
READ
NOP
NOP
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP
(= CL) after the precharge command.
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
DQ
NOP
READ PRE/PALL
NOP
High-Z
High-Z
out0 out1
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
Data Sheet E0950E30 (Ver. 3.0)
43
EHB0010A1MA
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
t0
t1
t2
t3
t4
tn
tn + 1
tn + 2
CK
/CK
Command
PRE/PALL
WRIT
NOP
tWPD
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
t0
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
CK
/CK
Command
PRE/PALL
WRIT
NOP
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data
input
Data
masked
BL = 4
WRITE to PRECHARGE Command Interval (same bank) (BL = 4, DM to mask data)
Data Sheet E0950E30 (Ver. 3.0)
44
EHB0010A1MA
Bank active command interval
Destination row of the consecutive ACT
command
Bank
Row address
address
1. Same
2. Different
State
Operation
Two successive ACT commands can be issued at tRC interval. In between two
successive ACT operations, precharge command should be executed.
Any
Any
ACTIVE
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
ACTIVE
IDLE
tRRD after an ACT command, the next ACT command can be issued.
CK
/CK
Command
ACT
ACT
NOP
PRE
NOP
ACT
NOP
Address
BA
ROW: 0
ROW: 1
ROW: 0
Bank0
Active
Bank3
Active
Bank0
Precharge
Bank0
Active
tRRD
tRC
Bank Active to Bank Active
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK
/CK
Command
MRS
NOP
ACT
NOP
Address
CODE
BS and ROW
Mode Register Set
Bank3
Active
tMRD
Data Sheet E0950E30 (Ver. 3.0)
45
EHB0010A1MA
DM Control
DM can mask input data. By setting DM to low, data can be written. When DM is set to high, the corresponding
data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask
function is 0.
t1
t2
t3
t4
t5
t6
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Data Sheet E0950E30 (Ver. 3.0)
46
EHB0010A1MA
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
tIS
tIH
tIH
Command
(/RAS, /CAS,
/WE, /CS)
tIS
Address
Read Timing Definition (1)
CK
/CK
Command
READ
tHZ (max.)
tHZ (min.)
High-Z
tLZ (max.)
tLZ (min.)
High-Z
High-Z
DQ
(Output)
tDQSHZ (max.)
tDQSHZ(min.)
High-Z
tDQSLZ (max.)
tDQSLZ (min.)
DQS
Read Timing Definition (2)
CK
/CK
tAC (min.)
tAC (max.)
tDQSCK
tDQSQ
High-Z
DQ
(Output
High-Z
High-Z
tDSC
tDQSQ
High-Z
DQS
(Output)
tQH
Data Sheet E0950E30 (Ver. 3.0)
47
EHB0010A1MA
Write Timing Definition
tCK
/CK
CK
tDQSS
tDSS
tDSH
tDSS
tDSC
tWPRES
DQS
tDQSL
tDQSH
tWPST
tWPRE
DQ
(Din)
tDIPW
tDS
tDH
tDH
DM
tDS
tDIPW
tDIPW
BL = 4
= Don't care
Data Sheet E0950E30 (Ver. 3.0)
48
EHB0010A1MA
Power on Sequence
CK
/CK
Clock cycle is necessary
VIH
CKE
/CS
tMRD
tMRD
2 refresh cycles are necessary
/RAS
/CAS
/WE
BA0
BA1
A10
Address key
Address key
Address
DM
DQ
High-Z
tRP
tRFC
tRFC
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
Extended
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
is necessary
Data Sheet E0950E30 (Ver. 3.0)
49
EHB0010A1MA
Read Cycle
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRP
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
tIS tIH
tIS tIH
/RAS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CAS
tIS tIH
/WE
BA
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
A10
tIS tIH
tIS tIH
tIS tIH
Address
DM
tRPST
tRPRE
tDSC
High-Z
DQS
High-Z
DQ (output)
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
CL = 3
BL = 4
Bank0 Access
= VIH or VIL
Data Sheet E0950E30 (Ver. 3.0)
50
EHB0010A1MA
Write Cycle
tCK
tCH
tCL
CK
/CK
tRC
VIH
CKE
/CS
tRP
tRAS
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/RAS
/CAS
/WE
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS
tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
BA
tIS tIH
A10
tIS tIH
tIS tIH
tIS tIH
Address
tDQSS
tDQSL
tWPST
tDH
DQS
(input)
tDQSH
tDS
tDS
tDS
DM
tDH
DQ (input)
tWR
tDH
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
Data Sheet E0950E30 (Ver. 3.0)
51
EHB0010A1MA
Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
code
code
Address
DM
C: b
R: b
valid
High-Z
High-Z
DQS
b
DQ (output)
tMRD
tRP
Bank 3
Read
Bank 3
Precharge
Mode
register
set
Bank 3
Active
CL = 3
BL = 4
Precharge
If needed
= VIH or VIL
Read/Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:b''
C:a R:b
C:b
DM
DQS
a
tRWD
b’’
DQ (output)
DQ (input)
High-Z
b
tWRD
Bank 3
Bank 0
Active
Bank 0 Bank 3
Read Active
Bank 3
Write
Read
Read cycle
CL = 3
BL = 4
=VIH or VIL
Data Sheet E0950E30 (Ver. 3.0)
52
EHB0010A1MA
Auto Refresh Cycle
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
b
DQ (output)
DQ (input)
High-Z
tRP
tRFC
Precharge
If needed
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 3
BL = 4
= VIH or VIL
Data Sheet E0950E30 (Ver. 3.0)
53
EHB0010A1MA
Self-Refresh Cycle
/CK
CK
tIS
tIH
CKE = low
CKE
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ (output)
DQ (input)
High-Z
tRP
tSREX
Precharge
If needed
Self
refresh
entry
Self refresh
exit
Bank 0
Active
Bank 0
Read
BL = 4
= VIH or VIL
Data Sheet E0950E30 (Ver. 3.0)
54
EHB0010A1MA
Power Down Entry and Exit
/CK
CK
t
t
IS
IH
CKE = low
CKE
tCKE
/CS
/RAS
/CAS
/WE
BA
Address
DM
A10=1
R: b
R: c
DQS
DQ (output)
DQ (input)
High-Z
tPDEN
tRP
tPDEX
Power
down
exit
Precharge
If needed
Bank 0
Active
Bank 0
Read
Power down
entry
BL = 4
=VIH or VIL
Data Sheet E0950E30 (Ver. 3.0)
55
EHB0010A1MA
64M bits NOR Flash Memory Parts
Data Sheet E0950E30 (Ver. 3.0)
56
EHB0010A1MA
Block Diagram
DQ15 to DQ0
RY(/BY)
V
CC
V
Sector
SS
Switches
V
CC
Input/Output
Buffers
/RESET
/WE
Erase Voltage
Generator
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
/CE
/OE
Data Latch
Y-Gating
Y-Decoder
X-Decoder
V
Detector
Timer
CC
A21 to A3
Cell Matrix
A2 to A0
Note: RY(/BY) is an open drain output.
Data Sheet E0950E30 (Ver. 3.0)
57
EHB0010A1MA
Simultaneous Read/Write Block Diagram
V
V
CC
SS
/OE
Mux
Bank A
Bank A Address
A21 to A0
X-Decoder
Bank B Address
RY(/BY)
Bank B
X-Decoder
A21 to A0
/RESET
STATE
CONTROL
&
Status
/WE
DQ15 to DQ0
Mux
/CE
/WP(ACC)
COMMAND
REGISTER
Control
X-Decoder
Bank C
DQ0 to DQ15
Bank C Address
Bank D Address
X-Decoder
Bank D
A21 to A0
Mux
Data Sheet E0950E30 (Ver. 3.0)
58
EHB0010A1MA
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location. The
register is a latch used to store the commands, along with the address and data information needed to execute the
command. The contents of the register serve as inputs to the internal state machine. The state machine outputs
dictate the function of the device. The Device Bus Operations table lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these operations in
further detail.
[Device Bus Operations]
Addresses
(A21–A0)
DQ15–
DQ0
Operation
Read
/CE
L
/OE
L
/WE
H
/RESET
H
/WP(ACC)
X
AIN
AIN
DOUT
DIN
Write
L
H
L
H
X*2
Standby
VCC 0.3V
X
H
X
X
H
X
VCC 0.3V
X
X
X
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
L
X
Temporary Sector Unprotect
(High Voltage)
X
X
X
VID
X
AIN
DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care,
SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment.
See the High Voltage Sector Protection section.
2. /WP(ACC) must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the /OE and appropriate /CE pins to VIL. /CE is the
power control. /OE is the output control and gates array data to the output pins. /WE should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the
device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access
until the command register contents are altered.
Refer to the Read Operation Timings figure for the timing diagram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access
time (tCE) is the delay from the stable addresses and stable /CE to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the /OE to valid data at the output inputs (assuming the addresses
have been stable for at least tACC–tOE time).
Data Sheet E0950E30 (Ver. 3.0)
59
EHB0010A1MA
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random locations within a page. Address bits A21–A3 select an 8
word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with
the microprocessor supplying the specific word location.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations
specified by the microprocessor falls within that page) is equivalent to tPACC. When /CE is deasserted (=VIH), the
reassertion of /CE for subsequent access has access time of tACC or tCE. Here again, /CE selects the device and
/OE is the output control and should be used to gate data to the output inputs if the device is selected. Fast page
mode accesses are obtained by keeping A21–A3 constant and changing A2–A0 to select the specific word within
that page.
[Page Select]
Word
A2
0
A1
0
A0
0
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, erase-suspend program, and program-
suspend read), the device is capable of reading data from one bank of memory while a program or erase operation
is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
[Bank Select]
Bank
A21–A19
000
Bank A
Bank B
Bank C
Bank D
001, 010, 011
100, 101, 110
111
Data Sheet E0950E30 (Ver. 3.0)
60
EHB0010A1MA
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of
memory), the system must drive /WE and /CE to VIL, and /OE to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock
Bypass mode, only two write cycles are required to program a word, instead of four. The Word Program Command
Sequence section has details on programming data to the device using both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. the Bank Select table indicates the
set of address space that each sector occupies. A “bank address” is the set of address bits required to uniquely
select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The
Command Definitions section has details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing
specification tables and timing diagrams in the Reset section for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode,
temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command sequence as required by the Unlock
Bypass mode. Removing VHH from the /WP(ACC) pin returns the device to normal operation. Note that VHH must
not be asserted on /WP(ACC) for operations other than accelerated programming, or device damage may result. In
addition, the /WP(ACC) pin should be raised to VCC when not in use. That is, the /WP(ACC) pin should not be left
floating or unconnected; inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. Refer to the Secured silicon Sector Address and Autoselect Command
Sequence for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the
/OE input.
The device enters the CMOS standby mode when the /CE and /RESET pins are both held at VCC ± 0.3 V. (Note
that this is a more restricted voltage range than VIH.) If /CE and /RESET are held at VIH, but not within VCC ± 0.3 V,
the device will be in the standby mode, but the standby current will be greater. The device requires standard access
time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is
completed.
ICC3 in DC Characteristics represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode
when addresses remain stable for tACC + 30ns. The automatic sleep mode is independent of the /CE, /WE, and /OE
control signals. Standard address access timings provide new data when addresses are changed. While in sleep
mode, output data is latched and always available to the system. Note that during automatic sleep mode, /OE must
be at VIH before the device reduces current to the stated sleep mode specification. Icc5 in DC Characteristics
represents the automatic sleep mode current specification.
Data Sheet E0950E30 (Ver. 3.0)
61
EHB0010A1MA
/RESET: Hardware Reset Pin
The /RESET pin provides a hardware method of resetting the device to reading array data. When the /RESET pin is
driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all
output pins, and ignores all read/write commands for the duration of the /RESET pulse. The device also resets the
internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the /RESET pulse. When /RESET is held at VSS±0.3 V, the device draws
CMOS standby current (I). If /RESET is held at VIL but not within VSS±0.3 V, the standby current will be greater.
The /RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,
enabling the system to read the bootup firmware from the Flash memory.
If /RESET is asserted during a program or erase operation, the RY(/BY) pin remains a “0” (busy) until the internal
reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus
monitor RY(/BY) to determine whether the reset operation is complete. If /RESET is asserted when a program or
erase operation is not executing (RY(/BY) pin is “1”), the reset operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read data tRH after the /RESET pin returns to VIH.
Refer to the AC Characteristic tables for /RESET parameters and to Reset Timings for the timing diagram.
Output Disable Mode
When the /OE input is at VIH, output from the device is disabled. The output pins (except for RY(/BY)) are placed in
the highest Impedance state
Data Sheet E0950E30 (Ver. 3.0)
62
EHB0010A1MA
[64M bits Flash Memory Sector Architecture]
Bank
Sector
SA0
Sector Address (A21-A12)
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
0000010XXX
0000011XXX
0000100XXX
0000101XXX
0000110XXX
0000111XXX
0001000XXX
0001001XXX
0001010XXX
0001011XXX
0001100XXX
0001101XXX
0001110XXX
0001111XXX
0010000XXX
0010001XXX
0010010XXX
0010011XXX
0010100XXX
0010101XXX
0010110XXX
0010111XXX
0011000XXX
0011001XXX
Sector Size (Kwords)
Address Range (x16)
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
4
SA1
4
SA2
4
SA3
4
SA4
4
SA5
4
SA6
4
SA7
4
SA8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
Data Sheet E0950E30 (Ver. 3.0)
63
EHB0010A1MA
Bank
Sector
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
Sector Address (A21-A12)
0011010XXX
0011011XXX
0011100XXX
0011101XXX
0011110XXX
0011111XXX
0100000XXX
0100001XXX
0100010XXX
0100011XXX
0100100XXX
0100101XXX
0100110XXX
0100111XXX
0101000XXX
0101001XXX
0101010XXX
0101011XXX
0101100XXX
0101101XXX
0101110XXX
0101111XXX
0110000XXX
0110001XXX
0110010XXX
0110011XXX
0110100XXX
0110101XXX
0110110XXX
0110111XXX
0111000XXX
0111001XXX
0111010XXX
0111011XXX
Sector Size (Kwords)
Address Range (x16)
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Data Sheet E0950E30 (Ver. 3.0)
64
EHB0010A1MA
Bank
Sector
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
Sector Address (A21-A12)
0111100XXX
0111101XXX
0111110XXX
0111111XXX
1000000XXX
1000001XXX
1000010XXX
1000011XXX
1000100XXX
1000101XXX
1000110XXX
1000111XXX
1001000XXX
1001001XXX
1001010XXX
1001011XXX
1001100XXX
1001101XXX
1001110XXX
1001111XXX
1010000XXX
1010001XXX
1010010XXX
1010011XXX
1010100XXX
1010101XXX
1010110XXX
1010111XXX
1011000XXX
1011001XXX
1011010XXX
1011011XXX
1011100XXX
1011101XXX
Sector Size (Kwords)
Address Range (x16)
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–287FFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Data Sheet E0950E30 (Ver. 3.0)
65
EHB0010A1MA
Bank
Sector
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Sector Address (A21-A12)
1011110XXX
1011111XXX
1100000XXX
1100001XXX
1100010XXX
1100011XXX
1100100XXX
1100101XXX
1100110XXX
1100111XXX
1101000XXX
1101001XXX
1101010XXX
1101011XXX
1101100XXX
1101101XXX
1101110XXX
1101111XXX
1110000XXX
1110001XXX
1110010XXX
1110011XXX
1110100XXX
1110101XXX
1110110XXX
1110111XXX
1111000XXX
1111001XXX
1111010XXX
1111011XXX
1111100XXX
1111101XXX
1111110XXX
1111111000
Sector Size (Kwords)
Address Range (x16)
2F0000h–2F7FFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
Data Sheet E0950E30 (Ver. 3.0)
66
EHB0010A1MA
Bank
Sector
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Sector Address (A21-A12)
1111111001
Sector Size (Kwords)
Address Range (x16)
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
4
4
4
4
4
4
4
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
[Secured Silicon Sector Addresses]
Sector Size
64 words
64 words
Address Range
Factory-Locked Area
000000h-00003Fh
000040h-00007Fh
Customer-Lockable Area
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through
identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically
match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes
can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as
shown in the table Autoselect Codes (High Voltage Method). In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order address bits (see [Bank Select] ). The table Autoselect Codes
(High Voltage Method) show the remaining address bits that are don’t care. When all necessary bits have been set
as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However,
the autoselect codes can also be accessed in-system through the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in Memory Array Command Definitions. Note that if a Bank Address (BA) (on address bits: A21–A19) is
asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank
and then immediately read array data from the other bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command
register, as shown in Memory Array Command Definitions. This method does not require VID. Refer to the
Autoselect Command Sequence for more information.
Data Sheet E0950E30 (Ver. 3.0)
67
EHB0010A1MA
[Autoselect Codes (High Voltage Method)]
A5
to
A21 to
DQ15
Description
/CE /OE /WE A12
A10 A9 A8 A7 A6 A4 A3 A2 A1 A0 to DQ0
Manufacturer ID:
Spansion products
L
L
L
L
L
L
H
BA
X
VID X
L
L
X
L
L
L
L
0001h
227Eh
2202h
2201h
Read
Cycle 1
L
L
L
H
L
Read
Cycle 2
L
H
BA
X
VID X
L
L
L
H
H
L
H
H
L
H
H
H
Read
Cycle 3
H
L
Sector Protection
Verification
0001h (protected),
0000h (unprotected)
L
L
H
H
SA
X
X
VID X
VID X
L
L
L
L
DQ7=1
(factory locked),
DQ6=1
Secured Silicon
Indicator Bit
L
BA*
X
X
L
L
H
H
(DQ7, DQ6)
(factory and
customer locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Note: When Polling the Secured Silicon indicator bit the Bank Address (BA) should be set within the address range
004000h-03FFFFh.
Data Sheet E0950E30 (Ver. 3.0)
68
EHB0010A1MA
[Boot Sector/Sector Block Addresses for Protection/Unprotection]
Sector
A21-A12
Sector/Sector Block Size
4 Kwords
SA0
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
0000010XXX
0000011XXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
SA9
32 Kwords
SA10
32 Kwords
SA11-SA14
SA15-SA18
SA19-SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55-SA58
SA59-SA62
SA63-SA66
SA67-SA70
SA71-SA74
SA75-SA78
SA79-SA82
SA83-SA86
SA87-SA90
SA91-SA94
SA95-SA98
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
Data Sheet E0950E30 (Ver. 3.0)
69
EHB0010A1MA
Sector
A21-A12
Sector/Sector Block Size
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
SA99-SA102
SA103-SA106
SA107-SA110
SA111-SA114
SA115-SA118
SA119-SA122
SA123-SA126
SA127-SA130
SA131
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
SA132
32 Kwords
SA133
32 Kwords
SA134
4 Kwords
SA135
4 Kwords
SA136
4 Kwords
SA137
4 Kwords
SA138
4 Kwords
SA139
4 Kwords
SA140
4 Kwords
SA141
4 Kwords
Data Sheet E0950E30 (Ver. 3.0)
70
EHB0010A1MA
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming
and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See the Secured Silicon Sector Addresses
for details.
[Sector Protection Schemes]
DYB
0
PPB
0
PPB Lock
Sector State
0
1
0
0
0
1
1
1
Unprotected—PPB and DYB are changeable
Unprotected—PPB not changeable, DYB is changeable
0
0
0
1
Protected—PPB and DYB are changeable
1
0
1
1
0
1
Protected—PPB not changeable, DYB is changeable
1
0
1
1
Sector Protection
The PL064J features several levels of sector protection, which can disable both the program and erase operations in
certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector
groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA1-133, SA1-134, SA2-0 and SA2-1.
The WP# Hardware Protection feature is always available, independent of the software managed protection method
chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the
Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits
that define which sector protection method will be used. If the Persistent Sector Protection method is desired,
programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector
Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit
permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two
protection modes once a locking bit has been set. One of the two modes must be selected when the device is first
programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause
an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode.
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming
and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Data Sheet E0950E30 (Ver. 3.0)
71
EHB0010A1MA
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12V controlled protection method in previous flash devices.
This new method provides three different sector protection states:
• Persistently Locked—The sector is protected and cannot be changed.
• Dynamically Locked—The sector is protected and can be changed by a simple command.
• Unlocked—The sector is unprotected and can be changed by a simple command.
To achieve these states, three types of “bits” are used:
• Persistent Protection Bit
• Persistent Protection Bit Lock
• Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables
for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection
Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command.
The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all
of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased.
The flash device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed.
When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared
after power-up or hardware reset. There is no command sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”.
Each DYB is individually modifiable through the DYB Write Command.
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power
up in the cleared state – meaning the PPBs are changeable.
When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for
each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have
the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write
command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state.
These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy
to switch back and forth between the protected and unprotected conditions. This allows software to easily protect
sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
The DYBs maybe set or cleared as often as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across
power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a
group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase
cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the
PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile
PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go
through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to
allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to
disable any further changes to the PPBs during system operation.
The /WP(ACC) write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and
SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold
system boot code. The /WP(ACC) pin can prevent any changes to the boot code that could override the choices
made while setting up sector protection during system initialization.
For customers who are concerned about malicious viruses there is another level of security - the persistently locked
state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to
“1”. Once all PPBs are programmed to the desired settings, the PPB Lock should be set to “1”. Setting the PPB Lock
automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock “freezes”
the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle.
Data Sheet E0950E30 (Ver. 3.0)
72
EHB0010A1MA
It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The
sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write
command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to
signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked
sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through
a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB
lock bit once again will lock the PPBs, and the device operates normally again.
The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the
boot code by holding /WP(ACC) = VIL.
CFI Query Identification String contains all possible combinations of the DYB, PPB, and PPB lock relating to the
status of the sector.
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed
until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or
unlocked. The DYB then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores the command and returns to read
mode. A program command to a protected sector enables status polling for approximately 1 µs before the device
returns to read mode without having modified the contents of the protected sector. An erase command to a protected
sector enables status polling for approximately 50 µs after which the device returns to read mode without having
erased the protected sector.
The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock
verify command to the device. There is an alternative means of reading the protection status. Take /RESET to VIL
and hold /WE at VIH. (The high voltage A9 Autoselect Mode also works for reading the status of the PPBs).
Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will produce a logical ‘1” code at device output
DQ0 for a protected sector or a “0” for an unprotected sector. In this mode, the other addresses are don’t cares.
Address location with A1 = VIL are reserved for autoselect manufacturer and device codes.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the
device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents
programming of the password protection mode locking bit. This guarantees that a hacker could not place the device
in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector
Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector
Protection Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather
than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device.
The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or
erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the
flash, along with a password. The flash device internally compares the given password with the pre-programmed
password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash
device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any
efforts to run a program that tries all possible combinations in order to crack the password.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. The
password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN
is different for every flash device; therefore each password should be different for every flash device. While
programming in the password region, the customer may perform Password Verify operations.
Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This
operation achieves two objectives:
Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this
Data Sheet E0950E30 (Ver. 3.0)
73
EHB0010A1MA
function.
Disables all further commands to the password region. All program, and read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user
must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More
importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to
the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the
password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further
password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is
programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no
changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program
and Verify commands (see “Password Verify Command”). The password function works in conjunction with the
Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of
the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors without
using VID. This function is provided by the /WP pin and overrides the previously discussed High Voltage Sector
Protection method.
If the system asserts VIL on the /WP(ACC) pin, the device disables program and erase functions in the two
outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or
unprotected.
If the system asserts VIH on the /WP(ACC) pin, the device reverts the upper two and lower two sectors to whether
they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected using the method described in the High Voltage Sector
Protection.
Note that the /WP(ACC) pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit
after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (/RESET asserted) or a
power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the
Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit,
allowing for sector PPBs modifications. Asserting /RESET, taking the device through a power-on reset, or issuing the
PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set.
If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after
power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only
means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is
ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure
requires high voltage (VID) to be placed on the /RESET pin. Refer to In-System Sector Protection/Sector
Unprotection Algorithm for details on this procedure. Note that for sector unprotect, all unprotected sectors must first
be protected prior to the first sector write cycle.
Data Sheet E0950E30 (Ver. 3.0)
74
EHB0010A1MA
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
/RESET = VID
PLSCNT = 1
/RESET = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
Yes
Set up first sector
address
A7-A0 = 00000010
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A7 to A0 =
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
01000010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
00000010
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
Read from
sector address
with A7-A0 =
00000010
Increment
PLSCNT
No
00000010
No
PLSCNT
= 25?
Read from
sector address
with A7 to A0 =
00000010
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Remove V
ID
Data = 00h?
Yes
from /RESET
No
Yes
Write reset
command
Remove VID
from /RESET
No
Last sector
verified?
Remove V
from /RESET
ID
Sector Protect
complete
Write reset
command
Yes
Write reset
command
Remove VID
from /RESET
Device failed
Sector Protect
complete
Sector Protect
complete
Write reset
command
Sector Protect
Algorithm
Device failed
Sector Unprotect
complete
Sector Unprotect
Algorithm
In-System Sector Protection/Sector Unprotection Algorithms
Data Sheet E0950E30 (Ver. 3.0)
75
EHB0010A1MA
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data insystem. The Sector
Unprotect mode is activated by setting the /RESET pin to V. During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses. Once VID is removed from the /RESET pin, all the
previously protected sectors are protected again. Temporary Sector Unprotect Operatio shows the algorithm, and
Temporary Sector Unprotect Timing Diagra shows the timing diagrams, for this feature. While PPB lock is set, the
device cannot enter the Temporary Sector Unprotection Mode.
START
/RESET = VID*1
Perform for Erase or
Program Operations
/RESET = VIH
Temporary Sector
Unprotect Completed*2
Notes: 1. All protected sectors unprotected (If /WP(ACC) = VIL, upper two and lower two sectors will remain
protected).
2. All previously protected sectors are protected once again
Temporary Sector Unprotect Operation
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification
through an Electronic Serial Number (ESN) The 128-word Secured Silicon sector is divided into 64 factory-lockable
words that can be programmed and locked by the customer. The Secured Silicon sector is located at addresses
000000h-00007Fh in both Persistent Protection mode and Password Protection mode. Indicator bits DQ6 and DQ7
are used to indicate the factory-locked and customer locked status of the part.
The system accesses the Secured Silicon Sector through a command sequence (see the Enter/Exit Secured Silicon
Sector command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it
may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is
removed from the device. Once the Enter SecSi Sector Command sequence has been entered, the standard array
cannot be accessed until the Exit SecSi Sector command has been entered or the device has been reset. On power-
up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that
the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Factory-Locked Area (64 words)
The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is locked when the part is shipped,
whether or not the area was programmed at the factory. The Secured Silicon Sector Factory-locked Indicator Bit
(DQ7) is permanently set to a “1”. Optional Spansion programming services can program the factory-locked area
with a random ESN, a customer-defined code, or any combination of the two. Because only Spansion can program
and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the
field. Contact your local sales office for details on using Spansion’s programming services. Note that the ACC
function and unlock bypass modes are not available when the Secured Silicon sector is enabled.
Data Sheet E0950E30 (Ver. 3.0)
76
EHB0010A1MA
Customer-Lockable Area (64 words)
The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is shipped unprotected, which allows
the customer to program and optionally lock the area as appropriate for the application. The Secured Silicon Sector
Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the Secured
Silicon Protection Bit Program Command. The Secured Silicon Sector can be read any number of times, but can be
programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are
not available when programming the Secured Silicon Sector.
The Customer-lockable Secured Silicon Sector area can be protected using one of the following procedures:
• Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system
sector protect algorithm as shown in In-System Sector Protection/Sector Unprotection Algorithm, except that
/RESET may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector Region
without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon
Sector.
• To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Secured Silicon
Sector Protect Verify.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector
Region command sequence to return to reading and writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for
unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be
modified in any way.
Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured Silicon Sector memory area. Once
set, the Secured Silicon Sector memory area contents are non-modifiable.
START
If data = 00h,
/RESET =
SecSi Sector is
VIH or VID
unprotected.
If data = 01h,
SecSi Sector is
protected.
Wait 1 μs
Write 60h to
any address
Remove VIH or VID
from /RESET
Write 40h to SecSi
Sector address
Write reset
with A6 = 0,
command
A1 = 1, A0 = 0
SecSi Sector
Read from SecSi
Protect Verify
Sector address
complete
with A6 = 0,
A1 = 1, A0 = 0
Secured Silicon Sector Protect Verify
Data Sheet E0950E30 (Ver. 3.0)
77
EHB0010A1MA
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC powerup and
powerdown transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC powerup
and powerdown. The command register and all internal program/erase circuits are disabled, and the device resets to
the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on /OE, /CE or /WE do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of /OE = VIL, /CE VIH or /WE = VIH. To initiate a write cycle, /CE and
/WE must be a logical zero while /OE is a logical one.
PowerUp Write Inhibit
If /WE = /CE = VIL and /OE = VIH during power up, the device does not accept commands on the rising edge of
/WE. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support
can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified
flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any
time the device is ready to read array data. The system can read CFI information at the addresses given in Tables
CFI Query Identification String –[Primary Vendor-Specific Extended Query. To terminate reading CFI data, the
system must write the reset command. The CFI Query mode is not accessible when the device is executing an
Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the
CFI query mode, and the system can read CFI data at the addresses given in Tables CFI Query Identification String
–[Primary Vendor-Specific Extended Query. The system must write the reset command to return the device to
reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office
for copies of these documents.
[CFI Query Identification String]
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Data Sheet E0950E30 (Ver. 3.0)
78
EHB0010A1MA
[System Interface String]
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0003h
0000h
0009h
0000h
0004h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
[Device Geometry Definition]
Addresses
27h
Data
Description
0017h (PL064J)
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
007Dh (PL064J)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
32h
33h
34h
0000h
0000h
0001h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Data Sheet E0950E30 (Ver. 3.0)
79
EHB0010A1MA
[Primary Vendor-Specific Extended Query]
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
45h
TBD
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
0002h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
0001h
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
0007h (PLxxxJ)
0077h (PL064J)
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
0002h (PLxxxJ)
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
0095h
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = Both top and bottom boot with write protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
4Fh
0001h
Program Suspend
0 = Not supported, 1 = Supported
50h
57h
58h
59h
5Ah
5Bh
0001h
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
0004h
Bank 1 Region Information
X = Number of Sectors in Bank 1
0017h (PL064J)
0030h (PL064J)
0030h (PL064J)
0017h (PL064J)
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
Data Sheet E0950E30 (Ver. 3.0)
80
EHB0010A1MA
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations.
The Memory Array Command Definitions table defines the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence may place the device in an unknown state. A
reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of /WE or /CE, whichever happens later. All data is latched on the rising
edge of /WE or /CE whichever happens first. Refer to the AC Characteristic section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve
data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read
mode, after which the system can read data from any non-erase-suspended sector within the same bank. The
system can read array data using the standard read timing, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend
mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume
Commands section for more information.
After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read
mode, after which the system can read data from any non-program-suspended sector within the same bank. See the
Program Suspend/Program Resume Commands for more information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes
high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section,
Reset Command , for more information.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the
device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that
bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read
mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read
mode (or erase-suspend-read mode if that bank was in Erase Suspend and program-suspend-read mode if that
bank was in Pro-gram Suspend).
Data Sheet E0950E30 (Ver. 3.0)
81
EHB0010A1MA
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and
determine whether or not a sector is protected. The autoselect command sequence may be written to an address
within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written
while the device is actively programming or erasing in the other bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The
system may read any number of autoselect codes without reinitiating the command sequence.
Memory Array Command Definitions shows the address and data requirements. To determine sector protection
information, the system must write to the appropriate bank address (BA) and sector address (SA). The Bank Select]
table shows the address range and bank number associated with each sector.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was
previously in Erase Suspend).
Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial
number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the
system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector
command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the
device is executing an Embedded Program or embedded Erase algorithm. Memory Array Command Definitions
shows the address and data requirements for both command sequences. See also Secured Silicon S for further
information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector
is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write
cycles, followed by the program setup command. The program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The
device automatically provides internally generated program pulses and verifies the programmed cell margin. Memory
Array Command Definitions shows the address and data requirements for the program command sequence. Note
that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in
progress.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no
longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY(/BY).
Refer to the Write Operation Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware
reset immediately terminates the program operation. The program command sequence should be reinitiated once
that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect
and CFI functions are unavailable when the Secured Silicon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0”
back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to
indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase
operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass
mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program command sequence, resulting in faster total programming time.
Memory Array Command Definitions shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence.
(See Memory Array Command Definitions)
Data Sheet E0950E30 (Ver. 3.0)
82
EHB0010A1MA
The device offers accelerated program operations through the /WP(ACC) pin. When the system asserts VHH on the
/WP(ACC) pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device uses the higher voltage on the /WP(ACC) pin to accelerate
the operation. Note that the /WP(ACC) pin must not be at VHH any operation other than accelerated programming,
or device damage may result. In addition, the /WP(ACC) pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
The figure Program Operation illustrates the algorithm for the program operation. Refer to the Erase/Program
Operations table in the AC Characteristics section for parameters, and Program Operation Timings for timing
diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Memory Array Command Definitions for program command sequence.
Program Operation
Data Sheet E0950E30 (Ver. 3.0)
83
EHB0010A1MA
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles,
followed by a setup command. Two additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to
erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations. Memory Array Command Definitions shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer
latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY(/BY). Refer to
the Write Operation Status section for information on these status bits.
Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector, autoselect,
and CFI functions are unavailable when a [program/erase] operation is in progress. However, note that a hardware
reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
The figure Erase Operation illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations
tables in the AC Characteristics section for parameters, and Chip/Sector Erase Operation Timings section for timing
diagrams.
Sector Erase Command Sequence.
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional unlock cycles are written, and are then followed by the
address of the sector to be erased, and the sector erase command. Memory Array Command Definitions shows the
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase timeout of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these
additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be reenabled after the last Sector
Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the
normal operation will not be guaranteed. The system must rewrite the command sequence and any additional
addresses and commands. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a
[program/erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector
Erase Timer). The time-out begins from the rising edge of the final /WE pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no
longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the
non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or
RY(/BY) in the erasing bank. Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector
erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
The figure Erase Operation illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations
tables in the AC Characteristics section for parameters, and Chip/Sector Erase Operation Timings section for timing
diagrams.
Data Sheet E0950E30 (Ver. 3.0)
84
EHB0010A1MA
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes: 1. See Memory Array Command Definitions for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from,
or program data to, any sector not selected for erasure. The bank address is required when writing this command.
This command is valid only during the sector erase operation, including the 80 µs timeout period during the sector
erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of
35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector
erase timeout, the device immediately terminates the timeout period and suspends the erase operation. Addresses
are “don’t-cares” when writing the Erase suspend command.
After the erase operation has been suspended, the bank enters the erase suspend read mode. The system can read
data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0.
The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-
suspended. Refer to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
Word Program operation. Refer to the Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for
another valid operation. Refer to the Secured silicon Sector Address and the Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t
care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the
Data Sheet E0950E30 (Ver. 3.0)
85
EHB0010A1MA
Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed
erasing.
If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector
Protection Mode Locking Bit Program Command should be reissued to improve program margin.
If the Secured Silicon Sector Protection Bit is verified as programmed without margin, the Secured Silicon Sector
Protection Bit Program Command should be reissued to improve program margin.
µµAfter programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed
with margin. If the PPB has been programmed without margin, the program command should be reissued to improve
the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling
the PPBs beyond 100 cycles is not guaranteed.
After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with
margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the
program margin. The programming of either the PPB or DYB for a given sector or sector group can be verified by
writing a Sector Protection Status command to the device.
Note that there is no single command to independently verify the programming of a DYB for a given sector group.
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation so that data
can read from any non-suspended sector. When the Program Suspend command is written during a programming
process, the device halts the programming operation within tPSL (program suspend latency) and updates the status
bits. Addresses are “don’t-cares” when writing the Program Suspend command. After the programming operation
has been suspended, the system can read array data from any non-suspended sector. The Program Suspend
command may also be issued during a programming operation while an erase is suspended. In this case, data may
be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured
Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system
may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows
reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid
operation. See “Autoselect Command Sequence” for more information. After the Program Resume command is
written, the device reverts to programming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information. The system must write the Program Resume command (address bits are “don’t care”) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program Resume command
are ignored. Another Program Suspend command can be written after the device has resumed programming.
Data Sheet E0950E30 (Ver. 3.0)
86
EHB0010A1MA
Command Definitions Tables
[Memory Array Command Definitions]
Bus Cycles*1, 2, 3, 4
Command (Notes)
Read *5
Cycles Addr
Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
1
RA
RD
F0
Reset*6
XXX
(BA)
555
(BA)
X00
Manufacturer ID
Device ID *10
4
6
4
4
555
555
555
555
AA
AA
AA
2AA 55
2AA 55
2AA 55
90
90
90
90
01
(BA)
555
(BA)
X01
(BA)
X0E
(BA)
X0F
10
10
227E
*
*
Secured Silicon Sector
(BA)
555
8
X03
*
Factory *8
Sector Group
(BA)
555
(SA) XX00/
X02
AAA 2AA 55
Protect Verify*9
XX01
Program
4
6
6
1
1
1
2
3
2
2
555
555
555
BA
BA
55
AA
AA
AA
B0
30
2AA 55
2AA 55
2AA 55
555
555
555
A0
80
80
PA
PD
Chip Erase
555
555
AA
AA
2AA 55
2AA 55
555
SA
10
30
Sector Erase
Program/Erase suspend*11
Program/Erase Resume *12
CFI Query*13
98
Accelerated Program*15
Unlock Bypass Entry *15
Unlock Bypass Program*15
Unlock Bypass Erase*15
XX
555
XX
XX
A0
AA
A0
80
PA
PD
2AA 55
555
20
PA
XX
PD
10
Unlock Bypass
CFI*13, 15
1
2
XX
98
90
Unlock Bypass Reset *15
XXX
XXX 00
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by
PL064J: A21:A19.
PA = Program Address (A21:A0). Addresses latch on falling edge of /WE or /CE pulse, whichever
happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of /WE or /CE pulse,
whichever happens first.
RA = Read Address (A21:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing.
WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising
edge of /WE.
X = Don’t care
Data Sheet E0950E30 (Ver. 3.0)
87
EHB0010A1MA
Notes: 1. See the Device bus Operation table for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address
bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in
Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status
information).
7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to
obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more
information.
8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.
9. The data is 00h for an unprotected sector group and 01h for a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh
= 220Ah, X0Fh = 2201h).
11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase
Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and
requires bank address.
12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or when device is in autoselect mode.
14. /WP(ACC) must be at VID during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset
command is required to return to the reading array.
Data Sheet E0950E30 (Ver. 3.0)
88
EHB0010A1MA
[Sector Protection Command Definitions]
Bus Cycles *1, 2, 3, 4
Command (Notes)
Reset
Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
3
XXX F0
555 AA
Secured Silicon
Sector Entry *16
2AA 55
2AA 55
555 88
555 90
Secured Silicon
Sector Exit *16
4
6
555 AA
555 AA
XX
00
Secured Silicon
Protection Bit
Program *5,6
RD
(0)
2AA 55
555 60
OW 68
OW 48
OW 48
OW
Secured Silicon
Protection Bit Status
RD
OW
5
4
4
7
6
4
555 AA
555 AA
555 AA
555 AA
555 AA
555 AA
2AA 55
2AA 55
2AA 55
2AA 55
2AA 55
2AA 55
555 60
555 38
555 C8
555 28
555 60
555 90
(0)
Password Program
XX
[0-3] [0-3]
PD
5,7, 8
*
Password Verify
PWA PWD
[0-3] [0-3]
6,8,9
*
Password Unlock
PWA PWD PWA PWD PWA PWD PWA PWD
[0]
7, 10, 11
*
[0]
[1]
[1]
[2]
[2]
[3]
[3]
PPB Program
(SA)
WP
(SA)
WP
(SA)
WP
68
48
RD(0)
5, 6, 11
*
(SA) RD
WP
PPB Status
(0)
All PPB Erase
*
(SA)
WP
6
3
4
555 AA
555 AA
555 AA
2AA 55
2AA 55
2AA 55
555 60
555 78
555 58
WP
60
(SA) 40
RD(0)
5, 6, 13, 14
PPB Lock Bit Set
PPB Lock Bit
Status*15
RD
(1)
SA
DYB Write*7
DYB Erase*7
4
4
555 AA
555 AA
2AA 55
2AA 55
555 48
555 48
SA
SA
X1
X0
RD
(0)
DYB Status*6
4
6
5
6
5
555 AA
555 AA
555 AA
555 AA
555 AA
2AA 55
2AA 55
2AA 55
2AA 55
2AA 55
555 58
555 60
555 60
555 60
555 60
SA
PL
PL
SL
SL
PPMLB Program
68
48
68
48
PL
PL
SL
SL
48
PL
SL
RD(0)
RD(0)
5, 6, 13, 14
*
RD
(0)
PPMLB Status*15
SPMLB Program
48
5, 6, 12
*
RD
(0)
SPMLB Status*5
Legend: DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
Data Sheet E0950E30 (Ver. 3.0)
89
EHB0010A1MA
SA = Sector Address where security command applies. Address bits Amax: A12 uniquely select any
sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes: 1. See Device Bus Operations for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address
bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when
DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 μs timeout is required between any two portions of password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in
cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs
should be programmed to prevent PPB overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. Once the Secured Silicon Sector Entry Command sequence has been entered, the standard array cannot
be accessed until the Exit SecSi Sector command has been entered or the device has been reset.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6,
and DQ7. Write Operation Status and the following subsections describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a program or erase operation is complete or in progress. The device
also provides a hardware-based output signal, RY(/BY), to determine whether an Embedded Program or Erase
operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final
/WE pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is
active for approximately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm
is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7
is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0
Data Sheet E0950E30 (Ver. 3.0)
90
EHB0010A1MA
on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ15–DQ0 while Output Enable (/OE) is asserted low. That is, the device may change
from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive
read cycles.
Write Operation Status shows the outputs for Data# Polling on DQ7. Data# Polling Algorit shows the Data# Polling
algorithm. Data in the AC Characteristic section shows the Data# Polling timing diagram.
START
Read DQ7 to DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7 to DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During chip erase, a valid address is any nonprotected sector
address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Data# Polling Algorithm
RY(/BY): Ready/Busy#
The RY(/BY) is a dedicated, opendrain output pin which indicates whether an Embedded Algorithm is in progress or
complete. The RY(/BY) status is valid after the rising edge of the final /WE pulse in the command sequence. Since
RY(/BY) is an opendrain output, several RY(/BY) pins can be tied together in parallel with a pullup resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks
is in the erase-suspend-read mode. Write Operation Status shows the outputs for RY(/BY).
Data Sheet E0950E30 (Ver. 3.0)
91
EHB0010A1MA
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after
the rising edge of the final /WE pulse in the command sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to
toggle. The system may use either /OE or /CE to control the read cycles. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the DQ7: Data# Polling ).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Write Operation Status shows the outputs for Toggle Bit I on DQ6. Toggle Bit Algorithm shows the toggle bit
algorithm. Toggle Bit Timings (During Embedded Algorithms in Read Operation Timings shows the toggle bit timing
diagrams. DQ2 vs. DQ6 shows the differences between DQ2 and DQ6 in graphical form. See also the DQ2: Toggle
Bit II.
START
Read DQ7 to DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7 to DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Note: 1.The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as
DQ5 changes to “1.” See the DQ6: Toggle Bit I and DQ2: Toggle Bit II for more information.
Toggle Bit Algorithm
Data Sheet E0950E30 (Ver. 3.0)
92
EHB0010A1MA
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final /WE pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The
system may use either /OE or /CE to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Write Operation Status to compare outputs for DQ2 and DQ6.
Toggle Bit Algorithm shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle Bit II explains the
algorithm. See also the DQ6: Toggle Bit I . Toggle Bit Timings (During Embedded Algorithms shows the toggle bit
timing diagram. DQ2 vs. DQ6 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Toggle Bit Algorithm for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After the second read, the system would
compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the
toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still
toggling, the device did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone
high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the
status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation
(top of Toggle Bit Algorithm).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has
begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is
complete, DQ3 switches from a “0” to a “1.” See also the sector erase command Sequence.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle
Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the
Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase
operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the
command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have
been accepted.
Write Operation Status shows the status of DQ3 relative to the other status bits.
Data Sheet E0950E30 (Ver. 3.0)
93
EHB0010A1MA
[Write Operation Status]
Status
DQ7*2
DQ7#
DQ6
DQ5*1
0
DQ3
N/A
DQ2*2
RY(/BY)
0
Embedded Program
Algorithm
Toggle
No toggle
Standard
Mode
Embedded Erase
Algorithm
0
1
Toggle
0
0
1
Toggle
Toggle
0
1
Erase
Suspended
Sector
No toggle
N/A
Erase
Suspend-
Read
Erase
Suspend
Mode
Non-Erase
Suspended
Sector
Data
Data
Data
Data
Data
1
0
1
Erase-Suspend
-Program
DQ7#
Toggle
Invalid
0
N/A
N/A
Reading within
Program
Suspended Sector
Invalid
Invalid
Invalid
Invalid
(Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed)
Program
Suspend
Mode*3
Reading within
Non-program
Data
Data
Data
Data
Data
1
Suspended Sector
Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate
subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the
Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy
bank.
Data Sheet E0950E30 (Ver. 3.0)
94
EHB0010A1MA
Absolute Maximum Ratings
Unit
Parameters
Pins
Range
Notes
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
Voltage with Respect to Ground
–65 to +150
–65 to +125
–0.5 to +4.0
–0.5 to +13.0
–0.5 to +10.5
–0.5 to VCC +0.5
200
°C
°C
V
VCC
1
2
2
1
3
A9, /OE, /RESET
/WP(ACC)
All other pins
V
V
V
Output Short Circuit Current
mA
Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5
V. Maximum Overshoot Waveforms During voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Maximum Overshoot Waveforms .
2. Minimum DC input voltage on pins A9, /OE, /RESET, and /WP(ACC) is –0.5 V. During voltage transitions,
A9, /OE, WP#/ACC, and /RESET may overshoot VSS to –2.0 V for periods of up to 20 ns. See Maximum
Overshoot Waveforms Maximum Overshoot Waveforms. Maximum DC input voltage on pin A9, /OE, and
/RESET is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage
on /WP(ACC) is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only; functional operation of the device at these or any other conditions
above those indicated in the operational sections of this data sheet is not implied. Exposure of the device
to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Maximum Overshoot Waveforms
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Range
Unit
Wireless (W) Devices
Ambient Temperature (TA)
Supply Voltages
–20 to +85
2.7 to 3.6
°C
VCC
V
Note: For all AC and DC specifications, VCC = VCC; contact your local sales office for other VCC options.
Data Sheet E0950E30 (Ver. 3.0)
95
EHB0010A1MA
DC Characteristics
[CMOS Compatible]
Parameter
Parameter
ILI
Description (notes)
Test Conditions
Min
Typ
Max
1.0
Unit
µA
VIN = VSS to VCC,
VCC = VCC max
Input Load Current
A9, /OE, /RESET
Input Load Current
ILIT
ILR
ILO
VCC = VCC max; VID= 12.5 V
VCC = VCC max; VID= 12.5 V
35
35
1.0
µA
µA
µA
Reset Leakage Current
Output Leakage Current
VOUT = VSS to VCC, /OE = VIH
VCC = VCC max
5 MHz
20
45
15
30
55
25
ICC1
VCC Active Read Current*1, 2
/OE = VIH, VCC = VCC max
mA
10 MHz
ICC2
ICC3
ICC4
ICC5
VCC Active Write Current *2, 3
VCC Standby Current *2
VCC Reset Current *2
/OE = VIH, /WE = VIL
mA
µA
µA
µA
/CE, /RESET, /WP(ACC)
= VCC 0.3 V
0.2
0.2
0.2
5
5
5
/RESET = VSS 0.3 V
VIH = VCC 0.3 V;
VIL = VSS 0.3 V
Automatic Sleep Mode*2, 4
5 MHz
10 MHz
5 MHz
10 MHz
21
46
21
46
45
70
45
70
VCC Active Read-While-Program
Current *1, 2
ICC6
/OE = VIH,
mA
VCC Active Read-While-Erase
Current *1, 2
ICC7
ICC8
/OE = VIH,
/OE = VIH
mA
mA
VCC Active Program-While-
Erase-Suspended Current *2,5
17
10
25
ICC9
VIL
VCC Active Page Read Current *2 /OE = VIH, 8 word Page Read
15
mA
V
Input Low Voltage
Input High Voltage
VCC = 2.7–3.6 V
VCC = 2.7–3.6 V
–0.5
2.0
0.8
VIH
VCC+0.3 V
Voltage for ACC
Program Acceleration
VHH
VID
VCC = 3.0 V ± 10%
VCC = 3.0 V 10%
8.5
9.5
V
V
V
Voltage for Autoselect and
Temporary Sector Unprotect
11.5
12.5
0.4
IOL = 2.0 mA, VCC = VCC min,
VCC = 2.7–3.6 V
VOL
Output Low Voltage
VOH
Output High Voltage
IOH = –100 µA, VCC = VCC min
VCC-0.2V
2.3
V
V
VLKO
Low VCC Lock-Out Voltage *5
2.5
Notes: 1. The ICC current listed is typically less than 5 mA/MHz, with /OE at VIH.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
Typical sleep mode current is 2 µA.
5. Not 100% tested.
Data Sheet E0950E30 (Ver. 3.0)
96
EHB0010A1MA
AC Characteristic
Test Conditions
2.7kΩ
Device
Under
Test
C
6.2kΩ
L
VCC = 3.6V
Test Setup*
Note: Diodes are IN3064 or equivalent.
Test Specifications
Test Conditions
All Speeds
Unit
Output Load
1 TTL gate
30
Output Load Capacitance, CL (including jig capacitance)
pF
ns
V
Input Rise and Fall Times
Input Pulse Levels
VCC = 3.0 V
VCC = 3.0 V
5
0.0–3.0
VCC/2
VCC/2
Input timing measurement reference levels
Output timing measurement reference levels
V
V
Data Sheet E0950E30 (Ver. 3.0)
97
EHB0010A1MA
Switching Waveforms
[Key To Switching Waveforms]
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VCC
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
Input Waveforms and Measurement Levels
Data Sheet E0950E30 (Ver. 3.0)
98
EHB0010A1MA
VCC Ramp Rate
All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC >=VCCQ - 100 mV. If the VCC ramp
rate is < 1V/100 µs, a hardware reset required.
Read Operations
[Read-Only Operations]
Speed
Parameter
JEDEC
Options
Std.
tRC
Description (Notes)
Test Setup
70
Unit
ns
ns
ns
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
Read Cycle Time*1
Min
70
tACC
tCE
Address to Output Delay
Chip Enable to Output Delay
Page Access Time
/CE, /OE = VIL
/OE = VIL
Max 70
Max 70
Max 30
Max 30
Max 16
Max 16
tPACC
tOE
tGLQV
tEHQZ
tGHQZ
Output Enable to Output Delay
Chip Enable to Output High Z*3
Output Enable to Output High Z*1, 3
tDF
tDF
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First*3
tAXQX
tOH
Min
5
ns
Read
Min
Min
0
ns
ns
tOEH
Output Enable Hold Time*1
Toggle and Data# Polling
10
Notes: 1. Not 100% tested.
2. See figure Test Setups and Test Specifications for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time
from /OE high to the data bus driven to VCC /2 is taken as tDF.
4. For 70pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all
speed grades
tRC
Addresses Stable
Addresses
tACC
/CE
tRH
tRH
tDF
tOE
/OE
WE
tOEH
tCE
tOH
High Z
High Z
Data
Valid Data
/RESET
RY(/BY)
0 V
Read Operation Timings
Data Sheet E0950E30 (Ver. 3.0)
99
EHB0010A1MA
Same Page
A21 to A3
A2 to A0
Data
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Qa
Qb
Qc
Qd
/CE
/OE
Page Read Operation Timings
Reset
[Hardware Reset (/RESET)]
Parameter
JEDEC Std
tReady /RESET Pin Low (During Embedded Algorithms) to Read Mode*
tReady /RESET Pin Low (NOT During Embedded Algorithms) to Read Mode*
Description
All Speed Options
Unit
µs
ns
Max
Max
Min
Min
Min
Min
20
500
500
50
20
0
tRP
/RESET Pulse Width
ns
tRH
tRPD
tRB
Reset High Time Before Read
/RESET Low to Standby Mode
RY(/BY) Recovery Time
ns
µs
ns
Note: Not 100% tested.
Data Sheet E0950E30 (Ver. 3.0)
100
EHB0010A1MA
RY(/BY)
/CE, /OE
/RESET
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY(/BY)
tRB
/CE, /OE
/RESET
tRP
Reset Timings
Data Sheet E0950E30 (Ver. 3.0)
101
EHB0010A1MA
Erase/Program Operations
[Erase and Program Operations]
Parameter
Speed Options (ns)
JEDEC
tAVAV
tAVWL
Std
Description
70
70
0
Unit
tWC
tAS
Write Cycle Time*1
Min
Min
Min
Min
Address Setup Time
ns
ns
ns
ns
ns
ns
ns
tASO
tAH
Address Setup Time to /OE low during toggle bit polling
Address Hold Time
15
35
0
tWLAX
tAHT
tDS
Address Hold Time From /CE or /OE high during toggle bit polling Min
tDVWH
tWHDX
Data Setup Time
Min
Min
Min
30
0
tDH
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
10
Read Recovery Time Before Write
(/OE High to /WE Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
/CE Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
Min
Max
Max
0
ns
ns
ns
ns
ns
µs
µs
sec
µs
ns
ns
ns
µs
µs
tCH
/CE Hold Time
0
tWP
Write Pulse Width
35
25
0
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
tWHWH1 tWHWH1 Programming Operation*2
tWHWH1 tWHWH1 Accelerated Programming Operation *2
tWHWH2 tWHWH2 Sector Erase Operation *2
6
4
0.5
50
0
tVCS
tRB
VCC Setup Time *1
Write Recovery Time from RY(/BY)
Program/Erase Valid to RY(/BY) Delay
90
35
35
35
tBUSY
tPSL
tESL
Program Suspend Latency
Erase Suspend Latency
Notes: 1. Not 100% tested.
2. See the Erase And Programming Performance section for more information.
Data Sheet E0950E30 (Ver. 3.0)
102
EHB0010A1MA
Timing Diagrams
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
/CE
/OE
tCH
tWHWH1
tWP
/WE
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY(/BY)
VCC
tVCS
Note: 1. PA = program address, PD = program data, DOUT is the true data at the program address
Program Operation Timings
VHH
VIL or VIH
VIL or VIH
/WP(ACC)
tVHH
tVHH
Accelerated Program Timing Diagram
Data Sheet E0950E30 (Ver. 3.0)
103
EHB0010A1MA
Erase Command Sequence (last two cycles)
tAS
Read Status Data
VA
VA
Addresses
/CE
2AAh
SA
555h for chip erase
tAH
tCH
/OE
tWP
/WE
tWPH
tWHWH2
tCS
tDS
tDH
Data
Status
D
OUT
55h
30h
10 for Chip Erase
tBUSY
tRB
RY(/BY)
VCC
tVCS
Note: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see W
Chip/Sector Erase Operation Timings
tWC
Valid PA
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tAS
tCPH
tAS
tAH
tACC
tCE
/CE
tCP
tOE
/OE
tOEH
tGHWL
tWP
/WE
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
/WE Controlled Write Cycle
Read Cycle
/CE Controlled Write Cycles
Back-to-back Read/Write Cycle Timings
Data Sheet E0950E30 (Ver. 3.0)
104
EHB0010A1MA
Addresses
VA
tACC
tCE
VA
VA
/CE
tCH
tOE
/OE
/WE
tOEH
tOH
High Z
DQ7
Valid Data
Complement
Complement
Tru
High Z
DQ6 to DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY(/BY)
Note: 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle,
and array data read cycle
Data# Polling Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
/CE
tAHT
tASO
tCEPH
tOEH
/WE
/OE
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY(/BY)
Note: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command
sequence, last status read cycle, and array data read cycle
Toggle Bit Timings (During Embedded Algorithms)
Data Sheet E0950E30 (Ver. 3.0)
105
EHB0010A1MA
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase
Erase Suspend
Read
/WE
Erase
Erase Suspend
Read
Erase
Complete
DQ6
DQ2
Note: 1. DQ2 toggles only when read at an address within an erasesuspended sector. The system may use /OE or
/CE to toggle DQ2 and DQ6.
DQ2 vs. DQ6
Protect/Unprotect
[Temporary Sector Unprotect]
Parameter
JEDEC
Std
Description
All Speed Options
Unit
ns
tVIDR
tVHH
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
/RESET Setup Time for Temporary Sector
Unprotect
tRSP
tRRB
Min
Min
4
4
µs
µs
/RESET Hold Time from RY(/BY) High for
Temporary Sector Unprotect
Note: Not 100% tested.
VID
VID
/RESET
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
/CE
/WE
tRRB
tRSP
RY(/BY)
Temporary Sector Unprotect Timing Diagram
Data Sheet E0950E30 (Ver. 3.0)
106
EHB0010A1MA
VID
VIH
/RESET
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
40h
Data
60h
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
/CE
/WE
/OE
Note: 1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Sector/Sector Block Protect and Unprotect Timing Diagram
Controlled Erase Operations
[Alternate /CE Controlled Erase and Program Operations]
Parameter
JEDEC
tAVAV
Speed Options
Unit
Std
Description (Notes)
Write Cycle Time*1
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
70
70
0
tWC
tAS
tAH
tDS
tDH
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
tAVWL
tELAX
35
30
0
tDVEH
tEHDX
Read Recovery Time Before Write (/OE High to /WE
Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tWS
tWH
tCP
/WE Setup Time
/WE Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
ns
ns
ns
ns
µs
µs
sec
tEHWH
tELEH
0
/CE Pulse Width
/CE Pulse Width High
40
25
6
tEHEL
tCPH
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation*2
tWHWH1 Accelerated Programming Operation*2
tWHWH2 Sector Erase Operation*2
4
0.5
Notes: 1. Not 100% tested.
2. See the Erase And Programming Performance section for more information.
Data Sheet E0950E30 (Ver. 3.0)
107
EHB0010A1MA
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
/WE
/OE
tGHEL
tWHWH1 or 2
tCP
/CE
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
/RESET
RY(/BY)
Notes: 1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device
Alternate /CE Controlled Write (Erase/Program) Operation Timings
Data Sheet E0950E30 (Ver. 3.0)
108
EHB0010A1MA
[Erase And Programming Performance]
Parameter
Typ*1
Max
2
Unit
sec
sec
Comments
Sector Erase Time
Chip Erase Time
0.5
71
Excludes 00h programming
prior to erasure *3
113.6
Excludes system level
overhead *4
Word Program Time
6
100
µs
Accelerated Word Program Time
Chip Program Time *2
4
60
µs
25.2
50.4
sec
Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles.
Additionally, programming typicals assume checkerboard pattern. All values are subject to change.
2. The typical chip programming time is considerably less than the maximum chip programming time listed,
since most bytes program faster than the maximum program times listed.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before
erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the
program command. See Memory Array Command Definitions for further information on command
definitions.
Pin Capacitance
Parameter Symbol Parameter Description
Test Setup
VIN = 0
Typ
6.3
7.0
5.5
11
Max
7
Unit
pF
CIN
Input Capacitance
COUT
CIN2
CIN3
Output Capacitance
VOUT = 0
VIN = 0
8
pF
Control Pin Capacitance
/WP(ACC)Pin Capacitance
8
pF
VIN = 0
12
pF
Notes: 1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Data Sheet E0950E30 (Ver. 3.0)
109
EHB0010A1MA
Package Drawing
151-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
10.4 ± 0.1
INDEX MARK
0.15 S A
0.15 S B
S
0.2
0.72 ± 0.08
S
S
0.1
0.22 ± 0.05
A
M
151-φ0.35 ± 0.05
φ0.15
S A B
B
0.65
9.1
ECA-TS2-0187-01
Data Sheet E0950E30 (Ver. 3.0)
110
EHB0010A1MA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EHB0010A1MA.
Type of Surface Mount Device
EHB0010A1MA: 151-ball FBGA < Lead free (Sn-Ag-Cu) >
Data Sheet E0950E30 (Ver. 3.0)
111
EHB0010A1MA
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0950E30 (Ver. 3.0)
112
EHB0010A1MA
Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC.
All other trademarks are the intellectual property of their respective owners.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0950E30 (Ver. 3.0)
113
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