HM51W16405LTS-7 [ELPIDA]
16 M EDO DRAM (4-Mword ´ 4-bit) 4 k Refresh/2 k Refresh; 16M的EDO DRAM （ 4 - Mword “ 4位）， 4K的刷新/ 2 k刷新
| 型号： | HM51W16405LTS-7 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 16 M EDO DRAM (4-Mword ´ 4-bit) 4 k Refresh/2 k Refresh |
| 文件： | 总35页 (文件大小：604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM51W16405 Series
HM51W17405 Series
16 M EDO DRAM (4-Mword × 4-bit)
4 k Refresh/2 k Refresh
E0152H10 (Ver. 1.0)
(Previous ADE-203-647D (Z))
Jul. 6, 2001 (K)
Description
The HM51W16405 Series, HM51W17405 Series are CMOS dynamic RAMs organized 4,194,304-word ×
4-bit. They employ the most advanced CMOS technology for high performance and low power. The
HM51W16405 Series, HM51W17405 Series offer Extended Data Out (EDO) Page Mode as a high speed
access mode.They have package variations of standard 300-mil 26-pin plastic SOJ and 300-mil 26-pin
plastic TSOP.
Features
•
•
•
Single 3.3 V (±0.3 V)
Access time: 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode : 324 mW /288 mW /252 mW (max) (HM51W16405 Series)
: 360mW/324 mW/288 mW (max) (HM51W17405 Series)
Standby mode : 7.2 mW (max)
: 0.36 mW (max) (L-version)
EDO page mode capability
•
•
Long refresh period
4096 refresh cycles : 64 ms (HM51W16405 Series)
: 128 ms (L-version)
2048 refresh cycles : 32 ms (HM51W17405 Series)
: 128 ms (L-version)
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM51W16405 Series, HM51W17405 Series
•
•
Battery backup operation (L-version)
Test function
16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM51W16405S-5
HM51W16405S-6
HM51W16405S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM51W16405LS-5
HM51W16405LS-6
HM51W16405LS-7
50 ns
60 ns
70 ns
HM51W17405S-5
HM51W17405S-6
HM51W17405S-7
50 ns
60 ns
70 ns
HM51W17405LS-5
HM51W17405LS-6
HM51W17405LS-7
50 ns
60 ns
70 ns
HM51W16405TS-5
HM51W16405TS-6
HM51W16405TS-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM51W16405LTS-5
HM51W16405LTS-6
HM51W16405LTS-7
50 ns
60 ns
70 ns
HM51W17405TS-5
HM51W17405TS-6
HM51W17405TS-7
50 ns
60 ns
70 ns
HM51W17405LTS-5
HM51W17405LTS-6
HM51W17405LTS-7
50 ns
60 ns
70 ns
Data Sheet E0152H10
2
HM51W16405 Series, HM51W17405 Series
Pin Arrangement
HM51W16405S/LS Series
HM51W16405TS/LTS Series
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
RAS
A11
RAS
A11
A9
A9
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
10
11
12
13
10
11
12
13
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A11
A0 to A11
— Column address
Data input/Data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
A0 to A9
I/O1 to I/O4
RAS
CAS
WE
OE
VCC
Power supply
VSS
Ground
Data Sheet E0152H10
3
HM51W16405 Series, HM51W17405 Series
Pin Arrangement
HM51W17405S/LS Series
HM51W17405TS/LTS Series
VCC
I/O1
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
VCC
I/O1
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
I/O2
WE
I/O2
WE
RAS
NC
RAS
NC
A9
A9
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
9
10
11
12
13
10
11
12
13
VCC
VCC
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A10
Address input
— Row/Refresh address A0 to A10
— Column address
Data input/Data output
Row address strobe
Column address strobe
Read/Write enable
Output enable
A0 to A10
I/O1 to I/O4
RAS
CAS
WE
OE
VCC
Power supply
VSS
Ground
NC
No connection
Data Sheet E0152H10
4
HM51W16405 Series, HM51W17405 Series
Block Diagram(HM51W16405 Series)
RAS
CAS
WE
OE
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A9
4M array
4M array
4M array
I/O1
to
I/O4
•
•
•
I/O buffers
Row
address
buffers
A10
A11
Data Sheet E0152H10
5
HM51W16405 Series, HM51W17405 Series
Block Diagram(HM51W17405 Series)
RAS
CAS
WE
OE
Timing and control
A0
A1
to
Column decoder
4M array
Column
address
buffers
•
•
•
A10
4M array
4M array
4M array
I/O1
to
I/O4
I/O buffers
•
•
•
Row
address
buffers
Data Sheet E0152H10
6
HM51W16405 Series, HM51W17405 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to VCC + 0.5 (≤ +4.6 V (max))
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70˚C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
Input high voltage
Input low voltage
3.6
1, 2
1
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Note: 1. All voltage referred to VSS.
Data Sheet E0152H10
7
HM51W16405 Series, HM51W17405 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16405 Series)
HM51W16405
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
90
2
—
—
80
2
—
—
70 mA
tRC = min
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
100 — 100 — 100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
90
5
—
—
80
5
—
—
70 mA
mA
tRC = min
5
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
ICC6
—
90
80
—
—
80
70
—
—
70 mA
65 mA
tRC = min
current
EDO page mode current*1, *3 ICC7
—
—
tHPC = min
Battery backup current
ICC10
300 — 300 — 300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 — 200 — 200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA
–10 10 –10 10 –10 10 µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
0
0
0
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Data Sheet E0152H10
8
HM51W16405 Series, HM51W17405 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17405 Series)
HM51W17405
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
100 — 90
—
—
80 mA
tRC = min
2
—
2
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
100 — 100 — 100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
100 — 90
—
—
80 mA
mA
tRC = min
5
—
5
5
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
ICC6
—
100 — 90
90 80
—
—
80 mA
75 mA
tRC = min
current
EDO page mode current*1, *3 ICC7
—
—
—
tHPC = min
Battery backup current
ICC10
300 — 300 — 300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 62.5 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 — 200 — 200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA
–10 10 –10 10 –10 10 µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
0
0
0
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Data Sheet E0152H10
9
HM51W16405 Series, HM51W17405 Series
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
Data Sheet E0152H10
10
HM51W16405 Series, HM51W17405 Series
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input levels: VIL = 0 V, VIH = 3 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
tRC
84
30
8
—
—
—
104
40
—
—
—
124
50
—
—
—
ns
ns
ns
tRP
tCP
10
13
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
50
8
10000 60
10000 10
10000 70
10000 13
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
0
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
0
10
0
0
8
10
14
12
13
40
5
13
14
12
13
45
5
12
10
10
35
5
3
4
RAS to column address delay time tRAD
RAS hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
13
0
15
0
18
0
5
6
6
7
0
0
0
2
2
2
Data Sheet E0152H10
11
HM51W16405 Series, HM51W17405 Series
Read Cycle
HM51W16405/HM51W17405
-5 -6 -7
Symbol Min Max Min Max Min
Parameter
Max Unit
Notes
Access time from RAS
Access time from CAS
tRAC
tCAC
—
—
50
13
—
—
60
15
—
—
70
18
ns
ns
8, 9, 20
9, 10, 17,
20
Access time from address
tAA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from OE
tOEA
tRCS
tRCH
tRCHR
—
0
13
—
—
—
—
0
15
—
—
—
—
0
18
—
—
—
ns
ns
ns
ns
9, 20
Read command setup time
Read command hold time to CAS
0
0
0
12
Read command hold time from
50
60
70
RAS
Read command hold time to RAS
tRRH
0
—
—
—
—
—
—
13
13
—
—
13
13
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
22
Column address to RAS lead time tRAL
Column address to CAS lead time tCAL
25
15
0
30
18
0
35
23
0
CAS to output in low-Z
tCLZ
Output data hold time
tOH
3
3
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
tOHR
tOFR
tWEZ
tWED
tRDD
tRNCD
3
3
3
—
—
13
3
—
—
15
3
—
—
18
3
13, 22
13
5
Output data hold time from RAS
Output buffer turn-off to RAS
Output buffer turn-off to WE
WE to Din delay time
22
—
—
13
13
50
—
—
15
15
60
—
—
18
18
70
22
RAS to Din delay time
RAS next CAS delay time
Data Sheet E0152H10
12
HM51W16405 Series, HM51W17405 Series
Write Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
8
8
8
8
0
8
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
14
10
10
10
10
0
13
10
13
13
0
tRWL
tCWL
tDS
15
15
Data-in hold time
tDH
10
13
Read-Modify-Write Cycle
HM51W16405/HM51W17405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
111
67
30
42
13
—
—
—
—
—
135
79
34
49
15
—
—
—
—
—
161
92
40
57
18
—
—
—
—
—
ns
ns
ns
ns
ns
14
14
14
Column address to WE delay time tAWD
OE hold time from WE
tOEH
Refresh Cycle
HM51W16405/HM51W17405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
WE setup time (CBR refresh cycle) tWRP
WE hold time (CBR refresh cycle) tWRH
5
8
0
8
5
—
—
—
—
—
5
—
—
—
—
—
5
—
—
—
—
—
ns
ns
ns
ns
ns
10
0
10
0
10
5
10
5
RAS precharge to CAS hold time
tRPC
Data Sheet E0152H10
13
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Cycle
HM51W16405/HM51W17405
-5 -6 -7
Symbol Min Max Min Max Min Max
25 30
100000 —
Parameter
Unit
Notes
21
EDO page mode cycle time
tHPC
20
—
—
30
3
—
—
—
ns
EDO page mode RAS pulse width tRASP
Access time from CAS precharge tCPA
100000 — 100000 ns
16
30
—
—
—
—
—
—
35
3
35
—
—
—
—
—
—
40
3
40
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9, 17, 20
RAS hold time from CAS precharge tCPRH
Output data hold time from CAS low tDOH
9, 17
CAS hold time referred OE
CAS to OE setup time
tCOL
8
10
5
13
5
tCOP
tRCHC
5
Read command hold time from
30
35
40
CAS precharge
EDO Page Mode Read-Modify-Write Cycle
HM51W16405/HM51W17405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
EDO page mode read- modify-write tHPRWC
cycle time
57
—
68
—
79
ns
WE delay time from CAS precharge tCPW
45
—
54
—
62
ns
14
Test Mode Cycle *19
HM51W16405/HM51W17405
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
Test mode WE setup time
Test mode WE hold time
tWTS
tWTH
0
8
—
—
0
—
—
0
—
—
ns
ns
10
10
Refresh (HM51W16405 Series)
Parameter
Symbol
tREF
Max
Unit
ms
Notes
Refresh period
64
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
Data Sheet E0152H10
14
HM51W16405 Series, HM51W17405 Series
Refresh (HM51W17405 Series)
Parameter
Symbol
tREF
Max
32
Unit
ms
Notes
Refresh period
2048 cycles
2048 cycles
Refresh period (L-version)
tREF
128
ms
Self Refresh Mode (L-version)
HM51W16405L/HM51W17405L
-5
Symbol Min
-6
-7
Parameter
Max Min
Max Min
Max Unit
Notes
RAS pulse width (self refresh)
tRASS
100
90
—
—
—
100
110
–50
—
—
—
100
—
—
—
µs
ns
ns
RAS precharge time (self refresh) tRPS
CAS hold time (self refresh) tCHS
130
–50
–50
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
Data Sheet E0152H10
15
HM51W16405 Series, HM51W17405 Series
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to device.
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
×4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-
before-RAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding theabove
value to the specified value in this data sheet.
21. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater
than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF
.
23. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS
precharge time should use tRPS instead of tRP.
24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048
cycles (4096 cycles: HM51W16405 Series, 2048 cycles: HM51W17405 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 32 ms (64 ms: HM51W16405
Series, 32 ms: HM51W17405 Series) immediately after exiting from and before entering into the
self refresh mode.
26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
27. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Data Sheet E0152H10
16
HM51W16405 Series, HM51W17405 Series
Timing Waveforms*27
Read Cycle
t
t
RC
t
RAS
RP
RAS
CAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
Row
ASC
t
RAH
Address
Column
t
RRH
t
RCHR
t
t
RCH
CDD
t
RCS
WE
t
WED
t
DZC
t
RDD
High-Z
Din
t
t
t
OED
DZO
OEA
OE
t
OEZ
t
OHO
t
CAC
t
OFF
t
AA
t
OH
t
t
RAC
OFR
t
t
CLZ
OHR
t
WEZ
Dout
Dout
Data Sheet E0152H10
17
HM51W16405 Series, HM51W17405 Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
Data Sheet E0152H10
18
HM51W16405 Series, HM51W17405 Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
Din
t
t
t
DH
DZC
DS
High-Z
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
Data Sheet E0152H10
19
HM51W16405 Series, HM51W17405 Series
Read-Modify-Write Cycle *18
t
t
RWC
RAS
t
RP
RAS
CAS
t
T
t
t
t
CRP
RCD
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
Data Sheet E0152H10
20
HM51W16405 Series, HM51W17405 Series
RAS-Only Refresh Cycle
t
RC
t
t
RAS
RP
RAS
CAS
t
T
t
t
t
CRP
CRP
RPC
t
t
RAH
ASR
Address
Row
t
OFR
t
OFF
High-Z
Dout
Data Sheet E0152H10
21
HM51W16405 Series, HM51W17405 Series
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
CRP
t
CSR
CHR
RPC
RPC
t
T
t
CP
t
t
t
WRH
CP
WRP
WE
Address
t
OFR
t
OFF
High-Z
Dout
Data Sheet E0152H10
22
HM51W16405 Series, HM51W17405 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASR
ASC
Address
Row
Column
t
t
t
RRH
t
WRH
t
WRP
RCH
t
RRH
t
WRH
WRP
t
t
RCS
DZC
WE
t
WED
t
t
CDD
RDD
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
OEZ
t
CAC
t
WEZ
OHO
t
AA
t
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
t
OFR
t
OHR
Data Sheet E0152H10
23
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Read Cycle
t
RP
t
t
RNCD
t
HPC
t
RASP
RAS
CAS
t
t
t
CRP
HPC
t
HPC
t
CPRH
CP
t
t
T
CSH
t
CP
t
t
CP
t
RSH
t
t
CAS
CAS
CAS
CAS
t
RCHC
t
RCHR
tRCS
t
t
RRH
RCH
tRCS
tRCH
WE
t
RAL
t
t
CAH
t
tCAH
tCAH
WED
tASC
tASC
tCAH
tRAH
ASC
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
CAL
Column 4
t
t
CAL
CAL
CAL
t
t
RDD
CDD
t
DZC
High-Z
Din
t
t
t
DZO
COP
COL
t
OED
OE
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
CPA
AA
t
OHR
OEZ
AA
t
t
OEZ
AA
t
t
CAC
t
CAC
t
OEZ
t
t
t
OHO
CAC
AA
t
t
t
t
t
CAC
WEZ
OHO
OFF
OH
tOEA
t
t
RAC
OEA
t
DOH
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
Data Sheet E0152H10
24
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Early Write Cycle
tRASP
tRP
RAS
tT
tCSH
tHPC
tRSH
tCAS
tCP
tCAS
tCP
tCRP
tCAS
tRCD
CAS
tRAH
tASR
tASC tCAH
tASC
tCAH
tCAH
tASC
Row
Column 1
Column 2
Column N
Address
tWCH
tWCH
tWCS
tWCS
tWCS tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
Data Sheet E0152H10
25
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Delayed Write Cycle *18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
HPC
RSH
CAS
t
t
t
CAS
RCD
CAS
CAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
Data Sheet E0152H10
26
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Read-Modify-Write Cycle *18
t
RASP
t
RP
RAS
t
t
T
HPRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
Data Sheet E0152H10
27
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Mix Cycle (1)
t
RP
t
RASP
RAS
t
CRP
t
T
t
t
t
CP
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
CAS
t
CSH
t
RSH
tRCD
tWCS
t
t
tRCS
RRH
RCH
tRCS
tWCH
t
t
WE
CPW
AWD
tWP
t
RAL
tCAH
tASC
tRAH
tASC
t
tASC tCAH
tCAH
CAH
tASC
tASR
Address
Row
Column 1
t
Column 2
t
Column 3
t
Column 4
CAL
CAL
CAL
t
t
RDD
CAL
t
t
CDD
DH
t
t
DH
Din 1
DS
t
DS
High-Z
Din
Din 3
t
OED
t
WED
OE
t
t
OFR
WEZ
t
CPA
CPA
t
t
t
t
CPA
t
AA
t
AA
t
OEZ
OEZ
t
t
t
OEA
AA
CAC
OHO
t
CAC
tOHO
t
t
OEA
CAC
t
t
OFF
OH
t
DOH
Dout
Dout 2
Dout 3
Dout 4
Data Sheet E0152H10
28
HM51W16405 Series, HM51W17405 Series
EDO Page Mode Mix Cycle (2)
t
RNCD
t
RP
t
RASP
RAS
CAS
t
CRP
t
t
T
t
CSH
t
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
tRCD
tRCS
tRCHR
t
RSH
t
RCS
t
RRH
RCH
tWCS
tWCH
t
RCS
tRCH
t
tWP
t
WE
CPW
t
RAL
tASC
tRAH
t
CAH
tASC
tASC tCAH
tCAH
tCAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
Column 4
t
t
CAL
CAL
CAL
CAL
t
DS
t
t
RDD
CDD
t
t
t
DH
DS
DH
High-Z
Din
Din 2
Din 3
t
t
OED
t
COP
OED
t
WED
t
COL
OE
t
OFR
WEZ
t
t
OEA
t
t
t
t
CPA
t
AA
t
CPA
t
OEA
AA
OEZ
t
t
AA
OEZ
t
CAC
t
t
CAC
OEZ
OHO
t
t
RAC
CAC
t
OEA
t
t
t
OFF
OH
t
OHO
OHO
Dout
Dout 1
Dout 4
Dout 3
Data Sheet E0152H10
29
HM51W16405 Series, HM51W17405 Series
Test Mode Cycle *19
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
Data Sheet E0152H10
30
HM51W16405 Series, HM51W17405 Series
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
CAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
t
t
t
t
CP
CP
WTS
WTH
WE
Address
t
OFR
t
OFF
High-Z
Dout
Data Sheet E0152H10
31
HM51W16405 Series, HM51W17405 Series
24, 25, 26
Self Refresh Cycle (L-version)*23,
*
*
*
t
t
t
RASS
RP
RPS
RAS
t
T
t
RPC
t
CRP
t
t
CSR
CP
t
CHS
CAS
WE
t
t
WRH
WRP
t
OFR
t
OFF
High-Z
Dout
Data Sheet E0152H10
32
HM51W16405 Series, HM51W17405 Series
Package Dimensions
HM51W16405S/LS Series
HM51W17405S/LS Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
26
1
21 19
14
13
6
8
0.74
1.30 Max
+ 0.19
– 0.18
1.27
0.10
6.79
0.43 ± 0.10
0.41 ± 0.08
2.54
Hitachi Code
JEDEC
EIAJ
CP-26/24DB
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.8 g
Data Sheet E0152H10
33
HM51W16405 Series, HM51W17405 Series
HM51W16405TS/LTS Series
HM51W17405TS/LTS Series (TTP-26/24DA)
Unit: mm
17.14
17.54 Max
26
1
21 19
14
13
6
8
1.27
0.80
0.42 ± 0.08
0.40 ± 0.06
0.21 M
9.22 ± 0.20
1.15 Max
2.54
0.10
0° – 5°
0.50 ± 0.10
Hitachi Code
TTP-26/24DA
JEDEC
EIAJ
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.30 g
Data Sheet E0152H10
34
HM51W16405 Series, HM51W17405 Series
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party’s rights, including intellectual property rights, in connection with use of the information contained
in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands
especially high quality and reliability or where its failure or malfunction may directly threaten human
life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control,
transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory,
Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure
or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider
normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic
measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not
cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc.
product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
Data Sheet E0152H10
36
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