HM5316123BF-7_技术文档

HM5316123B Series

Preliminary

131,072-word × 16-bit Multiport CMOS Video RAM

E0160H10 (Ver. 1.0)

(Previous ADE-203-266 (Z))

Jun. 14, 2001

The HM5316123B is a 2-Mbit multiport video • Bidirectional data transfer cycle between RAM

and SAM capability

RAM equipped with a 128-kword × 16-bit dynamic

• Split transfer cycle capability

RAM and a 256-word × 16-bit SAM (full-sized

• Block write mode capability

SAM). Its RAM and SAM operate independently

• Flash write mode capability

and asynchronously. The HM5316123B has • 3 variations of refresh (8 ms/512 cycles)

–RAS-only refresh

–CAS-before-RAS refresh

–Hidden refresh

compatibility with the HM5316123.

Features

• TTL compatible

• Multiport organization

Asynchronous and simultaneous operation of

RAM and SAM capability

RAM: 128-kword × 16-bit

SAM: 256-word × 16-bit

• Access time

RAM: 70 ns/80 ns/100 ns (max)

SAM: 20 ns/23 ns/25 ns (max)

• Cycle time

Ordering Information

Type No.

Access time Package

———————————————————————

HM5316123BF-7

——————————————

HM5316123BF-8 80ns

——————————————

HM5316123BF-10 100ns

———————————————————————

70ns

64-pin plastic

shrink SOP

(FP-64DS)

RAM: 130 ns/150 ns/180 ns (min)

SAM: 25 ns/28 ns/30 ns (min)

• Low power

Active

RAM: 660 mW/605 mW/550 mW

SAM: 468 mW/413 mW/385 mW

Standby 38.5mW (max)

• Masked-write-transfer cycle capability

• Stopping column feature capability

• Persistent mask capability

• Byte write control capability: 2WE control

• Fast page mode capability

Cycle time: 45ns/50ns/55ns

Power RAM: 688 mW/660 mW/633 mW

• Mask write mode capability

Preliminary: This document contains information on a new

product. Specifications and information contained herein

are subject to change without notice.

Elpida Memory, Inc. is a joint venture DRAM company of NEC corporation and Hitachi, Ltd.

HM5316123B Series

Pin Arrangement

Pin Description

HM5316123BF Series

Symbol

Function

——————————————————————–

A0 – A8 Address inputs

——————————————————————–

I/O0 – I/O15 RAM port data inputs/outputs

——————————————————————–

SI/O0 – SI/O15 SAM port data inputs/outputs

——————————————————————–

RAS Row address strobe

——————————————————————–

CAS Column address strobe

——————————————————————–

WEU Upper byte write enable

——————————————————————–

WEL Lower byte write enable

——————————————————————–

DT/OE Date transfer/output enable

——————————————————————–

SC Serial clock

——————————————————————–

SE SAM port enable

——————————————————————–

DSF1, DSF2 Special function input flag

——————————————————————–

QSF Special function output flag

——————————————————————–

Power Supply

——————————————————————–

Ground

——————————————————————–

V_CC

DT/DE

V_SS

SI/O0

I/O0

SI/O1

I/O1

1

2

3

4

5

6

7

8

9

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SC

SE

V_SS

SI/O15

I/O15

SI/O14

I/O14

V_CC

SI/O2

SI/O13

I/O13

SI/O12

I/O12

V_SS

SI/O11

I/O11

SI/O10

I/O10

V_CC

SI/O9

I/O9

SI/O8

I/O8

V_SS

I/O2 10

SI/O3 11

I/O3 12

V_SS13

SI/O4 14

I/O4 15

SI/O5 16

I/O5 17

V_CC18

SI/O6 19

I/O6 20

SI/O7 21

I/O7 22

V_SS23

WEL 24

WEU 25

RAS 26

A8 27

DSF1

DSF2

CAS

QSF

A0

A7 28

A6 29

A1

V

CC

A5 30

A2

A4 31

A3

V

SS

V_CC32

V_SS

(Top View)

Preliminary Data Sheet E0160H10

2

HM5316123B Series

Block Diagram

A0 – A8

A0 – A7

A0 – A8

Row Address

Buffer

Column Address

Buffer

Refresh

Counter

Serial Address

QSF

Row Decoder

Memory Array

Counter

0

255

511

0

Input Data

Control

Serial Output Serial Input

Buffer Buffer

SI/O0 – SI/O15

Input

Buffer

Output

Buffer

Timing Generator

I/O0 – I/O15

Preliminary Data Sheet E0160H10

3

HM5316123B Series

Pin Functions

RAS (input pin): RAS is a basic RAM signal. It is

active in low level and standby in high level. Row

address and signals as shown in table 1 are input at

the falling edge of RAS. The input level of these

signals determine the operation cycle of the

HM5316123B.

Table 1. Operation Cycles of the HM5316123B

RAS

Mnemonic ———————————————— ——————— —————— ——————————

Code CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS CAS RAS CAS/WE

———————————————————————————————————————————————–

CBRS Stop

———————————————————————————————————————————————–

CBRR

———————————————————————————————————————————————–

CBRN

———————————————————————————————————————————————–

MWT Row TAP WN

———————————————————————————————————————————————–

MSWT Row TAP WM

———————————————————————————————————————————————–

RT Row TAP

———————————————————————————————————————————————–

SRT Row TAP

———————————————————————————————————————————————–

RWM Row Column WM Input data

CAS

Address

I/On Input

0

—

0

1

0

—

0

—

0

—

1

0

—

0

—

0

—

1

0

—

0

—

1

0

—

0

—

1

0

1

0

—

0

—

1

0

1

0

—

0

—

1

0

1

0

—

0

—

1

0

———————————————————————————————————————————————–

Register

Mnemonic Write

Code Mask

Pers

W.M.

———————– No.of

WM Color Bndry

Function

———————————————————————————————————————————————–

CBRS Set CBR refresh with stop resister set

———————————————————————————————————————————————–

CBRR Reset Reset Reset CBR refresh with register reset

———————————————————————————————————————————————–

CBRN CBR refresh (no reset)

———————————————————————————————————————————————–

—

MWT

Yes

No

Yes

Load/use —

Use

—

Mask write transfer (new/old mask)

———————————————————————————————————————————————–

MSWT

Yes

No

Yes

Load/use —

Use

Masked split write transfer (new/old mask)

———————————————————————————————————————————————–

RT Read transfer

———————————————————————————————————————————————–

SRT Use Split read transfer

———————————————————————————————————————————————–

—

RWM

YES

No

Yes

Load/use —

Use

—

Road/write (new/old mask)

———————————————————————————————————————————————–

Preliminary Data Sheet E0160H10

4

HM5316123B Series

Table 1. Operation Cycles of the HM5316123B (cont)

Mnemonic RAS

————————————————

CAS DT/OE WE DSF1 DSF2

CAS

Address

—————— ——————

I/On Input

—————————–

Code

DSF1 DSF2 RAS CAS

RAS

CAS/WE

———————————————————————————————————————————————–

BWM

1

0

1

0

Row Column WM

Column

Mask

———————————————————————————————————————————————–

RW (No) Row Column Input data

———————————————————————————————————————————————–

1

0

—

BW (No)

1

0

1

0

Row Column

—

Column

Mask

———————————————————————————————————————————————–

FWM Row WM

———————————————————————————————————————————————–

1

0

1

0

—

0

—

LMR and

Old Mask Set

1

0

(Row) —

—

Mask

Data

———————————————————————————————————————————————–

LCR (Row) — Color

———————————————————————————————————————————————–

Option Mode — Data

1

0

1

0

—

0

—

0

—

———————————————————————————————————————————————–

Register

Mnemonic Write

Code Mask

Pers

W.M.

———————

WM Color

No.of

Bndry

Function

———————————————————————————————————————————————–

BWM

Yes

No

Yes

Load/use

Use

Block write (new/old mask)

Use

—

———————————————————————————————————————————————–

RW (No) No No Read/write (no mask)

———————————————————————————————————————————————–

BW (No) No No Use Block write (no mask)

———————————————————————————————————————————————–

—

FWM

Yes

No

Yes

Load/use Use

Use

—

Masked flash write (new/old mask)

———————————————————————————————————————————————–

LMR and Set Load Load mask register and old mask set

Old Mask Set

———————————————————————————————————————————————–

LCR Load Load color resister set

———————————————————————————————————————————————–

Option

—

———————————————————————————————————————————————–

Notes: 1. With CBRS, all SAM operations use stop register.

2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR.

3. DSF2 is fixed low in all operation. (for the addition of operation mode in future)

Preliminary Data Sheet E0160H10

5

HM5316123B Series

CAS (input pin): Column address and DSF1

signals are fetched into chip at the falling edge of

CAS, which determines the operation mode of the

HM5316123B. CAS controls output impedance of

I/O in RAM.

DT/OE (input pin): DT/OE pin functions as DT

(data transfer) pin at the falling edge of RAS and

as OE (output enable) pin after that. When DT is

low at the falling edge of RAS, this cycle becomes

a transfer cycle. When DT is high at the falling

edge of RAS, RAM and SAM operate

independently.

A0 – A8 (input pins): Row address (AX0 – AX8)

is determined by A0 – A8 level at the falling edge

of RAS. Column address (AY0 – AY7) is

determined by A0 – A7 level at the falling edge of

CAS. In transfer cycles, row address is the address

on the word line which transfers data with SAM

data register, and column address is the SAM start

address after transfer.

SC (input pin): SC is a basic SAM clock. In a

serial read cycle, data outputs from an SI/O pin

synchronously with the rising edge of SC. In a

serial write cycle, data on an SI/O pin at the rising

edge of SC is fetched into the SAM data register.

SE (input pin): SE pin activates SAM. When SE is

high, SI/O is in the high impedance state in serial

read cycle and data on SI/O is not fetched into the

SAM data register in serial write cycle. SE can be

used as a mask for serial write because the internal

pointer is incremented at the rising edge of SC.

WEU and WEL (Input pins): WEU and WEL pins

have two functions at the falling edge of RAS and

after. When either WEU or WEL is low at the

falling edge of RAS, the HM5316123B turns to

mask write mode. According to the I/O level at the

time, write on each I/O can be masked. (WEU and

WEL levels at the falling edge of RAS is don’t

care in read cycle.) When both WEU and WEL

are high at the falling edge of RAS, a no mask

write cycle is executed. After that, WEU and

WEL switch read/write cycles. Both WEU and

WEL must be held high in a read cycle. In a

transfer cycle, the direction of transfer is

determined by WEU and WEL levels at the falling

edge of RAS. When either WEU or WEL is low,

data is transferred from SAM to RAM (data is

written into RAM), and when both WEU and WEL

are high, data is transferred from RAM to SAM

(data is read from RAM).

SI/O0 – SI/O15 (input/output pins): SI/Os are

input/output pins in SAM. Direction of

input/output is determined by the previous transfer

cycle. When it was a read transfer cycle, SI/O

outputs data. When it was a masked write transfer

cycle, SI/O inputs data.

DSF1 (input pin): DSF1 is a special function data

input flag pin. It is set to high at the falling edge

of RAS when new functions such as color register

and mask register read/write, split transfer, and

flash write, are used.

DSF2 (input pin): DSF2 is also a special function

data input flag pin. This pin is fixed to low level in

all operations of the HM5316123B.

I/O0 – I/O15 (input/output pins): I/O pins function

as mask data at the falling edge of RAS (in mask

write mode). Data is written only to high I/O pins.

Data on low I/O pins are masked and internal data

are retained. After that, they function as

inut/output pins as those of a standard DRAM. In

block write cycle, they function as column mask

data at the falling edges of CAS, and WEU or

WEL.

QSF (output pin): QSF outputs data of address A7

in SAM. QSF is switched from low to high by

accessing address 127 in SAM and from high to

low by accessing address 255 in SAM.

Preliminary Data Sheet E0160H10

6

HM5316123B Series

cycle. In this cycle also, to avoid I/O contention,

data should be input after reading data and driving

OE high.

Operation of HM5316123B

RAM Port Operation

RAM Read Cycle (DT/OE high, CAS high and

DSF1 low at the falling edge of RAS, DSF1 low at

the falling edge of CAS)

• Mask Write Mode (WEU or WEL low at the

falling edge of RAS)

If WEU or WEL is set low at the falling edge of

RAS, two modes of mask write cycle are capable.

1. In new mask mode, mask data is loaded from

I/O pin and used. Whether or not an I/O is written

depends on I/O level at the falling edge of RAS.

The data is written in high level I/Os, and the data

is masked and retained in low level I/Os. This

mask data is effective during the RAS cycle. So,

in page mode cycles the mask data is retained

during the page access.

2. If a load mask register cycle (LMR) has been

performed, the mask data is not loaded from I/O

pins and the mask data stored in mask registers

persistently are used. This operation is known as

persistent write mask, set by LMR cycle and reset

by CBRR cycle.

Row address is entered at the RAS falling edge and

column address at the CAS falling edge to the

device as in standard DRAM. Then, when WEU

or WEL is high and DT/OE is low while CAS is

low, the selected address data outputs through I/O

pin. At the falling edge of RAS, DT/OE and CAS

become high to distinguish RAM read cycle from

transfer cycle and CBR refresh cycle. Address

access time (t ) and RAS to column address

AA

RAD

delay time (t

) specifications are added to

enable fast page mode.

RAM Write Cycle (Eraly Write, Delayed Write,

Read-Modify-Write)

(DT/OE high, CAS high and DSF1 low at the

falling edge of RAS, DSF1 low at the falling edge

of CAS)

Fast Page Mode Cycle (DT/OE high, CAS high

and DSF1 low at the falling edge of RAS)

• No Mask Write Cycle (WEU and WEL high at

the falling edge of RAS)

High-speed page mode cycle reads/writes the data

of the same row address at high speed by toggling

CAS while RAS is low. Its cycle time is one third

of the random read/write cycle. In this cycle, read,

write, and block write cycles can be mixed. Note

When CAS is set low and either WEU or WEL is

set low after RAS low, a write cycle is executed.

If either WEU or WEL is set low before the CAS

falling edge, this cycle becomes an early write

cycle and all I/O become in high impedance. All

16 data are latched on the falling edge of CAS. If

only one of WEU and WEL is low when CAS

falls, the write will affect only those corresponding

8 bits. If the other of WEU and WEL falls at the

same time in the cycle, the write will then occur

for those 8 bits, with the latched data.

that address access time (t ), RAS to column

AA

address delay time (t

), and access time from

RAD

CAS precharge (t

) are added. In one RAS

ACP

cycle, 256-word memory cells of the same row

address can be accessed. It is necessary to specify

access frequency within t

max (100 µs).

RASP

If both WEU and WEL are set low after the CAS

falling edge, this cycle becomes a delayed write

cycle and all 16 data are latched on the falling edge

of WEU or WEL. Byte write occures if only one

of WEU or WEL falls during the cycle. I/O does

not become high impedance in this cycle, so data

should be entered with OE in high.

If both WEU and WEL are set low after t

CWD

(min) and t

(min) after the CAS falling edge,

AWD

this cycle becomes a read-modify-write cycle and

enables read/write at the same address in one

Preliminary Data Sheet E0160H10

7

HM5316123B Series

so once it is set, it retains the data until reset.

Since mask register set cycle is just as same as the

usual read and write cycle, so read, early and

delayed write cycles can be executed.

Color Register Set/Read Cycle (CAS high,

DT/OE high, WEU and WEL high and DSF1 high

at the falling edge of RAS)

In color register set cycle, color data is set to the

internal color register used in flash write cycle or

block write cycle. 16 bits of internal color register

are provided at each I/O. This register is

composed of static circuits, so once it is set, it

retains the data until reset. Since color register set

cycle is just as same as the usual write cycle, so

read, early write and delayed write cycle can be

executed. In this cycle, the HM5316123B

refreshes the row address fetched at the falling

edge of RAS.

Flash Write Cycle (CAS high, DT/OE high, WEU

or WEL low, and DSF1 high at the falling edge of

RAS)

In a flash write cycle, a row of data (256 word x 16

bit) is cleared to 0 or 1 at each I/O according to the

data of color register mentioned before. It is also

necessary to mask I/O in this cycle. When CAS

and DT/OE is set high, WEU or WEL is low, and

DSF1 is high at the falling edge of RAS, this cycle

starts. Then, the row address to clear is given to

row address. Mask data is as same as that of a

Mask Register Set/Read Cycle (CAS high,

DT/OE high, WEU and WEL high, and DSF1 high

at the falling edge of RAS)

RAM write cycle.

Cycle time is the same as

those of RAM read/write cycles, so all bits can be

cleared in 1/256 of the usual cycle time. (See

figure 1.)

In mask register set cycle, mask data is set to the

internal mask register used in mask write cycle,

block write cycle, flash write cycle, masked write

transfer, and masked split write transfer. 16 bits of

internal mask register are provided at each I/O.

This mask register is composed of static circuits,

Color Register Set Cycle

RAS

Flash Write Cycle

CAS

Address

WEU,WEL

DT/OE

DSF1

Row

Xi

Xj

*1

Color Data

Set color register

*1

I/O

Execute flash write into each Execute flash write into

I/O on row address Xi using

color register.

each I/O on row address

Xj using color register.

Note: 1. I/O Mask Data (In new mask mode)

Low: Mask

High: Non Mask

In persistent mask mode, I/O don't care

Figure 1 Use of Flash Write

Preliminary Data Sheet E0160H10

8

HM5316123B Series

Block Write Cycle (CAS high, DT/OE high and

DSF1 low at the falling edge of RAS, DSF1 high

and WEU or WEL low at the falling edge of CAS)

In a block write cycle, 4 columns of data (4

column x 16 bit) are cleared to 0 or 1 at each I/O

according to the data of color register. Column

addresses A0 and A1 are disregarded. The mask

data on I/Os and the mask data on column

addresses can be determined independently. I/O

level at the falling edge of CAS determines the

address to be cleared. (See Figure 2.) The block

write cycle is as the same as the usual write cycle,

so early and delayed write, read-modify-write, and

page mode write cycle can be executed.

• No mask Mode Block Write Cycle (WEU and

WEL high at the falling edge of RAS)

The data on 16 I/Os are all cleared when WEU and

WEL are high at the falling edge of RAS.

• Mask Block Write Cycle (WEU or WEL low at

the falling edge of RAS)

When either WEU or WEL is low at the falling

edge of RAS, the HM5316123B starts mask block

write cycle to clear the data on an optional I/O.

The mask data is the same as that of a RAM write

cycle. High I/O is cleared, low I/O is not cleared

and the internal data is retained. In new mask

mode, the mask data is available in the RAS cycle.

In persistent mask mode, I/O don't care about mask

mode.

• Column Mask (WEU or WEL low at the falling

edge of CAS)

Column mask data is determined by 4I/Os (I/O0,

I/O1, I/O2, I/O3) level at CAS low and WEU or

WEL low edge. When upper byte column mask is

performed by WEL high and WEU low, column

mask data are determined by 4I/Os (I/O0, I/O1,

I/O2, I/O3) and other I/Os (I/O4 to I/O15) don't

care.

Preliminary Data Sheet E0160H10

9

HM5316123B Series

Color Register Set Cycle

Block Write Cycle

RAS

CAS

Row

Column A2–A7

Row

Address

*1

WEU, WEL

DT/OE

DSF1

I/O

Column Mask

Color Data

Column Mask

*1

I/O data/RAS

Mode

WEU, WEL

Either Low

New mask mode Mask

Persistent

mask mode

H or L

(mask register used)

H or L

Both High

No mask

I/O Mask Data (In new mask mode)

Low: Mask

High: Non Mask

In persistent mask mode, I/O don't care

Column Mask Data

Column0 (A0 = 0, A1 = 0) Mask Data

Column1 (A0 = 1, A1 = 0) Mask Data

Column2 (A0 = 0, A1 = 1) Mask Data

I/O0

I/O1

I/O2

Low: Mask

High: Non Mask

I/O3 Column3 (A0 = 1, A1 = 1) Mask Data

Figure 2 Use of Block Write

Preliminary Data Sheet E0160H10

10

HM5316123B Series

columns, but any boundaries cannot be set as the

start address.

Transfer Operation

The HM5316123B provides the read transfer

cycle, split read transfer cycle, masked write

transfer cycle and masked split write transfer cycle

as data transfer cycles. Theses transfer cycles are

set by driving CAS high and DT/OE low at the

falling edge of RAS. They have following

functions:

(1) Transfer data between row address and SAM

data register

Read transfer cycle and split read transfer cycle:

RAM to SAM

Masked write transfer cycle and masked split write

transfer cycle: SAM to RAM

(2) Determine SI/O state (except for split read

transfer cycle and masked split write transfer

cycle)

(5) Load/use mask data in masked write transfer

cycle and masked split write transfer cycle.

Read Transfer Cycle (CAS high, DT/OE low,

WEU and WEL high and DSF1 low at the falling

edge of RAS)

This cycle becomes read transfer cycle by driving

DT/OE low, WEU and WEL high and DSF1 low at

the falling edge of RAS. The row address data

(256 x 16 bits) determined by this cycle is

transferred to SAM data register synchronously at

the rising edge of DT/OE. After the rising edge of

DT/OE, the new address data outputs from SAM

start address determined by column address. In

read transfer cycle, DT/OE must be risen to

transfer data from RAM to SAM.

Read transfer cycle: SI/O output

This cycle can access SAM even during transfer

(real time read transfer). In this case, the timing

Masked write transfer cycle: SI/O input

(3) Determine first SAM address to access after

transferring at column address (SAM start

address).

t

(min) specified between the last SAM access

SDD

before transfer and DT/OE rising edge and t

SDH

(min) specified between the first SAM access and

DT/OE rising edge must be satisfied. (See figure

3.)

When read transfer cycle is executed, SI/O

becomes output state by first SAM access. Input

SAM start address must be determined by read

transfer cycle or masked write transfer cycle (split

transfer cycle isn’t available)before SAM access,

after power on, and determined for each transfer

cycle.

must be set high impedance before t

the first SAM access to avoid data contention.

(min) of

(4) Use the stopping columns (boundaries) in the

serial shift register. If the stopping columns have

been set, split transfer cycles use the stopping

SZS

RAS

CAS

Address

Xi

Yj

L

DT/OE

DSF1

t_SDDt_SDH

SC

SI/O

Yj

Yj + 1

SAM Data before Transfer

SAM Data after Transfer

Figure 3 Real Time Read Transfer

Preliminary Data Sheet E0160H10

11

HM5316123B Series

address A7 is 0) automatically. After data are read

from data register DR1, data start to be read from

SAM start addresses of data register DR0. If the

next split read transfer isn’t executed while data

are read from data register DR0, data start to be

read from SAM start address 0 of DR1 after data

are read from data register DR0. If split read

transfer is executed setting row address AX8 to 1

and SAM start addresses A0 to A6 while data are

read from data register DR1, 128-word x 16-bit

data are transferred to data register DR2. After

data are read from data register DR1, data start to

be read from SAM start addresses of data register

DR2. If the next split read transfer isn’t executed

while data is read from data register DR2, data

start to be read from SAM start address 0 of data

register DR1 after data are read from data register

DR2. In split read data transfer, the SAM start

address A7 is automatically set in the data register,

which isn’t used.

Masked Write Transfer cycle (CAS high, DT/OE

low, WEU or WEL low, and DSF1 low at the

falling edge of RAS)

Masked write transfer cycle can transfer only

selected I/O data in a row of data input by serial

write cycle to RAM. Whether one I/O data is

transferred or not depends on the corresponding

I/O level (mask data) at the falling edge of RAS.

This mask transfer operation is the same as a mask

write operation in RAM cycles, so the persistent

mode can be supported. The row address of data

transferred into RAM is determined by the address

at the falling edge of RAS. The column address is

specified as the first address for serial write after

terminating this cycle. Also in this cycle, SAM

access becomes enabled after t

(min) after

SRD

RAS becomes high. SAM access is inhibited

during RAS low. In this period, SC must bot be

risen. Data transferred to SAM by read transfer

cycle or split read transfer cycle can be written to

other addreses of RAM by write transfer cycle.

However, the adddress to write data must be the

same as that of the read transfer cycle or the split

read transfer cycle (row address AX8)

The data on SAM address A7, which will be

accessed next, outputs to QSF, QSF is switched

from low to high by accessing SAM last address

127 and from high to low by accessing address

255.

Split read transfer cycle is set when CAS is high,

DT/OE is low, WEU and WEL is high and DSF1 is

high at the falling edge of RAS. The cycle can be

executed asyncronously with SC. However,

HM5316123B must be satisfied tSTS (min) timing

specified between SC rising (Boundary address)

and RAS falling. In split transfer cycle, the

Split Read Transfer Cycle (CAS high, DT/OE low,

WEU and WEL high and DSF1 high at the falling edge of

RAS)

To execute a continuous serial read by real time

read transfer, the HM5316123B must satisfy SC

and DT/OE timings and requires an external circuit

to detect SAM last address. Split read transfer

cycle makes it possible to execute a continuous

serial read without the above timing limitation.

The HM5316123B supports two types of split

register operation. One is the normal split register

operation to split the data register into two halves.

The other is the boundary split register operation

using stopping columns described later.

Figure 4 shows the block diagram for the normal

split register operation. SAM data register (DR)

consists of 2 split buffers, whose organizations are

128-word x 16-bit each. Let us suppose that data

is read from upper data reagister DR1 (The row

address AX8 is 0 and SAM address A7 is 1.).

When split read transfer is executed setting row

address AX8 to 0 and SAM start addresses A0 to

A6, 128-word x 16-bit data are transferred from

RAM to the lower data register DR0 (SAM

HM5316123B must satisfy t

(min), t

(min)

RST

CST

and t

(min) timings specified between RAS or

AST

CAS falling and column address. (See figure 5.)

In split read transfer, SI/O isn’t switched to output

state. Therefore, read transfer must be executed to

switch SI/O to output state when the previous

transfer cycle is masked write transfer cycle or

masked split write transfer cycle. SAM start

address must be set in every split read transfer

cycle.

Preliminary Data Sheet E0160H10

12

HM5316123B Series

Memory

Array

Memory

Array

AX8 = 0

AX8 = 1

SAM I/O Buffer

SI/O

Figure 4 Block Diagram for Split Transfer

RAS

CAS

t_STS(min)

t_RST(min)

t_CST(min)

Yj

Address

Xi

t_AST(min)

DT/OE

DSF1

SC

Ym

Bi

Bj – 1

Bj

Yj

Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address.

Figure 5 Limitation in Split Transfer

Preliminary Data Sheet E0160H10

13

HM5316123B Series

Stopping Column in Split Transfer Cycle

Masked Split Write Transfer Cycle (CAS high,

DT/OE low, WEU or WEL low and DSF1 high at

the falling edge of RAS)

The HM5316123B has the boundary split register

operation using stopping columns. If a CBRS

cycle has been performed, split transfer cycle

performs the boundary operation. Figure 6 shows

an example of boundary split register. (Boundary

code is B6.)

A continuous serial write cannot be executed

because accessing SAM is inhibited during RAS

low in write transfer. Masked split write transfer

cycle makes it possible. In this cycle, t

(min),

STS

First of all a read data transfer cycle is executed,

and SAM start addresses A0 to A7 are set. The

RAM data are transferred to the SAM, and SAM

serial read starts from the start address (Y1) on the

lower SAM. After that, a split read transfer cycle

is executed, and the next start address (Y2) is set.

The RAM data are transferred to the upper SAM.

When the serial read arrive at the first boundary

after the split read transfer cycle, the next read

jumps to the start address (Y2) on the upper SAM

(jump 1) and continues. Then the second split read

transfer cycle is executed, and another start address

(Y3) is set. The RAM data are transferred to the

lower SAM. When the serial read arrive at the

other boundary again, the next read jumps to the

start address (Y3) on the lower SAM. In stopping

column, split transfer is needed for jump operation

between lower SAM and upper SAM.

t

(min), t

(min) and t

(min) timings

RST

CST

AST

must be satisfied like split read transfer cycle. And

it is impossible to switch SI/O to input state in this

cycle. If SI/O is in output state, masked write

transfer cycle should be executed to switch SI/O

into input state. Data transferred to SAM by read

transfer cycle or split read transfer cycle can be

written to other addresses of RAM by masked split

write transfer cycle. However, masked write

transfer cycle must be executed before split write

transfer cycle. And in this masked split write

transfer cycle, the MSB of row address (AX8) to

write data must be the same as that of the read

transfer cycle or the split read transfer cycle.

Column size

64 bit

Boundaries (B6)

(Y1)

(Y3)

(Y2)

Start

Jump 1

Jump 2

Lower SAM

128 bits

Upper SAM

128 bits

Figure 6 Example of Boundary Split Register

Preliminary Data Sheet E0160H10

14

HM5316123B Series

Stopping Column Boundary Table

——————————————————————————————

Stop Address

——————————————————————————————

Boundary code Column size A2 A3 A4 A5 A6

——————————————————————————————

B2

——————————————————————————————

B3

——————————————————————————————

B4 16

——————————————————————————————

B5 32

——————————————————————————————

B6 64

——————————————————————————————

B7 128

4

0

*

8

1

0

*

1

0

*

1

0

*

1

0

1

——————————————————————————————

Notes: 1. A0, A1, and A7: don't care

2. *: don’t care

Stopping Column Set Cycle (CBRS)

No Reset CBR Cycle (CBRN)

This cycle becomes stopping column set cycle by

driving CAS low, WEU or WEL low, DSF1 high at

the falling edge of RAS. Stopping column data

(boundaries) are latched from address inputs on the

falling edge of RAS. To determine the boundary,

This cycle becomes no reset CBR cycle (CBRN)

by driving CAS low, WE high and DSF1 high at

the falling edge of RAS. The CBRN can only

execute the refresh operation.

Byte Control (WEU, WEL)

A2 to A6 can be used and don’t care A0, A1, and

A7. In the HM5316123B, 6 types of boundary (B2

to B7) can be set including the default case. (See

stopping column boundary table.) If A2 to A5 are

set to high and A6 is set to low, the boundaries

(B6) are selected. Figure 6 shows the example.

The stop address that is set by the CBRS is used

from next split transfer cycle. Once a CBRS is

executed, the stopping column operation mode

continues until CBRR.

In a write cycle, when WEL set low and WEU set

high, I/O0 to I/O7 become write mode and I/O8 to

I/O15 become no write mode, and when WEL set

high and WEU set low, I/O0 to I/O7 become no

write mode and I/O8 to I/O15 become write mode.

The write cycle that byte control is capable are

RAM write cycle, block write cycle, load write

mask register cycle and load color register cycle.

The byte control write cycle is capable to execute

early write, delay write, read-modify-write and

page mode. But write mask in new mask mode,

flash write, transfer and refresh cycle can not

execute byte control.

Register Reset Cycle (CBRR)

This cycle becomes register reset cycle (CBRR) by

driving CAS low, WEU and WEL high, and DSF1

low at the falling edge of RAS. A CBRR can reset

the persistent mask operation and stopping column

operation, so the HM5316123B becomes the new

mask operation and boundary code B7. When a

CBRR is executed for stopping column operation

reset and split transfer operation, it need to satisfy

t

(min) and t

(min) between RAS falling

STS

RST

and SC rising for correct SAM read/write

operation.

Preliminary Data Sheet E0160H10

15

HM5316123B Series

SAM Port Operation

Serial Read Cycle

Refresh

RAM Refresh

SAM port is in read mode when the previous data

transfer cycle is a read transfer cycle. Access is

synchronized with SC rising, and SAM data is

output from SI/O. When SE is set high, SI/O

becomes high impedance, and the internal pointer

is incremented by the SC rising. After indicating

the last address (address 255), the internal pointer

indicates address 0 at the next access.

RAM, which is composed of dynamic circuits,

requires refresh cycle to retain data. Refresh is

executed by accessing all 512 row addresses within

8 ms. There are three refresh cycles: (1) RAS-only

refresh cycle, (2) CAS-before-RAS (CBRN,

CBRS, and CBRR) refresh cycle, and (3) Hidden

refresh cycle. Besides them, the cycles which

activate RAS, such as read/write cycles or transfer

cycles, can also refresh the row address.

Therefore, no refresh cycle is required when all

row addresses are accessed within 8 ms.

Serial Write Cycle

If previous data transfer cycle is masked write

transfer cycle, SAM port goes into write mode. In

this cycle, SI/O data is fetched into data register at

the SC rising edge like in the serial read cycle. If

SE is high, SI/O data isn’t fetched into data

register. The internal pointer is incremented by the

SC rising, so SE high can be used as mask data for

SAM. After indicating the last address (address

255), the internal pointer indicates address 0 at the

next access.

(1) RAS-Only Refresh Cycle: RAS-only refresh

cycle is executed by activating only the RAS cycle

with CAS fixed to high after inputting the row

address (= refresh address) from external circuits.

To distinguish this cycle from a data transfer cycle,

DT/OE must be high at the falling edge of RAS.

(2) CBR Refresh Cycle: CBR refresh cycle

(CBRN, CBRS and CBRR) are set by activating

CAS before RAS. In this cycle, the refresh address

need not to be input through external circuits

because it is input through an internal refresh

counter. In this cycle, output is in high impedance

and power dissipation is lowered because CAS

circuits don’t operate.

(3) Hidden Refresh Cycle: Hidden refresh cycle

executes CBR refresh with the data output by

reactivating RAS when DT/OE and CAS keep low

in normal RAM read cycles.

SAM Refresh

SAM parts (data register, shift resister and

selector), organized as fully static circuitry, require

no refresh.

Preliminary Data Sheet E0160H10

16

HM5316123B Series

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

——————————————————————————————————————————

Voltage on any pin relative to V

V

–1.0 to +7.0

V

SS

T

——————————————————————————————————————————

Supply voltage relative to V

V

–0.5 to +7.0

V

SS

CC

——————————————————————————————————————————

Short circuit output current

Iout

50

mA

——————————————————————————————————————————

Power dissipation

P

1.0

W

T

——————————————————————————————————————————

Operating temperature

Topr

0 to +70

°C

——————————————————————————————————————————

Storage temperature

Tstg

–55 to +125

°C

——————————————————————————————————————————

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

——————————————————————————————————————————

Supply voltage

V

4.5

5.0

5.5

V

1

CC

——————————————————————————————————————————

Input high voltage

V

2.4

—

6.5

V

1

IH

——————————————————————————————————————————

*2

Input low voltage

V

–0.5

—

0.8

V

1

IL

——————————————————————————————————————————

Notes: 1. All voltage referred to V

SS

2. –3.0 V for pulse width < 10 ns.

Preliminary Data Sheet E0160H10

17

HM5316123B Series

DC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)

CC

SS

HM5316123B

—————————————–

-7 -8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Test conditions

Parameter

——————————————————————————————————————————

Operating current I

—

120

————————————————————cycling

195 175 160 mA = min

—

110

—

100 mA RAS, CAS SC = V , SE = V

CC1

IL IH

—————————

I

—

t

SE = V , SC cycling

CC7

RC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

Block write current

I

—

125

————————————————————cycling

200 180 160 mA = min

—

115

—

100 mA RAS, CAS SC = V , SE = V

CC1BW

IL IH

—————————

I

—

t

SE = V , SC cycling

CC7BW

RC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

Standby current

I

—

7

—

7

—

7

mA RAS, CAS SC = V , SE = V

CC2

IL IH

————————————————————= V

—————————

IH

I

—

85

—

75

—

70

mA

SE = V , SC cycling

CC8

IL

t

= min

SCC

—————————————————————————————————————–––––––––

RAS-only refresh I

—

115

—

105

—

90

mA RAS cycling SC = V , SE = V

CC3

IL IH

current

————————————————————CAS =V

—————————

IH

= min

I

—

185

—

165

—

150 mA

t

SE = V , SC cycling

CC9

RC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

Fast page mode

current *3

I

—

125

—

120

—

115 mA CAS cycling SC = V , SE = V

CC4

IL IH

————————————————————RAS = V

—————————

IL

= min

I

—

200

—

185

—

175 mA

t

SE = V , SC cycling

CC10

PC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

Fast page mode

block write

current *3

I

—

145

—

135

—

130 mA CAS cycling SC = V , SE = V

CC4BW

IL IH

————————————————————RAS = V

—————————

IL

= min

I

—

220

—

205

—

195 mA

t

SE = V , SC cycling

CC10BW

PC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

CAS-before RAS

I

—

85

—

75

—

65

mA RAS cycling SC = V , SE = V

CC5

IL IH

refresh current

————————————————————t = min —————————

RC

I

—

155

—

140

—

125 mA

SE = V , SC cycling

IL

CC11

t

= min

SCC

—————————————————————————————————————–––––––––

Data transfer

current

I

—

130

————————————————————cycling

205 185 165 mA = min

—

120

—

110 mA RAS, CAS SC = V , SE = V

CC6

IL IH

—————————

I

—

t

SE = V , SC cycling

CC12

RC

IL

t

= min

SCC

—————————————————————————————————————–––––––––

Input leakage current

I

–10 10

µA

LI

—————————————————————————————————————–––––––––

Output leakage current

I

–10 10

µA

LO

—————————————————————————————————————–––––––––

Output high voltage

V

2.4

—

2.4

—

2.4

—

V

I

= –1 mA

OH

—————————————————————————————————————–––––––––

Output low voltage

V

—

0.4

—

0.4

—

0.4

V

I

= 2.1 mA

OL

——————————————————————————————————————————

Preliminary Data Sheet E0160H10

18

HM5316123B Series

Notes: 1. I

depends on output load condition when the device is selected. I

max is specified at the

CC

output open condition.

2. Address can be changed once while RAS is low and CAS is high.

3. Address can be changed once in 1 page cycle (t ).

PC

Capacitance (Ta = 25°C, V = 5 V ± 10 %, f = 1 MHz, Bias: Clock, I/O = V , address = V )

CC

SS

Parameter

Symbol

Typ

Max

Unit

Note

——————————————————————————————————————————

Input capacitance (Address)

C

—

5

pF

1

I1

——————————————————————————————————————————

Input capacitance (Clocks)

C

—

5

pF

1

I2

——————————————————————————————————————————

Output capacitance (I/O, SI/O, QSF)

C

—

7

pF

1

I/O

——————————————————————————————————————————

Notes: 1. This parameter is sampled and not 100% tested.

Preliminary Data Sheet E0160H10

19

HM5316123B Series

,

*1 *16

AC Characteristics (Ta = 0 to +70°C, V = 5 V ± 10%, V = 0 V)

CC

SS

Test Conditions

– Input rise and fall times: 5ns

– Input pulse levels: V to 3.0 V

SS

– Input timing reference levels: 0.8 V, 2.4 V

– Output timing reference levels: 0.8 V, 2.0 V

– Output load: RAM 1TTL+CL(50PF)

SAM, QSF 1TTL+CL(30PF)

(Including scope and jig)

Common Parameter

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

Random read or write cycle time

t

130 —

150 —

180

—

ns

RC

—————————————————————————————————————————

RAS precharge time

t

50

—

60

—

70

—

ns

RP

—————————————————————————————————————————

RAS pulse width

t

70 10000 80 10000 100 10000 ns

RAS

—————————————————————————————————————————

CAS pulse width

t

20

—

20

—

25

—

ns

CAS

—————————————————————————————————————————

Row address setup time

t

0

—

0

—

0

—

ns

ASR

—————————————————————————————————————————

Row address hold time

t

10

—

10

—

10

—

ns

RAH

—————————————————————————————————————————

Column address setup time

t

0

—

0

—

0

—

ns

ASC

—————————————————————————————————————————

Column address hold time

t

12

—

15

—

15

—

ns

CAH

—————————————————————————————————————————

RAS to CAS delay time

t

20 50

20 60

20 75

ns

2

RCD

—————————————————————————————————————————

RAS hold time referenced to CAS

t

20

—

20

—

25

—

ns

RSH

—————————————————————————————————————————

CAS hold time referenced to RAS

t

70

—

80

—

100

—

ns

CSH

—————————————————————————————————————————

CAS to RAS precharge time

t

10

—

10

—

10

—

ns

CRP

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

20

HM5316123B Series

Common Parameter (cont)

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

Transition time (rise to fall)

t

3

50

3

50

3

50

ns

3

T

—————————————————————————————————————————

Refresh period

t

—

8

—

8

—

8

ms

REF

—————————————————————————————————————————

DT to RAS setup time

t

0

—

0

—

0

—

ns

DTS

—————————————————————————————————————————

DT to RAS hold time

t

10

—

10

—

10

—

ns

DTH

—————————————————————————————————————————

DSF1 to RAS setup time

t

0

—

0

—

0

—

ns

FSR

—————————————————————————————————————————

DSF1 to RAS hold time

t

10

—

10

—

10

—

ns

RFH

—————————————————————————————————————————

DSF1 to CAS setup time

t

0

—

0

—

0

—

ns

FSC

—————————————————————————————————————————

DSF1 to CAS hold time

t

12

—

15

—

15

—

ns

CFH

—————————————————————————————————————————

Data-in to CAS delay time

t

0

—

0

—

0

—

ns

4

DZC

—————————————————————————————————————————

Data-in to OE delay time

t

0

—

0

—

0

—

ns

4

DZO

—————————————————————————————————————————

Output buffer turn-off delay

t

—

15

—

20

—

20

ns

5

OFF1

referenced to CAS

—————————————————————————————————————————

Output buffer turn-off delay

t

—

15

—

20

—

20

ns

5

OFF2

referenced to OE

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

21

HM5316123B Series

Read Cycle (RAM), Page Mode Read Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

Access time from RAS

t

—

70

—

80

—

100 ns

6, 7

RAC

—————————————————————————————————————————

Access time from CAS

t

—

20

—

20

—

25

ns

7, 8

CAC

—————————————————————————————————————————

Access time from OE

t

—

20

—

20

—

25

ns

7

OAC

—————————————————————————————————————————

Address access time

t

—

35

—

40

—

45

ns

7, 9

AA

—————————————————————————————————————————

Read command setup time

t

0

—

0

—

0

—

ns

RCS

—————————————————————————————————————————

Read command hold time

t

0

—

0

—

0

—

ns

10

RCH

—————————————————————————————————————————

Read command hold time

t

0

—

5

—

10

—

ns

10

RRH

referenced to RAS

—————————————————————————————————————————

RAS to column address delay time t

15 35

15 40

15 55

ns

2

RAD

—————————————————————————————————————————

Column address to RAS lead time t

35

—

40

—

45

—

ns

RAL

—————————————————————————————————————————

Column address to CAS lead time t

35

—

40

—

45

—

ns

CAL

—————————————————————————————————————————

Page mode cycle time

t

45

—

50

—

55

—

ns

PC

—————————————————————————————————————————

CAS precharge time

t

7

—

10

—

10

—

ns

CP

—————————————————————————————————————————

Access time from CAS precharge

t

—

40

—

45

—

50

ns

ACP

—————————————————————————————————————————

Page mode RAS pulse width

t

70 100000 80 100000 100 100000 ns

RASP

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

22

HM5316123B Series

Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

Write command setup time

t

0

—

0

—

0

—

ns

11

WCS

—————————————————————————————————————————

Write command hold time

t

12

—

15

—

15

—

ns

WCH

—————————————————————————————————————————

Write command pulse width

t

12

—

15

—

15

—

ns

WP

—————————————————————————————————————————

Write command to RAS lead time

t

20

—

20

—

20

—

ns

RWL

—————————————————————————————————————————

Write command to CAS lead time

t

20

—

20

—

20

—

ns

CWL

—————————————————————————————————————————

Data-in setup time

t

0

—

0

—

0

—

ns

12

DS

—————————————————————————————————————————

Data-in hold time

t

12

—

15

—

15

—

ns

12

DH

—————————————————————————————————————————

WE to RAS setup time

t

0

—

0

—

0

—

ns

WS

—————————————————————————————————————————

WE to RAS hold time

t

10

—

10

—

10

—

ns

WH

—————————————————————————————————————————

Mask data to RAS setup time

t

0

—

0

—

0

—

ns

MS

—————————————————————————————————————————

Mask data to RAS hold time

t

10

—

10

—

10

—

ns

MH

—————————————————————————————————————————

OE hold time referenced to WE

t

15

—

20

—

20

—

ns

OEH

—————————————————————————————————————————

Page mode cycle time

t

45

—

50

—

55

—

ns

PC

—————————————————————————————————————————

CAS precharge time

t

7

—

10

—

10

—

ns

CP

—————————————————————————————————————————

CAS to data-in delay time

t

15

—

20

—

20

—

ns

13

CDD

—————————————————————————————————————————

Page mode RAS pulse width

t

70 100000 80 100000 100 100000 ns

RASP

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

23

HM5316123B Series

Read-Modify-Write Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

Read-modify-write cycle time

t

180 —

200 —

230

—

ns

RWC

—————————————————————————————————————————

RAS pulse width (read-modify-write cycle)

t

120 10000 130 10000 150 10000 ns

RWS

—————————————————————————————————————————

CAS to WE delay time

t

40

—

45

—

50

—

ns 14

CWD

—————————————————————————————————————————

Column address to WE delay time

t

60

—

65

—

70

—

ns 14

AWD

—————————————————————————————————————————

OE to data-in delay time

t

15

—

20

—

20

—

ns 12

ODD

—————————————————————————————————————————

Access time from RAS

t

—

70

—

80

—

100

ns 6, 7

RAC

—————————————————————————————————————————

Access time from CAS

t

—

20

—

20

—

25

ns 7, 8

CAC

—————————————————————————————————————————

Access time from OE

t

—

20

—

20

—

25

ns

7

OAC

—————————————————————————————————————————

Address access time

t

—

35

—

40

—

45

ns 7, 9

AA

—————————————————————————————————————————

RAS to column address delay time

t

15 35

15 40

15 55

ns

RAD

—————————————————————————————————————————

Read command setup time

t

0

—

0

—

0

—

ns

RCS

—————————————————————————————————————————

Write command to RAS lead time

t

20

—

20

—

20

—

ns

RWL

—————————————————————————————————————————

Write command to CAS lead time

t

20

—

20

—

20

—

ns

CWL

—————————————————————————————————————————

Write command pulse width

t

12

—

15

—

15

—

ns

WP

—————————————————————————————————————————

Data-in setup time

t

0

—

0

—

0

—

ns 12

DS

—————————————————————————————————————————

Data-in hold time

t

12

—

15

—

15

—

ns 12

DH

—————————————————————————————————————————

OE hold time referenced to WE

t

15

—

20

—

20

—

ns

OEH

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

24

HM5316123B Series

Refresh Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

CAS setup time (CAS-before-RAS refresh)

t

10

—

10

—

10

—

ns

CSR

—————————————————————————————————————————

CAS hold time (CAS-before-RAS refresh)

t

10

—

10

—

10

—

ns

CHR

—————————————————————————————————————————

RAS precharge to CAS hold time

t

10

—

10

—

10

—

ns

RPC

—————————————————————————————————————————

Flash Write Cycle, Block Write Cycle, and Register Read Cycle

HM5316123B

——————————————

-7

8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

CAS to data-in delay time

t

15

—

20

—

20

—

ns

13

CDD

—————————————————————————————————————————

OE to data-in delay time

t

15

—

20

—

20

—

ns

13

ODD

—————————————————————————————————————————

CBR Refresh with Register Reset

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

Split transfer setup time

t

20

—

20

—

25

—

ns

STS

—————————————————————————————————————————

Split transfer hold time referenced to RAS

t

70

—

80

—

100

—

ns

RST

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

25

HM5316123B Series

Read Transfer Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

DT hold time referenced to RAS

t

60 10000 65 10000 80 10000 ns

RDH

—————————————————————————————————————————

DT hold time referenced to CAS

t

20

—

20

—

25

—

ns

CDH

—————————————————————————————————————————

DT hold time referenced to column address

t

25

—

30

—

30

—

ns

ADH

—————————————————————————————————————————

DT precharge time

t

20

—

20

—

30

—

ns

DTP

—————————————————————————————————————————

DT to RAS delay time

t

60

—

70

—

80

—

ns

DRD

—————————————————————————————————————————

SC to RAS setup time

t

15

—

20

—

30

—

ns

SRS

—————————————————————————————————————————

1st SC to RAS hold time

t

70

—

80

—

100 —

ns

SRH

—————————————————————————————————————————

1st SC to CAS hold time

t

25

—

25

—

25

—

ns

SCH

—————————————————————————————————————————

1st SC to column address hold time

t

40

—

45

—

50

—

ns

SAH

—————————————————————————————————————————

Last SC to DT delay time

t

5

—

5

—

5

—

ns

SDD

—————————————————————————————————————————

1st SC to DT hold time

t

10

—

13

—

15

—

ns

SDH

—————————————————————————————————————————

DT to QSF delay time

t

—

30

—

35

—

35

ns 15

DQD

—————————————————————————————————————————

QSF hold time referenced to DT

t

5

—

5

—

5

—

ns

DQH

—————————————————————————————————————————

Serial data-in to 1st SC delay time

t

0

—

0

—

0

—

ns

SZS

—————————————————————————————————————————

Serial clock cycle time

—————————————————————————————————————————

SC pulse width

—————————————————————————————————————————

SC precharge time

—————————————————————————————————————————

SC access time

—————————————————————————————————————————

Serial data-out hold time

—————————————————————————————————————————

Serial data-in setup time

—————————————————————————————————————————

Serial data-in hold time

t

25

—

28

—

30

—

ns

SCC

t

5

—

10

—

10

—

ns

SC

t

10

—

10

—

10

—

ns

SCP

t

—

20

—

23

—

25

ns 15

SCA

t

5

—

5

—

5

—

ns

SOH

t

0

—

0

—

0

—

ns

SIS

t

15

—

15

—

15

—

ns

SIH

—————————————————————————————————————————

RAS to column address delay time

t

15 35

15 40

15 55

ns

RAD

—————————————————————————————————————————

Column address to RAS lead time

t

35

—

40

—

45

—

ns

RAL

—————————————————————————————————————————

RAS to QSF delay time

t

—

70

—

75

—

85

ns 15

RQD

—————————————————————————————————————————

CAS to QSF delay time

t

—

35

—

35

—

35

ns 15

CQD

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

26

HM5316123B Series

Read Transfer Cycle (cont)

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

QSF hold time referenced toRAS

t

20

—

20

—

25

—

ns

RQH

—————————————————————————————————————————

QSF hold time referenced to CAS

t

5

—

5

—

5

—

ns

CQH

—————————————————————————————————————————

Masked Write Transfer Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Min Max Min Max Min Max Unit Notes

Parameter

Symbol

—————————————————————————————————————————

SC setup time referenced to RAS

t

15

—

20

—

30

—

ns

SRS

—————————————————————————————————————————

RAS to SC delay time

t

20

—

25

—

25

—

ns

SRD

—————————————————————————————————————————

Serial output buffer turn-off time

t

10 30

10 35

10 50

ns

SRZ

referenced to RAS

—————————————————————————————————————————

RAS to serial data-in delay time

t

30

—

35

—

50

—

ns

SID

—————————————————————————————————————————

RAS to QSF delay time

t

—

70

—

75

—

85

ns

15

RQD

—————————————————————————————————————————

CAS to QSF delay time

t

—

35

—

35

—

35

ns

15

CQD

—————————————————————————————————————————

QSF hold time referenced to RAS

t

20

—

20

—

25

—

ns

RQH

—————————————————————————————————————————

QSF hold time referenced to CAS

t

5

—

5

—

5

—

ns

CQH

—————————————————————————————————————————

Serial clock cycle time

t

25

—

28

—

30

—

ns

SCC

—————————————————————————————————————————

SC pulse width

t

5

—

10

—

10

—

ns

SC

—————————————————————————————————————————

SC precharge time

t

10

—

10

—

10

—

ns

SCP

—————————————————————————————————————————

SC access time

t

—

20

—

23

—

25

ns

15

SCA

—————————————————————————————————————————

Serial data-out hold time

t

5

—

5

—

5

—

ns

SOH

—————————————————————————————————————————

Serial data-in setup time

t

0

—

0

—

0

—

ns

SIS

—————————————————————————————————————————

Serial data-in hold time

t

15

—

15

—

15

—

ns

SIH

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

27

HM5316123B Series

Split Read Transfer Cycle, Masked Split Write Transfer Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

Split transfer setup time

t

20

—

20

—

25

—

ns

STS

—————————————————————————————————————————

Split transfer hold time referenced to RAS

t

70

—

80

—

100 —

ns

RST

—————————————————————————————————————————

Split transfer hold time referenced to CAS

t

20

—

20

—

25

—

ns

CST

—————————————————————————————————————————

Split transfer hold time referenced

t

35

—

40

—

45

—

ns

AST

to column address

—————————————————————————————————————————

SC to QSF delay time

t

—

30

—

30

—

30

ns

15

SQD

—————————————————————————————————————————

QSF hold time referenced to SC

t

5

—

5

—

5

—

ns

SQH

—————————————————————————————————————————

Serial clock cycle time

t

25

—

28

—

30

—

ns

SCC

—————————————————————————————————————————

SC pulse width

t

5

—

10

—

10

—

ns

SC

—————————————————————————————————————————

SC precharge time

t

10

—

10

—

10

—

ns

SCP

—————————————————————————————————————————

SC access time

t

—

20

—

23

—

25

ns

15

SCA

—————————————————————————————————————————

Serial data-out hold time

t

5

—

5

—

5

—

ns

SOH

—————————————————————————————————————————

Serial data-in setup time

t

0

—

0

—

0

—

ns

SIS

—————————————————————————————————————————

Serial data-in hold time

t

15

—

15

—

15

—

ns

SIH

—————————————————————————————————————————

RAS to column address delay time

t

15 35

15 40

15 55

ns

RAD

—————————————————————————————————————————

Column address to RAS lead time

t

35

—

40

—

45

—

ns

RAL

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

28

HM5316123B Series

Serial Read Cycle, Serial Write Cycle

HM5316123B

——————————————

-7

-8

-10

———— ———— ————

Symbol Min Max Min Max Min Max Unit Notes

Parameter

—————————————————————————————————————————

Serial clock cycle time

t

25

—

28

—

30

—

ns

SCC

—————————————————————————————————————————

SC pulse width

t

5

—

10

—

10

—

ns

SC

—————————————————————————————————————————

SC precharge width

t

10

—

10

—

10

—

ns

SCP

—————————————————————————————————————————

Access time from SC

t

—

20

—

23

—

25

ns

15

SCA

—————————————————————————————————————————

Access time from SE

t

—

17

—

20

—

25

ns

15

SEA

—————————————————————————————————————————

Serial data-out hold time

t

5

—

5

—

5

—

ns

SOH

—————————————————————————————————————————

Serial output buffer turn-off time

t

—

15

—

20

—

20

ns

5,17

SHZ

referenced to SE

—————————————————————————————————————————

SE to serial output in low-Z

t

0

—

0

—

0

—

ns

5,17

SLZ

—————————————————————————————————————————

Serial data-in setup time

t

0

—

0

—

0

—

ns

SIS

—————————————————————————————————————————

Serial data-in hold time

t

15

—

15

—

15

—

ns

SIH

—————————————————————————————————————————

Serial write enable setup time

t

0

—

0

—

0

—

ns

SWS

—————————————————————————————————————————

Serial wrtie enable hold time

t

15

—

15

—

15

—

ns

SWH

—————————————————————————————————————————

Serial write disable setup time

t

0

—

0

—

0

—

ns

SWIS

—————————————————————————————————————————

Serial write disable hold time

t

15

—

15

—

15

—

ns

SWIH

—————————————————————————————————————————

Preliminary Data Sheet E0160H10

29

HM5316123B Series

Notes: 1. AC measurements assume t = 5 ns.

T

2. When t

> t

(max) and t

> t (max), access time is specified by t

or t .

AA

RCD

RAD

CAC

3. V (min) and V (max) are reference levels for measuring timing of input signals. Transition

IH

IL

time t is measured between V and V .

IH

IL

T

4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write

cycle and delayed write cycle, either t (min) or t (min) must be satisfied.

DZC

DZO

5. t

(max), t

(max) and t

(min) are defined as the time at which the

OFF1

OFF2

SHZ

SLZ

output acheives the open circuit condition (V

– 100 mV, V

+ 100 mV). This parameter is

OH

OL

sampled and not 100% tested.

6. Assume that t

< t

(max) and t

< t

(max). If t

or t

is greater than the

RAD

RCD

RAD

RCD

maximum recommended value shown in this table, t

exceeds the value shown.

RAC

7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF.

8. When t

9. When t

10. If either t

11. When t

> t

< t

(max) and t

< t

> t

(max), access time is specified by t

.

RCD

RAD

CAC

AA

.

RCD

RAD

or t

is satisfied, operation is guaranteed.

RCH

RRH

> t

(min), the cycle is an early write cycle, and I/O pins remain in an open

WCS

circuit (high impedance) condition.

12. These parameters are specified by the later falling edge of CAS or WEU and WEL.

13. Either t

(min) or t

(min) must be satisfied because output buffer must be turned off by

CDD

ODD

CAS or OE prior to applying data to the device when output buffer is on.

14. When t > t (min) and t > t (min) in read-modify-write cycle, the data of the

AWD

CWD

selected address outputs to an I/O pin and input data is written into the selected address. t

ODD

(min) must be satisfied because output buffer must be turned off by OE prior to applying data to

the device.

15. Measured with a load circuit equivalent to 1 TTL loads and 30 pF.

16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal

memory cycle or refresh cycle), then start operation. Hitachi recommends that least 8

initialization cycle is the CBRR for internal register reset. This CBRR need not t

and t

.

STS

RST

17. When t

and t

are measured in the same V

and Ta condition and tr and tf of SE are

SHZ

SLZ

SHZ

CC

less than 5 ns, t

< t

+5 ns. This parameter is sampled and not 100% tested.

SLZ

18. When both WEU and WEL go low at the same time, all 16-bits data are written into the device,

WEU and WEL cannot be staggered within the same write cycles.

19. After power-up, QSF output may be High-Z, so 1 sc cycle is needed to be Low-Z it.

20. DSF2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition

mode in future.

Preliminary Data Sheet E0160H10

30

HM5316123B Series

*21

Timing Waveforms

Read Cycle

t_RC

t _RAS

t_RP

RAS

CAS

t_CRP

t _CSH

t_RSH

t_CAS

t_RCD

t_RAL

t_CAH

t _RAD

t _RAH

t_CAL

t _ASR

Row

t_ASC

Column

t_RCS

Address

t_RRH

t_RCH

WEL

t_CAC

t_AA

t_RAC

t_CDD

t_OFF1

I/O 0 to I/O 7

(Output)

Valid Dout

t_OAC

t_DZC

t_OFF2

I/O 0 to I/O 7

(Input)

t_DZO

t_RCS

t_RRH

t_RCH

WEU

t_CAC

t_CDD

t_AA

t_OFF1

Valid Dout

t_OFF2

t_RAC

I/O 8 to I/O 15

(Output)

t_OAC

t_DZC

I/O 8 to I/O 15

(Input)

t_DZO

t_DTS

t_DTH

DT/OE

t_RFH

t_FSC

t_FSR

t_CFH

DSF1

Note: 21.

V

or V

IL

IH

Invalid Dout

Preliminary Data Sheet E0160H10

31

HM5316123B Series

Fast page Mode Read Cycle

t_RC

t_RASP

t_RP

RAS

t_PC

t_CSH

t_RCD

t_RSH

t_CAS

t_CRP

t_CAS

t_CP

t_RAL

t_CP

t_CAS

CAS

t_RAD

t_CAL

t_CAH

t_CAL

t_CAH

t_CAL

t_CAH

t_ASR

t_ASC

t_RAH

Row

t_ASC

Address

WEU, WEL

Column

t_RRH

t_RCS

t_RCH

t_RCS

t_RCH

t_RCS

t

RCH

t_RAC

t_OFF1

t_AA

t_ACP

t_CAC

t_AA

t_ACP

t_CAC

t_OFF1

t_AA

t_CAC

t_OFF1

Valid

Dout

Valid

Dout

I/O

(Output)

Valid Dout

t_CDD

t_OAC

t_CDD

t_DZC

t_CDD

t_OFF2

t_OAC

t_OFF2

t_OAC

I/O

(Input)

t_DZO

t_DTH

t_DTS

DT/OE

t_RFH

t_CFH

t_FSR

t_FSC

t_CFHt_FSC

t_FSC

DSF1

Preliminary Data Sheet E0160H10

32

HM5316123B Series

Write Cycle

The write cycle state table as shown below is

applied to early write, delayed write, page mode

write, and read-modify write.

Write Cycle State Table

RAS

CAS RAS

RAS

CAS

—————————————————————————

DSF1 DSF1 WEU, WEL I/O

I/O

—————————————————————————

MNEU

Cycle

W1

W2

W3

W4

W5

——————————————————————————————————————————

RWM

Write mask (new/old)

0

Write mask^*1Valid data

Write DQs to I/Os

——————————————————————————————————————————

BWM

Write mask (new/old)

0

1

0

Write mask^*2Column mask^*2

Block write

——————————————————————————————————————————

RW

Normal write (no mask)

0

1

H or L^*1

Valid data

——————————————————————————————————————————

BW

Block write (no mask)

0

1

H or L^*2

Column mask^*2

——————————————————————————————————————————

LMR^*4

Load write mask resister

1

0

1

H or L

Write mask data^*3

——————————————————————————————————————————

LCR^*4

Load color resister

1

H or L

Color data

——————————————————————————————————————————

Notes: 1.

I/O data/RAS

Mode

New mask mode Mask

WEU, WEL

Either Low

Persistent

mask mode

H or L

(mask register used)

H or L

Both High

No mask

I/O Mask Data (In new mask mode)

Low: Mask

High: Non Mask

In persistent mask mode, I/O don't care

2. Reference Figure 2 Use of Block Write.

3. I/O Write Mask Data

Low: Mask

High: Non Mask

4. Column Address: H or L

Preliminary Data Sheet E0160H10

33

HM5316123B Series

Early Write Cycle

t_RC

t_RAS

t_RP

RAS

CAS

t_CRP

t_CSH

t_RSH

t_CAS

t_RCD

t_ASR

t_RAH

t_ASC

Column

(CASU/CASL)

t_CAH

Address

Row

t_WS

t_WH

t_WCS

t_WCH

W3

WEL

High-Z

I/O 0 to I/O7

(Output)

t_MH

t_MS

t_DH

t_DS

I/O 0 to I/O 7

(Input)

W4

W3

W5

t_WCS

t_WS

t_WH

t_WCH

WEU

High-Z

I/O 8 to I/O 15

(Output)

t_MH

t_MS

t_DH

t_DS

I/O 8 to I/O 15

(Input)

W4

W5

t_DTS

t_DTH

DT/OE

t_FSR

W1

t_RFH

t_CFH

t_FSC

W2

DSF1

W1 to W5: See write cycle state table for the logic states.

Preliminary Data Sheet E0160H10

34

HM5316123B Series

Delayed Write Cycle

t_RC

t_RAS

t_RP

RAS

t_CRP

t_CSH

t_RSH

t_RCD

t_CAS

CAS

t_ASRt_RAH

Row

t_ASC

Column

(CASU, CASL)

t_CAH

Address

t_RWL

t_WP

t_WS

t_WH

t_CWL

W3

WEL

I/O 0 to I/O 7

(Output)

t_DH

W5

t_DS

t_MS

t_MH

t_DZC

I/O 0 to I/O 7

(Input)

W4

W3

t_RWL

t_WP

t_WS

t_WH

CWL

WEU

I/O 8 to I/O 15

(Output)

t_DH

t_DS

t_MS

t_MH

t_DZC

I/O 8 to I/O 15

(Input)

W5

t_OEH

W4

t_OFF2

t_ODD

t_DTH

t_DTS

DT/OE

t_RFH

t_FSR

t_CFH

t_FSC

W2

W1

DSF1

W1 to W5: See write cycle state table for the logic states

Preliminary Data Sheet E0160H10

35

HM5316123B Series

Fast page Mode Write Cycle (Early Write)

t_RC

t_RP

t_RASP

RAS

t_CSH

t_PC

t_RSH

t_CAS

t_CP

t_CRP

t_CP

t_RCD

t_CAS

t_CAH

t_CAS

t_CAH

CAS

(CASU, CASL)

t_ASR

t_{RAH t}

ASC

t_ASC

t_CAH

Address

Row

t_WH

Column

t_WCS

Column

t_WCS

t_WS

t_WCS

t_WCH

WEU, WEL

W3

t_MSt_MHt_DS

High-Z

I/O

(Output)

t_DH

t_DS

I/O

(Input)

W4

W5

t_DTS

t_DTH

DT/OE

t_RFH

t_FSC

t_FSR

t_CFH

t_FSC

t_CFH

t_FSC

t_CFH

W1

W2

DSF1

W1 to W5: See write cycle state table for the logic states

Fast page Mode Write Cycle (Delayed Write)

t_RC

t_RP

t_RASP

RAS

t_CSH

t_PC

t_RSH

t_CAS

t_CP

t_CRP

t_RCD

t_ASC

t_CP

t_CAS

t_CAH

t_CAS

t_CAH

CAS

t_ASR

t_RAH

Row

t_WSt_WH

W3

t_MH

W4

t_ASC

Column

(CASU, CASL)

t_CAH

Address

Column

t_RWL

t_WP

t_CWL

t_WP

t_CWL

t_WP

t_CWL

WEU, WEL

High-Z

I/O

(Output)

t_MS

t_DS

t_DSt_DH

W5

t_DH

I/O

(Input)

W5

t_OEH

t_DTS

DT/OE

t_RFH

t_FSCt_CFH

W2

t_FSCt_CFH

W2

t_FSC

W2

t_CFH

t_FSR

DSF1

W1

W1 to W5: See write cycle state table for the logic states

Preliminary Data Sheet E0160H10

36

HM5316123B Series

Read Modify Write Cycle

t_RWC

t_RWS

t_RP

RAS

t_CRP

t_RCD

CAS

(CASU, CASL)

t_RAD

t_RAH

t_ASR

t_CAH

Column

t_ASC

Address

Row

t_AWD

t_CWD

t_RWL

t_CWL

t_WP

t_WS

t_WH

W3

t_RCS

t_CAC

t_AA

t_RAC

WEL

I/O 0 to I/O 7

(Output)

Valid Dout

t_DS

t_OAC

t_DH

W5

t_MS

t_MH

W4

t_DZC

I/O 0 to I/O 7

(Input)

t_OFF2

t_ODD

t_RWL

t_CWL

t_WP

t_WS

t_WH

W3

t_RCS

t_CWD

t_CAC

t_AA

WEU

t_RAC

I/O 8 to I/O 15

(Output)

Valid Dout

t_DS

t_OAC

t_DH

W5

t_MS

t_MH

t_DZC

I/O 8 to I/O 15

(Input)

W4

t_DZO

t_DTS

t_DTH

t_OEH

t_ODD

DT/OE

t_RFH

t_FSC

W2

t_FSR

t_CFH

DSF1

W1

W1 to W5: See write cycle state table for the logic states

Preliminary Data Sheet E0160H10

37

HM5316123B Series

RAS-Only Refresh Cycle

t_RC

t_RP

t_RAS

RAS

t_RPC

t_CRP

CAS

t_ASR

t_RAH

Row

Address

t_OFF1

I/O

(Output)

t_CDD

t_OFF2

I/O

(Input)

t_ODD

t_DTS

t_DTH

DT/OE

t_FSRt_RFH

DSF1

WE: H or L

CAS-Before-RAS refresh Cycle

t_RC

t_RP

t_RAS

RAS

t_RPC

t_CP

t_CSR

t_RPC

Inhibit Falling Transition

t_CSR

t_CHR

CAS

Address

t_WS

t_WH

WEU, WEL

t_OFF1

High-Z

I/O

(Output)

DT/OE

t_FSR

t_RFH

DSF1

SC : H or L

Preliminary Data Sheet E0160H10

38

HM5316123B Series

Hidden Refresh Cycle

t_RC

t_RAS

t_RP

RAS

CAS

t_CRP

t_RCD

t_RSH

t_CHR

t_RAD

t_RAH

t_RAL

t_ASC

Column

t_RCS

t_ASR

Row

t_CAH

Address

t_WH

t_RRH

t_WS

t_CAC

WEU, WEL

t_AA

t_RAC

t_OFF1

I/O

(Output)

Valid Dout

t_DZC

t_OAC

t_OFF2

I/O

(Input)

t_DZO

t_DTH

t_DTS

t_FSR

DT/OE

t_RFH

t_FSR

t_RFH

t_CFH

t_FSC

DSF1

Preliminary Data Sheet E0160H10

39

HM5316123B Series

CAS-Before-RAS Set Cycle (CBRS)

t_RC

t_RAS

t_RP

RAS

t_RPC

t_CSR

t_CHR

t_CRP

Inhibit falling transition

CAS

t_ASRt_RAH

Address

(A2-A6)

Stop Address

t_WSt_WH

WEU, WEL

High-Z

I/O

(Output)

I/O

(Input)

DT/OE

t_FSR

t_RFH

DSF1

A0, A1, A7 : Don't care

SC: Dont care

CAS-Before-RAS Reset Cycle (CBRR)

t_RC

t_RP

t_RAS

t_RP

RAS

t_RPC

t_CSR

t_CHR

t_CRP

Inhibit falling transition

CAS

Address

t_WS

t_WH

WEU, WEL

High-Z

I/O

(Output)

I/O

(Input)

DT/OE

t_FSR

t_RFH

t_RST

Bj-2

Note: 1. Bi, Bj initiate the boundary addresses.

DSF1

t_STS

Bi*1

SC

Bj-1

Bj*1

Preliminary Data Sheet E0160H10

40

HM5316123B Series

Flash Write Cycle

t_RC

t_RAS

t_RP

RAS

t_CRP

t_RCD

t_RAH

CAS

t_ASR

Row

t_WS

Address

t_WH

WEU, WEL

t_CDD

t_OFF1

t_OFF2

High-Z

I/O

(Output)

t_MS

t_MH

t_ODD

I/O

(Input)

Mask Data

t_DTH

t_DTS

DT/OE

t_FSR

t_RFH

DSF1

Preliminary Data Sheet E0160H10

41

HM5316123B Series

Register Read Cycle (Mask data, Color data)

t_RC

t_RAS

t_RP

t_CRP

RAS

t_CSH

t_CAS

t_RCD

t_RSH

CAS

t_ASRt_RAH

Row

Address

t_RRH

t_CDO

t_WSt_WH

t_RCS

t_RCH

WEU, WEL

t_CAC

t_RAC

t_OFF1

Valid Out

t_OFF2

I/O

(Output)

t_DZC

t_OAC

t_ODD

I/O

(Input)

t_DZO

t_DTH

t_DTS

DT/OE

t_FSC

t_FSRt_RFH

t_CFH

DSF1

*1

Note: 1. State of DSF1 at falling edge of CAS

State

0

1

Accessed Mask data Color data

data (LMR) (LCR)

Preliminary Data Sheet E0160H10

42

HM5316123B Series

Read Transfer Cycle-1

t_RC

t_RP

t_RAS

RAS

t_CRP

t_CSH

t_RCD

t_RSH

t_CAS

CAS

t_RAD

t_RAH

t_RAL

t_ASR

Row

t_CAH

t_ASC

SAM Start

Address

t_WS

t_WH

WEU, WEL

High-Z

I/O

(Output)

t_CDH

t_ADH

t_RDH

t_DRD

t_DTS

t_DTP

DT/OE

t_RFH

t_SCC

t_FSR

DSF1

t_SCC

t_SCP

t_SCC

t_SDH

t_SDD

t_SC

SC

t_SCA

t_SOH

t_SCA

t_SOH

Valid Sout

t_SCA

t_SOH

Valid Sout

Previous Row

Valid Sout

SI/O

(Output)

New Row

High-Z

SI/O

(Input)

t_DQD

t_DQH

QSF

SAM Address MSB

Preliminary Data Sheet E0160H10

43

HM5316123B Series

Read Transfer Cycle-2

t_RC

t_RAS

t_RP

RAS

t_CSH

t_CRP

t_RSH

t_CAS

t_RCD

CAS

t_RAD

t_RAH

t_RAL

t_ASR

t_ASC

t_CAH

SAM Start

Address

Row

t_WH

t_WS

WEU, WEL

High-Z

I/O

(Output)

t_DRD

t_DTS

t_DTH

t_DTP

DT/OE

t_RFH

t_FSR

DSF1

t_SRS

t_SC

t_SDH

t_SCP

t_SCC

t_SAH

t_SCP

t_SC

Inhibit Rising Transition

SC

t_SCA

t_SCH

t_SOH

Valid Sout

t_SRH

SI/O

(Output)

t_SIS

t_SIH

t_SZS

Valid

Sin

SI/O

(Input)

t_DQD

t_CQD

t_CQH

t_RQD

t_RQH

t_DQH

SAM Address MSB

QSF

Preliminary Data Sheet E0160H10

44

HM5316123B Series

Masked Write Transfer Cycle

t_RC

t_RAS

t_RP

RAS

CAS

t_CRP

t_CSH

t_CAS

t_RSH

t_RCD

t_ASRt_RAH

t_ASC

t_CAH

SAM Start

Address

Row

t_WSt_WH

WEU, WEL

High-Z

I/O

(Output)

t_DTSt_DTH

DT/OE

t_FSRt_RFH

DSF1

t_SRD

t_SRS

t_SC

t_SCC

t_SCPt_SCt_SCP

Inhibit Rising Transition

t_SID

SC

t_SRZ

t_SCA

Valid

t_SOH

SI/O

(Output)

Valid

t_SISt_SIH

High-Z

SI/O

(Input)

Valid Sin

t_CQD

t_CQH

t_RQD

t_RQH

SAM Address MSB

t_MSt_MH

QSF

I/O

(Input)

*1

I/O Mask Data

Note: 1. I/O mask data (In new mask mode)

Low: Mask

High: Non mask

I/O: Don't care in persistent mask mode.

Preliminary Data Sheet E0160H10

45

HM5316123B Series

Split Read Transfer Cycle

t

RC

t

RP

RAS

t

CSH

t

RSH

t

RCD

CRP

t

CRP

t

CAS

t

RAD

t

RAL

t

ASR

RAH

t

CAH

ASC

*3

SAM Start

Address Yi

Address

Row

t

WH

WS

WEU, WEL

t

OFF1

High-Z

I/O

(Output)

t

DTH

DTS

DT/OE

t

RFH

t

FSR

DSF1

t

CST

t

AST

t

RST

t

SCC

t

SC

SCP

STS

SC

*2

*1

Bi

t

Ym

Ym + 1

Ym + 2

Bj – 2

Bj – 1

Bj

Yi

t

SCA

t

SCA

t

SOH

SI/O

(Output)

Valid

Sout

Valid

Sout

Valid

Sout

Valid

Sout

Valid

Sout

Valid Sout

SI/O

(Input)

High-Z

t

SQD

t

SQH

t

SQH

QSF

SAM Address MSB

Notes: 1. Ym is the SAM start address in before SRT.

2. Bi, Bj initiate the boundary address.

3. A7 : H or L

SAM start address can't set on the boundary address.

Preliminary Data Sheet E0160H10

46

HM5316123B Series

Masked Split Write Transfer Cycle

t_RC

t_RAS

t_RP

RAS

CAS

t_CSH

t_CAS

t_RSH

t_RCD

t_ASRt_RAHt_ASCt_CAH

*4

SAM Start

Address Yi

Row

Address

t_WSt_WH

WEU, WEL

t_OFF1

High-Z

I/O

(Output)

t_DTSt_DTH

DT/OE

t_FSRt_RFH

DSF1

t_CST

t_AST

t_RST

t_SCC

t_SCt_SCP

t_STS

SC

Bi*2

Ym*1

Ym+1

Ym+2

Bj-2

Bj-1

Bj*2

Yi

SI/O

(Output)

t_SIH

t_SISt_SIH

t_SIS

SI/O

(Input)

Valid

Sin

Valid

Sin

Valid

Sin

Valid

Sin

Valid

Sin

Valid

Sin

t_SQD

t_SQH

Valid

Sin

t_SQD

t_SQH

SAM Address MSB

QSF

t_CDDt_MSt_MH

I/O

(Input)

*3

I/O Mask Data

Notes: 1. Ym is the SAM start address in before SRWT.

2. Bi, Bj initiate the boundary address.

3. I/O Mask data (In new mask mode)

Low: Mask

High: Non mask

I/O: Don't care in persistent mask mode.

4. A7: H or L

SAM start address can't set on the boundary address.

Preliminary Data Sheet E0160H10

47

HM5316123B Series

Serial Read Cycle

SE

t_SCC

t_SCP

t_SC

t_SCA

t_SCP

t_SC

t_SCP

t_SC

SC

t_SCA

t_SOH

t_SEA

t_SCA

t_SLZ

t_SHZ

t_SOH

Valid

Sout

SI/O

(Output)

Valid Sout

Sereal Write Cycle

t_SWH

t_SWISt_SWIH

t_SWS

SE

t_SCC

t_SC

t_SCP

t_SC

t_SCP

SC

t_SISt_SIH

Valid Sin

t_SIS

t_SIH

t_SIS

t_SIH

SI/O

(Input)

Valid Sin

Preliminary Data Sheet E0160H10

48

HM5316123B Series

Package Dimensions

HM5316123BF Series (FP-64DS)

Unit: mm

26.2

27.0 Max

64

33

1

32

13.8 ± 0.2

1.10 Max

0 – 10°

0.50 ⁺^–0⁰^.^.²³⁵⁰

+0.08

0.30

–0.02

M

0.16

0.80

0.10

Preliminary Data Sheet E0160H10

49

HM5316123B Series

Cautions

1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any

third party’s patent, copyright, trademark, or other intellectual property rights for information

contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise

with third party’s rights, including intellectual property rights, in connection with use of the

information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, contact Elpida Memory, Inc. before using the product in an application that demands

especially high quality and reliability or where its failure or malfunction may directly threaten human

life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control,

transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory,

Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for

failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and employ

systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc.

product does not cause bodily injury, fire or other consequential damage due to operation of the

Elpida Memory, Inc. product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Elpida Memory, Inc..

7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.

semiconductor products.

Preliminary Data Sheet E0160H10

50


型号：	HM5316123BF-7
厂家：	ELPIDA MEMORY
描述：	131,072-word x 16-bit Multiport CMOS Video RAM 131,072字×16位的多端口视频CMOS RAM
文件：	总50页 (文件大小：509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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