MC-45D16CB641KF-C80 [ELPIDA]
16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE; 16 M- WORD 64位DDR同步动态RAM模块UNBUFFERED TYPE
| 型号： | MC-45D16CB641KF-C80 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE |
| 文件： | 总16页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45D16CB641
16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45D16CB641 is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8 pieces
of 128M DDR SDRAM: µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 64 bits organization
• Clock frequency
Part number
MC-45D16CB641KF-C75
MC-45D16CB641KF-C80
/CAS latency
Clock frequency
(MAX.)
Module type
CL = 2.5
CL = 2
133 MHz
100 MHz
125 MHz
100 MHz
DDR SDRAM
Unbuffered DIMM
Design specification
Rev.0.9 compliant
CL = 2.5
CL = 2
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
DD
• 2.5 V ± 0.2 V Power supply for V
• 2.5 V ± 0.2 V Power supply for V
DDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0034N10 (1st edition)
(Previous No. M14897EJ2V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Ordering Information
Part number
Clock frequency
(MAX.)
Package
Mounted devices
MC-45D16CB641KF-C75
MC-45D16CB641KF-C80
133 MHz
184-pin Dual In-line Memory Module 8 pieces of µPD45D128842G5 (Rev. K)
(Socket Type)
(10.16 mm (400) TSOP (II))
125 MHz
Edge connector: Gold plated
31.75 mm height
2
Preliminary Data Sheet E0034N10
Pin Configuration
184-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
V
SS
VREF
1
93
94
DQ4
DQ5
DQ0
SS
2
V
3
95
V
DD
Q
DQ1
DQS0
DQ2
4
96
DM0/DQS9
DQ6
5
97
6
98
DQ7
V
VDD
DQ3
NC
7
99
SS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NC
NC
NC
9
/RESET
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V
SS
V
DD
Q
DQ8
DQ9
DQ12
DQ13
DQS1
DM1/DQS10
VDDQ
V
DD
CK1
DQ14
DQ15
NC
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
NC
DQ20
NC
VDDQ
DQ16
DQ17
DQS2
V
SS
A0 - A11
: Address Inputs
DQ21
A11
VSS
[Row: A0 - A11, Column: A0 - A9]
DM2/DQS11
A9
DQ18
A7
V
DQ22
A8
DD
BA0, BA1
: SDRAM Bank Select
VDDQ
DQ19
A5
DQ24
VSS
DQ23
V
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
SS
DQ0 - DQ63
CK0 - CK2
: Data Inputs/Outputs
: Clock Input
DQ25
DQS3
A4
(positive line of differential pair)
V
DD
DQ30
V
DQ26
DQ27
A2
SS
/CK0 - /CK2
: Clock Input
DQ31
NC
V
SS
NC
A1
NC
NC
(negative line of differential pair)
VDDQ
CK0
CKE0
/S0
: Clock Enable Input
/CK0
VDD
V
SS
NC
A0
NC
A10
NC
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
NC
V
SS
V
NC
DD
Q
NC
/RAS
BA1
/CAS
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
V
SS
DQ32
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQ36
DQ37
VDDQ
/WE
DQ33
DQS4
DQ34
V
DD
DM4/DQS13
DQ38
DQS0 - DQS7
: Low Data Strobe
V
SS
DQ39
V
DQ44
/RAS
DQ45
VDDQ
/S0
NC
DM5/DQS14
V
BA0
DQ35
DQ40
SS
DM(0 - 7) / DQS(9 - 16) : Low Data Masks /
High Data Strobe
VDDQ
/WE
DQ41
/CAS
SA0 - SA2
SDA
: Address Input for EEPROM
VSS
DQS5
DQ42
DQ43
SS
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
DQ46
DQ47
NC
V
DD
NC
DQ48
DQ49
SCL
VDDQ
DQ52
DQ53
NC
DD
V
V
SS
CK2
V
DD
/CK2
VDDQ
VSS
: Ground
DM6/DQS15
DQ54
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQ55
VDDID
DD
: VDD Identification Flag
: Power Supply for DQ and DQS
: Input Reference
VDDQ
NC
DQ60
DQ61
V
Q
V
SS
VREF
DM7/DQS16
DQ62
DQS7
DQ58
DQ59
DQ63
VDDQ
VDDSPD
NC
: Power supply for EEPROM
: No Connection
SA0
SA1
SA2
VSS
NC
SDA
SCL
V
DDSPD
/RESET
: Reset Input
Preliminary Data Sheet E0034N10
3
Block Diagram
/S0
DQS0
DQS4
DM0/DQS9
DM4/DQS13
DM
DQS
DM
/S
D0
/S DQS
D4
DQ 0
DQ 1
DQ 2
DQ 3
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 32
DQ 33
DQ 34
DQ 35
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 4
DQ 5
DQ 6
DQ 7
DQ 36
DQ 37
DQ 38
DQ 39
DQS1
DQS5
DM1/DQS10
DM5/DQS14
DM
DQS
DM
/S
D1
/S DQS
D5
DQ 8
DQ 9
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 40
DQ 41
DQ 42
DQ 43
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 44
DQ 45
DQ 46
DQ 47
DQS2
DQS6
DM2/DQS11
DM6/DQS15
DM
DQS
DM
/S
D2
/S DQS
D6
DQ 16
DQ 17
DQ 18
DQ 19
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 48
DQ 49
DQ 50
DQ 51
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 20
DQ 21
DQ 22
DQ 23
DQ 52
DQ 53
DQ 54
DQ 55
DQS3
DQS7
DM3/DQS12
DM7/DQS16
DM
DQS
DM
/S
D3
/S DQS
D7
DQ 24
DQ 25
DQ 26
DQ 27
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 56
DQ 57
DQ 58
DQ 59
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 28
DQ 29
DQ 30
DQ 31
DQ 60
DQ 61
DQ 62
DQ 63
SERIAL PD
BA0 - BA1
A0 - A11
/RAS
BA0 - BA1 : SDRAMs D0 - D7
A0 - A11 : SDRAMs D0 - D7
SDA
SCL
/RAS
/CAS
CKE0
/WE
: SDRAMs D0 - D7
: SDRAMs D0 - D7
: SDRAMs D0 - D7
: SDRAMs D0 - D7
A0
A1
A2
/CAS
CKE0
SA0 SA1 SA2
/WE
CK0, /CK0
CK1, /CK1
CK2, /CK2
CK, /CK : SDRAMs D3, D4
CK, /CK : SDRAMs D0, D1, D2
CK, /CK : SDRAMs D5, D6, D7
D0 - D7
V
DDQ
D0 - D7
D0 - D7
V
DD
V
REF
SS
DDID
V
D0 - D7
V
Remarks 1.
2.
The value of all resistors of DQs, DQSs, DM/DQSs is 22 Ω.
D0 – D7: PD45D128842 (4M words × 8 bits × 4 banks)
µ
4
Preliminary Data Sheet E0034N10
Electrical Specifications
• All voltages are referenced to V
SS (GND).
Power on sequence and CBR (auto) refresh
• After power up, wait more than 1 ms and then, execute
before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to VSS
Voltage on input pin relative to VSS
Short circuit output current
Power dissipation
Symbol
VDD, VDDQ
VT
Condition
Rating
–0.5 to +3.6
–0.5 to +3.6
50
Unit
V
V
IO
mA
W
D
P
12
stg
Storage temperature
T
–55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
2.3
TYP.
2.5
MAX.
Unit
V
DD
V
Supply voltage
2.7
2.7
Supply voltage for DQ, DQS
Input reference voltage
VDDQ
VREF
2.3
2.5
V
0.49 × VDDQ
VREF − 0.04
VREF + 0.15
−0.3
0.51 × VDDQ
VREF + 0.04
VDD + 0.3
VREF − 0.15
DD
V
Termination voltage
VTT
VREF
V
High level dc input voltage
Low level dc input voltage
Input differential voltage (CLK and /CLK)
Input crossing point voltage (CLK and /CLK)
Operating ambient temperature
VIH (DC)
VIL (DC)
ID
V
V
V
(DC)
0.36
V
Q + 0.6
V
IX
DD
DD
V
0.5 × V Q–0.2
0.5 × V Q+0.2
V
TA
0
70
°C
Capacitance (TA = 25 C, f = 100 MHz)
°
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
TBD
Unit
I1
C
Input capacitance
A0 - A11, BA0, BA1, /RAS,
/CAS, /WE
TBD
pF
CI2
CK0 - CK2, /CK0 - /CK2
TBD
TBD
TBD
TBD
CI3
CKE0
0
CI4 /S
TBD
TBD
I/O1
Data input/output capacitance
C
DM(0-7)/DQS(9-16),
DQS0 - DQS7
TBD
TBD
TBD
pF
CI/O2
DQ0 - DQ63
TBD
Preliminary Data Sheet E0034N10
5
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Notes
Parameter
Symbol
Test condition
/CAS Grade
latency
MIN.
MAX.
TBD
Unit
mA
RC
RC(MIN.) CK
CK (MIN.)
t
= t
, t = t
, One bank,
Operating current
(ACT-PRE)
IDD0
-C75
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
-C80
TBD
tRC = tRC(MIN.), tCK = tCK (MIN.), One
bank, Active-read-precharge,
Operating current
(ACT-READ-PRE)
IDD1
CL = 2 -C75
-C80
TBD
TBD
TBD
TBD
TBD
mA
1
O
I
= 0 mA, Burst length = 2,
CL = 2.5 -C75
-C80
Address and control inputs
changing once per clock cycle
CKE ≤ VIL(MAX.), tCK = tCK(MIN.),
All banks idle, Power down mode
Precharge power down
standby current
IDD2P
mA
mA
CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All banks idle, Address and other control inputs
changing once per clock cycle
DD2N
Idle standby current
I
TBD
CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active,
Power down mode
DD3P
Active power down
standby current
I
TBD
TBD
mA
mA
IH(MIN.)
/CS ≥ V
IH(MIN.) CK
CK(MIN.) RC
, CKE ≥ V
, t = t
, t
=
Active standby current
IDD3N
tRAS(MAX.), One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
tCK = tCK(MIN.), Continuous burst
read, Burst length = 2, IO =
0mA, One bank active,
Address and control inputs
changing once per clock cycle
Operating current
(Burst read)
IDD4R
CL = 2 -C75
-C80
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
2
2
CL = 2.5 -C75
-C80
tCK = tCK(MIN.), Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
Operating current
(Burst write)
IDD4W
CL = 2 -C75
-C80
CL = 2.5 -C75
-C80
tRFC = tRFC(MIN.)
CBR (auto) refresh current
Self refresh current
IDD5
-C75
mA
mA
-C80
CKE ≤ 0.2 V
DD6
I
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. DD4R
I and I
open.
DD4W
depend on output loading and cycle rates. Specified values are obtained with the output
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
TBD
TBD
TBD
TBD
MAX.
TBD
TBD
Unit Notes
I(L)
I
µ
A
Input leakage current
Output leakage current
Output high current
Output low current
I
V = 0 to 3.6 V, all other pins not under test = 0 V
DOUT is disabled, VO = 0 to VDDQ + 0.3 V
VOUT = VDDQ − 0.43 V
IO(L)
IOH
µA
mA
mA
OL
OUT
V
I
= 0.35 V
6
Preliminary Data Sheet E0034N10
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
Input Reference voltage (Input timing measurement reference level)
Termination voltage (Output timing measurement reference level)
High level ac input voltage
Symbol
Value
Unit Notes
V
REF
V
DD
Q x 0.5
V
VTT
VREF
V
V
1
VIH(ac)
VREF + 0.31
IL
REF
Low level ac input voltage
V (ac)
V
− 0.31
V
Input differential voltage (CK0 - CK2 and /CK0 - /CK2)
Input signal slew rate
VID(ac)
SLEW
0.7
V
1
V/ns
2
Notes 1.
2.
TT
Output waveform timing is measured where the output signal crosses through the V level.
IL
IH
IH
Slew rate is to be maintained in the V (ac) to V (ac) range of the input signal swing. SLEW = (V (ac)-
IL
V (ac))/ ∆t
VTT
RT = 50Ω
Output
CLOAD = 30 pF
Preliminary Data Sheet E0034N10
7
Synchronous Characteristics
Parameter
Symbol
tCK
-C75 (PC266B)
-C80 (PC200)
Unit
ns
Note
MIN.
MAX.
15
MIN.
MAX.
15
Clock cycle time
CL = 2.5
CL = 2
7.5
10
8
15
10
15
CLK high-level width
tCH
tCL
tAC
0.45
0.45
–0.75
–0.75
–0.5
0.55
0.55
0.75
0.75
0.5
0.45
0.45
–0.8
–0.8
–0.6
0.55
0.55
0.8
tCK
tCK
ns
ns
ns
CLK low-level width
DQ output access time from CLK, /CLK
DQS output access time from CLK, /CLK
DQSCK
t
0.8
DQSQ
DQS-DQ skew (for DQS and associated DQ
signals)
t
0.6
DQS-DQ skew (for DQS and all DQ signals)
tDQSQA
tLZ
–0.5
–0.75
–0.75
tCH, tCL
0.9
0.5
–0.6
–0.8
–0.8
tCH, tCL
0.9
0.6
0.8
0.8
ns
ns
ns
ns
Data out low-impedance time from CLK, /CLK
Data out high-impedance time from CLK, /CLK
Half clock period
0.75
0.75
tHZ
tHP
RPRE
CK
DQS read preamble
t
1.1
0.6
1.1
0.6
t
RPST
CK
DQS read postamble
t
0.4
0.4
t
QH
HP
HP
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
t
t
– 0.75
t
– 1
ns
DQ and DM input setup time
tDS
tDH
0.5
0.5
1.75
0
0.6
ns
ns
ns
ns
DQ and DM input hold time
0.6
2
DQ and DM input pulse width (for each input)
DQS write preamble setup time
DQS write preamble
tDIPW
WPRES
t
0
WPRE
CK
t
0.25
0.4
0.75
0.35
0.35
0.2
0.2
0.9
0.9
2.2
1
0.25
0.4
0.75
0.35
0.35
0.2
0.2
1.1
1.1
2.5
1
t
WPST
CK
Write postamble
t
0.6
0.6
t
DQSS
CK
Write command to first DQS latching transition
DQS input high pulse width
t
1.25
1.25
t
tDQSH
tDQSL
tDSS
tDSH
tIS
tCK
tCK
tCK
tCK
ns
ns
ns
tCK
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Internal write to read command delay
tIH
tIPW
tWTR
Remark
These specifications are applied to the monolithic device.
8
Preliminary Data Sheet E0034N10
Asynchronous Characteristics
Parameter
Symbol
-C75(PC266B)
-C80(PC200)
Unit
MIN.
MAX.
MIN.
MAX.
RC
ACT to REF/ACT command period (operation)
REF to REF/ACT command period (refresh)
ACT to PRE command period
t
65
75
45
20
20
15
15
35
15
75
70
80
50
20
20
15
15
35
15
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
RFC
t
tRAS
tRP
tRCD
tRRD
120,000
120,000
PRE to ACT command period
ACT to READ/WRITE delay
ACT(one) to ACT(another) command period
Write recovery time
WR
t
DAL
Auto precharge write recovery time + precharge time
Mode register set command cycle time
Exit self refresh to command
t
MRD
t
tXSNR
tREF
Refresh time (4,096 refresh cycles)
64
64
Preliminary Data Sheet E0034N10
9
Serial PD
(1/2)
Byte No.
0
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
07H
0CH
0AH
01H
40H
00H
04H
75H
80H
75H
80H
00H
80H
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
256 bytes
DDR SDRAM
12 rows
10 columns
1 bank
64 bits
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
SSTL2
7.5 ns
CL = 2.5 Cycle time
-C75
-C80
-C75
-C80
8 ns
10
CL = 2.5 Access time
0.75 ns
0.8 ns
11
12
13S
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
None
Normal
DRwAidMth
08H0 0 0 0 1 0 0x08
Error checking SDRAM width
Minimum clock delay
Burst length supported
00H
01H
0EH
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
None
1 clock
2, 4, 8
4 banks
2, 2.5
Number of banks on each SDRAM
/CAS latency supported
04H
0CH
01H
02H
20H
00H
A0H
A0H
75H
80H
1
0
0
/CS latency supported
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
/WE latency supported
1
SDRAM module attributes
SDRAM device attributes : General
Differential Clock
VDD ± 0.2 V
10 ns
CL = 2 Cycle time
-C75
-C80
-C75
-C80
10 ns
24
CL = 2 Access time
0.75 ns
0.8 ns
25-26
RP(MIN.)
27
28
29
30
31
t
-C75
-C80
-C75
-C80
-C75
-C80
-C75
-C80
50H
50H
3CH
3CH
50H
50H
2DH
32H
20H
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
20 ns
20 ns
tRRD(MIN.)
15 ns
15 ns
tRCD(MIN.)
20 ns
20 ns
tRAS(MIN.)
45 ns
50 ns
Module bank density
128M bytes
10
Preliminary Data Sheet E0034N10
(2/2)
Byte No.
32
Function Described
Command and address signal
input setup time
Hex
90H
B0H
90H
B0H
50H
60H
50H
60H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
0.9 ns
-C75
-C80
-C75
-C80
-C75
-C80
-C75
-C80
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.1 ns
0.9 ns
1.1 ns
0.5 ns
0.6 ns
0.5 ns
0.6 ns
33
34
35
Command and address signal
input hold time
Data signal input setup time
Data signal input hold time
36-61
62
SPD revision
00H
9CH
22H
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
63
Checksum for bytes 0 - 62
-C75
-C80
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-99 Assembly serial number
100-127 Mfg specific
00H
0
0
0
0
0
0
0
0
Timing Chart
Refer to the µPD45D128442, 45D128842, 45D128164 Data sheet (E0030N).
Preliminary Data Sheet E0034N10
11
Package Drawing
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
U
K
J1 (AREA B)
M
M
J
I
A
N
P
E
B
H
J2 (AREA A)
(OPTIONAL HOLES)
Q
D
G
C
A1 (AREA A)
ITEM MILLIMETERS
A
A1
B
133.35
133.35±0.13
64.77
C
6.35
C1
C2
D
1.80
3.80
detail of A part
49.53
E
1.27 (T.P.)
6.35
S
C2
G
H
10.00
I
17.80
J
31.75±0.13
J1
J2
K
23.38
19.80
4.0 MAX.
4.0
R
M
N
T
φ
2.50
C1
P
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
2.50±0.15
3.0 MIN.
Q
R
S
T
U
12
Preliminary Data Sheet E0034N10
[MEMO]
Preliminary Data Sheet E0034N10
13
[MEMO]
14
Preliminary Data Sheet E0034N10
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet E0034N10
15
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
•
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data
books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
M8E 00. 4
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