UPD4516161AG5-A10B-9NF [ELPIDA]
Synchronous DRAM, 1MX16, 7ns, MOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50;
| 型号： | UPD4516161AG5-A10B-9NF |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | Synchronous DRAM, 1MX16, 7ns, MOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总88页 (文件大小：1099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4516421A, 4516821A, 4516161A for Rev.P
16M-bit Synchronous DRAM
2-banks, LVTTL
Description
The µPD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access
memories, organized as 2,097,152 × 4 × 2, 1,048,576 × 8 × 2, 524,288 × 16 × 2 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 44-pin TSOP (II) (× 4, × 8) and 50-pin TSOP (II) (× 16).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Dual internal banks controlled by A11(Bank Select)
• Byte control (×16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 2,048 refresh cycles / 32 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0122N10 (Ver.1.0)
(Previous No. M12939EJ3V0DS00)
Date Published May 2001 CP (K)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Printed in Japan
µPD4516421A, 4516821A, 4516161A for Rev.P
Ordering Information
Organization
Clock frequency
MHz (MAX.)
Part number
Package
(word × bit × bank)
µPD4516421AG5-A80-9NF
µPD4516421AG5-A10-9NF
µPD4516421AG5-A10B-9NF
µPD4516421AG5-A12-9NF
µPD4516821AG5-A80-9NF
µPD4516821AG5-A10-9NF
µPD4516821AG5-A10B-9NF
µPD4516821AG5-A12-9NF
µPD4516161AG5-A80-9NF
µPD4516161AG5-A10-9NF
µPD4516161AG5-A10B-9NF
µPD4516161AG5-A12-9NF
µPD4516421AG5-A80L-9NF
µPD4516421AG5-A10L-9NF
µPD4516421AG5-A10BL-9NF
µPD4516421AG5-A12L-9NF
µPD4516821AG5-A80L-9NF
µPD4516821AG5-A10L-9NF
µPD4516821AG5-A10BL-9NF
µPD4516821AG5-A12L-9NF
µPD4516161AG5-A80L-9NF
µPD4516161AG5-A10L-9NF
µPD4516161AG5-A10BL-9NF
µPD4516161AG5-A12L-9NF
2M × 4 × 2
125
100
100
83
44-pin Plastic TSOP (II)
(10.16mm (400))
1M × 8 × 2
512K × 16 × 2
2M × 4 × 2
125
100
100
83
44-pin Plastic TSOP (II)
(10.16mm (400))
125
100
100
83
50-pin Plastic TSOP (II)
(10.16mm (400))
125
100
100
83
44-pin Plastic TSOP (II)
(10.16mm (400))
1M × 8 × 2
125
100
100
83
44-pin Plastic TSOP (II)
(10.16mm (400))
512K × 16 × 2
125
100
100
83
50-pin Plastic TSOP (II)
(10.16mm (400))
2
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Part Number
[ x4, x8 ]
µ
PD4516821AG5 - A10L
Synchronous
DRAM
Low Power
Memory Density
16 : 16M bits
Minimum Cycle Time
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
12 : 12 ns (83 MHz)
Organization
4 : x4
8 : x8
Number of Banks
RNote( 1 : 1Bank)
2 : 2Bank
Low Voltage
Interface
A : 3.3
± 0.3 V
1 : LVTTL
Package
G5 : TSOP(II)
Version
[ x16 ]
161
Organization
16 : x16
Number of Banks
& Interface
1 : 2Bank, LVTTL
3
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Pin Configurations
/xxx indicates active low signal.
[µPD4516421A]
44-pin Plastic TSOP (II) (10.16mm (400))
2M words × 4 bits × 2 banks
V
CC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
NC
2
NC
V
SS
Q
3
VSSQ
DQ0
4
DQ3
V
CC
Q
5
VCC
Q
NC
6
NC
V
SS
Q
7
V
SS
Q
DQ1
8
DQ2
V
CC
Q
9
VCCQ
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
/WE
/CAS
/RAS
/CS
A11
A10
A0
DQM
CLK
CKE
NC
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
CC
V
SS
A0 to A11 Note
DQ0 to DQ3
CLK
: Address inputs
: Data inputs / outputs
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
/CAS
/WE
: Row address strobe
: Column address strobe
: Write enable
DQM
VCC
: DQ mask enable
: Supply voltage
: Ground
VSS
Note A0 to A10
A0 to A9
: Row address inputs
: Column address inputs
: Bank select
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
A11
4
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
[µPD4516821A]
44-pin Plastic TSOP (II) (10.16mm (400))
1M words × 8 bits × 2 banks
V
CC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ0
2
DQ7
V
SS
Q
3
VSSQ
DQ1
4
DQ6
V
CC
Q
5
VCCQ
DQ2
6
DQ5
V
SS
Q
7
VSSQ
DQ3
8
DQ4
V
CC
Q
9
VCCQ
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
/WE
/CAS
/RAS
/CS
A11
A10
A0
DQM
CLK
CKE
NC
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
CC
V
SS
A0 to A11 Note
DQ0 to DQ7
CLK
: Address inputs
: Data inputs / outputs
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
/CAS
/WE
: Row address strobe
: Column address strobe
: Write enable
DQM
VCC
: DQ mask enable
: Supply voltage
: Ground
VSS
Note A0 to A10 : Row address inputs
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
A0 to A8 : Column address inputs
A11
: Bank select
5
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
[µPD4516161A]
50-pin Plastic TSOP (II) (10.16mm (400))
512K words × 16 bits × 2 banks
V
CC
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ0
DQ1
2
DQ15
DQ14
3
V
SS
Q
4
VSSQ
DQ2
DQ3
5
DQ13
DQ12
6
V
CC
Q
7
VCCQ
DQ4
DQ5
8
DQ11
DQ10
9
V
SS
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSSQ
DQ6
DQ7
DQ9
DQ8
V
CC
Q
VCCQ
LDQM
/WE
/CAS
/RAS
/CS
A11
A10
A0
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
CC
V
SS
A0 to A11 Note
DQ0 to DQ15
CLK
: Address inputs
: Data inputs / outputs
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
: Row address strobe
: Column address strobe
: Write enable
/CAS
/WE
LDQM
UDQM
VCC
: Lower DQ mask enable
: Upper DQ mask enable
: Supply voltage
VSS
: Ground
Note A0 to A10 : Row address inputs
VCCQ
: Supply voltage for DQ
: Ground for DQ
VSSQ
A0 to A7 : Column address inputs
NC
: No connection
A11
: Bank select
6
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Block Diagram
CLK
Clock
Generator
CKE
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Mode
Register
Bank A
Sense Amplifier
DQM
/CS
Column Decoder &
Column
Address
Buffer
&
Latch Circuit
/RAS
/CAS
/WE
Burst
Counter
Data Control Circuit
DQ
7
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
CONTENTS
1. Input / Output Pin Function ............................................................................................................ 10
2. Commands ....................................................................................................................................... 11
3. Simplified State Diagram ................................................................................................................. 14
4. Truth Table ....................................................................................................................................... 15
4.1 Command Truth Table............................................................................................................................. 15
4.2 DQM Truth Table...................................................................................................................................... 15
4.3 CKE Truth Table....................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE .............................................................................................................. 19
4.6 Command Truth Table for Two Banks Operation ................................................................................ 20
5. Initialization ...................................................................................................................................... 22
6. Programming the Mode Register ................................................................................................... 23
7. Mode Register .................................................................................................................................. 24
7.1 Burst Length and Sequence .................................................................................................................. 25
8. Address Bits of Bank-Select and Precharge ................................................................................. 26
9. Precharge .......................................................................................................................................... 27
10. Auto Precharge ................................................................................................................................ 28
10.1 Read with Auto Precharge .................................................................................................................. 28
10.2 Write with Auto Precharge .................................................................................................................. 29
11. Read / Write Command Interval ...................................................................................................... 30
11.1 Read to Read Command Interval ........................................................................................................ 30
11.2 Write to Write Command Interval ........................................................................................................ 30
11.3 Write to Read Command Interval ........................................................................................................ 31
11.4 Read to Write Command Interval ........................................................................................................ 32
12. Burst Termination ............................................................................................................................ 33
12.1 Burst Stop Command .......................................................................................................................... 33
12.2 Precharge Termination ........................................................................................................................ 34
12.2.1 Precharge Termination in READ Cycle .................................................................................... 34
12.2.2 Precharge Termination in WRITE Cycle .................................................................................. 35
8
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
13. Electrical Specifications .................................................................................................................. 36
13.1 AC Parameters for Read Timing ......................................................................................................... 42
13.2 AC Parameters for Write Timing ......................................................................................................... 43
13.3 Relationship between Frequency and Latency ................................................................................. 44
13.4 Mode Register Set ................................................................................................................................ 45
13.5 Power on Sequence and CBR (Auto) Refresh ................................................................................... 46
13.6 /CS Function ......................................................................................................................................... 47
13.7 Clock Suspension during Burst Read (using CKE Function) .......................................................... 48
13.8 Clock Suspension during Burst Write (using CKE Function) .......................................................... 50
13.9 Power Down Mode and Clock Mask ................................................................................................... 52
13.10 CBR (Auto) Refresh .............................................................................................................................. 53
13.11 Self Refresh (Entry and Exit) ............................................................................................................... 54
13.12 Random Column Read (Page with Same Bank) ................................................................................ 55
13.13 Random Column Write (Page with Same Bank) ................................................................................ 57
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 59
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................. 61
13.16 Read and Write ..................................................................................................................................... 63
13.17 Interleaved Column Read Cycle .......................................................................................................... 65
13.18 Interleaved Column Write Cycle ......................................................................................................... 67
13.19 Auto Precharge after Read Burst ........................................................................................................ 69
13.20 Auto Precharge after Write Burst ....................................................................................................... 71
13.21 Full Page Read Cycle ........................................................................................................................... 73
13.22 Full Page Write Cycle ........................................................................................................................... 75
13.23 Byte Write Operation ............................................................................................................................ 77
13.24 Burst Read and Single Write (Option) ................................................................................................ 78
13.25 Full Page Random Column Read ........................................................................................................ 79
13.26 Full Page Random Column Write ....................................................................................................... 80
13.27 PRE (Precharge) Termination of Burst ............................................................................................... 81
14. Package Drawings ........................................................................................................................... 83
15. Recommended Soldering Condition .............................................................................................. 85
16. Revision History ............................................................................................................................... 86
9
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
1. Input / Output Pin Function
Pin name
Input / Output
Input
Function
CLK
CKE
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge
is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not
issued and the µPD4516xxxA suspends operation.
When the µPD4516xxxA is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS low starts the command input cycle. When /CS is high, commands are ignored but
operations continue.
/CS
Input
Input
Input
/RAS, /CAS, /WE
A0 - A10
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9 at the CLK rising edge in the read or write
command cycle. It depends on the bit organization: A0 - A9 for ×4 device, A0 – A8 for
×8 device, A0 – A7 for ×16 device.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
both banks are precharged; when A10 is low, only the bank selected by A11 is
precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
A11
Input
Input
A11 is the bank select signal. In command cycle, A11 low select bank A and A11 high
high select bank B.
DQM, UDQM, LDQM
DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and
lower byte I/O buffers, respectively.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ15
Input / Output
DQ pins have the same function as I/O pins on a conventional DRAM.
VCC, VSS, VCCQ, VSSQ
(Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power
supply pins for the output buffers.
10
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
2. Commands
Mode register set command
Fig.1 Mode register set command
CLK
(/CS, /RAS, /CAS, /WE = Low)
CKE
/CS
H
The µPD4516xxxA has a mode register that defines how the device
operates. In this command, A0 through A11 are the data input pins.
After power on, the mode register set command must be executed to
initialize the device.
/RAS
/CAS
/WE
A11
The mode register can be set only when both banks are in idle state.
During 2 CLK (tRSC) following this command, the µPD4516xxxA
cannot accept any other commands.
A10
Add
Activate command
Fig.2 Row address strobe and
bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
CLK
CKE
/CS
H
The µPD4516xxxA has two banks, each with 2,048 rows.
This command activates the bank selected by BS(A11) and a row
address selected by A0 through A10.
/RAS
/CAS
/WE
This command corresponds to a conventional DRAM’s /RAS falling.
A11
(Bank select)
A10
Add
Row
Row
Precharge command
Fig.3 Precharge command
CLK
(/CS, /RAS, /WE = Low, /CAS = High)
CKE
/CS
H
This command begins precharge operation of the bank selected by
BS(A11). When A10 is High, both banks are precharged, regardless
of BS(A11). When A10 is Low, only the bank selected by BS(A11) is
precharged. BS(A11) low selects bank A and BS(A11) high selects
bank B.
/RAS
/CAS
/WE
A11
(Bank select)
After this command, the µPD4516xxxA can’t accept the activate
command to the precharging bank during tRP (precharge to activate
command period).
A10
(Precharge select)
Add
This command corresponds to a conventional DRAM’s /RAS rising.
11
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Write command
Fig.4 Column address and write command
CLK
(/CS, /CAS, /WE = Low, /RAS = High)
CKE
/CS
H
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
/RAS
/CAS
/WE
A11
(Bank select)
A10
Add
Col.
Read command
Fig.5 Column address and read command
CLK
(/CS, /CAS = Low, /RAS, /WE = High)
CKE
/CS
H
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the column
address.
/RAS
/CAS
/WE
A11
(Bank select)
A10
Add
Col.
CBR (auto) refresh command
Fig.6 CBR (auto) refresh command
CLK
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
CKE
/CS
H
This command is a request to begin the CBR (auto) refresh
operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, both banks must be
precharged.
/RAS
/CAS
/WE
After this cycle, both banks will be in the idle (precharged) state and
ready for a row activate command.
A11
(Bank select)
A10
Add
During tRC period (from refresh command to refresh or activate
command), the µPD4516xxxA cannot accept any other command.
12
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Self refresh entry command
Fig.7 Self refresh entry command
CLK
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
CKE
/CS
After the command execution, self refresh operation continues while
CKE remains low. When CKE goes high, the µPD4516xxxA exits the
self refresh mode.
/RAS
/CAS
/WE
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, both banks must be precharged.
A11
(Bank select)
A10
Add
Burst stop command
Fig.8 Burst stop command in Full Page
Mode
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A11
(Bank select)
A10
Add
No operation
Fig.9 No operation
CLK
(/CS = Low, /RAS, /CAS, /WE = High)
CKE
/CS
H
This command is not an execution command. No operations begin
or terminate by this command.
/RAS
/CAS
/WE
A11
(Bank select)
A10
Add
13
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
3. Simplified State Diagram
14
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
4. Truth Table
4.1 Command Truth Table
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
A11
A10
A9 - A0
n – 1
H
n
×
×
×
×
×
×
×
×
×
×
×
Device deselect
No operation
DESL
NOP
H
L
L
L
L
L
L
L
L
L
L
×
H
H
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
×
×
×
H
Burst stop
BST
H
×
×
×
Read
READ
READA
WRIT
WRITA
ACT
H
H
H
L
V
V
V
V
V
V
×
L
V
V
V
V
V
×
Read with auto precharge
Write
H
L
H
L
H
L
Write with auto precharge
Bank activate
H
L
L
H
V
L
H
H
H
H
L
H
L
Precharge select bank
Precharge both banks
Mode register set
PRE
H
L
PALL
MRS
H
L
L
H
L
×
H
L
L
L
V
Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function
Symbol
CKE
DQM
n – 1
H
n
×
×
×
×
×
×
U
L
Data write / output enable
ENB
L
Data mask / output disable
MASK
ENBU
ENBL
MASKU
MASKL
H
H
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
H
L
×
×
L
H
H
H
×
×
H
H
Remark H = High level, L = Low level, × = High or Low level (Don't care)
4.3 CKE Truth Table
Current state
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE Address
n – 1
H
L
n
L
Activating
Any
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
CBR (auto) refresh command
Self refresh entry
×
×
×
L
L
L
H
×
×
×
×
×
L
L
H
×
×
×
×
×
×
L
L
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
L
Clock suspend
Idle
L
H
H
L
×
REF
H
H
L
H
H
H
×
Idle
SELF
Self refresh
Self refresh exit
H
H
L
L
Idle
Power down entry
Power down exit
H
L
×
Power down
H
×
Remark H = High level, L = Low level, × = High or Low level (Don't care)
15
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
4.4 Operative Command Table Note1
(1/3)
Current state
Idle
/CS /RAS /CAS /WE
Address
Command
DESL
NOP or BST
Action
Nop or power down
Nop or power down
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
H
H
H
L
×
H
L
×
×
×
×
2
2
3
3
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
Row activating
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop
L
H
L
×
CBR (auto) refresh or self refresh
4
L
L
Op-Code
Mode register accessing
Row active
×
×
×
×
×
DESL
Nop
Nop
H
H
H
L
H
L
×
NOP or BST
H
L
BA, CA, A10 READ/READA Begin read : Determine AP
5
5
3
6
L
BA, CA, A10 WRIT/WRITA
Begin write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Precharge
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Read
×
×
×
×
×
×
DESL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, new read : Determine AP
7
7, 8
3
L
BA, CA, A10 WRIT/WRITA
Terminate burst, start write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Write
×
×
×
×
×
×
DESL
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP
7, 8
7
L
BA, CA, A10 WRIT/WRITA
Terminate burst, new write : Determine AP
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL
3
L
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
9
L
H
L
L
L
Op-Code
ILLEGAL
16
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
(2/3)
Current state
Read with auto
precharge
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
H
L
L
L
L
L
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Continue burst to end → Precharging
Continue burst to end → Precharging
ILLEGAL
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
×
Write with auto
precharge
H
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
×
NOP
BST
Continue burst to end → Write
recovering with auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
ILLEGAL
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Precharging
×
×
×
×
×
×
DESL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
Nop → Enter idle after tRP
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop → Enter idle after tRP
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Row activating
×
×
×
×
×
×
DESL
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
3, 10
3
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
17
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
Write recovering
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
NOP
BST
H
L
BA, CA, A10 READ/READA Start read, Determine AP
8
L
BA, CA, A10 WRIT/WRITA
New write, Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
3
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Write recovering
×
×
×
H
L
×
×
×
DESL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
with auto precharge
H
H
H
H
L
H
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3, 8
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
3
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Refreshing
×
×
×
×
×
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
DESL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
H
H
L
H
L
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
H
L
ILLEGAL
L
ILLEGAL
Mode register
accessing
×
×
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
ILLEGAL
H
H
H
H
H
L
NOP
BST
×
READ/WRIT
ILLEGAL
L
L
×
×
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Notes 1.
2.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If both banks are idle, and CKE is inactive (Low level), µPD4516xxxA will enter Power down mode.
All input buffers except CKE will be disabled.
3.
4.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If both banks are idle, and CKE is inactive (Low level), µPD4516xxxA will enter Self refresh mode. All
input buffers except CKE will be disabled.
5.
6.
7.
8.
9.
Illegal if tRCD is not satisfied.
Illegal if tRAS is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data
18
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
4.5 Command Truth Table for CKE
Current State CKE /CS /RAS /CAS /WE Address
n – 1
Action
Notes
n
×
Self refresh
H
L
×
H
L
L
L
×
H
L
L
L
H
L
L
L
×
×
×
H
L
L
L
L
H
L
L
L
L
×
×
×
×
×
×
×
×
×
H
H
L
×
×
H
H
L
×
H
H
L
×
×
×
×
H
L
L
L
×
H
L
L
L
×
×
×
×
×
×
×
×
×
H
L
×
×
×
H
L
×
×
H
L
×
×
×
×
×
×
H
L
L
×
×
H
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
L
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
INVALID, CLK (n – 1) would exit self refresh
H
H
H
H
L
Self refresh recovery
L
Self refresh recovery
L
ILLEGAL
L
ILLEGAL
L
Maintain self refresh
Self refresh recovery
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle after tRC
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
L
ILLEGAL
L
ILLEGAL
L
ILLEGAL
Power down
×
INVALID, CLK (n – 1) would exit power down
EXIT power down → Idle
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
CBR (auto) Refresh
H
L
×
×
L
Both banks idle
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
×
Op-Code Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
L
L
L
×
Self refresh
1
1
1
2
L
Op-Code Refer to operations in Operative Command Table
×
×
×
×
Power down
Row active
H
L
×
Refer to operations in Operative Command Table
Power down
×
Any state other than
listed above
H
H
L
H
L
Refer to operations in Operative Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
×
×
×
H
L
L
Notes 1. Self refresh can be entered only from the both banks idle state. Power down can be entered only from
both banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level, × = High or Low level (Don't care)
19
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
4.6 Command Truth Table for Two Banks Operation Notes1,2
/CS /RAS /CAS /WE
BA
×
A10 A9-A0
Action
From State Note3
To State Note4
H
L
L
×
H
H
×
H
H
×
H
L
×
×
×
×
×
×
NOP
NOP
BST
Any
Any
Any
Any
×
×
(R/W/A)0 (I/A)1
I0 (I/A)
A0(I/A)1
I0(I/A)1
A1(I/A)0
I1(I/A)0
RP1(I/A)0
RP1A0
R1(I/A)0
R1A0
(R/W/A)1 (I/A)0
I1 (I/A)0
L
H
L
H
H
H
H
H
L
H
H
L
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
Read
(R/W/A)1 (I/A)0
A1(R/W)0
(R/W/A)1 (I/A)0
A1(R/W)0
L
H
H
L
(R/W/A)0 (I/A)1
A0(R/W)1
RP0(I/A)1
RP0A1
R0(I/A)1
R0A1
L
L
(R/W/A)0 (I/A)1
A0(R/W)1
L
L
L
H
L
L
H
H
H
H
L
H
H
L
Write
(R/W/A)1 (I/A)0
A1(R/W)0
WP1(I/A)0
WP1A0
W1(I/A)0
W1A0
(R/W/A)1 (I/A)0
A1(R/W)0
L
H
H
L
(R/W/A)0 (I/A)1
A0(R/W)1
WP0(I/A)1
WP0A1
W0(I/A)1
W0A1
L
L
(R/W/A)0 (I/A)1
A0(R/W)1
L
L
L
L
L
L
H
H
H
L
H
L
RA
RA
H
H
L
Activate Row
Precharge
I1Any0
A1Any0
A0Any1
I0I1
I0Any1
×
×
×
×
×
×
×
×
(R/W/A/I)0 (I/A)1
(R/W/A/I)1 (I/A)0
(R/W/A/I)1 (I/A)0
(I/A)1 (R/W/A/I)0
(R/W/A/I)0 (I/A)1
(I/A)0 (R/W/A/I)1
I0I1
×
I1I0
H
H
L
I1(I/A)0
I1(R/W/A/I)0
I0(I/A)1
I0(R/W/A/I)1
I0I1
L
L
L
L
L
L
L
L
L
L
H
L
×
×
Refresh
Op - Code
Mode Register Access
I0I1
I0I1
Remark H = High level, L = Low level, × = High or Low level (Don't care)
BA = Bank Address (A11)
20
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Notes 1. State abbreviations
I = Idle
A = Row active
R = Read with No precharge (No precharge is posted)
W = Write with No precharge (No precharge is posted)
RP = Read with auto precharge (Precharge is posted)
WP = Write with auto precharge (Precharge is posted)
Any = Any State
X0Y1 = Y1X0 = Bank A is in state “X”, Bank B is in state “Y”
(X/Y)0Z1 = Z1(X/Y)0 = Bank A is in state “X” or “Y”, Bank B is in state “Z”
3. If the µPD4516xxxA is in a state other than above listed in the “From State” column, the command is
illegal.
4. The states listed under “To” might not be entered on the next clock cycle.
Timing restrictions apply.
21
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After
the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
22
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A11 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
/CAS latency : A6 through A4
Wrap type : A3
: A11 through A7
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
23
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
7. Mode Register
11
0
10
0
9
0
8
0
7
1
6
6
6
5
4
4
4
3
2
2
2
1
0
0
0
JEDEC Standard Test Set (refresh counter test)
11
10
9
1
8
0
7
0
5
3
1
×
×
LTMODE
WT
BL
Burst Read and Single Write
(for Write Through Cache)
11
10
9
8
1
7
0
5
3
1
Use in future
11
10
9
8
1
7
1
6
5
4
3
2
1
0
×
×
×
V
V
V
V
V
V
V
Vender Specific
V = Valid
× = Don’t care
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
LTMODE
WT
BL
Mode Register Set
Bits2-0
000
001
010
011
100
101
110
111
WT = 0
WT = 1
1
1
2
2
4
4
Burst length
8
8
R
R
R
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
R
R
2
3
Latency
mode
R
R
R
R
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11
Mode Register Write
24
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
Sequential addressing sequence
Interleave addressing sequence
(decimal)
(column address A0, binary)
(decimal)
0
1
0, 1
0, 1
1, 0
1, 0
[Burst of Four]
Starting address
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
(column address A1 - A0, binary)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
[Burst of Eight]
Starting address
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
(column address A2 - A0, binary)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 512 (for 2M ×8
device), 1,024 (for 4M ×4 device), and 256 (for 1M ×16 device).
25
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
8. Address Bits of Bank-Select and Precharge
Select Bank A
“Activate” command
0
1
Row
A0
A1
A2
A3
A4
A5
A6
A7
A7
A8
A8
A9 A10 A11
A9 A10 A11
Select Bank B
“Activate” command
(Activate command)
A0
A1
A2
A3
A4
A5
A6
A10 A11
Result
(Precharge command)
0
0
1
0
1
Precharge Bank A
Precharge Bank B
Precharge All Banks
×
× : Don’t care
disables Auto-Precharge
(End of Burst)
0
1
enables Auto-Precharge
(End of Burst)
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11
(/CAS strobes)
enables Read/Write
commands for Bank A
0
1
enables Read/Write
commands for Bank B
Precharge for Bank A
Precharge for Bank B
Precharge for Both Banks
CLK
CLK
CLK
H
H
H
CKE
CKE
CKE
/CS
/RAS
/CAS
/WE
A10
/CS
/RAS
/CAS
/WE
A10
/CS
/RAS
/CAS
/WE
A10
A11
A11
A11
26
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
Burst length=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
PRE
Q3
READ
Command
Hi-Z
DQ
Q1
Q2
Q4
Q3
/CAS latency = 3
Command
READ
PRE
Q2
Hi-Z
DQ
Q1
Q4
(tRAS must be satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL
(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (MIN.) with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
–1
Write
2
3
+tDPL (MIN.)
+tDPL (MIN.)
–2
27
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
(tRAS must be satisfied)
Remark READA means Read with Auto precharge
28
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts one clock after the last data word input to the device (/CAS latency of
2 or 3).
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
/CAS latency = 3
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
(tRAS must be satisfied)
Remark WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
–1
Write
+1
2
3
–2
+1
29
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Command
READ A
READ B
Hi-Z
DQ
QA1
QB1
QB2
QB3
QB4
1cycle
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ
WRITE A WRITE B
Hi-Z
DA1
DB1
DB2
DB3
DB4
1cycle
30
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst length = 4
T8
T0
T1
T2
T3
T4
T5
T6
T7
CLK
/CAS latency = 2
Command
WRITE A
DA1
READ B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
WRITE A
DA1
READ B
Hi-Z
DQ
QB1
QB2
QB3
QB4
31
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQM
READ WRITE
Hi-Z
DQ
D1
D2
D3
D4
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Command
READ
WRITE
DQM
DQ
Q1
Q2
Q3
D1
WRITE
D1
D2
D3
Hi-Z is
necessary
/CAS latency = 3
Command
READ
DQM
DQ
Q1
Q2
D2
D3
Hi-Z is
necessary
32
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
BST
/CAS latency = 2
Hi-Z
DQ
Q1
Q2
Q1
Q3
/CAS latency = 3
Hi-Z
DQ
Q2
Q3
Remark BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
WRITE
BST
/CAS latency = 2, 3
Hi-Z
DQ
D1
D2
D3
D4
Remark BST: Burst stop command
33
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
34
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
WRITE
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
WRITE
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
35
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on any pin relative to GND
Short circuit output current
Power dissipation
Symbol
Condition
Rating
−0.5 to +4.6
−0.5 to +4.6
50
Unit
V
VCC, VCCQ
VT
IO
V
mA
W
PD
TA
Tstg
1
Operating ambient temperature
Storage temperature
0 to 70
°C
°C
−55 to + 125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC, VCCQ
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
2.0
VCC+0.3Note1
V
Low level input voltage
VIL
−0.3Note2
0
+0.8
V
Operating ambient temperature
TA
70
°C
Notes 1. VIH (MAX.) = VCC + 2.0 V (Pulse width ≤ 3 ns)
2. VIL (MIN.) = –2.0 V (Pulse width ≤ 3 ns)
Pin Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Condition
MIN. TYP. MAX. Unit
Input capacitance
A0 - A11
2.5
2.5
4
4
pF
CI2
CLK, CKE, /CS, /RAS, /CAS, /WE,
DQM, UDQM, LDQM
DQ0 - DQ15
Data input / output capacitance
CI/O
4
6
pF
36
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS Grade
latency
Maximum
×8
Unit Notes
×4
100
100
85
×16
110
110
95
Operating current
ICC1
Burst length = 1,
CL = 2
CL = 3
-80
-10
105
105
90
mA
1
tRC ≥ tRC (MIN.), Io = 0 mA,
One bank active
-10B
-12
85
90
95
-80
110
110
90
115
115
95
120
120
100
100
3
-10
-10B
-12
90
95
Precharge standby current
in power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
3
3
mA
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
2
2
2
Precharge standby current
in non power down mode
ICC2N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
25
25
25
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞,
6
6
6
Input signals are stable.
Active standby current
in power down mode
ICC3P
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
ICC3N
CKE ≤ VIL (MAX.), tCK = 15 ns
3
2
3
2
3
2
mA
mA
Active standby current
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
28
12
28
12
30
15
in non power down mode
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞,
Input signals are stable.
Operating current
(Burst mode)
ICC4
ICC5
ICC6
tCK ≥ tCK (MIN.), Io = 0 mA,
CL = 2
CL = 3
CL = 2
CL = 3
-80
-10
95
75
75
65
110
90
90
80
90
90
90
90
90
90
90
90
1
105
85
110
90
mA
2
Both banks active
-10B
-12
85
90
75
80
-80
120
100
100
90
125
105
105
95
-10
-10B
-12
CBR (auto) refresh current
tRC = 100 ns,
tCK = MIN.
-80
90
90
mA
3
-10
90
90
-10B
-12
90
90
90
90
-80
90
90
-10
90
90
-10B
-12
90
90
90
90
Self refresh current
CKE ≤ 0.2 V
-**
1
1
mA
-**L
250
250
250
µA
37
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
II (L)
Test condition
MIN.
TYP.
MAX.
+1.0
Unit
Note
Input leakage current
0 ≤ VI ≤ VCCQ, VCCQ = VCC
All other pins not under test = 0 V
0 ≤ VO ≤ VCCQ, DOUT is disabled
IO = −4 mA
−1.0
µA
Output leakage current
High level output voltage
Low level output voltage
IO (L)
VOH
VOL
−1.5
+1.5
0.4
µA
V
2.4
IO = +4 mA
V
38
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
Value
2.0 / 0.8
1.4
Unit
V
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
V
1
ns
V
Output timing measurement reference level
1.4
t
CK
t
CH
t
CL
2.0 V
CLK
1.4 V
0.8 V
t
Setup
t
Hold
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
39
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Synchronous Characteristics
Parameter
Symbol
-80
-10
-10B
-12
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
/CAS latency = 3 tCK3
/CAS latency = 2 tCK2
8
10
13
10
13
12
15
ns
ns
(125 MHz)
(100 MHz)
(100 MHz)
(83 MHz)
10
(100 MHz)
(77 MHz)
(77 MHz)
(67 MHz)
Access time from CLK
/CAS latency = 3 tAC3
6
6
6
8
7
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
/CAS latency = 2 tAC2
CLK high level width
CLK low level width
tCH
tCL
tOH
tLZ
3
3
3
0
3
3
2
1
2
1
2
1
3
3
3
0
3
3
2
1
2
1
2
1
3.5
3.5
3
4
4
Data-out hold time
3
1
Data-out low-impedance time
0
0
Data-out high-impedance time /CAS latency = 3 tHZ3
/CAS latency = 2 tHZ2
6
6
6
8
3
7
8
3
8
8
3
3
Data-in setup time
Data-in hold time
tDS
tDH
2.5
1
3
1.5
3
Address setup time
Address hold time
CKE setup time
tAS
2.5
1
tAH
1.5
3
tCKS
tCKH
tCKSP
tCMS
2.5
1
CKE hold time
1.5
CKE setup time (Power down exit)
2
2
2
2
2.5
2.5
3
3
ns
ns
Command (/CS, /RAS, /CAS, /WE, DQM)
setup time
Command (/CS, /RAS, /CAS, /WE, DQM)
hold time
tCMH
1
1
1
1.5
ns
Note 1. Output load
1.4 V
50 Ω
Z = 50 Ω
Output
50 pF
40
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
Asynchronous Characteristics
Parameter
Symbol
-80
-10
-10B
-12
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
70
48
20
20
16
8
70
50
20
20
20
10
90
60
26
26
20
10
90
60
30
30
24
12
ns
ns
ns
ns
ns
ns
120,000
120,000
120,000
120,000
PRE to ACT command period
Delay time ACT to READ/WRITE command
ACT (one) to ACT (another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
Data-in to ACT (REF)
command period
/CAS latency = 3 tDAL3 1CLK
1CLK
+20
1CLK
+26
1CLK
+30
ns
ns
+20
/CAS latency = 2 tDAL2 1CLK
+20
1CLK
+20
1CLK
+26
1CLK
+30
(Auto precharge)
Mode register set cycle time
Transition time
tRSC
tT
2
2
1
2
1
2
1
CLK
ns
0.5
30
32
64
30
32
64
30
32
64
30
32
64
Refresh time
-**
tREF
ms
(2,048 refresh cycles)
-**L
41
Data Sheet E0122N10
13.1 AC Parameters for Read Timing (Burst Length = 2, /CAS Latency = 2)
T0
tCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CLK
tCH
tCL
Auto precharge
Start for Bank B
CKE
/CS
tCKS
tCKH
tCMS tCMH
/RAS
/CAS
µ
µ
/WE
A11
A10
ADD
tAS tAH
L
DQM
DQ
tAC
tAC
tHZ
Hi-Z
tRCD
tLZ
tOH
tOH
tRAS
tRP
tRRD
tRC
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command Command
Bank B
Activate
Bank B
Read Command
with Auto precharge
Bank A
Activate
Command
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank B
t
CKH
t
CKS
t
CMS CMH
t
/RAS
/CAS
/WE
A11
µ
µ
A10
ADD
DQM
DQ
t
AS
t
AH
t
DS
t
DH
L
Hi-Z
t
RCD
t
RRD
t
DAL
t
DPL
t
RP
t
RC
µPD4516421A, 4516821A, 4516161A for Rev.P
13.3 Relationship between Frequency and Latency
Speed version
Clock cycle time [ns]
-80
-10
-10B
-12
8
125
3
10
100
2
10
100
3
13
77
2
10
100
3
13
77
2
12
83
3
15
67
2
Frequency [MHz]
/CAS latency
[tRCD]
3
2
2
2
3
2
3
2
/RAS latency (/CAS latency + [tRCD])
6
4
5
4
6
4
6
4
[tRC]
9
7
7
6
9
7
8
6
[tRAS]
[tRRD]
[tRP]
6
5
5
4
6
5
5
4
2
2
2
2
2
2
2
2
3
2
2
2
3
2
3
2
[tDPL]
[tDAL]
[tRSC]
1
1
1
1
1
1
1
1
4
3
3
3
4
3
4
3
2
2
2
2
2
2
2
2
44
Data Sheet E0122N10
13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
t
RSC
H
2CLK (MIN.)
/RAS
/CAS
/WE
A11
µ
µ
A10
ADDRESS KEY
ADD
DQM
DQ
Hi-Z
All Banks
Precharge
Command
Register
Write
Command
Activate
Command
is valid
t
RP
13.5 Power On Sequence and CBR (Auto) Refresh
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
Clock signal is necessary
High level is necessary
t
RSC
2 refresh cycles are necessary
/RAS
/CAS
/WE
A11
µ
µ
A10
ADDRESS KEY
ADD
DQM
DQ
High level is necessary
Hi-Z
All Banks
Precharge
Command
is necessary
Register
Write
Command
is necessary
Refresh
Command
is necessary
Refresh
Command
is necessary
Activate
Command
t
RP
t
RC
t
RC
13.6 /CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 3)
Only /CS signal needs to be issued at minimum rate
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
L
A10
RAa
ADD
DQM
DQ
RAa
CAa
CAb
L
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
L
QAa1 QAa2
QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Hi-Z
(turn off)
at end of burst
Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
L
QAa1 QAa2
QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Hi-Z
(turn off)
at end of burst
13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
L
DAa1
Write
DAa2
DAa3
DAa4
Activate
Command
for Bank A
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A11
µ
µ
RAa
RAa
A10
CAa
ADD
DQM
DQ
L
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Write
command
for Bank A
13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
t
CKSP
t
CKSP
VALID
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
L
QAa1 QAa2 QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
Power Down
Mode Entry
Power Down
Mode Entry
Power Down
Mode Exit
Clock Mask
Start
Clock Mask
End
Power Down
Mode Exit
ACTIVE STANDBY
PRECHARGE STANDBY
13.10 CBR (Auto) Refresh
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
ADD
DOQM
DQ
L
Q1
Precharge
Command
if necessary
CBR refresh
CBR refresh
Activate
Command
Read
Command
t
RP
t
RC
t
RC
13.11 Self Refresh (Entry and Exit)
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A11
µ
µ
A10
ADD
DOQM
DQ
L
Precharge
Command
if necessary
Self refresh
entry
Self refresh
Exit
Self refresh
entry
Self refresh
Exit
Activate
Command
or
(Activate
Command)
Next
clock
enable
Next clock
enable
t
RC
t
RP
t
RC
13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RAd
RAd
ADD
DQM
DQ
CAa
CAb
CAc
CAd
L
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RAa
ADD
DQM
DQ
RAa
CAa
CAb
CAc
CAa
L
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Activate Command
for Bank A
Read Command
for Bank A
Read Command
for Bank A
Precharge Command
for Bank A
Activate Command
for Bank A
Read Command
for Bank A
Read Command
for Bank A
13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RBa
RBa
RBd
RBd
ADD
DQM
DQ
CBa
CBb
CBc
CBd
L
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
DBd1 DBd2 DBd3 DBd4
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank B
Write
Command
for Bank B
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RBa
RBd
RBd
ADD
DQM
DQ
RBa
CBa
CBb
CBc
CBd
L
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
DBd1 DBd2
Activate Command
for Bank B
Write Command
for Bank B
Write Command
for Bank B
Precharge Command
for Bank B
Activate Command
for Bank B
Write Command
for BankB
Write Command
for Bank B
13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RBa
RBa
RAa
RAa
RBb
RBb
ADD
DQM
DQ
CBa
CAa
CBb
L
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank B
t
RCD
t
RP
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RBa
RBa
RAa
RAa
RBb
RBb
ADD
DOQM
DQ
CBa
CAa
CBb
L
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Precharge
Command Command
for Bank B for Bank A
t
RCD
t
RP
13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RAb
RAb
ADD
DQM
DQ
CAa
CBa
CAb
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Precharge
Command
for Bank A
Command
for Bank B
t
RCD
t
DPL
t
RP
t
DPL
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A11
µ
µ
RAa
RBa
RAb
A10
RAa
CAa
RBa
CBa
RAb
CAb
ADD
DQM
DQ
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Precharge
Command
for Bank A
Command
for Bank B
tRCD
tDPL
tRP
tDPL
13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
CAb
Write latency = 0
CAc
Word Masking
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
QAc4
Hi-Z
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Hi-Z at the end of wrap function
0-clock latency
2-clock latency
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
ADD
DQM
DQ
CAa
CAb
Write latency = 0
CAc
Word Masking
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
Hi-Z
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Hi-Z at the end of wrap function
0-clock latency
2-clock latency
13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CBb
CBc
CAb
CBd
L
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb1
Bb2
Bc1
Bc2
Ab1
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank B
Read
Command
for Bank B
Read
Command
for Bank B
Read
Command
for Bank A
Read
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
t
RCD
t
RRD
Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CBb
CBc
CAb
L
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb1
Bb2
Bc1
Bc2
Ab1
Ab2
Ab3
Ab4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank B
Read
Command
for Bank B
Read
Command
for Bank B
Read
Command
for Bank A
Activate
Command
for Bank B
Precharge
Command
for Bank B
Precharge
Command
for Bank A
t
RCD
t
RRD
13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CBb
CBc
Bc1
CAb
Ab1
CBd
Bd1
L
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb1
Bb2
Bc2
Ab2
Bd2
Bd3
Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Write
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
t
RCD
t
RRD
t
DPL
t
DPL
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CBb
Bb1
CBc
Bc1
CAb
Ab1
CBd
Bd1
L
Aa1
Aa2
Aa3
Aa4
Ba1
Ba2
Bb2
Bc2
Ab2
Bd2
Bd3
Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Write
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank B
Precharge
Command
for Bank A
t
RCD
t
RRD
t
DPL
t
DPL
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
RBb
RAc
RAc
ADD
DQM
DQ
CAa
CBa
CAb
CBb
CAc
L
Hi-Z
Activate Command
for Bank A
Activate
Command
for Bank B
Activate
Command
for Bank B
Activate
Command
for Bank A
Bank A
Read Command
with
Bank A
Bank B
Read Command with
Auto Precharge
Read Command without
Auto Precharge
Auto Precharge
Bank B
Bank A
Read Command
with
Auto Precharge
Start for Bank B
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank B
Read Command
with
Auto Precharge
Auto Precharge
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
RBb
ADD
DQM
DQ
CAa
CBa
CAb
CBb
L
Hi-Z
Activate Command
for Bank A
Activate
Command
for Bank B
Bank A
Read Command with
Auto Precharge
Bank B
Read Command with
Auto Precharge
Auto
Precharge
Start for
Bank A
Bank A
Read Command without
Auto Precharge
Bank B
Read Command with
Auto Precharge
Auto Precharge
Start for Bank B
Activate Command
for Bank B
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
RBb
RAc
RAc
ADD
DQM
DQ
CAa
CBa
CAb
CBb
CAc
L
Hi-Z
Activate Command
for Bank A
Activate
Command
for Bank B
Activate
Command
for Bank B
Activate
Command
for Bank A
Bank A
Write Command without
Auto Precharge
Bank B
Write Command with
Auto Precharge
Bank A
Write Command
with
Bank B
Write Command
with
Bank A
Write Command
with
Auto Precharge
Auto Precharge
Auto Precharge
Auto Precharge
Start for Bank B
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank B
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
RBb
ADD
DQM
DQ
CAa
CBa
CAb
CBb
L
Hi-Z
Activate Command
for Bank A
Activate
Command
for Bank B
Bank A
Write Command
with
Activate
Command
for Bank B
Bank B
Write Command
with
Auto Precharge
Bank A
Bank B
Write Command without
Auto Precharge
Write Command with
Auto Precharge
Auto Precharge
Auto Precharge
Start for Bank B
Auto Precharge
Start for Bank A
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
ADD
DQM
DQ
CAa
CBa
RBb
L
Hi-Z
Aa
Aa+1 Aa+2 Aa–2 Aa–1
Aa
Aa+1
Ba
Ba+1 Ba+2 Ba+3 Ba+4 Ba+5 Ba+6
Read
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank B
Activate
Command
for Bank B
Burst stop
Command
Full Page Read Cycle (2/2) (/CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
ADD
DQM
DQ
CAa
CBa
RBb
L
Hi-Z
Aa
Aa+1
Aa–3 Aa–2 Aa–1
Aa
Aa+1
Ba
Ba+1 Ba+2 Ba+3 Ba+4 Ba+5
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank B
Burst stop
Command
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
ADD
DQM
DQ
CAa
Aa
CBa
RBb
L
Hi-Z
Aa+1 Aa+2
Aa–2 Aa–1
Aa
Aa+1
Ba
Ba+1 Ba+2 Ba+3 Ba+4 Ba+5
Write
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Activate
Command
for Bank B
Burst stop
Command
Full Page Write Cycle (2/2) (/CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
RBb
RBb
ADD
DQM
DQ
CAa
Aa
CBa
Ba
L
Hi-Z
Aa+1 Aa+2 Aa+3 Aa–1
Aa
Aa+1
Ba+1 Ba+2 Ba+3 Ba+4
Write
Command
for Bank B
Precharge
Command
for Bank B
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Activate
Command
for Bank B
Burst stop
Command
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
/CAS
µ
µ
/WE
A11
A10
ADD
LDQM
UDQM
DQ lower
DQ upper
Activate
Command
Read
Command
U-byte
not Read
L-byte
not Read
L-byte
not Write
U-byte
not Write
L-byte
not Read
L-byte
not Read
L-byte
not Write
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
/CAS
µ
µ
/WE
A11
A10
ADD
LDQM
UDQM
DQ lower
DQ upper
Activate
Command
Read
Command
Single
Write
Single
Write
Read
Command
Single
Write
Command
Command
Command
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CAb
CBb
CAc
CBc
t
RCD
t
RRD
t
RCD
L
Hi-Z
QAa1 QBa1 QAb1 QAb2 QBb1 QBb2 QAc1 QAc2 QAc3 QBc1 QBc2 QBc3
Activate
Command
for Bank A
Activate
Command
for Bank B
Precharge Command
for Bank B
(PRE Termination)
Read
Command
for Bank A
Read
Command
for Bank B
Read
Command
for Bank A
Read
Command
for Bank B
Read
Command
for Bank A
Read
Command
for Bank B
13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11
µ
µ
A10
RAa
RAa
RBa
RBa
ADD
DQM
DQ
CAa
CBa
CAb
CBb
CAc
CBc
t
RCD
t
RRD
t
RCD
L
DAa1 DBa1 DAb1 DAb2 DBb1 DBb2 DAc1 DAc2 DAc3 DBc1 DBc2 DBc3 DBc4
Activate
Command
for Bank A
Activate
Command
for Bank B
Precharge Command
for Bank B
(PRE Termination)
Write
Write
Command
for Bank A
Write
Command
for Bank B
Write
Command
for Bank A
Write
Command
for Bank B
Command
for Bank A
Write
Command
for Bank B
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A11
µ
µ
RAa
RAa
RAb
RAb
A10
CAa
CAb
ADD
DQM
DQ
L
Write
Masking
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4 QAb5
Activate
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Command
Termination
PRE Command
Termination
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A11
µ
µ
RAa
RAa
RAb
A10
CAa
RAb
CAb
ADD
DQM
DQ
L
Write
Masking
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4
Activate
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Bank A
Precharge Command
Activate
Command
for Bank A
Bank A
Precharge Command
PRE Command
Termination
PRE Command
Termination
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
µPD4516421A, 4516821A, 4516161A for Rev.P
14. Package Drawings
44-PIN PLASTIC TSOP(II) (10.16 mm (400))
44
23
detail of lead end
S
T
R
L
Q
1
22
U
2
A
H
I
J
S
G
N
S
C
B
K
M
D
M
NOTES
1. Each lead centerline is located within 0.13 mm of
ITEM MILLIMETERS
A
B
C
18.32±0.04
0.905 MAX.
0.8 (T.P.)
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
+0.08
0.32
D
−0.07
G
H
I
1.0±0.05
11.76±0.2
10.11±0.04
0.825±0.2
J
+0.025
0.145
K
−0.015
L
M
N
Q
0.5
0.13
0.10
0.1±0.05
+5°
3°
R
−3°
S
T
1.2 MAX.
0.25 (T.P.)
U
0.60±0.15
S44G5-80-9NF-1
83
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
50-PIN PLASTIC TSOP(II) (10.16 mm (400))
50
26
detail of lead end
S
T
R
L
Q
1
25
U
2
A
H
I
J
S
G
N
S
C
B
K
M
D
M
NOTES
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
20.86±0.04
1.0 MAX.
0.8 (T.P.)
2. Dimension “A” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
+0.08
0.32
D
−0.07
G
H
I
1.0±0.05
11.76±0.2
10.11±0.04
0.825±0.2
J
+0.025
0.145
K
−0.015
L
M
N
Q
0.5
0.13
0.10
0.1±0.05
+5°
3°
R
−3°
S
T
1.2 MAX.
0.25 (T.P.)
U
0.60±0.15
S50G5-80-9NF-1
84
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
15. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4516xxxA.
Type of Surface Mount Device
µPD4516421AG5-9NF : 44-pin Plastic TSOP (II) (10.16mm (400))
µPD4516821AG5-9NF : 44-pin Plastic TSOP (II) (10.16mm (400))
µPD4516161AG5-9NF : 50-pin Plastic TSOP (II) (10.16mm (400))
85
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
16. Revision History
Edition /
Date
Page
Description
This
Previous
edition
Type of
Location
edition
revision
NEC Corporation (M12939E)
3rd edition /
Apr. 1998
–
–
–
–
–
Elpida Memory, Inc. (E0122N)
1st edition /
May. 2001
–
–
Republished by Elpida Memory, Inc.
86
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
87
Data Sheet E0122N10
µPD4516421A, 4516821A, 4516161A for Rev.P
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M02 01. 2
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