EKTF5832SS28 [ELAN]
8-Bit Microcontroller;
| 型号： | EKTF5832SS28 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总112页 (文件大小：3864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
eKTF5832
8-Bit
Microcontroller
IC Product
Specification
DOC. VERSION 0.4
ELAN MICROELECTRONICS CORP.
September 2019
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2019 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
ELAN (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
ELAN Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
Shenzhen:
Shanghai:
ELAN Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
General Description ......................................................................................1
Features .........................................................................................................1
Pin Assignment..............................................................................................2
3.1 Package: QFN 32 .............................................................................................2
4
Pin Description ..............................................................................................5
4.1 eKTF5832 Kernel Pin........................................................................................5
5
6
Functional Block Diagram ............................................................................9
Functional Description................................................................................10
6.1 Operational Registers .....................................................................................10
6.1.1 R0: IAR (Indirect Addressing Register) .............................................................10
6.1.2 R1: BSR (Bank Selection Control Register)......................................................10
6.1.3 R2: PCL (Program Counter Low) ......................................................................11
6.1.4 R3: SR (Status Register)...................................................................................16
6.1.5 R4: RSR (RAM Select Register) .......................................................................17
6.1.6 Bank 0 R5 ~ R8: (Port 5 ~ Port 8).....................................................................17
6.1.7 Bank 0 R9 ~ RA: (Reserved).............................................................................17
6.1.8 Bank 0 RB~RD: (IOCR5 ~ IOCR7) ...................................................................17
6.1.9 Bank 0 RE: OMCR (Operating Mode Control Register)....................................17
6.1.10 Bank 0 RF: EIESCR (External Interrupt Edge Select Control Register) ...........19
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1) ........................................20
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2).........................................20
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3) ........................................21
6.1.14 Bank 0 R13: (Reserved)....................................................................................22
6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1) .....................................................22
6.1.16 Bank 0 R15: (Reserved)....................................................................................22
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3) .....................................................22
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4) .....................................................23
6.1.19 Bank 0 R18: (Reserved)....................................................................................23
6.1.20 Bank 0 R19: SFR6 (Status Flag Register 6) ......................................................23
6.1.21 Bank 0 R1A: (Reserved) ...................................................................................24
6.1.22 Bank 0 R1B: IMR1 (Interrupt Mask Register 1) ................................................24
6.1.23 Bank 0 R1C: (Reserved) ...................................................................................25
6.1.24 Bank 0 R1D: IMR3 (Interrupt Mask Register 3) ................................................25
6.1.23 Bank 0 R1E: IMR4 (Interrupt Mask Register 4) ................................................26
6.1.24 Bank 0 R1F: (Reserved) ...................................................................................26
6.1.24 Bank 0 R20: IMR6 (Interrupt Mask Register 6).................................................26
6.1.25 Bank 0 R21: WDTCR (Watchdog Timer Control Register) ...............................27
IC Product Specification (V0.4) 09.09.2019
iii
Contents
6.1.26 Bank 0 R22: TCCCR (TCC Control Register)...................................................28
6.1.27 Bank 0 R23: TCCD (TCC Data Register)..........................................................29
6.1.28 Bank 0 R24 ~ R2F: (Reserved).........................................................................29
6.1.29 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1) ...............................29
6.1.30 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2) ...............................30
6.1.31 Bank 0 R32: I2CSA (I2C Slave Address Register)............................................31
6.1.32 Bank 0 R33: I2CDB (I2C Data Buffer Register) ................................................31
6.1.33 Bank 0 R34: I2CDAL (I2C Device Address Register) .......................................32
6.1.34 Bank 0 R35: I2CDAH (I2C Device Address Register).......................................32
6.1.35 Bank 0 R36: SPICR (SPI Control Register) ......................................................32
6.1.36 Bank 0 R37: SPIS (SPI Status Register) ..........................................................33
6.1.37 Bank 0 R38: SPIR (SPI Read Buffer Register) .................................................34
6.1.38 Bank 0 R39: SPIW (SPI Write Buffer Register).................................................34
6.1.39 Bank 0 R3A ~ R4F: (Reserved).........................................................................34
6.1.40 Bank 1 R5: IOCR8.............................................................................................34
6.1.41 Bank 1 R6 ~ R7: (Reserved).............................................................................34
6.1.42 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)..................................35
6.1.43 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)..................................35
6.1.44 Bank 1 RA: P78PHCR (Ports 7~8 Pull-high Control Register) .........................36
6.1.45 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register) ...................................36
6.1.46 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register)...................................37
6.1.47 Bank 1 RD: P78PLCR (Ports 7~8 Pull-low Control Register)...........................37
6.1.48 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control Register)....................38
6.1.49 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control Register)....................38
6.1.50 Bank 1 R10: P78HDSCR (Port 7~8 High Drive/Sink Control Register)............38
6.1.51 Bank 1 R11: P5ODCR (Port 5 Open-Drain Control Register)...........................39
6.1.52 Bank 1 R12: P6ODCR (Port 6 Open-Drain Control Register)...........................39
6.1.53 Bank 1 R13: P78ODCR (Ports 7~8 Open-Drain Control Register)...................39
6.1.54 Bank 1 R14 ~ R15: (Reserved).........................................................................39
6.1.55 Bank 1 R16: PWMSCR (PWM Source Clock Control Register) .......................40
6.1.56 Bank 1 R17: PWMACR (PWM1 Control Register)............................................40
6.1.57 Bank 1 R18: PRDAL (Low Byte of PWMA Period)............................................41
6.1.58 Bank 1 R19: PRDAH (High Byte of PWMA Period) ..........................................41
6.1.59 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)..................................................41
6.1.60 Bank 1 R1B: DTAH (High Byte of PMWA Duty) ................................................42
6.1.61 Bank 1 R1C: TMRAL (Low Byte of Timer 1)......................................................42
6.1.62 Bank 1 R1D: TMRAH (High Byte of Timer 1)....................................................42
6.1.63 Bank 1 R1E: PWMBCR (PWMB Control Register)...........................................42
6.1.64 Bank 1 R1F: PRDBL (Low Byte of PWMB Period) ...........................................43
6.1.65 Bank 1 R20: PRDBH (High Byte of PWMB Period) ..........................................43
6.1.66 Bank 1 R21: DTBL (Low Byte of PMWB Duty) .................................................43
6.1.67 Bank 1 R22: DTBH (High Byte of PMW2 Duty) ................................................44
6.1.68 Bank 1 R23: TMRBL (Low Byte of Timer B)......................................................44
6.1.69 Bank 1 R24: TMRBH (High Byte of Timer 2).....................................................44
6.1.70 Bank 1 R25: PWMCCR (PWMC Control Register)...........................................44
6.1.71 Bank 1 R26: PRDCL (Low byte of PWMC Period)............................................45
iv
IC Product Specification (V0.4) 09.09.2019
Contents
6.1.72 Bank 1 R27: PRDCH (High Byte of PWMC Period)..........................................45
6.1.73 Bank 1 R28: DTCL (Low Byte of PMWC Duty).................................................45
6.1.74 Bank 1 R29: DTCH (High Byte of PMWC Duty) ...............................................46
6.1.75 Bank 1 R2A: TMRCL (Low byte of Timer C) .....................................................46
6.1.76 Bank 1 R2B: TMRCH (High byte of Timer C)....................................................46
6.1.77 Bank 1 R2C ~ R44: (Reserved) ........................................................................46
6.1.78 Bank 1 R45: TBPTL (Table Point Low Register) ...............................................46
6.1.79 Bank 1 R46: TBPTH (Table Point High Register) .............................................46
6.1.80 Bank 1 R47: STKMON (Stack Pointer) .............................................................47
6.1.81 Bank 1 R48: PCH (Program Counter High) ......................................................47
6.1.82 Bank 1 R49: LVDCR (Low Voltage Detector Control Register).........................47
6.1.83 Bank 1 R4A~ R4F: (Reserved) .........................................................................48
6.1.84 Bank 2 R5 ~ R46: (Reserved)...........................................................................48
6.1.85 Bank 2 R47: DACR (DAC Control Register) .....................................................48
6.1.86 Bank 2 R48: DACD (Digital to Analog Converter Data Buffer)..........................48
6.1.87 Bank 2 R49 ~ R4F: (Reserved).........................................................................48
6.1.88 R50~R7F, Banks 0~3 R80~RFF .......................................................................48
6.2 TCC/WDT and Prescaler ................................................................................49
6.3 I/O Ports .........................................................................................................50
6.3.1 Usage of Ports 5~8 Input Change Wake-up/Interrupt Function........................52
6.4 Reset and Wake-up ........................................................................................53
6.4.1 Summary of Wake-up and Interrupt Mode Operation ..........................................54
6.4.2 The Status of RST, T, and P of the Status Register ..........................................56
6.4.3 Summary of Register Initial Values after Reset.................................................57
6.5 Interrupt ..........................................................................................................66
6.6 Dual Set of PWM (Pulse Width Modulation)....................................................68
6.6.1 Overview ...........................................................................................................68
6.6.2 Control Register ................................................................................................69
6.6.3 Increment Timer Counter (TMRX: TMRxH/TMRxL)..........................................70
6.6.4 PWM Time Period (PRDX: PRDxL/H)...............................................................70
6.6.5 PWM Duty Cycle (DTX: DTxH/DT1L) ..............................................................71
6.6.6 PWM Programming Process/Steps...................................................................71
6.7 SPI (Serial Peripheral Interface) .....................................................................72
6.7.1 Overview and Features .....................................................................................72
6.7.2 SPI Function Description...................................................................................74
6.7.3 SPI Signal and Pin Description .........................................................................75
6.7.4 SPI Mode Timing...............................................................................................77
6.8 I2C Function....................................................................................................78
6.8.1 7-Bit Slave Address...........................................................................................80
6.8.2 10-Bit Slave Address.........................................................................................81
6.8.3 Master Mode .....................................................................................................84
6.8.4 Slave Mode I2C Transmit..................................................................................84
6.9 Oscillator.........................................................................................................85
6.9.1 Oscillator Modes................................................................................................85
IC Product Specification (V0.4) 09.09. 2019
v
Contents
6.9.2 Internal RC Oscillator Mode ..............................................................................85
6.10 Power-On Considerations...............................................................................86
6.11 External Power-on Reset Circuit.....................................................................86
6.12 Residue-Voltage Protection.............................................................................86
6.13 Code Option ...................................................................................................88
6.13.1 Code Option Register (Word 0).........................................................................88
6.13.2 Code Option Register (Word 1).........................................................................89
6.13.3 Code Option Register (Word 2).........................................................................90
6.13.4 Code Option Register (Word 3).........................................................................92
6.14 Instruction Set.................................................................................................92
Absolute Maximum Ratings........................................................................96
DC Electrical Characteristics......................................................................96
AC Electrical Characteristics......................................................................98
7
8
9
APPENDIX
A
B
Package Type...............................................................................................99
Package Information .................................................................................100
B.1 eKTF5832QN32............................................................................................100
B.2 eKTF5832QN24............................................................................................101
B.3 eKTF5832SO28............................................................................................102
B.4 eKTF5832SS28 ............................................................................................103
B.5 eKTF5832SO24............................................................................................104
C
Ordering and Manufacturing Information................................................105
Specification Revision History
Version
Revision Description
Date
0.1
2015/01/13
Initial Release Version
0.2
0.3
0.4
2015/03/24
2016/03/24
2019/09/09
Updated the format and corrected the error content
Modified the package information
Added some package type
vi
IC Product Specification (V0.4) 09.09.2019
eKTF5832
8-Bit Microcontroller
1 General Description
The eKTF5832 is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. It has a built-in 12K16-bit programmable ROM and is equipped with touch
sensors. The capacitive touchkey sensor uses plastic or glass substrate as cover.
The system controller converts fingertip position data into button presses, depending on finger location
and human interface context. The eKTF5832 OCD can be used to develop user program for this
microcontroller and several other ELAN Flash type ICs.
2 Features
CPU configuration
Peripheral configuration
Supports 12K16 bits program ROM
(48+1024) bytes general purpose register.
16-level stacks for subroutine nesting
Typical 1 A, during sleep mode
3 programmable Level Volt Reset
LVR: 3.5V, 2.8V, 2.4V
1 sets of 4 programmable Level Voltage Detector
LVD: 4V, 3.2V, 2.8V, 2.5V
Four CPU operation modes (Normal, Green, Idle,
8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow
interrupt
Three Pulse Width Modulation (PWMA, PWMB,
PWMC) with 16-bit resolution shared with Timers
A,B and C
Provide the 24 sensor pins.
1-channel Digital-to-Analog converter for 256 steps
Sleep)
Serial transmitter/receiver interface (SPI): 3-wire
I/O port configuration
synchronous communication
I2C function with 7/10 bits address and 8 bits data
Independent I/O_VDD for VOH and VIH/VIL
4 bidirectional I/O ports: P5 ~ P8
4 programmable pin change wake-up ports:
P5~P8
4 programmable pull-down I/O ports: P5~P8
4 programmable pull-high I/O ports: P5~P8
4 programmable open-drain I/O ports: P5~P8
4 programmable high-sink/drive I/O ports: P5~P8
transmit/receive mode
Power down (Sleep) mode
Idle with scan mode
15 available interrupts: (2 external, 13 internal)
External interrupt: INT0, INT1
TCC overflow interrupt
Operating voltage range:
2.8V~5.5V with IC LDO at -40 C~85 C (industrial)
Input-port status changed interrupt (wake up from
Operating frequency range (base on two clocks):
sleep mode)
Main oscillator:
PWMA, PWMB, PWMC period match completion
I2C transfer/receive/stop interrupt
SPI interrupt
IRC mode:
DC ~ 16 MHz at 3V; DC ~ 8 MHz at 2V
Drift Rate
LVD interrupt
Internal RC
Voltage
Temperature
Frequency
System hold interrupt
Process Total
(-40℃~+85℃)
(2.8V~5.5V)
Single instruction cycle commands
Package Type:
1 MHz
4 MHz
6 MHz
8 MHz
12 MHz
16 MHz
±2%
±2%
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
±4%
±4%
32 QFN(5x5x0.8mm)
24 QFN(4x4x0.8mm)
28 SOP(300mil)
:
:
:
eKTF5832QN32
eKTF5832QN24
eKTF5832SO28
28 SSOP(209mil)
24 SOP(300mil)
: eKTF5832SS28
eKTF5832SO24
:
Sub oscillator:
IRC mode: 16K/32K
Note: These are all Green products which do not
contain hazardous substances.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
1
eKTF5832
8-Bit Microcontroller
3 Pin Assignment
3.1 Package: QFN 32
33 32 31 30 29 28
27 26 25
TPS16/P67
TPS15/P66
TPS14/P65
TPS13/P64
TPS12/P63
TPS11/P62
TPS10/P61
TPS9/P60
TPC
VDD
24
23
22
1
2
3
IO_VDD
SDA0/P70
4
5
21
20
19
eKTF5832QN32
SCL0/P71
/RESET/P72
6
2W_DATA/SDA1/INT0/P73
2W_CLK/SCL1/OSCO/INT1/P74
18
17
7
8
9
10 11 12 13 14
15 16
Figure 3-1 QFN-32 Pin Assignment
2
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
20
25 24 23 22 21
19
TPS18/SO/P81
1
TPC
VDD
18
2
3
TPS17/SCK/P80
TPS12/P63
17
16
15
IO_VDD
eKTF5832QN24
TPS11/P62
TPS10/P61
TPS9/P60
SDA0/P70
SCL0/P71
/RESET/P72
4
5
14
13
6
7
8
9
10 11 12
Figure 3-2 QFN-24 Pin Assignment
1
2
3
4
5
6
7
28
27
26
25
24
23
TPC
VDD
TPS24/PWMC/P87
TPS23/PWMB/P86
TPS22/PWMA/P85
TPS21/DAC/P84
VSS
SDA0/P70
SCL0/P71
TPS20//SS/P83
TPS19/SI/P82
/RESET/P72
eKTF5832
SO28/SS28
22 TPS18/SO/P81
2W_DATA/SDA1/INT0/P73
TPS17/SCK/P80
21
8
9
2W_CLK/SCL1/OSCO/INT1/P74
TPS1/TPD1/P50
20
TPS12/P63
19 TPS11/P62
TPS10/P61
TPS2/TPD2/P51 10
11
TPS3/P52
18
17 TPS9/P60
12
13
TPS4/P53
TPS5/P54
TPS6/P55
16
15
TPS8/P57
TPS7/P56
14
Figure 3-3 SOP-28/SSOP-28 Pin Assignment
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
3
eKTF5832
8-Bit Microcontroller
1
2
3
4
5
6
7
24
23
22
21
20
19
TKC
VDD
TPS24/PWMC/P87
TPS23/PWMB/P86
TPS22/PWMA/P85
TPS21/DAC/P84
VSS
SDA0/P70
SCL0/P71
/RESET/P72
TPS20//SS/P83
TPS19/SI/P82
eKTF5832SO24
18 TPS18/SO/P81
2W_DATA/SDA1/INT0/P73
TPS17/SCK/P80
17
8
9
2W_CLK/SCL1/OSCO/INT1/P74
TPS1/TPD1/P50
16
TPS12/P63
15 TPS11/P62
TPS2/TPD2/P51 10
11
12
TPS3/P52
TPS4/P53
TPS10/P61
TPS9/P60
14
13
Figure 3-4 SOP-24 Pin Assignment
4
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
4 Pin Description
4.1 eKTF5832 Kernel Pin
Output
Type
Name
Function Input Type
Description
VDD
VDD
TK VDD
I/O VDD
VSS
Power
Power
Power
Power
AN
Kernel Power
TK Power
AVDD
IO_VDD
VSS
I/O Power (IOH, VIH, VIL)
Ground
TPC
TPC
Touch key external Capacitor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P50
ST
CMOS
P50/TPS1/AS1
P51/TPS2/AS2
TPS1
AS1
AN
AN
TPS1 is a Touch Key Sensor pin
Active Shielding pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P51
ST
CMOS
TPS2
AS2
AN
AN
TPS2 is a Touch Key Sensor pin
Active Shielding pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P52
TPS3
P53
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
CMOS
P52/TPS3
P53/TPS4
P54/TPS5
P55/TPS6
P56/TPS7
TPS3 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS4
P54
TPS4 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS5
P55
TPS5 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS6
P56
TPS6 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS7
TPS7 is a Touch Key Sensor pin
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
5
eKTF5832
8-Bit Microcontroller
Output
Type
Name
Function Input Type
Description
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P57
TPS8
P60
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
ST
CMOS
P57/TPS8
TPS8 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
P60/TPS9
P61/TPS10
P62/TPS11
P63/TPS12
P64/TPS13
P65/TPS14
P66/TPS15
P67/TPS16
P70/SDA0
TPS9
P61
TPS9 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS10
P62
TPS10 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS11
P63
TPS11 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS12
P64
TPS12 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS13
P65
TPS13 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS14
P66
TPS14 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS15
P67
TPS15 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TPS16
P70
TPS16 is a Touch Key Sensor pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
CMOS
I2C serial data line. It is open-drain
SDA0
6
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Output
Type
Name
Function Input Type
Description
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P71
ST
CMOS
P71/SCL0
I2C serial clock line. It is open-drain.
CMOS
SCL0
P72
ST
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain
P72//RESET
/RESET
P73
ST
Internal pull-high reset pin
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain
I2C serial data line. It is open-drain
CMOS
SDA1
INT0
ST
ST
ST
P73/SDA1/INT0
/2W_DATA
External interrupt pin
2W_DATA
CMOS
OCD data line
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain
P74
I2C serial clock line. It is open-drain.
Clock output of internal RC oscillator
External interrupt pin
CMOS
CMOS
SCL1
OSCO
INT1
ST
P74/SCL1OSCO/I
NT1
/2W_CLK
ST
ST
2W_CLK
CMOS
OCD clock line
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P80
ST
CMOS
P80/TPS17/SCK
P81/TPS18/SO
P82/TPS19/SI
P83/TPS20//SS
TPS17
SCK
AN
ST
TPS17 is a Touch Key Sensor pin
SPI serial clock input/output
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P81
ST
CMOS
TPS18
SO
AN
TPS18 is a Touch Key Sensor pin
SPI serial data output
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P82
ST
CMOS
TPS19
SI
AN
ST
TPS19 is a Touch Key Sensor pin
SPI serial data input
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P83
ST
CMOS
TPS20
/SS
AN
ST
TPS20 is a Touch Key Sensor pin
SPI slave mode enable
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
7
eKTF5832
8-Bit Microcontroller
Output
Type
Name
Function Input Type
Description
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P84
ST
CMOS
P84/TPS21/DAC
TPS21
DAC
AN
AN
TPS21 is a Touch Key Sensor pin
Digital to Analog Converter PIN
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P85
ST
CMOS
P85/TPS22/PWMA
P86/TPS23/PWMB
P87/TPS24/PWMC
TPS22
PWMA
AN
TPS22 is a Touch Key Sensor pin
PWMA output
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P86
ST
CMOS
TPS23
PWMB
AN
TPS23 is a Touch Key Sensor pin
PWMB output
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P87
ST
CMOS
TPS24
PWMC
AN
TPS24 is a Touch Key Sensor pin
PWMC output
CMOS
Note: OCD: On Chip Debug system
8
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
5 Functional Block Diagram
Internal RC
Flash ROM
PC
OscillatorGenerator
16-level
Stack
Instruction
Register
WDT
P8
TCC
TCC
P87
P86
P85
P84
P83
P82
P81
P80
Reset
PWMA
PWMA
Instruction
Decoder
PWMB
PWMC
PWMB
PWMC
MUX
RAM
P7
ALU
P74
R4
P73
P72
P71
P70
LVD
LVR
P6
P67
P66
P65
P64
P63
P62
P61
P60
Interrupt
Control
Register
Status
Register
ACC
P5
Interrupt
Circuit
P57
P56
P55
P54
Touch
I2C
SPI
DAC
DAC
P53
P52
P51
P50
SO,SI
SCK
Ext
INT0,INT1
SCL0, SCL1
SDA0, SDA1
TPC
TPD1~TPD2
TPS1~TPS24
Figure 5-1 eKTF5832 Functional Block Diagram
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
9
eKTF5832
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0: IAR (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
6.1.2 R1: BSR (Bank Selection Control Register)
Bit 7
Bit 6
Bit 5
SBS1
R/W
Bit 4
SBS0
R/W
Bit 3
Bit 2
GBS2
R/W
Bit 1
GBS1
R/W
Bit 0
GBS0
R/W
-
-
-
-
-
0
Bits 7~6: Not used. Set to “0” all the time.
Bits 5~4 (SBS1~SBS0): Special register bank select bit. It is used to select Banks
0/1/2 of Special Registers R5~R4F.
SBS1
SBS0
Special Register Bank
0
0
1
1
0
1
0
1
0
1
2
X
Bit 3:
Not used. Set to “0” all the time.
Bits 2~0 (GBS2~GBS0): General register bank select bit. It is used to select
Banks 0~7 of General Registers R80~RFF.
GBS2
GBS1
GBS0
RAM Bank
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
10
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.3 R2: PCL (Program Counter Low)
Bit 7
PC7
R/W
Bit 6
PC6
R/W
Bit 5
PC5
R/W
Bit 4
PC4
R/W
Bit 3
PC3
R/W
Bit 2
PC2
R/W
Bit 1
PC1
R/W
Bit 0
PC0
R/W
Bits 7~0 (PC7~PC0): The low byte of program counter.
Depending on the device type, R2 and hardware stack are 16-bits wide. The
structure is depicted in Figure 6-1 Program Counter Organization.
Generating 12K16 bits on-chip Flash ROM addresses to the relative programming
instruction codes. One program page is 4096 words long.
R2 is set as all "0"s when under RESET condition.
"JMP" instruction allows direct loading of the lower 12 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
"CALL" instruction loads the lower 12 bits of the PC, and the present PC value will
add 1 and is pushed into the stack. Thus, the subroutine entry address can be
located anywhere within a page.
"LJMP" instruction allows direct loading of the lower 14 program counter bits.
Therefore, "LJMP" allows PC to jump to any location within 12K (214).
"LCALL" instruction loads the lower 14 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within 12K
(214).
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of
the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and above bits of the PC won’t be changed.
Any instruction except “ADD R2,A” that is written to R2 (e.g. "MOV R2, A", "BC R2,
6",“INC R2”,) will cause the ninth bit and the above bits (PC8~PC12) of the PC not
change.
All instructions are single instruction cycle (Fsys/2) except “LCALL”, “CALL”, “LJMP”
and “JMP” instructions. The “LCALL” and “LJMP” instructions need two instruction
cycles.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
11
eKTF5832
8-Bit Microcontroller
A 13 ~ A 0
PC
Reset vector
INT interrupt vector
pin change interrupt vector
TCC interrupt vector
LVDinterrupt vector
SPI interrupt vector
PWMPAinterrupt vector
0000h
0002h
0004h
0006h
0008h
000Ch
0014h
STACK LEVEL1
STACK LEVEL2
STACK LEVEL3
STACK LEVEL4
STACK LEVEL5
STACK LEVEL6
STACK LEVEL7
STACK LEVEL8
STACK LEVEL9
PWMDA interrupt vector
I2C Tx interrupt vector
I2C Rxinterrupt vector
I2Cstopinterrupt vector
PWMPBinterrupt vector
PWMDB interrupt vector
PWMPC interrupt vector
0016h
001Ah
001Ch
001Eh
0024h
0026h
002Ah
PWMDC interrupt vector
System hold interrupt vector
002Ch
003Ah
STACK LEVEL10
STACK LEVEL11
STACK LEVEL12
STACK LEVEL13
STACK LEVEL14
STACK LEVEL15
STACK LEVEL16
On-Chip Program memory
2FFFh
Figure 6-1 eKTF5832 Program Counter Organization
12
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Data Memory Configuration
BANK 0
Address
0X00
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X08
0X09
0X0A
0x0B
0X0C
0X0D
BANK 1
IAR (Indirect Addressing Reg.)
BSR (Bank Selection Control Reg.)
PCL (Program Counter Low)
SR (Status Reg.)
RSR (RAM Selection Reg.)
IOCR8
Port 5
Port 6
Port 7
Port 8
Unused
Unused
P5PHCR
P6PHCR
Unused
Unused
IOCR5
IOCR6
P78PHCR
P5PLCR
P6PLCR
P78PLCR
IOCR7
OMCR (Operating Mode
Control Register)
EIESCR (External
Interrupt Edge Selection
Control Register)
0X0E
0X0F
P5HDSCR
P6HDSCR
0X10
0X11
0X12
0X13
WUCR1
WUCR2
P789AHDSCR
P5ODCR
P6ODCR
WUCR3
Unused
P78ODCR
SFR1 (Status Flag
Register 1)
0X14
0X15
0X16
Unused
Unused
Unused
SFR3 (Status Flag
Register 3)
PWMSCR
SFR4 (Status Flag
Register 4)
0X17
0X18
0X19
0X1A
0X1B
0X1C
0X1D
PWMACR
PRDAL
PRDAH
DTAL
Unused
SFR6 (Status Flag
Register 6)
Unused
IMR1 (Interrupt Mask
Register 1)
DTAH
TMRAL
TMRAH
Unused
IMR3 (Interrupt Mask
Register 3)
IMR4 (Interrupt Mask
Register 4)
0X1E
0X1F
0X20
PWMBCR
PRDBL
Unused
IMR6 (Interrupt Mask
Register 6)
PRDBH
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
13
eKTF5832
8-Bit Microcontroller
0X21
0X22
0X23
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0x2B
0X2C
0X2D
0X2E
0X2F
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3A
0x3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0X42
0X43
0X44
0X45
0X46
DTBL
DTBH
WDTCR
TCCCR
TCCD
TMRBL
TMRBH
PWMCCR
PRDCL
PRDCH
DTCL
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
I2CCR1
I2CCR2
I2CSA
DTCH
TMRCL
TMRCH
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TBPTL
I2CDB
I2CDAL
I2CDAH
SPICR
SPIS
SPIR
SPIW
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TBPTH
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IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
0X47
0X48
0X49
0X4A
0x4B
0X4C
0X4D
0X4E
0X4F
0X50
0X51
.
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
STKMON
PCH
LVDCR
Unused
Unused
Unused
Unused
Unused
Unused
GENERAL PURPOSE REGISTER
.
0X7F
0X80
0X81
.
.
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
.
0XFE
0XFF
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
15
eKTF5832
8-Bit Microcontroller
6.1.4 R3: SR (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT
F
N
OV
T
P
Z
DC
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 (INT): Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/RETI instructions
Bit 6 (N): Negative flag.
The negative flag stores the state of the most significant bit of the output result
0: The result of the operation is not negative.
1: The result of the operation is negative.
Bit 5 (OV): Overflow flag.
OV is set when a two’s complement overflows occurs as a result of an operation
0: No overflow occurred.
1: Overflow occurred.
Bit 4 (T): Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by
WDT time-out.
Bit 3 (P): Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"
command.
Bit 2 (Z): Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry or Borrow flag
C : C is set when a carry occurs and cleared when a borrow occurs during an arithmetic
operation. The Carry Flag bit is set or cleared, depending on the operation that is
performed
For ADD, ADC, INC, INCA instructions
0: No carry occurs.
1: Carry occurs.
16
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
For SUB, SUBB, DEC, DECA, NEG instructions
0: Borrow occurs.
1: No borrow occurs.
For RLC, RRC, RLCA, RRCA instructions
The Carry flag is used as a link between the least significant bit (LSB) and most
significant bit
(MSB).
6.1.5 R4: RSR (RAM Select Register)
Bit 7
RSR7
R/W
Bit 6
RSR6
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7~0 (RSR7~RSR0): These bits are used to select registers (Address 00 ~ FF) in
indirect addressing mode. For more details, refer to the table on Data
Memory Configuration in Section 6.1.3, R2: PCL (Program Counter Low).
6.1.6 Bank 0 R5 ~ R8: (Port 5 ~ Port 8)
R5, R6, R7, and R8 are I/O data registers.
6.1.7 Bank 0 R9 ~ RA: (Reserved)
6.1.8 Bank 0 RB~RD: (IOCR5 ~ IOCR7)
These registers are used to control the I/O port direction. They are both
readable and writable.
0: Set the relative I/O pin as output
1: Set the relative I/O pin into high impedance
6.1.9 Bank 0 RE: OMCR (Operating Mode Control Register)
Bit 7
CPUS
R/W
Bit 6
IDLE
R/W
Bit 5
Bit 4
Bit 3
Bit 2
RCM2
R/W
Bit 1
RCM1
R/W
Bit 0
RCM0
R/W
-
-
-
-
-
-
Bit 7 (CPUS): CPU Oscillator Source Select.
0 : Fs: sub-oscillator
1 : Fm: main-oscillator (default)
When CPUS=0, the CPU oscillator select sub-oscillator and the main
oscillator is stopped.
Bit 6 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode to
go.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
17
eKTF5832
8-Bit Microcontroller
0: “IDLE=0”+SLEP instruction sleep mode
1: “IDLE=1”+SLEP instruction idle mode (default)
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
Code option
HLFS=0
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
+ SLEP
(*)
wakeup
(**)
Sleep mode
Fm: stop
Green mode
Fm: stop
Idle mode
Fm: stop
Fs: stop
CPU: stop
Fs: oscillation
CPU: using Fs
Fs: oscillation
CPU: stop
Interrupt or
wakeup
IDLE=0
+ SLEP
Figure 6-2 CPU Operation Mode
Note
(*)
If Watchdog function is enabled before into sleep mode, some circuits like timer (Its clock source
is Fs) must stop counting.
If Watchdog function is enabled before into sleep mode, some circuits like timer (Its clock source
is external pin) can still count and its interrupt flag can be active at matching condition as
corresponding interrupt is enabled. But CPU cannot be wake up by this event.
(**)
Switching Operation Mode at sleep Normal, Green Normal:
If the clock source of timer is Fm, timer/counter must stop counting at sleep or green mode. Then,
timer can continue to count until clock source is stable at normal mode. That clock source is
stable means CPU starts to work at normal mode.
18
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Switching Operation Mode at Sleep green:
If the clock source of the timer is Fs, the timer must stop counting at sleep mode. Then, the timer
can continue to count until the clock source is stable at green mode. That clock source is stable
means that CPU starts to work at green mode.
Switching Operation Mode at Sleep Normal:
If the clock source of the Timer is Fs, the timer must stop counting at sleep mode. Then, the timer
can continue to count until the clock source is stable at normal mode. That clock source is stable
means that CPU starts to work at normal mode.
CPU Mode Switch
IRC Frequency
Waiting Time before CPU starts to work
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
12M, 16M
1M, 4M, 6M, 8M
32kHz
WSTO + 32 clocks (main frequency)
WSTO + 8/32 clocks (main frequency)
WSTO + 8 clocks (sub frequency)
WSTO: Waiting time of Start-to-Oscillation
Bits 5~3: Not used, set to “0” all the time
Bits 2~0 (RCM2~RCM0): Internal RC mode selection bits
*Default value corresponding code option Word1 RCM2~RCM0
*RCM2
*RCM1
*RCM0
Frequency (MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
4
1
6
8
12
16
6.1.10 Bank 0 RF: EIESCR (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EIES1
R/W
Bit 2
EIES0
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time
Bits 3~2 (EIES1~0): external interrupt edge select bit
0: Falling edge interrupt
1: Rising edge interrupt
Bits 1~0: Not used, set to "0" all the time
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
19
eKTF5832
8-Bit Microcontroller
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
LVDWK
R/W
Bit 4
Bit 3
INTWK1 INTWK0
R/W R/W
Bit 2
Bit 1
Bit 0
Bits 7~6, 4: Not used, set to “0” all the time
Bit 5 (LVDWK): Low Voltage Detect Wake-up Enable Bit
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
Bits 3~2 (INTWK1~0): External Interrupt (INT pin) Wake-up Function Enable Bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status changed is used to enter interrupt vector or to
wake-up IC from Sleep/Idle, the INTWK bits must be set to “enable”.
Bits 1~0: Not used, set to “0” all the time
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SPIWK
R/W
Bit 2
I2CWK
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~4:
Not used. Set to "0" all the time.
Bit 3 (SPIWK): SPI wake-up enable bit. Applicable when SPI works in Slave mode.
0: Disable SPI wake-up
1: Enable SPI wake-up
Bit 2 (I2CWK): I2C wake-up enable bit. Applicable when I2C works in Slave mode.
0: Disable I2C wake-up
1: Enable I2C wake-up
NOTE
When I2C is in Slave mode, it cannot communicate with the MCU in Green mode. At the
same time the SCL in on hold and kept at low level when the MCU is in Green mode.
SCL is released when the MCU switches to Normal mode.
Bits 1~0:
Not used. Set to "0" all the time.
20
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3)
Bit 7
ICWKP8 ICWKP7 ICWKP6 ICWKP5
R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7~4 (ICWKP8~ICWKP5): Pin change Wake-up enable for Ports 8/7/6/5.
0: Disable wake-up function
1: Enable wake-up function
Bits 3~0:
Not used. Set to "0" all the time.
Sleep Mode Idle Mode
DISI ENI DISI ENI
Green Mode
Normal Mode
Wake-up Condition
Signal
Signal
DISI
ENI
DISI
ENI
ICWKPx = 0,
PxICIE = 0
Wake-up is invalid
Interrupt is invalid
Interrupt
+
Interrupt +
Next
ICWKPx = 0,
PxICIE = 1
Next
Wake-up is invalid
Interrupt
Instruction
Instruction Interrupt
Vector
Vector
Pin
Change
INT
ICWKPx = 1,
PxICIE = 0
Wake-up +
Interrupt is invalid
Next Instruction
Interrupt
+
Wake-up Wake-up Wake-up Wake-up
+ Next + Interrupt + Next + Interrupt
Instruction Vector Instruction Vector
Interrupt +
Next
ICWKPx = 1,
PxICIE = 1
Next
Interrupt
Instruction
Instruction Interrupt
Vector
Vector
NOTE
When the MCU wakes up from Sleep or Idle mode, the ICSF must be equal to 1. If ICSF
is equal to 0, it means the pin status does not change or the pin change ICIE is disabled.
Hence the MCU cannot wake-up.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
21
eKTF5832
8-Bit Microcontroller
6.1.14 Bank 0 R13: (Reserved)
6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1)
Bit 7
Bit 6
Bit 5
LVDSF
F
Bit 4
Bit 3
EXSF1
F
Bit 2
EXSF0
F
Bit 1
Bit 0
TCSF
F
Each corresponding status flag is set to "1" when interrupt condition is triggered.
Bits 7~6, 4, 1: Not used, set to "0" all the time
Bit 5 (LVDSF): Low Voltage Detector status flag
LVDEN
LVDS1,LVDS0
LVD Voltage Interrupt Level
LVDSF
1
1
1
1
0
11
10
01
00
XX
4.0V
3.2V
2.8V
2.5V
NA
1*
1*
1*
1*
0
* If Vdd has crossover at the LVD voltage interrupt level as Vdd varies, LVDSF =1.
Bits 3~2 (EXSF1~0): External interrupt status flag.
Bit 0 (TCSF): TCC overflow status flag. Set when TCC overflows, reset by software.
NOTE
If a function is enabled, the corresponding status flag would be active regardless of
whether the interrupt mask is enabled or not.
6.1.16 Bank 0 R15: (Reserved)
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMCPSF PWMCDSF PWMBPSF PWMBDSF PWMAPSF PWMADSF
F
F
F
F
F
F
Bits 7~6: Not used, set to "0" all the time
Bit 5 (PWMCPSF): Status flag of period-matching for PWMC (Pulse Width Modulation).
Set when a selected period is reached, reset by software.
Bit 4 (PWMCDSF): Status flag of duty-matching for PWMC (Pulse Width Modulation).
Set when a selected duty is reached, reset by software.
Bit 3 (PWMBPSF): Status flag of period-matching for PWMB (Pulse Width Modulation).
Set when a selected period is reached, reset by software.
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IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bit 2 (PWMBDSF): Status flag of duty-matching for PWMB (Pulse Width Modulation).
Set when a selected duty is reached, reset by software.
Bit 1 (PWMAPSF): Status flag of period-matching for PWMA (Pulse Width Modulation).
Set when a selected period is reached, reset by software.
Bit 0 (PWMADSF): Status flag of duty-matching for PWMA (Pulse Width Modulation).
Set when a selected duty is reached, reset by software.
NOTE
If a function is enabled, the corresponding status flag would be active whether the
interrupt mask is enabled or not.
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4)
Bit 7
P8ICSF
F
Bit 6
P7ICSF
F
Bit 5
P6ICSF
F
Bit 4
P5ICSF
F
Bit 3
Bit 2
Bit 1
Bit 0
I2CTSF
F
SPISF I2CSTPSF I2CRSF
F
F
F
Bits 7~4 (P8ICSF~P5ICSF): Ports 5~8 input status change status flag. Set when
Ports 5~8 input changes. Reset by software.
Bit 3 (SPISF):
SPI mode status flag. Flag is cleared by software.
Bit 2 (I2CSTPSF): I2C stop status flag. Set when I2C stop signal occurs.
Bit 1 (I2CRSF): I2C receive status flag. Set when I2C receives 1byte data and
responds ACK signal. Reset by firmware or I2C disable.
Bit 0 (I2CTSF): I2C transmit status flag. Set when I2C transmits a 1 byte data and
receives a handshake signal (ACK or NACK). Reset by firmware or
I2C disable.
NOTE
If a function is enabled, the corresponding status flag will be active regardless
whether the interrupt mask is enabled or not.
6.1.19 Bank 0 R18: (Reserved)
6.1.20 Bank 0 R19: SFR6 (Status Flag Register 6)
Bit 7
SHSF
F
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 (SHSF): System hold status flag, Set when system hold occur, reset by software.
Bits 6~0: Not used, set to "0" all the time
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
23
eKTF5832
8-Bit Microcontroller
6.1.21 Bank 0 R1A: (Reserved)
6.1.22 Bank 0 R1B: IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
LVDIE
R/W
Bit 4
Bit 3
EXIE1
R/W
Bit 2
EXIE0
R/W
Bit 1
Bit 0
TCIE
R/W
-
-
-
-
-
-
-
-
Bits 7~6, 4, 1: Not used, set to "0" all the time.
Bit 5 (LVDIE): LVDSF interrupt enable bit.
0: Disable LVDSF interrupt
1: Enable LVDSF interrupt
Bit 3 (EXIE1): EXSF1 interrupt enable and /INT1 function enable bit.
0: P74/INT1/SCL1/OSCO is P74/SCL1/OSCO pin, EXSF1 always
equals 0.
1: Enable EXSF1 interrupt and P74/INT1/SCL1/OSCO is /INT1 pin
Bit 2 (EXIE0): EXSF0 interrupt enable and /INT0 function enable bit.
0: P73/INT0/SDA1 is P73/SDA1 pin, EXSF0 always equals 0.
1: Enable EXSF0 interrupt and P73/INT0/SDA1 is /INT0 pin
Bit 0 (TCIE): TCSF interrupt enable bit.
0: Disable TCSF interrupt
1: Enable TCSF interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump
into the corresponding interrupt vector when the corresponding status flag is set.
24
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.23 Bank 0 R1C: (Reserved)
6.1.24 Bank 0 R1D: IMR3 (Interrupt Mask Register 3)
Bit 7
Bit 6
Bit 5
PWMCPIE PWMCDIE PWMBPIE PWMBDIE PWMAPIE PWMADIE
R/W R/W R/W R/W R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
Bits 7~6: Not used, set to "0" all the time.
Bit 5 (PWMCPIE): PWMCPSF interrupt enable bit.
0: Disable period-matching of PWMC interrupt
1: Enable period-matching of PWMC interrupt
Bit 4 (PWMCDIE): PWMCDSF interrupt enable bit.
0: Disable duty-matching of PWMC interrupt
1: Enable duty-matching of PWMC interrupt
Bit 3 (PWMBPIE): PWMBPSF interrupt enable bit.
0: Disable period-matching of PWMB interrupt
1: Enable period-matching of PWMB interrupt
Bit 2 (PWMBDIE): PWMBDSF interrupt enable bit.
0: Disable duty-matching of PWMB interrupt
1: Enable duty-matching of PWMB interrupt
Bit 1 (PWMAPIE): PWMAPSF interrupt enable bit.
0: Disable period-matching of PWMA interrupt
1: Enable period-matching of PWMA interrupt
Bit 0 (PWMADIE): PWMADSF interrupt enable bit.
0: Disable duty-matching of PWMA interrupt
1: Enable duty-matching of PWMA interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump
into the corresponding interrupt vector when the corresponding status flag is set.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
25
eKTF5832
8-Bit Microcontroller
6.1.23 Bank 0 R1E: IMR4 (Interrupt Mask Register 4)
Bit 7
Bit 6
P7ICIE
R/W
Bit 5
P6ICIE
R/W
Bit 4
P5ICIE
R/W
Bit 3
SPIIE
R/W
Bit 2
I2CSTPIE I2CRIE
R/W R/W
Bit 1
Bit 0
I2CTIE
R/W
P8ICIE
R/W
Bits 7~4 (P8ICIE~P5ICIE): PxICSF interrupt enable bit
0: Disable PxICSF interrupt
1: Enable PxICSF interrupt
Bit 3 (SPIIE): Interrupt enable bit
0: Disable SPSF interrupt
1: Enable SPSF interrupt
Bit 2 (I2CSTPIE): I2C stop interrupt enable bit.
0: Disable interrupt
1: Enable interrupt
Bit 1 (I2CRIE): I2C Interface Rx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
Bit 0 (I2CTIE): I2C Interface Tx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump
into the corresponding interrupt vector when the corresponding status flag is set.
6.1.24 Bank 0 R1F: (Reserved)
6.1.24 Bank 0 R20: IMR6 (Interrupt Mask Register 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SHIE
R/W
Bit 7 (SHIE): SHSF Interrupt Enable Bit.
0: Disable SHSF interrupt
1: Enable SHSF interrupt
Bits 6~0: Not used, set to "0" all the time.
26
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.25 Bank 0 R21: WDTCR (Watchdog Timer Control Register)
Bit 7
WDTE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
PSWE
R/W
Bit 2
WPSR2
R/W
Bit 1
WPSR1
R/W
Bit 0
WPSR0
R/W
-
-
-
-
-
-
Bit 7 (WDTE):
Watchdog Timer enable bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bits 6~4:
Not used. Set to "0" all the time.
Bit 3 (PSWE):
Prescaler enable bit for WDT
0: Prescaler disable bit. WDT rate is 1:1.
1: Prescaler enable bit. The WDT rate is set at Bits 2~0.
Bits 2~0 (WPSR2~WPSR0): WDT Prescaler bits
WPSR2
WPSR1
WPSR0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
27
eKTF5832
8-Bit Microcontroller
6.1.26 Bank 0 R22: TCCCR (TCC Control Register)
Bit 7
Bit 6
TCCS
R/W
Bit 5
Bit 4
Bit 3
PSTE
R/W
Bit 2
TPSR2
R/W
Bit 1
TPSR1
R/W
Bit 0
TPSR0
R/W
-
-
-
0
0
0
Bit 7:
Not used. Set to “0” all the time.
Bit 6 (TCCS): TCC Clock Source select bit
0: Fs (sub clock)
1: Fm (main clock)
Bits 5~4:
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. TCC rate is 1:1.
1: Prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0.
Bits 2~0 (TPSR2~TPSR0): TCC Prescaler Bits
Not used. Set to “0” all the time.
TPSR2
TPSR1
TPSR0
TCC Rate
0
0
0
1:2
1:4
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1:8
1:16
1:32
1:64
1:128
1:256
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IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.27 Bank 0 R23: TCCD (TCC Data Register)
Bit 7
TCC7
R/W
Bit 6
TCC6
R/W
Bit 5
TCC5
R/W
Bit 4
TCC4
R/W
Bit 3
TCC3
R/W
Bit 2
TCC2
R/W
Bit 1
TCC1
R/W
Bit 0
TCC0
R/W
Bits 7~0 (TCC7~TCC0): TCC data
Counter is increased by the instruction cycle clock. Writable and readable
as any other registers.
6.1.28 Bank 0 R24 ~ R2F: (Reserved)
6.1.29 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1)
Bit 7
Strobe/Pend
R/W
Bit 6
IMS
Bit 5
ISS
Bit 4
STOP SAR_EMPTY
R/W
Bit 3
Bit 2
ACK
R
Bit 1
FULL
R
Bit 0
EMPTY
R
R/W
R/W
R
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control I2C circuit in
sending SCL clock. Automatically resets after receiving or
transmitting handshake signal (ACK or NACK). In Slave mode, it
is used as pending signal. User should clear it after writing data
into Tx buffer or taking data from Rx buffer to inform Slave I2C
circuit to release SCL signal.
Bit 6 (IMS):
I2C Master/Slave mode select bit
0: Slave (Default)
1: Master
Bit 5 (ISS):
I2C C Fast/Standard mode select bit (if Fm is 4 MHz and
I2CTS1~0<0,0>)
0: Standard mode (100K bit/s)
1: Fast mode (400K bit/s)
Bit 4 (STOP):
In Master mode, if STOP=1 and R/nW=1, then MCU must return
nACK signal to Slave device before sending STOP signal. If
STOP=1 and R/nW=0, then MCU sends STOP signal after
receiving an ACK signal. MCU resets when it sends STOP
signal to Slave device.
In Slave mode, if STOP=1 and R/nW=0 then MCU must return
nACK signal to Master device.
Bit 3 (SAR_EMPTY): Set when MCU transmits 1 byte data from I2C Slave Address
Register and receive ACK (or nACK) signal. Reset when MCU
writes 1 byte data to I2C Slave Address Register.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
29
eKTF5832
8-Bit Microcontroller
Bit 2 (ACK):
The ACK condition bit is set to 1 by hardware when the device
responds with an acknowledge (ACK). Resets when the device
responds with a not-acknowledge (nACK) signal
Bit 1 (FULL):
Set by hardware when I2C Receive Buffer register is full. Reset
by hardware when the MCU reads data from the I2C Receive
Buffer register.
Bit 0 (EMPTY):
Set by hardware when I2C Transmit Buffer register is empty and
ACK (or nACK) signal is received. Reset by hardware when the
MCU writes new data into the I2C Transmit Buffer register.
6.1.30 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2)
Bit 7
I2CBF
R
Bit 6
GCEN
R/W
Bit 5
I2COPT
R/W
Bit 4
BBF
R
Bit 3
I2CTS2
R/W
Bit 2
I2CTS1
R/W
Bit 1
I2CTS0
R/W
Bit 0
I2CEN
R/W
Bit 7 (I2CBF): I2C Busy Flag Bit
0: clear to "0", in Slave mode, if receive STOP signal or I2C slave
address not match.
1: set when I2C communicate with master in slave mode.
*Set when STAR signal, clear when I2C disable or STOP signal for
Slave mode.
Bit 6 (GCEN): I2C General Call Function Enable Bit
0: Disable General Call Function
1: Enable General Call Function
Bit 5 (I2COPT): I2C pin optional bit. It is used to switch the pin position of I2C function.
0: Placed I2C pins in P70 (SDA0) and P71 (SCL0).
1: Placed I2C pins in P73 (SDA1) and P74 (SCL1).
*Default value corresponding code option Word 2 I2COPT
Bit 4 (BBF): Busy Flag Bit. I2C detection is busy in the master mode. Read only.
*Set when STAR signal, clear when STOP signal for Master mode.
Bits 3~1 (I2CTS2~I2CTS0): I2C Transmit Clock Select Bits. When using different
operating frequency (Fm), these bits must be set correctly to let SCL clock fill in with
standard/fast mode.
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IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
I2CCR1 Bit 5=1, Fast Mode
I2CTS2
I2CTS1
I2CTS0
SCL CLK
NA
Operating Fm (MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
NA
4
Fm/10
Fm/15
Fm/20
Fm/30
Fm/40
6
8
12
16
I2CCR1 Bit 5=0, Standard Mode
I2CTS2
I2CTS1
I2CTS0
SCL CLK
Fm/10
Fm/40
Fm/60
Fm/80
Fm/120
Fm/160
NA
Operating Fm (MHz)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
4
6
8
12
16
NA
Bit 0 (I2CEN): I2C Enable Bit
0: Disable I2C mode (Default)
1: Enable I2C mode
6.1.31 Bank 0 R32: I2CSA (I2C Slave Address Register)
Bit 7
SA6
R/W
Bit 6
SA5
R/W
Bit 5
SA4
R/W
Bit 4
SA3
R/W
Bit 3
SA2
R/W
Bit 2
SA1
R/W
Bit 1
SA0
R/W
Bit 0
IRW
R/W
Bits 7~1 (SA6~SA0): When the MCU is used as Master device for I2C application,
these bits are the Slave Device Address register.
Bit 0 (IRW): When the MCU is used as Master device for I2C application, this bit is
Read/Write transaction control bit.
0: Write
1: Read
6.1.32 Bank 0 R33: I2CDB (I2C Data Buffer Register)
Bit 7
DB7
R/W
Bit 6
DB6
R/W
Bit 5
DB5
R/W
Bit 4
DB4
R/W
Bit 3
DB3
R/W
Bit 2
DB2
R/W
Bit 1
DB1
R/W
Bit 0
DB0
R/W
Bits 7~0 (DB7~DB0): I2C Receive/Transmit Data Buffer
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
31
eKTF5832
8-Bit Microcontroller
6.1.33 Bank 0 R34: I2CDAL (I2C Device Address Register)
Bit 7
Bit 6
DA6
R/W
Bit 5
DA5
R/W
Bit 4
DA4
R/W
Bit 3
DA3
R/W
Bit 2
DA2
R/W
Bit 1
DA1
R/W
Bit 0
DA0
R/W
DA7
R/W
Bits 7~0 (DA7~DA0): When the MCU is used as Slave device for I2C application, this
register stores the MCU address. It is used to identify the data on the
I2C bus to extract the message delivered to the MCU.
NOTE
Slave Address 0x77 is reserved for WTR use.
6.1.34 Bank 0 R35: I2CDAH (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DA9
R/W
Bit 0
DA8
R/W
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~2:
Not used. Set to "0" all the time.
Bits 1~0 (DA9~DA8): Device Address bits
6.1.35 Bank 0 R36: SPICR (SPI Control Register)
Bit 7
CES
R/W
Bit 6
SPIE
R/W
Bit 5
SRO
R/W
Bit 4
SSE
R/W
Bit 3
SDOC
R/W
Bit 2
SBRS2
R/W
Bit 1
SBRS1
R/W
Bit 0
SBRS0
R/W
Bit 7 (CES): Clock Edge Select bit
0: Data shifted-out on a rising edge, and shift-in on a falling edge. Data
is on hold during a low-level.
1: Data shifted-out on a falling edge, and shift-in on a rising edge. Data
is on hold during a high-level.
Bit 6 (SPIE): SPI Enable bit
0: Disable SPI mode
1: Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0: No overflow
1: A new data is received while the previous data is still being held in
the SPIR register. Under this condition, the data in the SPIS register
is destroyed. To avoid setting this bit, user should read the SPIR
register although only transmission is implemented. This can only
occur in Slave mode.
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eKTF5832
8-Bit Microcontroller
Bit 4 (SSE): SPI Shift Enable bit
0: Reset as soon as the shifting is completed, and the next byte is read
to shift.
1: Start to shift, and it remains at "1" while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control bit
0: After serial data output, the SDO remains high
1: After serial data output, the SDO remains low
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
/SS enable
1
1
1
Slave
/SS disable
6.1.36 Bank 0 R37: SPIS (SPI Status Register)
Bit 7
DORD
R/W
Bit 6
TD1
R/W
Bit 5
TD0
R/W
Bit 4
Bit 3
OD3
R/W
Bit 2
OD4
R/W
Bit 1
Bit 0
RBF
R
0
-
0
-
Bit 7 (DORD): Data shift type control bit
0: Shift left (MSB first)
1: Shift right (LSB first)
Bits 6~5 (TD1~TD0): SDO status output delay time options (Normal mode only).
When the CPU oscillator source uses Fs, it will result to 1 CLK delay
time.
NOTE
TD1~TD0 bits are applicable only to Normal mode Normal mode. If
under Sleep mode Normal mode condition, then Wake-up time is
“Warm up time + 1CLK”.
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
24 CLK
32 CLK
1
0
1
1
Bit 4:
Bit 3 (OD3): Open-drain control bit
IC Product Specification (V0.4) 09.09. 2019
Not used. Set to “0” all the time.
33
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
0: Open-drain disabled for SDO
1: Open-drain enabled for SDO
Bit 2 (OD4): Open-drain control bit
0: Open-drain disabled for SCK
1: Open-drain enabled for SCK
Bit 1:
Not used. Set to “0” all the time.
Bit 0 (RBF): Read Buffer Full flag
0: Receiving is not completed, and SPIR has not fully exchanged data.
1: Receiving is completed, and SPIR has fully exchanged data.
6.1.37 Bank 0 R38: SPIR (SPI Read Buffer Register)
Bit 7
SRB7
R
Bit 6
SRB6
R
Bit 5
SRB5
R
Bit 4
SRB4
R
Bit 3
SRB3
R
Bit 2
SRB2
R
Bit 1
SRB1
R
Bit 0
SRB0
R
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.1.38 Bank 0 R39: SPIW (SPI Write Buffer Register)
Bit 7
SWB7
R/W
Bit 6
SWB6
R/W
Bit 5
SWB5
R/W
Bit 4
SWB4
R/W
Bit 3
SWB3
R/W
Bit 2
SWB2
R/W
Bit 1
SWB1
R/W
Bit 0
SWB0
R/W
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
6.1.39 Bank 0 R3A ~ R4F: (Reserved)
6.1.40 Bank 1 R5: IOCR8
These registers are used to control I/O port direction. They are both
readable and writable.
1: Put the relative I/O pin into high impedance
0: Put the relative I/O pin as output
6.1.41 Bank 1 R6 ~ R7: (Reserved)
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IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.42 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)
Bit 7
PH57
R/W
Bit 6
PH56
R/W
Bit 5
PH55
R/W
Bit 4
PH54
R/W
Bit 3
PH53
R/W
Bit 2
PH52
R/W
Bit 1
PH51
R/W
Bit 0
PH50
R/W
Bit 7 (PH57): Control bit used to enable pull-high of the P57 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (PH56): Control bit used to enable pull-high of the P56 pin
Bit 5 (PH55): Control bit used to enable pull-high of the P55 pin
Bit 4 (PH54): Control bit used to enable pull-high of the P54 pin
Bit 3 (PH53): Control bit used to enable pull-high of the P53 pin
Bit 2 (PH52): Control bit used to enable pull-high of the P52 pin
Bit 1 (PH51): Control bit used to enable pull-high of the P51 pin
Bit 0 (PH50): Control bit used to enable pull-high of the P50 pin
6.1.43 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)
Bit 7
PH67
R/W
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
Bit 7 (PH67): Control bit used to enable the pull high of P67 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (PH66): Control bit used to enable the pull high of P66 pin
Bit 5 (PH65): Control bit used to enable the pull high of P65 pin
Bit 4 (PH64): Control bit used to enable the pull high of P64 pin
Bit 3 (PH63): Control bit used to enable the pull high of P63 pin
Bit 2 (PH62): Control bit used to enable the pull high of P62 pin
Bit 1 (PH61): Control bit used to enable the pull high of P61 pin
Bit 0 (PH60): Control bit used to enable the pull high of P60 pin
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
35
eKTF5832
8-Bit Microcontroller
6.1.44 Bank 1 RA: P78PHCR (Ports 7~8 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HPH
R/W
Bit 2
P8LPH
R/W
Bit 1
P7HPH
R/W
Bit 0
P7LPH
R/W
Bits 7~4: Not used, set to "0" all the time.
Bit 3 (P8HPH): Control bit used to enable the pull high of Port 8 high nibble pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 2 (P8LPH): Control bit used to enable the pull high of Port8 low nibble pin
Bit 1 (P7HPH): Control bit used to enable the pull high of Port74 pin
Bit 0 (P7LPH): Control bit used to enable the pull high of Port7 low nibble pin
6.1.45 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register)
Bit 7
PL57
R/W
Bit 6
PL56
R/W
Bit 5
PL55
R/W
Bit 4
PL54
R/W
Bit 3
PL53
R/W
Bit 2
PL52
R/W
Bit 1
PL51
R/W
Bit 0
PL50
R/W
Bit 7 (PL57): Control bit used to enable pull-low of the P57 pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 6 (PL56): Control bit used to enable pull-low of the P56 pin
Bit 5 (PL55): Control bit used to enable pull-low of the P55 pin
Bit 4 (PL54): Control bit used to enable pull-low of the P54 pin
Bit 3 (PL53): Control bit used to enable pull low of the P53 pin
Bit 2 (PL52): Control bit used to enable pull-low of the P52 pin
Bit 1 (PL51): Control bit used to enable pull-low of the P51 pin
Bit 0 (PL50): Control bit used to enable pull-low of the P50 pin
36
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.46 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register)
Bit 7
PL67
R/W
Bit 6
PL66
R/W
Bit 5
PL65
R/W
Bit 4
PL64
R/W
Bit 3
PL63
R/W
Bit 2
PL62
R/W
Bit 1
PL61
R/W
Bit 0
PL60
R/W
Bit 7 (PL67): Control bit used to enable the pull low of P67 pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 6 (PL66): Control bit used to enable the pull low of P66 pin
Bit 5 (PL65): Control bit used to enable the pull low of P65 pin
Bit 4 (PL64): Control bit used to enable the pull low of P64 pin
Bit 3 (PL63): Control bit used to enable the pull low of P63 pin
Bit 2 (PL62): Control bit used to enable the pull low of P62 pin
Bit 1 (PL61): Control bit used to enable the pull low of P61 pin
Bit 0 (PL60): Control bit used to enable the pull low of P60 pin
6.1.47 Bank 1 RD: P78PLCR (Ports 7~8 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HPL
R/W
Bit 2
P8LPL
R/W
Bit 1
P7HPL
R/W
Bit 0
P7LPL
R/W
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time.
Bit 3 (P8HPL): Control bit used to enable the pull low of Port 8 high nibble pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 2 (P8LPL): Control bit used to enable the pull low of Port 8 low nibble pin
Bit 1 (P7HPL): Control bit used to enable the pull low of Port 7 high nibble pin
Bit 0 (P7LPL): Control bit used to enable the pull low of Port 7 low nibble pin
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
37
eKTF5832
8-Bit Microcontroller
6.1.48 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control
Register)
Bit 7
H57
R/W
Bit 6
H56
R/W
Bit 5
H55
R/W
Bit 4
H54
R/W
Bit 3
H53
R/W
Bit 2
H52
R/W
Bit 1
H51
R/W
Bit 0
H50
R/W
Bits 7~0 (H57~H50): P57~P50 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.1.49 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control
Register)
Bit 7
H67
R/W
Bit 6
H66
R/W
Bit 5
H65
R/W
Bit 4
H64
R/W
Bit 3
H63
R/W
Bit 2
H62
R/W
Bit 1
H61
R/W
Bit 0
H60
R/W
Bits 7~2, 0 (H67~H62,H60): P67~P60 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
Bit 1:
Not used. Set to “0” all the time.
6.1.50 Bank 1 R10: P78HDSCR (Port 7~8 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HHDS P8LHDS P7HHDS P7LHDS
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time.
Bit 3 (P8HHDS): Control bit used to enable high drive/sink of Port8 high nibble pin
0: Enable high drive/sink
1: Disable high drive/sink
Bit 2 (P8LHDS): Control bit used to enable high drive/sink of Port8 low nibble pin
Bit 1 (P7HHDS): Control bit used to enable high drive/sink of Port7 high nibble pin
Bit 0 (P7LHDS): Control bit used to enable high drive/sink of Port7 low nibble pin
38
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.1.51 Bank 1 R11: P5ODCR (Port 5 Open-Drain Control Register)
Bit 7
OD57
R/W
Bit 6
OD56
R/W
Bit 5
OD55
R/W
Bit 4
OD54
R/W
Bit 3
OD53
R/W
Bit 2
OD52
R/W
Bit 1
OD51
R/W
Bit 0
OD50
R/W
Bits 7~0 (OD57~OD50): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.52 Bank 1 R12: P6ODCR (Port 6 Open-Drain Control Register)
Bit 7
OD67
R/W
Bit 6
OD66
R/W
Bit 5
OD65
R/W
Bit 4
OD64
R/W
Bit 3
OD63
R/W
Bit 2
OD62
R/W
Bit 1
OD61
R/W
Bit 0
OD60
R/W
Bits 7~0 (OD67~OD60): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.53 Bank 1 R13: P78ODCR (Ports 7~8 Open-Drain Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HOD
R/W
Bit 2
P8LOD
R/W
Bit 1
P7HOD
R/W
Bit 0
P7LOD
R/W
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time.
Bit 3 (P8HOD): Control bit used to enable open-drain of Port 8 high nibble pin
0: Disable open-drain function
1: Enable open-drain function
Bit 2 (P8LOD): Control bit used to enable open-drain of Port 8 low nibble pin
Bit 1 (P7HOD): Control bit used to enable open-drain of Port 7 high nibble pin
Bit 0 (P7LOD): Control bit used to enable open-drain of Port 7 low nibble pin
6.1.54 Bank 1 R14 ~ R15: (Reserved)
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
39
eKTF5832
8-Bit Microcontroller
6.1.55 Bank 1 R16: PWMSCR (PWM Source Clock Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
PWMCS PWMBS PWMAS
R/W
R/W
R/W
Bits 7~3: Not used, set to "0" all the time.
Bit 2 (PWMCS): Clock selection for PWMC timer
0: Fs (default)
1: Fm
Bit 1 (PWMBS): Clock selection for PWMB timer
0: Fs (default)
1: Fm
Bit 0 (PWMAS): Clock selection for PWMA timer
0: Fs (default)
1: Fm
6.1.56 Bank 1 R17: PWMACR (PWM1 Control Register)
Bit 7
PWMAE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
TAEN
R/W
Bit 2
TAP2
R/W
Bit 1
TAP1
R/W
Bit 0
TAP0
R/W
-
-
-
-
-
-
Bit 7 (PWMAE): PWMA enable bit
0: Disable (default)
1: Enable. The compound pin is used as PWMA pin
Bits 6~4: Not used, set to "0" all the time.
Bit 3 (TAEN): TMRA enable bit. All PWM function is valid only as this bit is set
0: TMRA is off (default value)
1: TMRA is on
PWMXEN
TXEN
Function description
0
0
1
1
0
1
0
1
Not used as PWM function; I/O pin or other functional pin.
Timer function; I/O pin or other function pin.
PWM function, the waveform keeps at low level.
PWM function, the normal PWM output waveform.
40
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bits 2~0 (TAP2~TAP0): TMRA clock prescaler option bits
TAP2
TAP1
TAP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.57 Bank 1 R18: PRDAL (Low Byte of PWMA Period)
Bit 7
PRDA7
R/W
Bit 6
PRDA6
R/W
Bit 5
PRDA5
R/W
Bit 4
PRDA4
R/W
Bit 3
PRDA3
R/W
Bit 2
PRDA2
R/W
Bit 1
PRDA1
R/W
Bit 0
PRDA0
R/W
Bits 7~0 (PRDA7~0): The contents of the register are low bytes of the PWMA period.
NOTE
If the PWMA duty/period needs to reload, the PRDAL register must be updated.
6.1.58 Bank 1 R19: PRDAH (High Byte of PWMA Period)
Bit 7
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDA9
R/W
Bit 0
PRDA8
R/W
Bits 7~0 (PRDA15~8): The contents of the register are high bytes of PWMA period
6.1.59 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)
Bit 7
DTA7
R/W
Bit 6
DTA6
R/W
Bit 5
DTA5
R/W
Bit 4
DTA4
R/W
Bit 3
DTA3
R/W
Bit 2
DTA2
R/W
Bit 1
DTA1
R/W
Bit 0
DTA0
R/W
Bits 7~0 (DTA7~0): The contents of the register are low bytes of the PWMA duty.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
41
eKTF5832
8-Bit Microcontroller
6.1.60 Bank 1 R1B: DTAH (High Byte of PMWA Duty)
Bit 7
Bit 6
DTA14
R/W
Bit 5
DTA13
R/W
Bit 4
DTA12
R/W
Bit 3
DTA11
R/W
Bit 2
DTA10
R/W
Bit 1
DTA9
R/W
Bit 0
DTA8
R/W
DTA15
R/W
Bits 7~0 (DTA15~8): The contents of the register are high bytes of the PWMA duty.
6.1.61 Bank 1 R1C: TMRAL (Low Byte of Timer 1)
Bit 7
TMRA7
R
Bit 6
TMRA6
R
Bit 5
TMRA5
R
Bit 4
TMRA4
R
Bit 3
TMRA3
R
Bit 2
TMRA2
R
Bit 1
TMRA1
R
Bit 0
TMRA0
R
Bits 7~0 (TMRA7~0): The contents of the register are low bytes of the PWMA timer
which is counting. This is read-only.
6.1.62 Bank 1 R1D: TMRAH (High Byte of Timer 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRA9
R
Bit 0
TMRA8
R
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11 TMRA10
R
R
R
R
R
R
Bits 7~0 (TMRA15~8): The contents of the register are high bytes of the PWMA timer
which is counting. This is read-only
6.1.63 Bank 1 R1E: PWMBCR (PWMB Control Register)
Bit 7
PWMBE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
TBEN
R/W
Bit 2
TBP2
R/W
Bit 1
TBP1
R/W
Bit 0
TBP0
R/W
-
-
-
-
-
-
Bit 7 (PWMBE): PWMB enable bit
0: Disable (default)
1: Enable. The compound pin is used as PWMB pin
Bits 6~4: Not used, set to "0" all the time.
Bit 3 (TBEN): TMRB enable bit. All PWM function is valid only as this bit is set
0: TMRB is off (default value)
1: TMRB is on
42
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bits 2~0 (TBP2~TBP0): TMRB clock prescaler option bits
TBP2
TBP1
TBP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.64 Bank 1 R1F: PRDBL (Low Byte of PWMB Period)
Bit 7
PRDB7
R/W
Bit 6
PRDB6
R/W
Bit 5
PRDB5
R/W
Bit 4
PRDB4
R/W
Bit 3
PRDB3
R/W
Bit 2
PRDB2
R/W
Bit 1
PRDB1
R/W
Bit 0
PRDB0
R/W
Bits 7~0 (PRDB7~0): The contents of the register are low byte of the PWMB period
NOTE
If the PWMB duty/period needs to reload, the PRDBL register must be updated.
6.1.65 Bank 1 R20: PRDBH (High Byte of PWMB Period)
Bit 7
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDB9
R/W
Bit 0
PRDB8
R/W
Bits 7~0 (PRDB15~8): The contents of the register are high byte of PWMB period
6.1.66 Bank 1 R21: DTBL (Low Byte of PMWB Duty)
Bit 7
DTB7
R/W
Bit 6
DTB6
R/W
Bit 5
DTB5
R/W
Bit 4
DTB4
R/W
Bit 3
DTB3
R/W
Bit 2
DTB2
R/W
Bit 1
DTB1
R/W
Bit 0
DTB0
R/W
Bits 7~0 (DTB7~0): The contents of the register are low byte of the PWMB duty
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
43
eKTF5832
8-Bit Microcontroller
6.1.67 Bank 1 R22: DTBH (High Byte of PMW2 Duty)
Bit 7
Bit 6
DTB14
R/W
Bit 5
DTB13
R/W
Bit 4
DTB12
R/W
Bit 3
DTB11
R/W
Bit 2
DTB10
R/W
Bit 1
DTB9
R/W
Bit 0
DTB8
R/W
DTB15
R/W
Bits 7~0 (DTB15~8): The contents of the register are high byte of the PWMB duty
6.1.68 Bank 1 R23: TMRBL (Low Byte of Timer B)
Bit 7
TMRB7
R
Bit 6
TMRB6
R
Bit 5
TMRB5
R
Bit 4
TMRB4
R
Bit 3
TMRB3
R
Bit 2
TMRB2
R
Bit 1
TMRB1
R
Bit 0
TMRB0
R
Bits 7~0 (TMRB7~0): The contents of the register are low byte of the PWMB timer
which is counting. This is read-only
6.1.69 Bank 1 R24: TMRBH (High Byte of Timer 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRB9
R
Bit 0
TMRB8
R
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10
R
R
R
R
R
R
Bits 7~0 (TMRB15~8): The contents of the register are high byte of the PWMB timer
which is counting. This is read-only
6.1.70 Bank 1 R25: PWMCCR (PWMC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMCE
R/W
-
-
-
-
-
-
TCEN
R/W
TCP2
R/W
TCP1
R/W
TCP0
R/W
Bit 7 (PWMCE): PWMC enable bit
0: Disable (default)
1: Enable. The compound pin is used as PWMC pin
Bits 6~4: Not used, set to "0" all the time.
Bit 3 (TCEN): TMRC enable bit. All PWM function is valid only as this bit is set
0: TMRC is off (default value)
1: TMRC is on
44
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bits 2~0 (TCP2~TCP0): TMRC clock prescaler option bits
TCP2
TCP1
TCP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.71 Bank 1 R26: PRDCL (Low byte of PWMC Period)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDC7
R/W
PRDC6
R/W
PRDC5
R/W
PRDC4
R/W
PRDC3
R/W
PRDC2
R/W
PRDC1
R/W
PRDC0
R/W
Bits 7~0 (PRDC7~0): The contents of the register are low byte of the PWMC period
*PWMC duty/period reload for PRDCL register update.
6.1.72 Bank 1 R27: PRDCH (High Byte of PWMC Period)
Bit 7
PRDC15 PRDC14 PRDC13 PRDC12 PRDC11 PRDC10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDC9
R/W
PRDC8
R/W
Bits 7~0 (PRDC15~8): The contents of the register are high byte of PWMC period
6.1.73 Bank 1 R28: DTCL (Low Byte of PMWC Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTC7
R/W
DTC6
R/W
DTC5
R/W
DTC4
R/W
DTC3
R/W
DTC2
R/W
DTC1
R/W
DTC0
R/W
Bits 7~0 (DTC7~0): The contents of the register are low byte of the PWMC duty
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
45
eKTF5832
8-Bit Microcontroller
6.1.74 Bank 1 R29: DTCH (High Byte of PMWC Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTC15
R/W
DTC14
R/W
DTC13
R/W
DTC12
R/W
DTC11
R/W
DTC10
R/W
DTC9
R/W
DTC8
R/W
Bits 7~0 (DTC15~8): The contents of the register are high byte of the PWMC duty
6.1.75 Bank 1 R2A: TMRCL (Low byte of Timer C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRC7
R
TMRC6
R
TMRC5
R
TMRC4
R
TMRC3
R
TMRC2
R
TMRC1
R
TMRC0
R
Bits 7~0 (TMRC7~0): The contents of the register are low byte of the PWMC timer
which is counting. This is read-only
6.1.76 Bank 1 R2B: TMRCH (High byte of Timer C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 TMRC9
TMRC8
R
R
R
R
R
R
R
R
Bits 7~0 (TMRC15~8): The contents of the register are high byte of the PWMC timer
which is counting. This is read-only
6.1.77 Bank 1 R2C ~ R44: (Reserved)
6.1.78 Bank 1 R45: TBPTL (Table Point Low Register)
Bit 7
TB7
R/W
Bit 6
TB6
R/W
Bit 5
TB5
R/W
Bit 4
TB4
R/W
Bit 3
TB3
R/W
Bit 2
TB2
R/W
Bit 1
TB1
R/W
Bit 0
TB0
R/W
Bits 7~0 (TB7~TB0): Table Point Address Bits 7~0.
6.1.79 Bank 1 R46: TBPTH (Table Point High Register)
Bit 7
HLB
R/W
Bit 6
RDS
R/W
Bit 5
TB13
R/W
Bit 4
TB12
R/W
Bit 3
TB11
R/W
Bit 2
TB10
R/W
Bit 1
TB9
R/W
Bit 0
TB8
R/W
Bit 7 (HLB): Obtain MLB or LSB at machine code of ROM or Data area.
0: the address of read byte value is Bit7 ~Bit0
1: the address of read byte value is Bit15~Bit8
Bit 6 (RDS): ROM / Data select bit, read machine code information area select.
0: ROM (default)
46
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
1: Data area (Data Address 000~17F)
HLB
RDS
Read to Register Data Value Description
Read byte value is Bit 7 ~ Bit 0 from machine code.
0
0
0
1
Read byte value is Bit 7 ~ Bit 0 from Data area.
Read byte value is– Highest bit fixed at “0” and Bit 15 ~ Bit 8
from machine code.
1
1
0
1
Read byte value is Bit 15 ~ Bit 8 from Data area.
Bits 5~0 (TB13~TB8): Table point Address Bits 13~8.
6.1.80 Bank 1 R47: STKMON (Stack Pointer)
Bit 7
STOV
R
Bit 6
Bit 5
Bit 4
STL4
R
Bit 3
STL3
R
Bit 2
STL2
R
Bit 1
STL1
R
Bit 0
STL0
R
-
-
-
-
Bit 7 (STOV): Stack pointer overflow indicator bit. Read only.
Bits 4~0 (STL4~0): Stack pointer number. Read only.
6.1.81 Bank 1 R48: PCH (Program Counter High)
Bit 7
Bit 6
Bit 5
PC13
R/W
Bit 4
PC12
R/W
Bit 3
PC11
R/W
Bit 2
PC10
R/W
Bit 1
PC9
R/W
Bit 0
PC8
R/W
-
-
-
-
Bits 7~6:
Not used. Set to “0” all the time.
Bits 5~0 (PC13~PC8): The high byte of program counter
6.1.82 Bank 1 R49: LVDCR (Low Voltage Detector Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDEN
R/W
LVDS1
R/W
LVDS0
R/W
LVDB
R
Bit 7 (LVDEN): Low Voltage Detector Enable Bit
0: Disable low voltage detector
1: Enable low voltage detector
Bits 5~4 (LVDS1~LVDS0): Low Voltage Detector Level Bits.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
47
eKTF5832
8-Bit Microcontroller
LVDEN
LVDS1, LVDS0
LVD Voltage Interrupt Level
LVDB
VDD <2.5V
VDD >2.7V
VDD <2.8V
VDD >3.0V
VDD <3.2V
VDD >3.4V
VDD <4V
VDD >4.2V
NA
0
1
0
1
0
1
0
1
1
1
1
1
00
01
10
1
0
11
XX
Bit 3 (LVDB): Low Voltage Detector State Bit. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (selected by LVDS1 ~ LVDS0), this bit
will be cleared.
0: Low voltage is detected.
1: Low voltage is not detected or LVD function is disabled.
Bits 6, 2~0: Not used, set to "0" all the time.
6.1.83 Bank 1 R4A~ R4F: (Reserved)
6.1.84 Bank 2 R5 ~ R46: (Reserved)
6.1.85 Bank 2 R47: DACR (DAC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAE
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~1: not used bits, fixed to “0” all the time.
Bits 0 (DAE): DAC enable bit of P84 pin.
0: Disable DAC, P84/TPS21/DAC act as P84/TPS21 pin.
1: Enable DAC to act as analog output pin.
6.1.86 Bank 2 R48: DACD (Digital to Analog Converter Data Buffer)
Bit 7
DAD0[7] DAD0[6] DAD0[5] DAD0[4] DAD0[3] DAD0[2] DAD0[1] DAD0[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (DAD0[7]~DAD0[0]): DAC Data Buffer.
6.1.87 Bank 2 R49 ~ R4F: (Reserved)
6.1.88 R50~R7F, Banks 0~3 R80~RFF
These are all 8-bit general-purpose registers.
48
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.2 TCC/WDT and Prescaler
Two 8-bit counters are available as prescalers for the TCC and WDT. The TPSR0~
TPSR2 bits of the TCCCR register (Bank 0 R22) are used to determine the ratio of the
TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the WDTCR register (Section
6.1.25Bank 0 R21) are used to determine the WDT prescaler. The prescaler counter is
cleared by the instructions each time they are written into TCC. The WDT and
prescaler are cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 below
depicts the circuit diagram of TCC/WDT.
The TCCD (Section 6.1.27 TCC Data Register) is an 8-bit timer/counter. The TCC
clock source is from the internal clock only and TCC will be incremented by 1 at Fc
clock (without prescaler). The TCC will stop running when Sleep mode occurs.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e., in Sleep mode). During
Normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to
reset. The WDT can be enabled or disabled any time during Normal mode by software
programming (see WDTE bit of WDTCR (Section 6.1.25Bank 0 R21) register). With
no prescaler, the WDT time-out period is approximately 18 ms1 (one oscillator start-up
timer period).
Data Bus
8 Bit Counter
TCC(R23)
8 to 1 MUX
Prescaler
TCC overflow
interrupt
TPSR2~TPSR0
(R22)
WDT
8 Bit Counter
8 to 1 MUX
Prescaler
WDTE(R21)
WDT time out
WPSR2~ WPSR0
(R21)
Figure 6-3 TCC and WDT Block Diagram
1 VDD=5V, WDT time-out period = 16.5ms ± 8%.
VDD=3V, WDT time-out period = 18ms ± 8%.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
49
eKTF5832
8-Bit Microcontroller
6.3 I/O Ports
The I/O registers, Port 5~Port 8 are bidirectional tri-state I/O ports. All can be pulled
high and pulled low internally by software. Furthermore, they can also be set as
open-drain output and high sink/drive by software. Ports 5~8 features wake-up and
interrupt function as well as input status change interrupt function. Each I/O pin can be
defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC8).
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 ~ Port 8 are shown in the following Figure 6-4a to 6-4d.
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
R
IOD
PORT
Q
D
CLK
PDWR
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-4a I/O Port and I/O Control Register for Port 5~8 Circuit Diagram
50
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
PCRD
P
Q
D
R
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
0
1
P
D
R
Q
M
U
X
_
Q
CLK
C
L
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4b I/O Port and I/O Control Register for /INT Circuit
PCRD
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
P61~P67
PORT
IOD
P
R
Q
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4c I/O Port and I/O Control Register for Ports 5~8 Circuit
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
51
eKTF5832
8-Bit Microcontroller
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.
1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-4d I/O Port 5~8 with Input Change Interrupt/Wake-up Block Diagram
6.3.1 Usage of Ports 5~8 Input Change Wake-up/Interrupt
Function
1. Wake-up
a) Before Sleep:
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Wake-up bit (Set ICWKPx = 1)
5) Execute "SLEP" instruction
b) After Wake-up:
Next instruction
2. Wake-up and Interrupt
a) Before SLEEP
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Wake-up bit (Set ICWKPx = 1)
5) Enable interrupt (Set PxICIE = 1)
6 Execute "SLEP" instruction
b) After Wake-up
1) IF "ENI" Interrupt vector (0006H)
2) IF "DISI" Next instruction
52
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.4 Reset and Wake-up
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) LVR (if enabled)
The device is kept in a Reset condition for a period of approximately 18ms2 (one
oscillator start-up timer period) after a reset is detected. If the /Reset pin goes “low” or
the WDT time-out is active, a reset is generated. In IRC mode, the reset time is 8-/32
clocks. Once a Reset occurs, the following functions are performed (see Figure 6-5
below):
The oscillator is continuously running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog Timer and prescaler are cleared.
The control register bits are set as shown in the table below under Section 6.4.3,
Summary of Register Initial Values after Reset.
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. Wake-up is
then generated (in IRC mode the wake-up time is 8-/32 clocks). The controller can be
awakened by any of the following events:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) External (/INT) pin changes (if INTWE is enabled)
4) Port input status changes (if ICWKPx is enabled)
5) SPI receives data while it serves as Slave device (if SPIWK is enabled)
6) I2C receives data while it serves as Slave device (if I2CWK is enabled)
7) TCC Counter mode overflow occur.(if TCIE is enable)
The first two events (1 and 2) will cause the eKTF5832 to reset. The T and P flags of
R3 are used to determine the source of the reset (Wake-up). Events 3 to 7 are
considered as continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 0x02~0x40 after wake-up. If DISI is executed before SLEP, the
execution will restart from the instruction right next to SLEP after wake-up.
2 Vdd = 5V, set up time period = 16.5ms ± 8%
Vdd = 3V, set up time period = 16.5ms ± 8%
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
53
eKTF5832
8-Bit Microcontroller
Only one of Events 3 to 6 can be enabled before entering into Sleep mode. That is:
a) If WDT is enabled before SLEP, the eKTF5832 can wake-up only when Events 1 or
2 occurs. Refer to the Section 6.5 Interrupt, for further details.
b) If External (/INT) pin change is used to wake-up the eKTF5832 and the EXWE bit is
enabled before SLEP (with WDT disabled). Hence, the eKTF5832 can wake-up
only when Event 3 occurs.
c) If Port Input Status Change is used to wake-up the eKTF5832 and the
corresponding wake-up setting is enabled before SLEP (with WDT disabled), the
eKTF5832 can wake-up only when Event 4 occurs.
d) With SPI serving as Slave device and the SPIWK bit of Bank0 R11 register is
enabled before SLEP (with WDT disabled), the SPI will wake-up the eKTF5832
after it receives data. Hence, the eKTF5832 can wake-up only when Event 5
occurs.
e) When I2C serving as Slave device and I2CWK bit of Bank 0 R11 register is enabled
before SLEP (with WDT disabled), the I2C will wake-up the eKTF5832 after it
receives data. Hence, the eKTF5832 can be waken-up only by Event 6.
6.4.1 Summary of Wake-up and Interrupt Mode Operation
Sleep Mode
Idle Mode
DISI ENI
Green Mode
Normal Mode
Wake-up
Signal
Condition
Signal
DISI
ENI
DISI
ENI
DISI
ENI
INTWK = 0,
EXIE = 0
/INT pin Disable
Interrupt
+
Interrupt
+
INTWK = 0,
EXIE = 1
Next
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
External INT
INTWK = 1,
EXIE = 0
/INT pin Disable
Wake up
Wake up
+
Next
Wake up
+
Interrupt
Vector
Wake up
+
Next
Interrupt
+
Interrupt
+
INTWK = 1,
EXIE = 1
+
Next
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Instruction
Vector
Vector
Vector
TCIE = 0
TCIE = 1
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Wake up
+
Wake up
+
Interrupt
+
TCC INT
Next
+
Next
Wake-up is invalid.
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
PWMxPIE = 0
PWMxPIE = 1
Wake-up is invalid.
Interrupt is invalid.
Interrupt
PWMA/B/C
(When
TimerA/B/C
Match PRD or
DT)
Wake up
+
Wake up
+
Interrupt
+
Next
+
Next
Wake-up is invalid.
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
WKPxH/L = 0,
PxICIE = 0
Wake-up is invalid.
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Pin Change
INT
Interrupt
+
WKPxH/L = 0,
PxICIE = 1
Next
+
Next
Instruction Interrupt Instruction Interrupt
Vector Vector
54
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Wake up
+
Next Instruction
WKPxH/L = 1,
PxICIE = 0
Interrupt is invalid.
Wake up
+
Next
Wake up
Wake up
+
Next
Wake up
+
Interrupt
+
Interrupt
WKPxH/L = 1,
PxICIE = 1
+
Next
Next
+
Interrupt
Vector
Interrupt Instruction Interrupt Instruction Interrupt
Vector
Instruction
Instruction
Vector
Vector
LVDWK = 0,
LVDIE = 0
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Interrupt
+
LVDWK = 0,
LVDIE = 1
Next
+
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
Low Voltage
Detector
Wake up
Wake up
LVDWK = 1,
LVDIE = 0
+
+
Interrupt is invalid.
Interrupt
Next Instruction
Next Instruction
Wake up
Wake up
Wake up
Wake up
Interrupt
+
LVDWK = 1,
LVDIE = 1
+
+
+
+
Next
+
Next
Next
Instruction
Interrupt
Vector
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
Interrupt is invalid.
Interrupt
I2CWK = 0,
I2CxIE = 0
I2C
Wake-up is invalid.
Can’t use
I2CWK = 0,
I2CxIE = 1
I2C
Can’t use
Next
+
Wake-up is invalid.
Instruction Interrupt
Vector
I2C
(Slave mode)
Wake up
+
Next Instruction
I2C must be slave mode
I2CWK = 1,
I2CxIE = 0
I2C
Can’t use
Interrupt is invalid.
Wake up
+
Next
Wake up
+
Interrupt
Vector
Wake up
+
Next
Wake up
+
Interrupt
Vector
Interrupt
I2CWK = 1,
I2CxIE = 1
I2C
Can’t use
Next
+
Instruction Interrupt
Vector
Instruction
Instruction
SPIWK = 0,
SPIE = 0
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Interrupt
+
SPIWK = 0,
SPIE = 1
Next
+
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
SPI
(Slave mode)
Wake up
+
Next Instruction
SPIWK = 1,
SPIE = 0
Interrupt is invalid.
Wake up
+
Next
Wake up
+
Interrupt
Vector
Wake up
+
Next
Wake up
+
Interrupt
Interrupt
+
SPIWK = 1,
SPIE = 1
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector
Instruction
Instruction
Vector
Vector
RESET
RESET
RESET
RESET
RESET
WDT time out
RESET
RESET
RESET
NOTE
After wake up:
1. If interrupt enable interrupt+ next instruction
2. If interrupt disable next instruction
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
55
eKTF5832
8-Bit Microcontroller
6.4.2 The Status of RST, T, and P of the Status Register
A reset condition is initiated by one of the following events:
1) Power-on condition
2) High-low-high pulse on the /RESET pin
3) Watchdog timer time-out
4) When LVR occurs
The values of T and P, as listed in the following table are used to check how the MCU
wakes up. The next table shows the events that may affect the status of T and P.
Values of RST, T and P after Reset:
Reset Type
T
P
Power-on
1
1
P
/RESET during Operation mode
P
/RESET Wake-up during Sleep mode
WDT during Operation mode
1
0
0
1
0
P
WDT Wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
0
P: Previous status before reset
Status of T and P being affected by Events:
Event
T
P
Power-on
1
1
0
1
1
1
1
WDTC instruction
WDT time-out
P
0
SLEP instruction
Wake-up on pin change during Sleep mode
0
P: Previous value before reset
56
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT Timeout
Setup Time
RESET
WDT
/RESET
Figure 6-5 Block Diagram of Controller Reset
6.4.3 Summary of Register Initial Values after Reset
Legend: U: Unknown or don’t care
C: Same with Code option
P: Previous value before reset
t: Check tables under Section 6.4.2
Bank
Name
Address
0x00
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
R0
(IAR)
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
SBS1 SBS0
0
0
0
GBS2 GBS1 GBS0
0
0
0
0
0
0
0
0
0
0
R1
(BSR)
0x01
0x02
0x03
0x04
0
0
P
P
0
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
(PCL)
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
INT
0
0
N
U
P
OV
U
P
T
1
t
P
1
t
Z
U
P
DC
U
P
C
U
P
R3
(SR)
P
P
P
t
t
P
P
P
Bit Name
RSR7 RSR6 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R4
(RSR)
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
57
eKTF5832
8-Bit Microcontroller
Bank
Address
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P57
0
0
P56
0
0
P55
0
0
P54
0
0
P53
0
0
P52
0
0
P51
0
0
P50
0
0
Bank 0, R5
(Port 5)
0X05
0x06
0x07
0x08
0X0B
0x0C
0X0D
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P67
0
0
P66
0
0
P65
0
0
P64
0
0
P63
0
0
P62
0
0
P61
0
0
P60
0
0
Bank 0, R6
(Port 6)
P
P
P
P
P
P
P
P
P74
0
0
P73
0
0
P72
0
0
P71
0
0
P70
0
0
0
0
0
0
0
0
Bank 0, R7
(Port 7)
0
0
0
P
P
P
P
P
P87
0
0
P86
0
0
P85
0
0
P84
0
0
P83
0
0
P82
0
0
P81
0
0
P80
0
0
Bank 0, R8
(Port 8)
P
P
P
P
P
P
P
P
IOC57 IOC56 IOC55 IOC54 IOC53 IOC52 IOC51 IOC50
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RB
(IOCR5)
P
P
P
P
P
P
P
P
IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RC
(IOCR6)
P
P
P
P
P
P
P
P
IOC74 IOC73 IOC72 IOC71 IOC70
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Bank 0, RD
(IOCR7)
0
0
0
P
P
P
P
P
Bit Name
CPUS IDLE
Code
RCM2 RCM1 RCM0
Code Code Code
option option option
(RCM2) (RCM1) (RCM0)
Power-On
option
(HLFS)
Code
1
0
0
0
Bank 0, RE
(OMCR)
0x0E
0X0F
/RESET and WDT option
(HLFS)
1
0
0
0
0
0
0
P
P
P
P
P
Wake-up from
Sleep/Idle
P
P
P
Bit Name
EIES1 EIES0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
Bank 0, RF
EIESCR
0
0
0
0
P
P
0
0
58
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bank
Name
Address
0x10
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTWK INTWK
LVDWK
1
0
0
0
0
0
Bank 0,
R10
(WUCR1)
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
P
P
0
0
Bit Name
I2CWK
SPIWK
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R11
WUCR2
0x11
0x12
0X14
0X16
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
P
P
0
0
ICWKP ICWKP
ICWKP
Bit Name
ICWKP6
8
0
0
7
0
0
5
0
0
Bank 0,
R12
WUCR3
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
P
P
P
P
0
0
0
0
-
LVDSF
EXSF1 EXSF0
TCSF
0
0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R14
SFR1
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
P
0
P
P
0
P
PWMCP PWMC PWMB PWMB PWMA PWMA
Bit Name
SF
0
0
DSF
0
0
PSF
0
0
DSF
0
0
PSF
0
0
DSF
0
0
Bank 0,
R16
SFR3
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
P
P
P
P
P
P
P7ICS
P5ICS
I2CSTP
SF
0
Bit Name
P8ICSF
P6ICSF
SPISF
I2CRSF I2CTSF
F
0
0
F
0
0
Bank 0,
R17
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0X17
0
SFR4
P
P
P
P
P
P
P
P
Bit Name
SHSF
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R19
SFR6
0X19
0X1B
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
LVDIE
EXIE1 EXIE0
TCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R1B
IMR1
0
0
P
0
P
P
0
P
PWMCPI PWMC PWMB PWMB PWMA PWMA
Bit Name
E
0
0
DIE
0
0
PIE
0
0
DIE
0
0
PIE
0
0
DIE
0
0
BANK 0,
R1D
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0X1D
IMR3
0
0
P
P
P
P
P
P
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
59
eKTF5832
8-Bit Microcontroller
Bank
Address
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
I2CSTP
P8ICIE P7ICIE P6ICIE P5ICIE SPIIE
I2CRIE I2CTIE
IE
0
0
Bank 0,
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0X1E
R1E
IMR4
P
P
P
P
P
P
P
P
Bit Name
SHIE
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R20
IMR6
0X20
0X21
0X22
0X23
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
0
0
P
0
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
WDTE
PSWE WPSR2 WPSR1 WPSR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R21
WDTCR
P
0
0
0
P
P
P
P
TCCS
0
0
PSTE TPSR2 TPSR1 TPSR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R22
TCCCR
0
P
P
P
P
P
P
P
TCC7 TCC6
0
0
TCC5
0
0
TCC4 TCC3 TCC2 TCC1 TCC0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R23
TCCD
P
P
P
P
P
P
P
P
Strobe/
Pend
SAR_E
MPTY
Bit Name
IMS
ISS
STOP
ACK
FULL EMPTY
Bank 0,
R30
I2CCR1
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0X30
0X31
P
P
P
P
P
P
P
P
Bit Name
I2CBF GCEN I2COPT BBF I2CTS2 I2CTS1 I2CTS0 I2CEN
Code
option
(I2COPT
Power-On
0
0
0
0
0
0
1
Bank 0,
R31
I2CCR2
)
P
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
1
P
P
P
P
P
P
P
P
Bit Name
Power-On
SA6
0
SA5
0
SA4
0
SA3
0
SA2
0
SA1
0
SA0
0
IRW
0
Bank 0,
R32
I2CSA
0X32
0X33
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
DB7
0
0
DB6
0
0
DB5
0
0
DB4
0
0
DB3
0
0
DB2
0
0
DB1
0
0
DB0
0
0
Bank 0,
R33
I2CDB
P
P
P
P
P
P
P
P
60
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bank
Name
Address
0X34
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DA7
1
1
DA6
1
1
DA5
1
1
DA4
1
1
DA3
1
1
DA2
1
1
DA1
1
1
DA0
1
1
Bank 0,
R34
I2CDAL
P
P
P
P
P
P
P
P
Bit Name
DA9
DA8
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Bank 0,
R35
I2CDAH
0X35
0X36
0X37
0X38
0X39
0X05
0X08
0X09
0X0A
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
CES
0
0
SPIE
0
0
SRO
0
0
SSE SDOC SBRS2 SBRS1 SBRS0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R36
SPICR
P
P
P
P
P
P
P
P
DORD TD1
TD0
0
0
OD3
OD4
RBF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0,
R37
SPIS
P
P
P
0
P
P
0
P
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
Bank 0,
R38
SPIR
P
P
P
P
P
P
P
P
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
U*
P
BANK 0,
R39
SPIW
P
P
P
P
P
P
P
P
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1, R5
IOCR8
P
P
P
P
P
P
P
P
PH57 PH56
1
1
PH55
1
1
PH54 PH53 PH52 PH51 PH50
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1, R8
P5PHCR
P
P
P
P
P
P
P
P
PH67 PH66
1
1
PH65
1
1
PH64 PH63 PH62 PH61 PH60
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1, R9
P6PHCR
P
P
P
P
P
P
P
P
P8HPH P8LPH P7HPH P7LPH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bank 1, RA
P78PHCR
0
0
0
0
P
P
P
P
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
61
eKTF5832
8-Bit Microcontroller
Bank
Address
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
PL57 PL56
PL55
1
1
PL54 PL53
PL52
1
1
PL51
1
1
PL50
1
1
1
1
1
1
1
1
1
1
Bank 1, RB
P5PLCR
0X0B
0X0C
0X0D
0X0E
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
PL67 PL66
PL65
1
1
PL64 PL63
PL62
1
1
PL61
1
1
PL60
1
1
1
1
1
1
1
1
1
1
Bank 1, RC
P6PLCR
P
P
P
P
P
P
P
P
P8HPL P8LPL P7HPL P7LPL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bank 1, RD
P78PLCR
0
0
0
0
P
P
P
P
H57
1
H56
1
H55
1
1
H54
1
H53
1
H52
1
1
H51
1
1
H50
1
1
Bank 1, RE
P5HDSCR
1
1
1
1
P
P
P
P
P
P
P
P
Bit Name
Power-On
H67
1
H66
1
H65
1
H64
1
H63
1
H62
1
H61
1
H60
1
/RESET and WDT
1
1
1
1
1
1
1
1
Bank 1, RF
P6HDSCR
0X0F
0X10
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
P8HHD P8LHD P7HHD P7LHD
Bit Name
S
1
1
S
1
1
S
1
1
S
1
1
Bank 1,
R10
P78HDSCR
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
Bit Name
OD57 OD56
OD55
OD54 OD53 OD52 OD51 OD50
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R11
P5ODCR
0X11
0X12
0X13
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
OD67 OD66
OD65
0
0
OD64 OD63 OD62 OD61 OD60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R12
P6ODCR
P
P
P
P
P
P
P
P
P8HOD P8LOD P7HOD P7LOD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R13
P78ODCR
0
0
0
0
P
P
P
P
PWMC PWMB PWMA
Bit Name
S
0
0
S
0
0
S
0
0
Bank 1,
R16
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0X16
PWMSCR
0
0
0
0
0
P
P
P
62
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bank
Name
Address
0X17
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMA
TAEN TAP2 TAP1 TAP0
E
0
0
Bank 1,
R17
PWMACR
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
P
P
P
P
PRDA
PRDA
Bit Name
PRDA7
PRDA5
PRDA3 PRDA2 PRDA1 PRDA0
6
0
0
4
0
0
Bank 1,
R18
PRDAL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0X18
0X19
P
P
P
P
P
P
P
P
PRDA1 PRDA
PRDA PRDA1 PRDA1
Bit Name
PRDA13
PRDA9 PRDA8
5
0
0
14
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R19
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
PRDAH
P
P
P
P
P
P
P
P
Bit Name
DTA7 DTA6
DTA5
DTA4 DTA3 DTA2 DTA1 DTA0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R1A
DTAL
0X1A
0X1B
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DTA15 DTA14 DTA13 DTA12 DTA11 DTA10 DTA9 DTA8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R1B
DTAH
P
P
P
P
P
P
P
P
TMRA
TMRA
Bit Name
TMRA7
TMRA5
TMRA3 TMRA2 TMRA1 TMRA0
6
0
0
4
0
0
Bank 1,
R1C
TMRAL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
1
1
0X1C
0X1D
0X1E
0X1F
0X20
P
P
P
P
P
P
P
P
TMRA1 TMRA
TMRA TMRA1 TMRA1
Bit Name
TMRA13
TMRA9 TMRA8
5
0
0
14
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R1D
TMRAH
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
P
P
P
P
P
P
P
P
PWMB
Bit Name
TBEN TBP2 TBP1 TBP0
E
0
0
BANK 1,
R1E
PWMBCR
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
P
P
P
P
PRDB
PRDB
Bit Name
PRDB7
PRDB5
PRDB3 PRDB2 PRDB1 PRDB0
6
0
0
4
0
0
Bank 1,
R1F
PRDBL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
PRDB1 PRDB
PRDB PRDB1 PRDB1
Bit Name
PRDB13
PRDB9 PRDB8
5
0
0
14
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R20
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
PRDBH
P
P
P
P
P
P
P
P
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
63
eKTF5832
8-Bit Microcontroller
Bank
Address
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DTB7 DTB6
DTB5
0
0
DTB4 DTB3 DTB2 DTB1 DTB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R21
DTBL
0X21
0X22
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DTB15 DTB14 DTB13 DTB12 DTB11 DTB10 DTB9 DTB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R22
DTBH
P
P
P
P
P
P
P
P
TMRB
TMRB
Bit Name
TMRB7
TMRB5
TMRB3 TMRB2 TMRB1 TMRB0
6
0
0
4
0
0
Bank 1,
R23
TMRBL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
1
1
0X23
0X24
0X25
0X26
0X27
P
P
P
P
P
P
P
P
TMRB1 TMRB
TMRB TMRB1 TMRB1
Bit Name
TMRB13
TMRB9 TMRB8
5
0
0
14
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R24
TMRBH
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
P
P
P
P
P
P
P
P
PWMC
Bit Name
TCEN TCP2 TCP1 TCP0
E
0
0
Bank 1,
R25
PWMCCR
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
P
P
P
P
PRDC
PRDC
Bit Name
PRDC7
PRDC5
PRDC3 PRDC2 PRDC1 PRDC0
6
0
0
4
0
0
Bank 1,
R26
PRDCL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
PRDC1 PRDC
PRDC PRDC1 PRDC1
Bit Name
PRDC13
PRDC9 PRDC8
5
0
0
14
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R27
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
PRDCH
P
P
P
P
P
P
P
P
Bit Name
DTC7 DTC6
DTC5
DTC4 DTC3 DTC2 DTC1 DTC0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R28
DTCL
0X28
0X29
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DTC15 DTC14 DTC13 DTC12 DTC11 DTC10 DTC9 DTC8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R29
DTCH
P
P
P
P
P
P
P
P
64
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bank
Name
Address
0X2A
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRC
TMRC7 TMRC6 TMRC5
TMRC3 TMRC2 TMRC1 TMRC0
4
0
0
Bank 1,
R2A
TMRCL
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
1
1
P
P
P
P
P
P
P
P
TMRC1 TMRC1 TMRC1 TMRC TMRC1 TMRC1
Bit Name
TMRC9 TMRC8
5
0
0
4
0
0
3
0
0
12
0
0
1
0
0
0
0
0
Bank 1,
R2B
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0X2B
TMRCH
P
P
P
P
P
P
P
P
Bit Name
Power-On
TB7
0
TB6
0
TB5
0
TB4
0
TB3
0
TB2
0
TB1
0
TB0
0
Bank 1,
R45
TBPTL
0X45
0X46
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
HLB
RDS
TB13
TB12 TB11
TB10
TB9
TB8
Bank 1,
R46
TBPTH
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
STOV
STL4 STL3
STL2
STL1 STL0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R47
STKMON
0X47
0X48
0X49
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
0
0
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
PC13 PC12 PC11 PC10
PC9
0
0
PC8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1,
R48
PCH
0
0
P
P
P
P
P
P
LVDEN
LVDS1 LVDS0 LVDB
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Bank 1,
R49
LVDCR
P
0
P
P
P
0
0
0
Bit Name
DAE
Bank 2,
R47
DACR
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0X47
0X48
0
0
0
0
0
0
0
P
Bit Name
DAD0[7] DAD0[6] DAD0[5] DAD0[4] DAD0[3] DAD0[2] DAD0[1] DAD0[0]
Bank 2,
R48
DACD
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
65
eKTF5832
8-Bit Microcontroller
6.5 Interrupt
The eKTF5832 has 15 interrupts (External, Internal) as listed below:
Interrupt Source
Enable Condition
Int. Flag
Int. Vector Priority
Internal /
Reset
-
-
0
High 0
External
External
External
Internal
INT
Pin change
TCC
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
ENI+LVDEN &
LVDIE=1
ENI + SPIIE=1
ENI+PWMAPIE=1 PWMAPSF
ENI+PWMADIE=1 PWMADSF
ENI+ I2CTIE
ENI+ I2CRIE
ENI+ I2CSTPIE
ENI+PWMBPIE=1 PWMBPSF
ENI+PWMBDIE=1 PWMBDSF
ENI+PWMCPIE=1 PWMCPSF
ENI+PWMCDIE=1 PWMCDSF
EXSF
ICSF
TCSF
2
4
6
1
2
3
Internal
LVD
LVDSF
SPISF
8
4
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
SPI
PWMPA
PWMDA
I2C Transmit
I2C Receive
I2CSTOP
PWMPB
PWMDB
PWMPC
C
5
6
7
8
9
10
11
12
13
14
15
14
16
1A
1C
1E
24
26
2A
2C
3A
I2CTSF
I2CRSF
I2CSTPSF
PWMDC
System hold
ENI+SHIE
SHSF
Bank 0 R14~R19 are the interrupt status registers that record the interrupt requests in
the relative flags/bits. Bank0 R1B~R20 are the interrupt Mask register. The global
interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When
one of the enabled interrupts occurs, the next instruction will be fetched from individual
address. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICSF bit which is set to “0”) in the Interrupt Status Register is set
regardless of the status of its mask bit or the execution of ENI. The RETI instruction
ends the interrupt routine and enables the global interrupt (the execution of ENI).
External interrupt is equipped with digital noise rejection circuit (input pulse of less than
4 System Clock Time is eliminated as noise). When an interrupt (Falling edge) is
generated by the External interrupt (if enabled), the next instruction will be fetched from
Address 002H.
Before the interrupt subroutine is executed, the contents of ACC and the R3 (Bit 0~Bit 6)
and R4 registers are saved by hardware. If another interrupt occurs, the ACC, R3
(Bit 0~Bit 4), and R4 will be replaced by the new interrupt. After the interrupt service
routine is completed, ACC, R3 (Bit 0~Bit 6), and R4 restored.
Interrupt
Interrupt
sources
occurs
ACC
R1
STACKACC
ENI/ DISI
STACKR 1
STACKR 3
STACKR 4
R3(bit6~bit0)
R4
RETI
Figure 6-6a Interrupt Backup Diagram
66
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Figure 6-6b Interrupt Input Circuit
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
67
eKTF5832
8-Bit Microcontroller
6.6 Dual Set of PWM (Pulse Width Modulation)
6.6.1 Overview
In PWM mode, PWMA~C produce up to 16-bit resolution PWM output (see. functional
block diagram below). A PWM output consists of a time period and a duty cycle, and it
keeps the output high. The PWM baud rate is the inverse of the time period. Figure
6-7b below; PWM Output Timing, depicts the relationships between a time period and a
duty cycle.
Data
Bus
DTH+DTL
Writing DTL
TXP2 TXP1 TXP0
Duty
Fosc
1:1
1:2
1:4
TMRX
prescaler
1:8
MUX
1:16
1:64
1:128
1:256
To
PWMXDIF
Comparator
TMRX
prescaler TXEN
PWMXE
PWMXA
MUX
1
0
PWMX
R
S
Q
Q
TMRXH+TMRXL
Period match
Reset
Comparator
Period
To
PWMXPIF
Writing PRDL
PRDH+
PRDL
Data
Bus
Figure 6-7a Dual PWMs Functional Block Diagram
Period
Duty
Cycle
PRDA = TMRA
DTA = TMRA
Figure 6-7b PWM Output Timing
68
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.6.2 Control Register
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMCPS PWMCDS
-
-
PWMBPSF PWMBDSF PWMAPSF PWMADSF
F
F
0x16
0x1D
SFR3
IMR3
Bank 0
Bank 0
-
-
F
F
F
F
F
F
PWMCP PWMCD
PWMBPIE PWMBDIE PWMAPIE PWMADIE
-
-
IE
IE
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
PWMCS PWMBS PWMAS
-
-
-
-
-
-
-
-
-
-
-
-
PWMSC
R
0x16
0x17
Bank 1
Bank 1
R/W
TAP2
R/W
R/W
TAP1
R/W
R/W
TAP0
R/W
PWMAE
R/W
TAEN
R/W
PWMAC
R
PRDA7 PRDA6 PRDA5 PRDA4 PRDA3
PRDA2
PRDA1
R/W
PRDA0
R/W
0x18 PRDAL
0x19 PRDAH
Bank 1
Bank 1
R/W
R/W
R/W
R/W
R/W
R/W
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10
PRDA9
PRDA8
R/W
DTA7
R/W
R/W
DTA6
R/W
R/W
DTA5
R/W
R/W
DTA4
R/W
R/W
DTA3
R/W
R/W
DTA2
R/W
R/W
DTA1
R/W
R/W
DTA0
R/W
0x1A
0x1B
DTAL
DTAH
Bank 1
Bank 1
Bank 1
DTA15 DTA14 DTA13 DTA12
R/W R/W R/W R/W
DTA11
R/W
DTA10
R/W
DTA9
R/W
DTA8
R/W
TMRA7 TMRA6 TMRA5 TMRA4 TMRA3
TMRA2
R/W
TMRA1
R/W
TMRA0
R/W
0x1C TMRAL
0x1D TMRAH
R/W
R/W
R/W
R/W
R/W
TMRA1
5
TMRA14 TMRA13 TMRA12 TMRA11 TMRA10
TMRA9
TMRA8
Bank 1
Bank 1
Bank 1
R/W
PWMBE
R/W
R/W
R/W
R/W
R/W
TBEN
R/W
R/W
TBP2
R/W
R/W
TBP1
R/W
R/W
TBP0
R/W
-
-
-
-
-
-
PWMBC
0x1E
R
PRDB7 PRDB6 PRDB5 PRDB4 PRDB3
PRDB2
PRDB1
R/W
PRDB0
R/W
0x1F PRDBL
0x20 PRDBH
R/W
R/W
R/W
R/W
R/W
R/W
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10
PRDB9
PRDB8
Bank 1
R/W
DTB7
R/W
R/W
DTB6
R/W
R/W
DTB5
R/W
R/W
DTB4
R/W
R/W
DTB3
R/W
R/W
DTB2
R/W
R/W
DTB1
R/W
R/W
DTB0
R/W
0x21
0x22
DTBL
DTBH
Bank 1
Bank 1
Bank 1
DTB15 DTB14 DTB13 DTB12
R/W R/W R/W R/W
DTB11
R/W
DTB10
R/W
DTB9
R/W
DTB8
R/W
TMRB7 TMRB6 TMRB5 TMRB4 TMRB3
TMRB2
R/W
TMRB1
R/W
TMRB0
R/W
0x23 TMRBL
0x24 TMRBH
R/W
R/W
R/W
R/W
R/W
TMRB1
5
TMRB14 TMRB13 TMRB12 TMRB11 TMRB10
TMRB9
TMRB8
Bank 1
Bank 1
Bank 1
R/W
PWMCE
R/W
R/W
R/W
R/W
R/W
TCEN
R/W
R/W
TCP2
R/W
R/W
TCP1
R/W
R/W
TCP0
R/W
-
-
-
-
-
-
PWMCC
0x25
R
PRDC7 PRDC6 PRDC5 PRDC4 PRDC3
R/W R/W R/W R/W R/W
PRDC2
PRDC1
PRDC0
0x26 PRDCL
R/W
R/W
R/W
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
69
eKTF5832
8-Bit Microcontroller
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDC15 PRDC14 PRDC13 PRDC12 PRDC11 PRDC10
PRDC9
PRDC8
0x27 PRDCH
Bank 1
R/W
DTC7
R/W
R/W
DTC6
R/W
R/W
DTC5
R/W
R/W
DTC4
R/W
R/W
DTC3
R/W
R/W
DTC2
R/W
R/W
DTC1
R/W
R/W
DTC0
R/W
0x28
0x29
DTCL
DTCH
Bank 1
Bank 1
Bank 1
DTC15 DTC14 DTC13 DTC12
R/W R/W R/W R/W
DTC11
R/W
DTC10
R/W
DTC9
R/W
DTC8
R/W
TMRC7 TMRC6 TMRC5 TMRC4 TMRC3
TMRC2
R/W
TMRC1
R/W
TMRC0
R/W
0x2A TMRCL
0x2B TMRCH
R/W
R/W
R/W
R/W
R/W
TMRC1
5
TMRC14 TMRC13 TMRC12 TMRC11 TMRC10
R/W R/W R/W R/W R/W
TMRC9
TMRC8
Bank 1
R/W
R/W
R/W
6.6.3 Increment Timer Counter (TMRX: TMRxH/TMRxL)
TMRX’s are 16-bit clock counters with programmable prescalers. They are designed
for the PWM module as baud rate clock generators. TMR can be read only. If
employed, they can be turned off for power saving by setting the TxEN Bit to “0”.
TMRA, TMRB and TMRC, are internal designs and cannot be read.
6.6.4 PWM Time Period (PRDX: PRDxL/H)
The PWM time period has a 16-bit resolution and is defined by writing to the PRDX
register. When TMRX is equal to PRDX, the following events occur on the next
increment cycle:
1) TMRX is cleared
2) The PWMX pin is set to “1”
NOTE
The PWM output cannot be set if the duty cycle is “0.”
3) The PWMXPSF bit is set to “1”
To calculate the PWM time period, use the following formula:
Example:
PRDX = 49; Fosc = 4 MHz; TMRX (0, 0, 0) = 1 : 1;
Then
1
Period
49 1
1 12.5s
4M
70
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
6.6.5 PWM Duty Cycle (DTX: DTxH/DT1L)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded anytime. However, it cannot be latched into DLX until the current
value of DLX is equal to TMRX.
The following formula shows how to calculate the PWM duty cycle:
1
Duty cycle
DTX
TMRX prescale value
FOSC
Example:
DTX = 10;
Then
Fosc = 4 MHz;
TMRX (0, 0, 0) = 1 : 1;
1
Duty cycle
10
1 2.5s
4M
6.6.6 PWM Programming Process/Steps
1) Load the PWM duty cycle to DT
2) Load the PWM time period to PRD
3) Enable the interrupt function by writing Bank0-R1D, if required
4) Load a desired value for the timer prescaler
5) Enable PWMX function, i.e., enable PWMXE control bit
6) Finally, enable TMRX function, i.e., enable TXEN control bit
If the application needs to change PWM duty and period cycle at run time, refer to the
following programming steps:
1) Load new duty cycle (if using dual PWM function) at any time.
2) Load new period cycle. You must take note of the order of loading period cycle. As
the low byte of PWM period cycle is assigned a value, the new PWM cycle is
loaded into circuit.
3) The circuit will automatically update the new duty and period cycles to generate
new PWM waveform at the next PWM cycle.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
71
eKTF5832
8-Bit Microcontroller
6.7 SPI (Serial Peripheral Interface)
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2 SBRS1 SBRS0
Bank 0
Bank 0
Bank 0
Bank 0
0X36
0X37
0X38
0X39
SPICR
SPIS
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
-
-
DORD
TD1
TD0
OD3
OD4
-
-
RBF
R/W
R/W
R
R/W
R/W
R/W
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
SPIR
SPIW
R
R
R
R
R
R
R
R
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
SPSF
R/W
-
-
-
-
-
-
Bank 0
Bank 0
0X18
0X1E
SFR4
IMR4
-
-
-
-
-
-
-
-
SPIE
R/W
-
-
-
-
-
-
6.7.1 Overview and Features
Overview:
Figures 6-8a and 6-8b show how the eKTF5832 communicates with other devices
through SPI module. If the eKTF5832 is the Master controller, it will send clock through
the SCK pin. A couple of 8-bit data are transmitted and received at the same time.
However, if the eKTF5832 is defined as a Slave, its SCK pin could be programmed as
an input pin. Data will continue to be shifted based on both clock rate and the selected
edge. User can also set the –
SPIS Bit 7 (DORD) to determine the SPI transmission order,
SPICR Bit 3 (SDOC) to control SDO pin after serial data output status,
SPIS Bit 6 (TD1) and Bit 5 (TD0) determine the SDO status output delay times.
Features:
1) Operation in either Master mode or Slave mode
2) Three-wire or four-wire full duplex synchronous communication
3) Programmable baud rates of communication
4) Programmable clock polarity, (Bank 0 R36 Bit 7)
5) Interrupt flag available for read buffer full
6) SPI transmission order
7) SDO status select after serial data output
8) SDO status output delay time
9) SPI handshake pin
10) Up to 8 MHz (maximum) bit frequency
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8-Bit Microcontroller
SDO
SPIR Reg
SPIW Reg
SPIR Reg
SPIW Reg
/SS
SDI
SPIS Reg
SPIS Module
SCK
Master Device
Slave Device
Figure 6-8a SPI Master/Slave Communication Block Diagram
SDI
SDO
SCK
/SS
Vdd
Master
P60
P61
P62
P63
Slave Device 1
Slave Device 2
Slave Device 4
Slave Device 3
Figure 6-8b Single-Master and Multi-Slave SPI Configuration
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6.7.2 SPI Function Description
Read
Write
RBF
SPIIF
SSE
SPIW
SPIR reg
reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
SI
SPIC reg
SO
Edge
Select
SBR0 ~SBR2
SBR2~SBR0
Noise
Filter
/SS
/ SS
Clock Select
Prescaler
2, 4, 8, 16, 32
Fosc
Edge
Select
SCK
TMR2
CES
Figure 6-9a SPI Function Block Diagram
SPI
SO
SI
Shift Clock
SPI Shift
Buffer
FOSC
2 1 0
SPIC
7 6 4 5 4
3
0
7~0
SPIW
7~0
SPIR
SPIC
ISR4
SPIC
SPIS
DATA Bus
Figure 6-9b SPI Transmission Function Block Diagram
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8-Bit Microcontroller
The following explains the functions of each block in the above figures as SPI carries
out communication with the depicted signals:
P52/SI/TPA2: Serial Data In
P51/SO/TPA1: Serial Data Out
P53/SCK/TPA3: Serial Clock
P50//SS/TPA0: /Slave Select (Option). This pin (/SS) may be required during
Slave mode.
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift. The SSE bit will be kept
in “1” if the communication is still undergoing. This flag must be cleared as
shifting is completed. You can determine if the next write attempt is available.
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and
the SPIW registers are shifted at the same time. Once data are written, SPIS
starts transmitting / receiving. The data received will be moved to the SPIR
register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full)
flag and the SPISF (SPI Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer is updated as the 8-bit shifting is completed.
The data must be read before the next reception is completed. The RBF flag is
cleared as the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
SBRS2~SBRS0: Programming of the clock frequency/rates and sources.
Clock Select: Select either the internal or the external clock as shifting clock.
Edge Select: Select the appropriate clock edges by programming the CES bit
6.7.3 SPI Signal and Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
P52/SI/TPA2:
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last.
Defined as high-impedance if not selected.
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Program the same clock rate and clock edge to latch on both the Master and Slave
devices.
The byte received will update the transmitted byte.
The RBF will be set as the SPI operation is completed.
Timing is shown in Figures 6-10a and 6-10b below.
P51/SO/TPA1:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last.
Program the same clock rate and clock edge to latch on both the Master and Slave
devices.
The received byte will update the transmitted byte.
The CES bit is reset, as the SPI operation is completed.
Timing is shown in Figures 6-10a and 6-10b.
P53/SCK/TPA3:
Serial Clock
Generated by a Master device
Synchronize the data communication on both the SI and SO pins.
The CES is used to select the edge to communicate.
The SBR0~SBR2 is used to determine the baud rate of communication.
The CES, SBR0, SBR1, and SBR2 bits have no effect in Slave mode.
Timing is shown in Figures 6-10a and 6-10b.
P50//SS/TPA0:
Slave Select; negative logic.
Generated by a Master device to indicate the Slave(s) has to receive data.
Goes low before the first cycle of SCK occurs, and remains low until the last (8th)
cycle is completed
Ignore the data on the SI and SO pins when /SS is high, because SO is no longer
driven
Timing is shown in Figures 6-10a and 6-10b.
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6.7.4 SPI Mode Timing
Figure 6-10a SPI Mode with /SS Disabled Timing Diagram
The SCK edge is selected by programming the bit CES. The waveform shown in
Figure 6-10a above, is applicable regardless of whether the eKTF5832 is in Master or
Slave mode with /SS disabled. However, the waveform in Figure 6-10b below can only
be implemented in Slave mode with /SS enabled.
Figure 6-10b SPI Mode with /SS Enabled Timing Diagram
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6.8 I2C Function
The I2C function and transmit/receive pin are enabled by default when eKTF5832 is
powered-on.
Registers for I2C circuit:
R_BANK Address Name
Bit 7
Bit 6
IMS
R/W
Bit 5
ISS
Bit 4
Bit 3
Bit 2
ACK
R/W
Bit 1
FULL
R/W
Bit 0
EMPTY
R/W
Strobe
/Pend
SAR_
EMPTY
STOP
Bank 0 0x30
I2CCR1
R/W
R/W
R/W
BBF
R
R/W
I2CBF
GCEN I2COPT
I2CTS2 I2CTS1 I2CTS0 I2CEN
Bank 0 0x31
Bank 0 0x32
Bank 0 0x33
Bank 0 0x34
Bank 0 0x35
Bank 0 0x18
Bank 0 0x1E
I2CCR2
I2CSA
I2CDB
I2CDAL
I2CDAH
SFR4
R
R/W
R/W
R/W
R/W
SA1
R/W
DB2
R/W
DA2
R/W
-
R/W
SA0
R/W
DB1
R/W
DA1
R/W
DA9
R/W
R/W
IRW
R/W
DB0
R/W
DA0
R/W
DA8
R/W
SA6
SA5
SA4
SA3
R/W
DB4
R/W
DA4
R/W
-
SA2
R/W
R/W
R/W
R/W
DB7
DB6
DB5
DB3
R/W
R/W
R/W
R/W
DA7
DA6
DA5
DA3
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2CSTPIF I2CRSF I2CTSF
R/W R/W R/W
I2CSTPIE I2CRIE I2CTIE
R/W R/W R/W
-
-
-
IMR4
-
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8-Bit Microcontroller
Read
Write
FULL
I2CRIF
I2CTIF
I2CDB reg
Buffer Full Detector
Control and
Status reg
SCL
I2CSA reg
MSb
LSb
SDA
Add Match
Match Detect
I2CDA reg
Start and Stop
bit Detect
Figure 6-11 eKTF5832 I2C Block Diagram
The eKTF5832 supports a bidirectional, 2-wire bus, 7/10-bit addressing, and data
transmission protocol. A device that sends data to the bus is defined as transmitter,
while a device receiving the data is defined as a receiver. The bus has to be controlled
by a Master device which generates the Serial Clock (SCL), controls the bus access,
and generates the Start and Stop conditions. Both Master and Slave can operate as
transmitter or receiver, but the Master device determines which mode is activated.
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
pull-up resistor. When the bus is free, both lines are HIGH. The output stages of the
devices connected to the bus must have an open-drain or open-collector to perform the
wired-AND function. Data on the I2C-bus can be transferred at the rates of up to 100
kbit/sec in Standard-mode or up to 400 kbit/sec in Fast-mode.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH
or LOW state of the data line can only be changed when the clock signal on the SCL
line is LOW.
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The I2C interrupt occurs as describe below:
Condition
Master/Slave Transmit Address Transmit Data
Stop
Master
Slave
Transmit interrupt Transmit interrupt Stop interrupt
Receive interrupt Receive interrupt Stop interrupt
Transmit interrupt Receive interrupt Stop interrupt
Master Transmitter
(transmits to
Slave-Receiver)
Master Receiver
(read Slave-
Transmitter)
Master
Slave
Transmit interrupt
Transmit interrupt Stop interrupt
Within the procedure of the I2C bus, unique situations could arise which are defined as
START (S) and STOP (P) conditions.
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case.
This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
SCL
SDA
data line change
stable;
data valid allowed
of data
START
STOP
Figure 6-12 I2C Transfer Condition
6.8.1 7-Bit Slave Address
Master-transmitter transmits to Slave-receiver. The transfer direction is not changed.
Master reads Slave immediately after first byte. At the moment of the first
acknowledgement, the Master-transmitter becomes a Master-receiver and the
Slave-receiver becomes a Slave-transmitter. This first acknowledgement is still
generated by the Slave. The STOP condition is generated by the Master, which has
previously sent a Not-Acknowledge (A). The difference between Master-transmitter
and Master-receiver is only in their R//W bit. If the R//W bit is “0”, the Master device
would be transmitter. Otherwise, the Master device would be the receiver (R//W Bit =
“1”).
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8-Bit Microcontroller
Communications between the Master-transmitter/receiver and Slave-
transmitter/receiver are illustrated in the following Figures 6-13a and 6-13b.
8 Bits
8 Bits
Data
8 Bits
Data
S
Slave Address
7 Bits
R//W
A
A
A//A
P
'0'
Write
data transferred
(n byte + acknowledge)
Master to Slave
Slave to Master
A = acknowledge (SDA low)
/A = not acknowledge (SDA high)
S = Start
P = Stop
Figure 6-13a Master-Transmitter Transmits to Slave-Receiver with 7-Bit Slave Address
8 Bits
S
Slave Address
7 Bits
R//W
A
Data
A
Data
/A
P
'1' Read
data transferred
(n byte + acknowledge)
Figure 6-13b Master-Receiver Reads from Slave-Transmitter with 7-Bit Slave Address
6.8.2 10-Bit Slave Address
In 10-Bit Slave address mode, using 10-bit for addressing exploits the reserved
combination 11110XX for the first seven bits of the first byte following a START(S) or
repeated START (Sr) condition. The first seven bits of the first byte are the
combination 11110XX of which the last two bits (XX) are the two most-significant bits of
the 10-bit address. If the R//W bit is “0”, the second byte after acknowledge would be
the eight address bits of 10-bits Slave address. Otherwise, the second byte would just
be the next transmitted data from a Slave to Master device. The first byte 11110XX is
transmitted by using the Slave address register (I2CSA), and the second byte
XXXXXXXX is transmitted by using the data buffer (I2CDB).
The possible data transfer formats for 10-bit Slave address mode are explained in the
following paragraphs and Figures 6-14a ~ 6-14e.
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Master-Transmitter Transmits to Slave-Receiver with a 10-bit
Slave Address
When the Slave receives the first byte after START bit from Master, each Slave device
will compare the first seven bits of the first byte (11110XX) with their own address and
check the 8th bit (R//W). If the R//W bit is “0”, a Slave or more, will return an
Acknowledge (A1). Then all Slave devices will continue to compare the second
address (XXXXXXXX). If a Slave device finds a match, that particular Slave device will
be the only one to return an Acknowledge (A2). The matched Slave device will remain
addressed by the Master until it receives the STOP condition or until a repeated START
condition followed by the different Slave address is received.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A1
A2
A
A//A
R//W
Data
Data
P
Write
1st 7 Bits
2nd 8 Bits
Figure 6-14a Master-Transmitter Transmits to Slave-Receiver with a 10-Bit Slave Address
Master-Receiver Read Slave-Transmitter with a 10-bit Slave Address
Up to, and including Acknowledge Bit A2, the procedure is the same as that described
above for Master-Transmitter addressing a Slave-Receiver. After the Acknowledge
(A2), a repeated START condition (Sr) takes place followed by seven bits Slave
address (11110XX), but the 8th bit R//W is “1.” The addressed Slave device will then
return the Acknowledge (A3). If the repeated START (Sr) condition occurs and the
seven bits of first byte (11110XX) are received by Slave device, all the Slave devices
will compare with their own address and check the 8th bit (R//W). However, none of the
Slave devices can return an acknowledgement because R//W=1.
1 1 1 1 0 X X
0
1 1 1 1 0 X X
1
Slave
Address
Slave
Address
Slave
Address
S
DATA
A1
A2 Sr
A3
A
DATA /A
P
R//W
R//W
1st 7 Bits
2nd 8 Bits
1st 7 Bits Read
Write
Figure 6-14b Master-Receiver reads Slave-Transmitter with a 10-Bit Slave Address
Master Transmits and Receives Data to and from the Same Slave
Device with 10-Bit Addresses
The initial operation of this data transfer format is the same as explained in the above
paragraph on “Master-Transmitter transmits to Slave-Receiver with a 10-bit Slave
Address.” Then the Master device starts to transmit the data to the Slave device.
When the Slave device receives the Acknowledge or None-Acknowledge that is
followed by repeat START (Sr), the above operation under “Master-Receiver Reads
Slave-Transmitter with a 10-Bit Slave Address” is repeatedly performed.
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8-Bit Microcontroller
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
R//W
A
A
A
A//A
Data
Data
1st 7 Bits
Write
2nd 8 Bits
1 1 1 1 0 X X
1
Slave
Address
Sr
R//W
A
A
/A
Data
Data
P
1st 7 Bits
Read
Figure 6-14c Master Addresses a Slave with 10-Bit Addresses Transmits and Receives Data
with the Same Slave Device
Master Device Transmits Data to Two or More Slave Devices with 10 &
7 Bits Slave Address
For 10-bit address, the initial operation of this data transfer format is the same as
explained in the above paragraph on “Master-Transmitter transmits to Slave-Receiver
with a 10-bit Slave Address,” which describes how to transmit data to Slave device.
After the Master device completes the initial transmittal, and wants to continue
transmitting data to another device, the Master needs to address each of the new Slave
devices by repeating the initial operation mentioned above. If the Master device wants
to transmit the data in 7-bit and 10-bit Slave address modes successively, this could be
done after the Start or repeat Start conditions as illustrated in the following figures.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
Data
Data
R//W
1st 7-Bits
Write
2nd 8-Bits
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-Bits
Write
2nd 8-Bits
Figure 6-14d Master Transmitting to More than One Slave Devices with 10-Bit Slave Address
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eKTF5832
8-Bit Microcontroller
0
Slave
Address
S
A
A
A//A
R//W
Data
Data
7 Bits
Write
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7 Bits
Write
2nd 8 Bits
Figure 6-14e Master Successively Transmitting to 7-Bit and 10-Bit Slave Address
6.8.3 Master Mode
In transmitting (receiving) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable THE I2C Master function.
3) Write Slave address into the I2CSA register and IRW bit to select read or write.
4) Set strobe bit to start transmitting and then check I2CTSF (I2CTSF) bit.
5) Write 1st data into the I2CDB register, set strobe bit, and check I2CTSF (I2CRSF)
bit.
6) Write 2nd data into the I2CDB register, set strobe bit, STOP bit, and check I2CTSF
(I2CRSF) bit.
6.8.4 Slave Mode I2C Transmit
In receiving (transmitting) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable I2C Slave function.
3) Write device address into the I2CDA register.
4) Check I2CRSF (I2CTSF) bit, read I2CDB register (address), and then clear the
Pend bit.
5) Check I2CRSF (I2CTSF) bit, read I2CDB register (1st data), and then clear the
Pend bit.
6) Check I2CRSF (I2CTSF) bit, read I2CDB register (2nd data), and then clear the
Pend bit.
7) Check the I2CSTPSF bit, end transmission.
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eKTF5832
8-Bit Microcontroller
6.9 Oscillator
6.9.1 Oscillator Modes
The eKTF5832 can be operated in the one oscillator mode, i.e., Internal RC oscillator
mode (IRC). You need to set the main-oscillator modes by selecting the OSC0, and set
sub-oscillator modes by selecting the FSS in the Code Option register to complete the
overall oscillator mode setting.
Main-Oscillator Modes Defined By OSC0
Main-Oscillator Mode
OSC0
IRC (Internal RC oscillator mode; default)
RCOUT (P74) acts as I/O pin
1
IRC (Internal RC oscillator mode)
RCOUT (P74) acts as clock output pin
0
Summary of Maximum Operating Speeds
Conditions
VDD
2.4
3
Fxt Max. (MHz)
4.0
8.0
Two cycles with two clocks
4
12.0
16.0
5
6.9.2 Internal RC Oscillator Mode
The eKTF5832 offers a versatile internal RC mode with default frequency value of
4 MHz. The Internal RC oscillator mode has other frequencies (16 MHz, 12 MHz, 8
MHz, 6 MHz, and 1 MHz) that can be set by Code Option; RCM2~RCM0. The Table
below describes a typical drift rate of the calibration.
Internal RC Drift Rate (Ta=25 C, VDD=3.6V±5%, VSS=0V)
Drift Rate
Internal RC
Frequency
Temperature
(-40℃~+85℃)
Voltage
Process
Total
(2.8V~5.5V)
1MHz
4MHz
6MHz
8MHz
12MHz
16MHz
±2%
±2%
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
±4%
±4%
Note: These are theoretical values intended for reference only. Actual values may vary
depending on actual conditions.
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6.10 Power-On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply reaches its steady state. The eKTF5832 is equipped with a Power-on Voltage
Detector (POVD) with a detection level of 2.2V. It will work well if Vdd rises fast enough
(50 ms or less). However, in critical applications, extra devices are still required to
assist in solving power-up problems.
6.11 External Power-on Reset Circuit
The circuits diagram in Figure 6-15 implements an external RC to generate the reset
pulse. The pulse width (time constant) should be kept long enough for VDD to reach
minimum operational voltage. Apply this circuit when the power supply has slow rise
time. Since the current leakage from the /RESET pin is about 5 A, it is
recommended that R should not be greater than 40KΩ in order for the /RESET pin
voltage to remain at below 0.2V. The diode (D) functions as a short circuit at the instant
of power down. The capacitor (C) will discharge rapidly and fully. The current-limited
resistor (Rin) will prevent high current or ESD (electrostatic discharge) from flowing into
/RESET pin.
VDD
/RESET
R
D
Rin
C
Figure 6-15 External Power-Up Reset Circuit
6.12 Residue-Voltage Protection
When the battery is replaced, device power (VDD) is taken off but residue-voltage
remains. The residue-voltage may trip below VDD minimum, but not to zero. This
condition may cause a poor power-on reset. Figures 6-16a and 6-16b show how to
accomplish a proper residue-voltage protection circuit.
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eKTF5832
8-Bit Microcontroller
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-16a Circuit 1 for Residue Voltage Protection
VDD
VDD
R1
R2
Q1
R3
/RESET
Figure 6-16b Circuit 2 for Residue Voltage Protection
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8-Bit Microcontroller
6.13 Code Option
6.13.1 Code Option Register (Word 0)
Word 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Mnemonic
-
-
High
Low
IRCWUT
32 clks
8 clks
0
-
-
HLFS
Green
Normal
0
HLP
Low
High
0
LVR1
High
Low
0
1
0
High
Low
0
High
Low
1
High
Low
0
Default
0
Bit 7
LVR0
High
Low
0
Bit 6
RESETEN
/RST
P72
Bit 5
Bit 4
NRHL
8/fc
32/fc
0
Bit 3
NRE
Disable
Enable
0
Bit 2
-
High
Low
0
Bit 1
-
High
Low
0
Bit 0
-
High
Low
0
Mnemonic
ENWDT
Enable
Disable
0
1
0
Default
0
Bits 15~14, 11: Not used, set to "0" all the time.
Bit 13 (IRCWUT): IRC Warm Up time (Support IRC Frequency 1 MHz~8 MHz)
1: 32 clocks
0: 8 clocks (default)
CPU mode switch IRC Frequency Waiting time before CPU starting to work
12M, 16M
1M, 4M, 6M, 8M WSTO + 8/32 clocks (main frequency)
32kHz WSTO + 8 clocks (sub frequency)
WSTO + 32 clocks (main frequency)
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
Bits 12: Not used, set to "1" all the time.
Bit 10 (HLFS): Reset to Normal or Green Mode Select Bit
1: CPU is selected as Green mode when a reset occurs.
0: CPU is selected as Normal mode when a reset occurs (default)
Bit 9 (HLP): Power Consumption Selection
1: Low power consumption, apply to working frequency at 4 MHz or below
0: High power consumption, apply to working frequency above 4 MHz
Bits 8~7 (LVR1~LVR0): Low voltage reset enable bit.
VDD Release Level
LVR1, LVR0
*VDD Reset Level
00
01
NA (Power on reset) (default)
2.6V
3.0V
3.7V
2.4V
2.8V
3.5V
10
11
Note *: If VDD < 2.4V and keep about 5µs, IC will be reset.
If VDD < 2.8V and keep about 5µs, IC will be reset.
If VDD < 3.5V and keep about 5µs, IC will be reset.
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(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Bit 6 (RESETEN): P72//RESET pin selection bit
1: Enable, /RESET pin.
0: Disable, P72 pin (default)
Bit 5 (ENWDT): WDT enable bit
1: Enable
0: Disable (default)
Bit 4 (NRHL): noise rejection high/low pulse defined bit.
1: pulses equal to 8/fc [s] is regarded as signal
0: pulses equal to 32/fc [s] is regarded as signal (default)
Bit 3 (NRE): noise rejection enable bit
1: Disable.
0: Enable (default) In Green, Idle, and Sleep modes the noise rejection
circuit is always disabled.
Bits 2~0: Not used, set to "0" all the time.
6.13.2 Code Option Register (Word 1)
Word 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Mnemonic
-
-
FSS
32K
16K
0
1
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
Default
Bit 7
Bi t6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
-
RCM2
High
Low
0
RCM1
High
Low
1
RCM0
High
Low
1
OSC0
High
Low
0
RCOUT
High
Low
0
1
0
High
Low
0
High
Low
0
High
Low
0
Default
Bits 15~14: Not used, set to "0" all the time.
Bits 13 (FSS): Sub-oscillator mode selection bits
1: Fs is 32kHz
0: Fs is 16kHz
Note: WDT frequency is always 16kHz whatever the FSS bits are set.
Bits 12~7: Not used, set to "0" all the time.
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(This specification is subject to change without prior notice)
89
eKTF5832
8-Bit Microcontroller
Bits 6~4 (RCM2~RCM0): IRC frequency selection.
* Corresponding with control register Bank0 RE RCM2~RCM0
RCM2
RCM1
RCM0
Frequency (MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
4
1
6
8 (default)
12
16
Bits 3~2: Not used, set to "0" all the time.
Bit 1 (OSC0): Main-oscillator mode selection bits.
Main-Oscillator Mode
IRC (Internal RC oscillator mode) (default)
RCOUT (P74) acts as I/O pin
OSC0
0
IRC (Internal RC oscillator mode)
1
RCOUT (P74) acts as clock output pin
Bit 0 (RCOUT): System Clock Output Enable Bit in IRC mode
1: OSCO pin is open drain
0: OSCO output instruction cycle time (default)
6.13.3 Code Option Register (Word 2)
Word 2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Mnemonic
-
SHEN
Disable
Enable
0
SHCLK1 SHCLK0 BOREN
BORT2 BORT1
BORT0
High
Low
0
1
0
High
Low
0
High
Low
0
High
Low
0
Disable
Enable
1
High
Low
High
Low
0
Default
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
I2COPT
High
Low
0
Bit 3
TPPSB
VDD
LDO
0
Bit 2
TPECS
Internal
External
0
Bit 1
-
Bit 0
-
Mnemonic
1
0
High
Low
0
High
Low
0
High
Low
0
High
Low
1
High
Low
1
Default
Bit 15: Not used, set to "0" all the time.
Bit 14 (SHEN): System hold enable bit.
1: Disable
0: Enable
Bits 13~12 (SHCLK1~SHCLK0): System hold clock selection bits (extra 32kHz
source)
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(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
SHCLK1~0
System Hold Clock
4 clocks (default)
2 clocks
00
01
10
11
8 clocks
16 clocks
Bit 11 (BOREN): BOR Enable bit
1: BOR Disable (default)
0: BOR Enable
Bits 10~8 (BORT2~ BORT0)
BORT 2~0
000
BOR Sample Time (µs)
Always On (default)
16000
001
010
011
100
101
110
111
8000
4000
2000
1000
500
250
Bit 7~5: Not used, set to "0" all the time.
Bit 4 (I2COPT): I2C pin optional bit. It is used to switch the pin position of I2C function.
1: Placed I2C pins in P73 (SDA1) and P74 (SCL1).
0: Placed I2C pins in P70 (SDA0) and P71 (SCL0) (default)
*Corresponding with control register Bank 0 R31 I2COPT
Bit 3 (TPPSB): TK power source select bit.
1: TK power source from VDD
0: TK power source from LDO (default)
Bit 2 (TPECS): TPC external capacitor select bit
1: Internal, TPC pin floating.
0: External, TPC pin connect a capacitor to GND. (default)
Bits 1~0: Not used, set to "1" all the time.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
91
eKTF5832
8-Bit Microcontroller
6.13.4 Code Option Register (Word 3)
Word 3
Bit 12
-
Bit 15
-
Bit 14
-
Bit 13
-
Bit 11
-
Bit 10
-
Bit 9
-
Bit 8
-
Mnemonic
1
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
High
Low
0
Default
Bit 7
-
Bit 6
-
Bit 5
ID5
Bit 4
ID4
Bit 3
ID3
Bit 2
ID2
Bit 1
ID1
Bit 0
ID0
Mnemonic
1
0
High
Low
0
High
Low
1
Customer ID
Default
Bits 15~7: Not used, set to "0" all the time
Bit 6: Not used, set to "1" all the time
Bits 5~0 (ID5~ID0): Customer’s ID Code
6.14 Instruction Set
Each instruction in the instruction set is a 15-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2, A", "ADD R2, A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2, A", "BS(C) R2, 6", "CLR R2", etc). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
“LCALL”, “LJMP”, "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip
("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were tested to be true,
are executed within two instruction cycles. The instructions that are written to the
program counter also take two instruction cycles.
Moreover, the instruction set has the following features:
1) Every bit of any register can be directly set, cleared, or tested.
2) The I/O register can be considered as general register. That is; the same instruction
can operate on I/O register.
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eKTF5832
8-Bit Microcontroller
Instruction Set Table:
In the following Instruction Set table, the following symbols are used:
"R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the
register "R", and affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Mnemonic
Operation
Status Affected
NOP
DAA
SLEP
WDTC
ENI
No Operation
Decimal Adjust A
None
C
0 WDT, Stop oscillator
0 WDT
T,P
T,P
Enable Interrupt
None
DISI
Disable Interrupt
None
RET
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
None
RETI
None
ALL Registers
= Reset Value
Flags*
RESET
Software Device Reset
= Reset Value
None
TBWR
INT k
Table Writer Start instruction
PC+1 → [SP], k*2 → PC
Bit Toggle R ; /(R<b>)->R<b>
*Range R5~RA
A R
None
BTG R,b
None
MOV R,A
CLRA
None
0 A
Z
Z
CLR R
0 R
SUB A,R
SUB R,A
DECA R
DEC R
R-A A
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,N
R-A R
R-1 A
R-1 R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
A R A
A R R
Z,N
A & R A
Z,N
A & R R
Z,N
A R A
Z,N
A R R
Z,N
A + R A
Z,C,DC,OV,N
Z,C,DC,OV,N
A + R R
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
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eKTF5832
8-Bit Microcontroller
Mnemonic
Operation
Status Affected
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
R A
R R
Z
Z
/R A
Z,N
/R R
Z,N
R+1 A
Z,C,DC,OV,N
Z,C,DC,OV,N
None
R+1 R
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
R(n) A(n-1),
None
RRCA R
RRC R
C, N
C, N
C, N
C,N
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
RLCA R
RLC R
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
R(0-3) A(4-7),
R(4-7) A(0-3)
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
SWAPA R
None
SWAP R
JZA R
None
None
JZ R
None
BC R,b
BS R,b
JBC R,b
JBS R,b
None <Note2>
None <Note3>
None
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
None
PC+1 [SP],
CALL k
None
(Page, k) PC
(Page, k) PC
k A
JMP k
MOV A,k
JE R
None
None
None
None
None
Z,N
Compare R with ACC, Skip =
Compare R with ACC, Skip >
Compare R with ACC Skip <
A k A
JGE R
JLE R
OR A,k
JE k
Compare K with ACC, Skip =
ROM[(TABPTR)] → R, A
A ← program code (low byte) ;
R ← program code (high byte)
A & k A
None
TBRDA R
AND A,k
None
Z,N
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(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
Mnemonic
Operation
Status Affected
Short jump to K if Carry
if C=1 PC+1+offset → PC
*offset = -128≦k≦127
Short jump to K if Not Carry
if C=0 PC+1+offset → PC
*offset = -128≦k≦127
Short jump to K if Zero
if Z=1 PC+1+offset → PC
*offset = -128≦k≦127
A k A
SJC k
None
None
SJNC k
SJZ k
XOR A,k
SJNZ k
None
Z,N
Short jump to K if Not Zero
if Z=0 PC+1+offset → PC
*offset = -128≦k≦127
R(n) → A(n-1), R(0) → A(7)
R(n) → R(n-1), R(0) → R(7)
k A,
None
RRA R
RR R
N
N
RETL k
None
[Top of Stack] PC
R ←→ A
XCH R
RLA R
None
N
R(n) → A(n+1), R(7) → A(0)
R(n) → R(n+1), R(7) → R(0)
k-A A
RL R
N
SUB A,k
SUBB A,R
SUBB R,A
SBANK k
GBANK k
Z,C,DC,OV,N
Z, C, DC, OV, N
Z, C, DC, OV, N
None
R-A-/C → A
R-A-/C → R
KR1(4)
KR1(3:0)
None
Next instruction : k kkkk kkkk kkkk
PC+1[SP], kPC
Next instruction : k kkkk kkkk kkkk
KPC
LCALL k
LJMP k
None
None
TBRD R
ADD A,k
NEG R
ROM[(TABPTR)] R
k+A A
None
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
2's complement, /R +1 → R
A+R+C → A
ADC A,R
ADC R,A
A+R+C → R
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
95
eKTF5832
8-Bit Microcontroller
7 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
-65C
to
to
to
to
to
to
85C
150C
Vss-0.3V
Vss-0.3V
2.0V
VDD+0.3V
VDD+0.3V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
16 MHz
8 DC Electrical Characteristics
(Ta=25 C, VDD=5.0V5%, VSS=0V)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MHz, 6 MHz, 8 MHz,
12 MHz, 16 MHz, 4 MHz
Fxt
IRC: VDD to 5 V
F
Hz
IRCE
IRC1
IRC2
IRC3
IRC4
IRC5
IRC6
IIL
Internal RC oscillator error per stage
IRC:VDD to 5V
±1
4
1
6
8
12
16
0
%
RCM2~RCM1=000
RCM2~RCM1=001
RCM2~RCM1=010
RCM2~RCM1=011
RCM2~RCM1=100
RCM2~RCM1=101
VIN = VDD, VSS
MHz
MHz
MHz
MHz
MHz
MHz
A
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
Input Leakage Current for input pins
-1
1
0.56
IO_VDD
IO_VDD
+0.3V
0.44
IO_VDD
IO_VDD
+0.3V
VIH1
VIL1
Input High Voltage (Schmitt trigger )
Input Low Voltage (Schmitt trigger )
Ports 5, 6, 7, 8
Ports 5, 6, 7, 8
/RESET
V
-0.3V
V
Input High Threshold Voltage (Schmitt
trigger )
Input Low Threshold Voltage (Schmitt
trigger )
Input High Threshold Voltage (Schmitt
trigger )
Input Low Threshold Voltage (Schmitt
trigger )
0.56
IO_VDD
VIHT1
VILT1
VIHT2
VILT2
IOH1
IOH2
IOH2
IOL1
IOL2
IOL2
IPH
V
0.44
/RESET
-0.3V
V
IO_VDD
IO_VDD
+0.3V
0.44
IO_VDD
0.56
IO_VDD
TCC,INT
V
TCC,INT
-0.3V
-2.5
V
Output High Voltage
(Port 72)
Output High Voltage
(Ports 5, 6, 7, 8)
VOH =
IO_VDD-0.1IO_VDD
mA
mA
mA
mA
mA
mA
A
VOH = IO_VDD-0.1IO_VDD
VOH = IO_VDD-0.1IO_VDD
VOL = GND+0.1IO_VDD
VOL = GND+0.1IO_VDD
VOL = GND+0.1IO_VDD
-3
11
12
14
30
Output High Voltage (high drvie)
(Ports 5, 6, 7, 8)
Output Low Voltage
(Port 72)
Output Low Voltage
(Ports 5, 6, 7, 8)
Output Low Voltage (high sink)
(Ports 5, 6, 7, 8)
Pull-high active, input pin at
VSS
Pull-high current
-80
Pull-low active, input pin at
IO_VDD
/RESET= 'High', Fm & Fs off
IPL
ISB1
96
Pull-low current
30
2
A
A
Power down current
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
(Sleep mode)
All input and I/O pins at
VDD, output pin floating,
WDT disabled
/RESET= 'High', Fm & Fs off
All input and I/O pins at
VDD, output pin floating,
WDT enabled
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type)
output pin floating, WDT
disabled,
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
enabled
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
disabled
Power down current
(Sleep mode)
ISB2
ISB3
ISB4
ICC1
4
4
A
A
A
A
Power down current
(Idle mode)
Power down current
(Idle mode)
4
Operating supply current
(Green mode)
30
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
enabled
/RESET= 'High', Fm=1MHz,
Fs on, output pin floating,
WDT enabled
Operating supply current
(Green mode)
ICC2
ICC4
30
A
Operating supply current
(Normal mode)
500
uA
NOTE
The above parameters are theoretical values only and have not been tested or
verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or
verified.
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
97
eKTF5832
8-Bit Microcontroller
9 AC Electrical Characteristics
(eKTF5832 -40≦ Ta≦ 85C, VDD=5.5V, VSS=0V)
Symbol
Dclk
Parameter
Conditions
Min.
Typ.
50
-
Max.
55
Unit
%
Input CLK duty cycle
Instruction cycle time
TCC input period
-
45
Tins
RC type
500
DC
-
ns
Ttcc
-
(Tins+20)/N*
-
ns
Tdrh
Device reset hold time
/RESET pulse width
-
11.3
2000
11.3
-
16.2
-
21.6
-
ms
ns
Trst
Ta = 25C
Twdt
Tset
Watchdog timer period Ta = 25C
16.2
0
21.6
ms
ns
Input pin setup time
Input pin hold time
Output pin delay time
-
Thold
Tdelay
-
15
20
50
25
55
ns
Cload=20pF
45
ns
* N: Selected prescaler ratio…
NOTE
The above parameters are theoretical values only and have not been tested or
verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or
verified.
98
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eKTF5832
8-Bit Microcontroller
APPENDIX
A Package Type
MCU
Package Type
QFN
Pin Count
32 pins
24 pins
28 pins
28 pins
24 pins
Package Size
5x5x0.8 mm
4x4x0.8 mm
300 mil
eKTF5832QN32
eKTF5832QN24
eKTF5832SO28
eKTF5832SS28
eKTF5832SO24
QFN
SOP
SSOP
SOP
209mil
300 mil
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
The Pb contents are less 100ppm and comply with Sony specifications.
Part No.
eKTF5832 S/J
Pure Tin
Electroplate type
Ingredient (%)
Melting point(°C)
Sn: 100%
232°C
Electrical resistivity
11.4
(µ-cm)
Hardness (hv)
Elongation (%)
8~10
>50%
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
99
eKTF5832
8-Bit Microcontroller
B Package Information
B.1 eKTF5832QN32
Figure B-1 eKTF5832 32-pin QFN Package Type
100
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
B.2 eKTF5832QN24
Figure B-2 eKTF5832 24-pin QFN Package Type
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
101
eKTF5832
8-Bit Microcontroller
B.3 eKTF5832SO28
Symbal
Min
2.370
0.102
0.350
Normal
2.500
Max
2.630
0.300
0.500
A
A1
b
c
E
E1
D
L
0.406
0.254(TYP)
7.500
7.410
10.000
17.700
0.678
7.590
10.650
18.100
1.084
10.325
17.900
0.881
L1
e
1.194
1.397
1.600
1.27(TYP)
θ
0
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 eKTF5832 28-pin SOP Package Type
102
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(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
B.4 eKTF5832SS28
Symbal
Min
Normal
Max
2.130
0.250
1.880
0.380
0.200
8.200
5.600
10.500
1.030
A
A1
A2
b
c
E
E1
D
L
0.050
1.620
0.220
0.090
7.400
5.000
9.900
0.630
1.750
7.800
5.300
10.200
0.900
e
θ
0.650(TYP)
4
0
8
b
e
c
TITLE:
SSOP-28L(209MIL) OUTLINE
PACKAGE PACKA OUTLINE
DIMENSION
File :
Edtion: A
SSO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 eKTF5832 28-pin SSOP Package Type
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
103
eKTF5832
8-Bit Microcontroller
B.5 eKTF5832SO24
Symbal
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
10.000
15.200
0.630
10.650
15.600
1.100
0.838
e
1.27(TYP)
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TITLE:
SOP-24L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SO24
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 eKTF5832 24-pin SOP Package Type
104
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
eKTF5832
8-Bit Microcontroller
C Ordering and Manufacturing Information
eKTF5832QN32J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
SS: SSOP
Product Number
Product Type
F:Flash
Elan 8- bit Product
For example:
eKTF5832QN32J
is eKTF5832with Flash program memory ,
package
in32-pin QFN
‧‧‧‧‧‧‧
Elan Product Number
Batch Number
eKTFaaaa
1041 bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
105
eKTF5832
8-Bit Microcontroller
Ordering Code
KTF5832QN32J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
106
IC Product Specification (V0.4) 09.09. 2019
(This specification is subject to change without prior notice)
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