EM78P156KSO18J [ELAN]
8-Bit Microcontroller with OTP ROM;
| 型号： | EM78P156KSO18J |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller with OTP ROM OTP只读存储器 微控制器 |
| 文件： | 总52页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P156K
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
July 2012
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2010 ~ 2012 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification. Such
information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information
Technology Group
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Flat A, 19F., World Tech Centre 95 (U.S.A.)
How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Korea:
Shenzhen:
Shanghai:
Elan Korea Electronics
Company, Ltd.
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
301 Dong-A Building
632 Kojan-Dong, Namdong-ku Gaoxin South Road 6
8A Floor, Microprofit Building
6F, Ke Yuan Building
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Incheon City, KOREA
Tel: +82 32 814-7730
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Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
General Description.................................................................................................. 1
Features ..................................................................................................................... 1
Pin Assignment ......................................................................................................... 2
Pin Description.......................................................................................................... 3
Block Diagram........................................................................................................... 4
Functional Description ............................................................................................. 5
6.1 Operational Registers......................................................................................... 5
6.1.1 R0 (Indirect Addressing Register).......................................................................5
6.1.2 R1 (Timer Clock / Counter) .................................................................................5
6.1.3 R2 (Program Counter and Stack)........................................................................5
6.1.4 R3 (Status Register)............................................................................................7
6.1.5 R4 (RAM Select Register)...................................................................................7
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)....................................................................................7
6.1.7 RF (Interrupt Status Register).............................................................................7
6.1.8 R10 ~ R3F...........................................................................................................8
6.2 Special Function Registers................................................................................. 8
6.2.1 A (Accumulator)...................................................................................................8
6.2.2 CONT (Control Register).....................................................................................8
6.2.3 IOC5 ~ IOC6 (I/O Port Control Register) ............................................................9
6.2.4 IOCA (Prescaler Counter Register).....................................................................9
6.2.5 IOCB (Pull-down Control Register).....................................................................9
6.2.6 IOCC (Open-drain Control Register).................................................................10
6.2.7 IOCD (Pull-high Control Register).....................................................................10
6.2.8 IOCE (WDT Control Register)........................................................................... 11
6.2.9 IOCF (Interrupt Mask Register)......................................................................... 11
6.3 TCC/WDT and Prescaler.................................................................................. 12
6.4 I/O Ports ........................................................................................................... 13
6.5 Reset and Wake-up.......................................................................................... 17
6.5.1 Reset.................................................................................................................17
6.5.2 Summary of Registers Initialized Values...........................................................19
6.5.3 Status of RST, T, and P of the Status Register..................................................21
6.6 Interrupt............................................................................................................ 22
6.7 Oscillator .......................................................................................................... 23
6.7.1 Oscillator Modes ...............................................................................................23
6.7.2 Crystal Oscillator / Ceramic Resonators (Crystal) ............................................24
6.7.3 External RC Oscillator Mode.............................................................................26
6.7.4 Internal RC Oscillator Mode..............................................................................28
Product Specification (V1.3) 07.25.2012
• iii
Contents
6.8 Code Option Register....................................................................................... 28
6.8.1 Code Option Register (Word 0) ........................................................................28
6.8.2 Code Option Register (Word 1) ........................................................................29
6.8.3 Customer ID Register (Word 2) ........................................................................30
6.9 Power-on Consideration................................................................................... 30
6.10 External Power-on Reset Circuits..................................................................... 31
6.11 Residue-Voltage Protection.............................................................................. 31
6.12 Instruction Set .................................................................................................. 32
7
8
Absolute Maximum Ratings................................................................................... 35
Electrical Characteristics ....................................................................................... 35
8.1 DC Characteristics ........................................................................................... 35
8.2 AC Characteristics............................................................................................ 37
8.3 Device Characteristics...................................................................................... 38
9
Timing Diagrams ..................................................................................................... 42
APPENDIX
A
B
C
D
Ordering and Manufacturing Information ............................................................. 43
Package Type........................................................................................................... 44
Package Information............................................................................................... 45
Quality Assurance and Reliability ......................................................................... 48
C.1 Address Trap Detect......................................................................................... 48
Specification Revision History
Doc. Version
Revision Description
Official Original Specification
Date
1.0
1.1
2012/03/22
2012/04/12
Corrected the package type
1. Modified the numbers of I/O description in the Features
section.
2. Modified the diagram of the data memory configuration
3. Added Ordering and Manufacturing Information
4. Modified the Instruction Table, not the Instruction Set
1.2
1.3
2012/05/11
5. Added diagram of Frequency to Voltage Curve in
Section 8.3 Device Characteristics
6. Modified the part number
7. Modified the description about POR and LVR in the
Features section.
Rectified the part numbers
2012/07/25
iv •
Product Specification (V1.3) 07.25.2012
EM78P156K
8-Bit Microcontroller with OTP ROM
1 General Description
The EM78P156K is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The device has an on-chip 1024 ×13-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three
Code option words are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P156K provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates,
using development and programming tools. Users can avail of the ELAN Writer to easily program their
development code.
2 Features
CPU configuration
• IRC mode:
• 1k × 13 bits on-chip ROM
Drift Rate
Voltage
Internal
RC Freq.
• 48 × 8 bits on-chip registers (SRAM, general
purpose)
Temp.
(-40~85°C)
Process Total
4 MHz
16 MHz
8 MHz
1 MHz
± 1%
± 3% @ 2.1~5.5V ± 2% ± 6%
± 1% @ 4.0~5.5V ± 2% ± 4%
± 2% @ 3.0~5.5V ± 2% ± 5%
± 3% @ 2.1~5.5V ± 2% ± 6%
• 5-level stacks for subroutine nesting
• Less than 1.5 mA at 5V / 4MHz
• Typically 15 µA at 3V / 32kHz
• Typically 1 µA during Sleep mode
± 1%
± 1%
± 1%
Peripheral configuration
I/O port configuration
• 2 bidirectional I/O ports : P5, P6
• 12 I/O pins
• 8-bit real time clock / counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
• Power on reset and 3 programmable level voltage
• Wake-up port : P6
reset
• 5 Programmable pull-down I/O pins (P50 ~
POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
P52, P60 ~ P63)
• 2 / 4 clocks per instruction cycle selected by
code option
• 6 programmable pull-high I/O pins (P60 ~ P67)
• 6 programmable open-drain I/O pins (P60 ~
P67)
• High EFT immunity
Three available interrupts:
• TCC overflow interrupt
• 2 programmable R-option pins
• External interrupt : P60
• Input-port status changed interrupt (wake-up
from sleep mode)
Operating voltage range:
• 2.1V ~ 5.5V at 0 ~ 70 (C (Commercial)
• 2.3V ~ 5.5V at -40 ~ 85 (C (Industrial)
• External interrupt
Special Features
• Programmable free running watchdog timer
• Power saving sleep mode
• Selectable oscillation mode
Package type:
Operating frequency range (base on 2 clocks):
• Crystal mode:
DC ~ 20MHz / 2clks @ 5V
DC ~ 8MHz / 2clks @ 3V
DC ~ 4MHz / 2clks @ 2.1V
• ERC mode:
• 18-pin DIP 300mil
: EM78P156KD18J
• 18-pin SOP 300mil : EM78P156KSO18J
• 20-pin SSOP 209mil : EM78P156KJSS20J
DC ~ 2MHz / 2clks @ 2.1V
Note: These are all Green products which do not
contain hazardous substances.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 1
EM78P156K
8-Bit Microcontroller with OTP ROM
3 Pin Assignment
(1) 18-Pin DIP / SOP
(2) 20-Pin SSOP
Figure 3-1 18-pin EM78P156KD18J/SO18J
Figure 3-2 20-pin EM78P156KJSS20J
2 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
4 Pin Description
Input Output
Name
Function
Description
Type
Type
P53
P53
ST
CMOS Bidirectional I/O pin
P52
P51
P50
P52
P51
P50
Bidirectional I/O pin with programmable
pull-down.
ST
ST
CMOS
P67
P66
P65
P64
P67
P66
P65
P64
Bidirectional I/O pin with programmable
CMOS open-drain, pull-high and pin change
wake-up.
P63
P62
P61
P63
P62
P61
Bidirectional I/O pin with programmable
CMOS pull-down, open-drain, pull-high and pin
change wake-up.
ST
ST
Bidirectional I/O pin with programmable
CMOS pull-down, open-drain, pull-high and pin
change wake-up.
P60
P60//INT
/INT
ST
ST
−
−
−
−
External interrupt pin
TCC
TCC
Real Time Clock/Counter clock input
External pull-high reset pin
/RESET
/RESET
OSCI
ST
XTAL
Clock input of crystal / resonator oscillator
Clock output of internal RC oscillator
OSCI/RCOUT
OSCO/ERCin
RCOUT
OSCO
−
CMOS
XTAL
Clock output of external RC oscillator
(open-drain)
Clock output of crystal / resonator
oscillator
−
ERCin
VDD
AN
−
−
−
External RC input pin
Power
VDD
VSS
Power
Power
VSS
Ground
Legend: ST: Schmitt Trigger input
CMOS: CMOS output
XTAL: oscillation pin for crystal / resonator
AN: analog pin
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 3
EM78P156K
8-Bit Microcontroller with OTP ROM
5 Block Diagram
Figure 5-1 EM78P156K Functional Block Diagram
4 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6 Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer.
Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
6.1.2 R1 (Timer Clock / Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when the TCC register is
written with a value.
6.1.3 R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
000H
008H
Reset Vector
Interrupt Vector
PC (A9 ~ A0)
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Figure 6-1 Program Counter Organization
The configuration structure generates 1024 × 13 bits on-chip OTP ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
R2 is set as all "0" when under RESET condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to go to any location within a page.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 5
EM78P156K
8-Bit Microcontroller with OTP ROM
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 are pushed
onto the stack. Thus, the subroutine entry address can be located anywhere within
a page.
"RET" ("RETLk", "RETI") instruction loads the program counter with the contents of
the top-level stack.
Any instruction written to R2 (e.g. “ADD R2, A＂, "MOV R2, A", "BC R2, 6",⋅etc.)
will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to be cleared. Hence,
the computed jump is limited to the first 256 locations of a page.
All instructions are single instruction cycle (FCLK / 2 or FCLK / 4) except for
instructions that would change the contents of R2. Such instructions will need one
more instruction cycle.
The Data Memory Configuration is as follows:
Address
R Registers
IOC Registers
CONT
(Indirect Addressing Register) Reserve
(Control Register)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R0
R1
R2
R3
R4
R5
R6
(TCC Buffer)
Reserve
Reserve
Reserve
Reserve
IOC5
(Program Counter)
(Status Register)
(RSR)
(Port 5 I/O Data)
(Port 6 I/O Data)
(I/O Port Control Register)
(I/O Port Control Register)
IOC6
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
IOCA
(Prescaler Control Register)
(Pull-down Control Register)
(Open-drain Control Register)
(Pull-high Control Register)
(WDT Control Register)
IOCB
IOCC
IOCD
IOCE
RF
(Interrupt Status Register)
IOCF
(Interrupt Mask Register)
10
:
General Registers
3F
Figure 6-2 Data Memory Configuration
6 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP2
GP1
GP0
T
P
Z
DC
C
Bits 7 ~ 5 (GP2 ~ GP0): General-purpose read / write bits
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0” by
a "SLEP" command.
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bits 7 ~ 6 are not used (read only).
Bits 7 ~ 6 set to “1” at all time.
Bits 5 ~ 0 are used to select registers (Address: 0x00 ~ 0x06, 0x0F ~ 0x3F) in the
indirect addressing mode.
See the Data Memory Configuration in Figure 6-2.
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers.
Only the lower 4 bits of R5 are available.
The upper 4 bits of R5 are fixed to “0”.
6.1.7 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
Note: “ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bits 7 ~ 3: Not used.
Bit 2 (EXIF): External interrupt flag. Set by a falling edge on the /INT pin, reset by
software.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 7
EM78P156K
8-Bit Microcontroller with OTP ROM
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes,
reset by software.
Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows, reset by
software.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
6.1.8 R10 ~ R3F
These are all 8-bit general-purpose registers.
6.2 Special Function Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (GP): General purpose register
Bit 6 (/INT): Interrupt Enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI / RETI instructions
Bit 5 (TS): TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Bit 4 (TE): TCC Signal Edge
0: increment if the transition from low to high takes place on the TCC pin
1: increment if the transition from high to low takes place on the TCC pin
Bit 3 (PAB): Prescaler Assigned Bit
0: TCC
1: WDT
8 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Bits 2 ~ 0 (PSR2 ~ PSR0): TCC / WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
The CONT register is both readable and writable.
6.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
0: defines the relative I/O pin as output
1: puts the relative I/O pin into high impedance
Only the lower 4 bits of IOC5 are available to be defined.
The IOC5 and IOC6 registers are both readable and writable.
6.2.4 IOCA (Prescaler Counter Register)
The IOCA register is readable.
The value of IOCA is equal to the contents of the Prescaler counter.
Down counter.
6.2.5 IOCB (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD63
/PD62
/PD61
/PD60
-
/PD52
/PD51
/PD50
Bit 7 (/PD63): Control bit used to enable pull-down of the P63 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
Bit 3:
Not used. Set to “1” at all time.
Bit 2 (/PD52): Control bit used to enable pull-down of the P52 pin.
Bit 1 (/PD51): Control bit used to enable pull-down of the P51 pin.
Bit 0 (/PD50): Control bit used to enable pull-down of the P50 pin.
The IOCB Register is both readable and writable.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 9
EM78P156K
8-Bit Microcontroller with OTP ROM
6.2.6 IOCC (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Bit 7 (OD67): Control bit used to enable open-drain of the P67 pin.
0: Disable open-drain output
1: Enable open-drain output
Bit 6 (OD66): Control bit used to enable open-drain of the P66 pin.
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin.
Bit 3 (OD63): Control bit used to enable open-drain of the P63 pin.
Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin.
The IOCC Register is both readable and writable.
6.2.7 IOCD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Bit 7 (/PH67): Control bit is used to enable pull-high of the P67 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable pull-high of the P66 pin.
Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin.
Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin.
Bit 3 (/PH63): Control bit used to enable pull-high of the P63 pin.
Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
10 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.2.8 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
ROC
-
-
-
-
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS): Control bit is used to define the function of P60 (/INT) pin.
0: P60, bidirectional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to "1".
When EIS is "0," the path of /INT is masked. When EIS is "1," the status
of /INT pin can also be read by way of reading Port 6 (R6). See Figure
6-6 under Section 6.4 for reference.
EIS is both readable and writable.
Bit 3:
Not used. Set to “1” at all time.
Bit 4 (ROC): ROC is used for the R-option.
Setting the ROC to "1" will enable the status of R-option pins (P50~P51)
that are read by the controller. Clearing the ROC will disable the
R-option function. If the R-option function is selected, user must connect
the P51 pin and/or P50 pin to VSS with a 430K external resistor (Rex). If
the Rex is connected / disconnected, the status of P50 & P51 is read as
"0" / "1". Refer to Figure 6-8 Block Diagram of I/O Port 6 with Input
Change Interrupt/Wake-Up.
Bits 3 ~ 0: Not used. Set to “1” at all time.
6.2.9 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIE
ICIE
TCIE
Bits 7 ~ 3: Not used. Set to “1” at all time.
Individual interrupt is enabled by setting its associated control bit in the
IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. Refer to Figure 6-8 Block Diagram of I/O Port 6 with
Input Change Interrupt/Wake-up.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 11
EM78P156K
8-Bit Microcontroller with OTP ROM
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
The IOCF register is both readable and writable.
6.3 TCC/WDT and Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or the WDT only and the PAB bit of the CONT register is
used to determine the prescaler assignment. The PSR0 ~ PSR2 bits determine the
ratio. The prescaler is cleared each time the instruction is written to TCC under TCC
mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the
“WDTC” or “SLEP” instructions. If the prescaler is earlier assigned to TCC and later
assigned to WDT, or vice versa, the contents of the prescaler counter would be cleared
automatically. Figure 6-4 depicts the circuit diagram of TCC / WDT.
R1 (TCC) is an 8-bit timer / counter. The TCC clock source can be internal or
external clock input (edge selectable from the TCC pin). If the TCC signal source
is from an internal clock, the TCC will be incremented by 1 at every instruction
cycle (without prescaler). Referring to Figure 5-4, CLK = FOSC / 2 or CLK=FOSC / 4,
depends on the Code Option bit CLK. CLK=FOSC / 2 is used if CLK bit is "0", and
CLK=FOSC / 4 is used if CLK bit is "1". If the TCC signal source is from an external
clock input, TCC is incremented by 1 at every falling edge or rising edge of the
TCC pin.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of the IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
1
°
VDD = 5V, WDT time-out period = 16.8ms ± 30% at 25 C
°
VDD = 3V, WDT time-out period = 18ms ± 30% at 25 C
12 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Data Bus
CLK (Fosc/2 or Fosc/4)
0
1
0
M
U
X
M
U
X
TCC
Pin
SYNC
2 cycles
TCC (R1)
1
TE
TS
PAB
TCC Overflow Interrupt
0
M
U
X
8-bit Counter
8-to-1 MUX
WDT
1
PSR0~PSR2
PAB
PAB
0
1
WDTE
(in IOCE)
MUX
WDT Time Out
Figure 6-4 TCC and WDT Block Diagram
6.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bidirectional tri-state I/O ports. Port 6 can
be pulled high internally by software. In addition, Port 6 can also have open-drain
output by software. Input status change interrupt (or wake-up) function is available
from Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O
pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6).
P50 ~ P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to
“1”. When the R-option function is used, it is recommended that P50 ~ P51 are used as
output pins. When R-option is in enable state, P50 ~ P51 must be programmed as
input pins. Under R-option mode, the current / power consumption by REX should be
taken into consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 and Port 6 are shown in the following Figure 6-5 ~ Figure 6-9
respectively.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 13
EM78P156K
8-Bit Microcontroller with OTP ROM
Note: Pull-down is not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for Ports 5 and 6
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-6 I/O Port and I/O Control Register Circuit for P60 (/INT)
14 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
PR
Q
_
Q
D
D
PCWR
CLK
CL
IOD
PR
PORT
Q
_
Q
PDWR
CLK
CL
0
1
M
U
X
TIN
PDRD
PR
D
Q
_
Q
CLK
CL
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-7 I/O Port and I/O Control Register Circuit for P61 ~ P67
Figure 6-8 Block Diagram of I/O Port 6 with Input Change Interrupt / Wake-up
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 15
EM78P156K
8-Bit Microcontroller with OTP ROM
PCRD
ROC
VCC
PR
D
Q
Q
Weakly
Pull-up
CLK
CL
PCWR
PR
CL
Q
Q
D
IOD
PORT
PDWR
PDRD
0
1
M
U
X
Rex*
*Rex is a 430K ohm external resistor
Figure 6-9 Circuit of I/O Port with R-Option (P50, P51)
Table 6-1 Usage of Port 6 Input Change Wake-up / Interrupt Function
Usage of Port 6 Input Status Change Wake-up / Interrupt
(I) Wake-up from Port 6 Input Status Change
(a) Before Sleep
(II) Port 6 Input Status Change Interrupt
1. Read I/O Port 6 (MOV R6,R6)
2. Execute “ENI”
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable interrupt (Set IOCF.1)
5. Execute "SLEP" instruction
(b) After Wake-up
3. Enable interrupt (Set IOCF.1)
4. IF Port 6 change (interrupt)
→ Interrupt vector (008H)
1. IF "ENI" → Interrupt Vector (008H)
2. IF "DISI" → Next instruction
16 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.5 Reset and Wake-up
6.5.1 Reset
A reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) Low Voltage Reset
The device is kept under reset condition for a period of approximately 18 ms or 150 µs
(one oscillator start-up timer period. Events 1 and 4 are approximately 18 ms and
Events 2 and 3 are approximately 150 µs) after a reset is detected. Once a reset
occurs, the following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0."
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
The bits of the IOCA register are set to all "1."
The bits of the IOCB register are set to all "1."
The IOCC register is cleared.
The bits of the IOCD register are set to all "1."
Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.
Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. After a
wake-up, in IRC mode (IRC 4 MHz / 5V) wake-up time 1.5 µs, in XT mode (4 MHz / 5V)
wake-up time is 1.5 ms.
The controller can be awakened by:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) Port 6 Input Status changed (if enabled)
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 17
EM78P156K
8-Bit Microcontroller with OTP ROM
The first two cases will cause the EM78P156K to reset. The T and P flags of R3 are
used to determine the source of the reset (wake-up). The last case is considered a
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 008H after a wake-up. If DISI is executed before SLEP, the
operation will restart from the succeeding instruction right next to SLEP after a
wake-up.
After a wake-up in IRC mode (IRC 4 MHz / 5V), the wake-up time is 1.5 µs, in XT mode
(4 MHz / 5V), the wake-up time is 1.5 ms.
Only one of Cases 2 and 3 can be enabled before going into Sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P156K can be awakened only by Case 1 or
Case 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P156K can be awakened only by Case 1 or Case 2.
Refer to Section 6.6, Interrupt for further details.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P156K (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xxxx1110b
; Select the WDT prescaler, it must be
; set over 1:1
CONTW
WDTC
; Clear WDT and prescaler
; Disable WDT
MOV A, @0xxxxxxxb
IOW RE
MOV R6, R6
MOV A, @00000x1xb
IOW RF
; Read Port 6
; Enable Port 6 input change interrupt
ENI (or DISI)
SLEP
; Enable (or disable) global interrupt
; Sleep
NOTE
After waking up from sleep mode, WDT is automatically enabled. The WDT enable / disable
operation after waking up from sleep mode should be appropriately defined in the software.
18 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.5.2 Summary of Registers Initialized Values
Address Name
Reset Type
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
Power-on
0×00
R0 (IAR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0×01 R1 (TCC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0×02
0×03
R2 (PC)
R3 (SR)
/RESET and WDT
Wake-up from Pin Change Jump to Address 0x08 or continue to execute next instruction
Bit Name
GP2
GP1
GP0
T
1
*
*
-
P
1
*
*
-
Z
U
P
P
-
DC
U
P
C
U
P
P
-
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
/RESET and WDT
Wake-up
P
-
Bit Name
1
1
1
1
1
1
1
P
P
1
P
P
1
P
P
1
P
P
1
P
P
1
P
P
Power-on
0×04 R4 (RSR)
/RESET and WDT
Wake-up
Bit Name
×
1
×
1
×
1
×
1
P53
1
P52
1
P51
1
P50
1
Power-on
0×05
0×06
P5
P6
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P67
1
P66
1
P65
1
P64
1
P63
1
P62
1
P61
1
P60
1
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
×
×
×
×
×
EXIF ICIF TCIF
Power-on
0
0
0
0
0
0
0
P
0
0
0
0
0×0F RF (ISR)
/RESET and WDT
Wake-up from Pin Change
0
0
0
0
0
0
0
0
0
0
P
P
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 19
EM78P156K
8-Bit Microcontroller with OTP ROM
(Continuation)
Address Name
Reset Type
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GP
1
/INT
0
TS
1
TE
1
PAB PSR2 PSR1 PSR0
Power-on
1
1
1
1
1
1
1
1
N/A
N/A
CONT
IOC5
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
1
1
P
P
P
P
P
P
P
P
×
×
×
×
C53
1
C52
1
C51
1
C50
1
Power-on
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
1
1
1
1
0
0
0
0
P
P
P
P
C67
1
C66
1
C65
1
C64
1
C63
1
C62
1
C61
1
C60
1
Power-on
N/A
IOC6
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
-
/PD63 /PD62 /PD61 /PD60
/PD52 /PD51 /PD50
Power-on
1
1
P
1
1
P
1
1
P
1
1
P
1
1
1
1
1
P
1
1
P
1
1
P
0×0B
0×0C
0×0D
0×0E
0×0F
IOCB
/RESET and WDT
Wake-up
Bit Name
OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
0
0
IOCC
/RESET and WDT
Wake-up
P
P
Bit Name
/PH67 /PH66 /PH65 /PH64 /PH63 /PH62 /PH61 /PH60
Power-on
1
1
P
1
1
P
1
1
P
-
1
1
1
1
P
-
1
1
P
-
1
1
P
-
1
1
P
-
IOCD
/RESET and WDT
Wake-up
P
ROC
Bit Name
WDTE EIS
Power-on
1
1
1
×
1
1
1
-
0
0
P
×
1
1
1
-
1
1
1
×
1
1
1
-
1
1
P
×
1
1
1
-
1
1
1
×
1
1
1
-
1
1
1
1
1
1
1
1
1
IOCE
/RESET and WDT
Wake-up
Bit Name
EXIE ICIE TCIE
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
IOCF
/RESET and WDT
Wake-up
Bit Name
0×10~
0×3F
Power-on
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
R10~R3F
/RESET and WDT
Wake-up
Legend: ×: Not used U: Unknown or don’t care P: Previous value before reset
* Refer to the tables provided in the next section (Section 6.5.3).
20 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.5.3 Status of RST, T, and P of the Status Register
A Reset condition is initiated by the following events
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
The values of T and P listed in the table below are used to check how the processor
wakes up.
Table 6-2 Values of RST, T, and P after a Reset
Reset Type
RST
T
P
0
1
1
Power on
0
0
0
0
1
*P
1
*P
0
/RESET during Operation mode
/RESET wake-up during Sleep mode
WDT during Operation mode
0
*P
0
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
1
0
* P: Previous status before reset
The following table shows the events that may affect the status of T and P.
Table 6-3 Status of T and P Being Affected by Events
Event
RST
T
P
0
1
1
Power on
*P
0
1
0
1
1
1
*P
0
WDTC instruction
WDT time-out
SLEP instruction
*P
1
0
Wake-up on pin change during Sleep mode
* P: Previous status before reset
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 21
EM78P156K
8-Bit Microcontroller with OTP ROM
Figure 6-10 Controller Reset Block Diagram
6.6 Interrupt
The EM78P156K has three interrupts as listed below:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV
R6, R6") is necessary. Each pin of Port 6 will have this feature if its status changes.
Any pin configured as output or P60 pin configured as /INT is excluded from this
function. The Port 6 Input Status Changed Interrupt can wake up the EM78P156K from
Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP
instruction. When the IC wakes-up, the controller will continue to execute the program
in-line if the global interrupt is disabled. If the global interrupt is enabled, it will branch
to the interrupt Vector 008H.
RF is the interrupt status register that records the interrupt requests in the relative flags/
bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI
instruction and is disabled by the DISI instruction. When one of the interrupts (enabled)
occurs, the next instruction will be fetched from Address 008H. Once in the interrupt
service routine, the source of an interrupt can be determined by polling the flag bits in
RF. The interrupt flag bit must be cleared by instructions prior to leaving the interrupt
service routine before interrupts are enabled to avoid recursive interrupts.
22 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 6-11 Interrupt Input Circuit). The RETI
instruction ends the interrupt routine and enables the global interrupt (the execution of
ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from Address 001H.
Figure 6-11 Interrupt Input Circuit Diagram
6.7 Oscillator
6.7.1 Oscillator Modes
The EM78P156K can be operated in four different oscillator modes, such as External
RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator
mode (XT, HXT1/2), and Low Crystal oscillator mode (LXT1/2). The desired mode can
be selected by programming OSC3 ~ OSC0 in the Code Option register. Table 6-4
shows how these four oscillator modes are defined.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 23
EM78P156K
8-Bit Microcontroller with OTP ROM
Table 6-4 Oscillator Modes Defined by OSC
Oscillator Modes
OSC3 OSC2 OSC1 OSC0
ERC1 (External RC oscillator mode); RCOUT is deactivated
ERC1 (External RC oscillator mode); RCOUT is activated
IRC2 (Internal RC oscillator mode); RCOUT is deactivated
IRC2 (Internal RC oscillator mode); RCOUT is activated
LXT13 (Frequency range of LXT1 mode is 1MHz ~ 100kHz)
HXT13 (Frequency range of HXT1 mode is 20 MHz ~ 12 MHz)
LXT23 (Frequency range of LXT2 mode is 32.768kHz)
HXT23 (Frequency range of HXT2 mode is 12 MHz ~ 6 MHz)
XT (Frequency range of XT mode is 6 MHz ~ 1 MHz) (default)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1 In ERC mode, ERCin is used as oscillator pin. RCOUT is defined by Code Option Word 1
Bit 4 ~ Bit 1.
2 In IRC mode, RCOUT is defined by code option Word 1 Bit 4 ~ Bit 1.
3 In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
The maximum operational frequency of the crystal / resonator under different VDD is
listed below.
Table 6-5 Summary of the Maximum Operating Speeds
Conditions
VDD
2.1
Max Freq. (MHz)
4.0
8.0
Two cycles with two clocks
3.0
5.0
20.0
6.7.2 Crystal Oscillator / Ceramic Resonators (Crystal)
The EM78P156K can be driven by an external clock signal through the OSCI pin as
shown in the following figure.
OSCI
Ext. Clock
OSCO
EM78P156K
Figure 6-12 Circuit for External Clock Input
24 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-13 depicts such a circuit. The
same thing applies whether it is in the HXT mode or in the LXT mode.
In Figure 6-14, when the connected resonator in OSCI and OSCO is used in
applications, the 1 MΩ R1 needs to be shunted with a resonator.
C1
OSCI
EM78P156K
Crystal
OSCO
C2
RS
Figure 6-13 Circuit for Crystal / Resonator
C1
OSCI
Resonator
EM78P156K
R1
OSCO
C2
Figure 6-14 Circuit for Crystal / Resonator
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, refer to its specification for appropriate values of C1 and
C2. A serial resistor RS, may be necessary for AT strip cut crystal or low frequency
mode.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 25
EM78P156K
8-Bit Microcontroller with OTP ROM
Table 6-6 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
100 kHz
200 kHz
455 kHz
1 MHz
C1 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
40pF
60pF
60pF
40pF
30pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
30pF
20pF
15pF
C2 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
40pF
60pF
60pF
40pF
30pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
30pF
20pF
15pF
LXT1
(100k ~ 1 MHz)
Ceramic Resonators
1.0 MHz
2.0 MHz
4.0 MHz
32.768 kHz
100 kHz
200 kHz
455 kHz
1 MHz
XT
(1M~6 MHz)
LXT2 (32.768kHz)
LXT1
(100k ~ 1 MHz)
455 kHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
10.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
XT
(1 ~ 6 MHz)
Crystal Oscillator
HXT2
(6 ~ 12 MHz)
HXT1
(12 ~ 20 MHz)
6.7.3 External RC Oscillator Mode
For some applications that do not require a very precise timing calculation, the RC
oscillator (Figure 6-15) offers a cost-effective oscillator configuration. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by the supply
voltage, the values of the resistor (REXT), the capacitor (CEXT), and even by the
operation temperature. Moreover, the frequency also changes slightly from one chip to
another due to manufacturing process variations.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of REXT should not be greater than 1 MΩ. If they
cannot be kept in this range, the frequency can be easily affected by noise, humidity,
and leakage.
26 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
The smaller the REXT in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low REXT values, for instance, 1 kΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
Rext
ERCin
Cext
EM78P156K
Figure 6-15 External RC Oscillator Mode Circuit
Table 6-7 RC Oscillator Frequencies
Average Fosc
Average Fosc
Cext
Rext
5V, 25°C
3V, 25°C
3.3k
5.1k
10k
2.064 MHz
1.403 MHz
750 kHz
1.901 MHz
1.316 MHz
719.7 kHz
81.33 kHz
615.1 MHz
414.3 kHz
219.8 kHz
23.96 kHz
245.3 kHz
163.0 kHz
86.14 kHz
9.255 kHz
20pF
100k
3.3k
5.1k
10k
81.45 kHz
647.3 kHz
430.8 kHz
225.8 kHz
23.88 kHz
256.6 kHz
169.5 kHz
88.53 kHz
9.283 kHz
100pF
300pF
100k
3.3k
5.1k
10k
100k
Note: 1: These are measured in DIP packages.
2. The values are for design reference only.
3. The frequency drift is ± 30%.
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 27
EM78P156K
8-Bit Microcontroller with OTP ROM
6.7.4 Internal RC Oscillator Mode
EM78P156K offers a versatile internal RC mode with default frequency value of 4 MHz.
The Internal RC oscillator mode has other frequencies (1 MHz, 8 MHz, and 16 MHz)
that can be set by Code Option (Word 1), RCM1, and RCM0. All these four main
frequencies can be calibrated by programming the Option Bits C0 ~ C4. The table
below describes the EM78P156K internal RC drift with variation of voltage,
temperature, and process.
Table 6-8 Internal RC Drift Rate (TA = 25°C, VDD = 5V, VSS = 0V)
Drift Rate
Internal RC
Temperature
(-40°C ~ 85°C)
Voltage
(2.1V ~ 5.5V)
Process
Total
4 MHz
16 MHz
8 MHz
1 MHz
± 1%
± 1%
± 1%
± 1%
± 3% @ 2.1~5.5V
± 1% @ 4.0~5.5V
± 2% @ 3.0~5.5V
± 3% @ 2.1~5.5V
± 2%
± 2%
± 2%
± 2%
± 6%
± 4%
± 5%
± 6%
Note: These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
6.8 Code Option Register
The EM78P156K has a Code Option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register Arrangement Distribution:
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
6.8.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bits 2~0
Protect
Disable
Enable
Mnemonic
−
−
−
ENWDT CLKS LVR1 LVR0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
0
Disable 4clocks High
Enable 2clocks Low
High
Low
Bit 12: Not used. Set to “1” at all time.
Bit 11 (ENWDT): Watchdog timer enable bit
0: Enable
1: Disable
28 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Bit 10 (CLKS): Instruction period option bit.
0: Two oscillator periods
1: Four oscillator periods
Refer to the Instruction Set section.
Bits 9 ~ 8 (LVR1 ~ LVR0): Low Voltage Reset control bits
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.0V
Bits 7 ~ 3: Not used. Set to “1” at all time.
Bits 2 ~ 0 (Protect): Protect Bits. Each protect status is as follows:
Protect Bits
Protect
Enable
0
1
Disable (Default)
6.8.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic HLP
C4
High High High High High High High High High High High High
Low Low Low Low Low Low Low Low Low Low Low Low
C3
C2 C1 C0 RCM1 RCM0 OSC3 OSC2 OSC1 OSC0
−
−
−
1
0
Bit 12 (HLP): Power consumption mode
0: Low power consumption mode, applies to operating frequency at
400kHz or below 400kHz
1: High power consumption mode, applies to operating frequency above
400kHz (default)
Bits 11 ~ 7 (C4 ~ C0): Internal RC mode Calibration bits. These bits must always be
set to “1” only (auto calibration)
Bits 6 ~ 5 (RCM1 ~ RCM0): RC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
1
1
0
0
1
0
1
0
4
16
8
1
* Theoretical values, for reference only
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 29
EM78P156K
8-Bit Microcontroller with OTP ROM
Bits 4 ~ 1 (OSC3, ~ OSC0): Oscillator Mode Select bits
Oscillator Modes
OSC3 OSC2 OSC1 OSC0
ERC1 (External RC oscillator mode); RCOUT is deactivated
ERC1 (External RC oscillator mode); RCOUT is activated
IRC2 (Internal RC oscillator mode); RCOUT is deactivated
IRC2 (Internal RC oscillator mode); RCOUT is activated
LXT13 (Frequency range of LXT1 mode is 1MHz ~ 100kHz)
HXT13 (Frequency range of HXT1 mode is 20 MHz ~ 12 MHz)
LXT23 (Frequency range of LXT2 mode is 32.768kHz)
HXT23 (Frequency range of HXT2 mode is 12 MHz ~ 6 MHz)
XT (Frequency range of XT mode is 6 MHz ~ 1 MHz) (default)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1 In ERC mode, ERCin is used as oscillator pin. RCOUT is defined by code option Word 1
Bit 4 ~ Bit 1.
2 In IRC mode, RCOUT is defined by code option Word 1 Bit 4 ~ Bit 1.
3 In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
Bit 0: Not used. Set to “1” at all time.
6.8.3 Customer ID Register (Word 2)
Word 2
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Mnemonic ID12 ID11 ID10 ID9
1
0
High High High High High High High High High High High High High
Low Low Low Low Low Low Low Low Low Low Low Low Low
Bits 12 ~ 0: Customer’s ID code
6.9 Power-on Consideration
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes at its steady state.
EM78156K POR voltage range is 1.7V ~ 1.9V. Under customer application, when
power is OFF, VDD must drop to below 1.8V and remains OFF for 10 µs before power
can be switched ON again. This way, the EM78P156K will reset and operate normally.
The extra external reset circuit will work well if VDD can rise at very fast speed (50 ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problems.
30 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
6.10 External Power-on Reset Circuits
The circuitry in the figure
implements an external RC
to produce the reset pulse.
The pulse width (time
constant) should be kept
long enough for Vdd to
reach minimum operation
voltage. This circuit is
used when the power
supply has a slow rise
time.
Vdd
R
C
/RESET
D
EM78P156K
Rin
Figure 6-16 External Power-up Reset Circuit
Since the current leakage from the /RESET pin is ± 5 μA, it is recommended that R
should not be greater than 40k. In this way, the /RESET pin voltage is held below 0.2V.
The diode (D) acts as a short circuit at the moment of power down. The capacitor C will
discharge rapidly and fully. The current-limited resistor, Rin, will prevent high current or
ESD (electrostatic discharge) from flowing to pin /RESET.
6.11 Residue-Voltage Protection
When the battery is replaced, the device power (VDD) is cut off but the residue-voltage
remains. The residue-voltage may trip below the minimum Vdd, but not to zero. This
condition may cause a poor power-on reset. The following figures illustrate two
recommended methods on how to build a residue-voltage protection circuit for the
EM78P156K.
Vdd
Vdd
33K
EM78P156K
/RESET
Q1
10K
100K
1N4684
Figure 6-17 Residue Voltage Protection Circuit 1
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 31
EM78P156K
8-Bit Microcontroller with OTP ROM
Vdd
Vdd
R1
R2
EM78P156K
/RESET
Q1
R3
Figure 6-18 Residue Voltage Protection Circuit 2
NOTE
Figure 6-17 and Figure 6-18 should be designed to ensure that the voltage of the
/RESET pin is larger than VIH (min)
6.12 Instruction Set
Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instruction "MOV R2, A", "ADD R2, A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2, A", "BS(C) R2, 6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
A) Modify one instruction cycle to consist of four oscillator periods.
B) "JMP", "CALL", "RET", "RETL", "RETI" or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ”, "DJZA") commands which were tested to be true, are executed within
one instruction cycle. The instructions that are written to the program counter also
take one instruction cycle.
Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists
of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.
Note that once the four oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK = FOSC / 4, instead of FOSC / 2.
32 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Moreover, the instruction set has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register “R” and which
affects the operation.
k = 8 or 10-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
None
C
DAA
Decimal Adjust A
A → CONT
CONTW
SLEP
None
T, P
T, P
None 1
None
None
None
None
None
None 1
None
Z
0 → WDT, Stop oscillator
0 → WDT
WDTC
IOW R
ENI
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable Interrupt
CONT → A
DISI
RET
RETI
CONTR
IOR
R
IOCR → A
MOV R, A
CLRA
A → R
0 → A
CLR R
0 → R
Z
SUB A, R
SUB R, A
DECAR
R - A → A
Z, C, DC
Z, C, DC
Z
R - A → R
R - 1 → A
DEC R
R - 1 → R
Z
OR A, R
OR R, A
AND A, R
AND R, A
A ∨ R → A
Z
A ∨ R → R
Z
A & R → A
Z
A & R → R
Z
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 33
EM78P156K
8-Bit Microcontroller with OTP ROM
(Continuation)
Mnemonic
XOR A, R
XOR R, A
ADD A, R
ADD R, A
MOV A, R
MOV R, R
COMAR
Operation
Status Affected
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
Z
Z
Z, C, DC
Z, C, DC
Z
R → R
Z
Z
/R → A
COM R
/R → R
Z
INCA R
R + 1 → A
R + 1 → R
Z
INC
DJZA R
DJZ
R
Z
R - 1 → A, skip if zero
R - 1 → R, skip if zero
None
None
R
R(n) → A(n - 1),
R(0) → C, C → A(7)
RRCAR
RRC R
RLCAR
RLC R
C
C
R(n) → R(n - 1),
R(0) → C, C → R(7)
R(n) → A(n + 1),
R(7) → C, C → A(0)
C
R(n) → R(n + 1),
R(7) → C, C → R(0)
C
R(0-3) → A(4 - 7),
R(4-7) → A(0 - 3)
SWAPAR
SWAPR
None
R(0-3) ↔ R(4 - 7)
R + 1 → A, skip if zero
R + 1 → R, skip if zero
0 → R(b)
None
None
JZA
JZ
R
R
None
BC R, b
BS R, b
JBC R, b
JBS R, b
None 2
None 3
None
1 → R(b)
if R(b) = 0, skip
if R(b) = 1, skip
None
PC + 1 → [SP],
(Page, k) → PC
CALL k
None
JMP k
(Page, k) → PC
k → A
None
MOV A, k
OR A, k
AND A, k
XOR A, k
None
A ∨ k → A
A & k → A
A ⊕ k → A
Z
Z
Z
34 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
(Continuation)
Mnemonic
Operation
Status Affected
k → A,
[Top of Stack] → PC
RETL k
None
SUB A, k
INT
K - A → A
Z, C,DC
None
PC + 1 ® [SP], 001H ® PC
K + A → A
ADD A, k
Z, C, DC
Note: 1 This instruction is applicable to IOC5 ~ IOC6, IOCA ~ IOCF only.
2 This instruction is not recommended for interrupt status register operation.
3 This instruction cannot operate under interrupt status register.
7 Absolute Maximum Ratings
Items
Rating
°
°
85 C
Temperature under bias
Storage temperature
Input voltage
-40 C
to
to
to
to
to
to
°
°
-65 C
150 C
Vss-0.3V
Vss-0.3V
2.1V
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
20 MHz
*
Note: These parameters are theoretical values and have not been tested.
8 Electrical Characteristics
8.1 DC Characteristics
TA = 25°C, VDD = 5V, VSS = 0V
Symbol
Parameter
Crystal: VDD to 2.1V
Condition
Min. Typ. Max. Unit
Two cycles with two clocks DC
Two cycles with two clocks DC
Two cycles with two clocks DC
−
−
−
4.0 MHz
8.0 MHz
20.0 MHz
FXT
Crystal: VDD to 3V
Crystal: VDD to 5V
ERC ERC: VDD to 5V
R: 5kΩ, C: 39pF
VIN = VDD, VSS
Ports 5, 6
F±30% 1500 F±30% kHz
IIL
Input Leakage Current for input pins
−
2.0
−
−
−
−
±1
−
µA
V
VIH1 Input High Voltage (VDD=5V)
VIL1 Input Low Voltage (VDD=5V)
Ports 5, 6
0.8
V
/RESET, TCC
(Schmitt trigger)
VIHT1 Input High Threshold Voltage (VDD=5V)
VILT1 Input Low Threshold Voltage (VDD=5V)
2.0
−
−
−
V
V
/RESET, TCC
(Schmitt trigger)
−
0.8
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 35
EM78P156K
8-Bit Microcontroller with OTP ROM
(Continuation)
Symbol
Parameter
Condition
Min. Typ.
Max. Unit
VIHX1 Clock Input High Voltage (VDD=5V) OSCI
VILX1 Clock Input Low Voltage (VDD=5V) OSCI
2.5
−
−
−
−
−
Vdd+0.3
1.0
V
V
V
V
VIH2 Input High Voltage (VDD=3V)
VIL2 Input Low Voltage (VDD=3V)
Ports 5, 6
Ports 5, 6
1.5
−
−
0. 4
Input High Threshold Voltage
(VDD=3V)
/RESET, TCC
(Schmitt trigger)
VIHT2
1.5
−
−
−
V
V
Input Low Threshold Voltage
(VDD=3V)
/RESET, TCC
(Schmitt trigger)
VILT2
−
0.4
VIHX2 Clock Input High Voltage (VDD=3V) OSCI
VILX2 Clock Input Low Voltage (VDD=3V) OSCI
Output High Voltage
1.5
−
−
−
V
V
−
0.6
VOH1
IOH = -12mA
2.4
−
−
V
V
(Ports 5, Ports 6)
Output Low Voltage
VOL1 (P50 ~ 53 and Port 6)
(Schmitt trigger)
IOL = 12mA
−
−
0.4
Pull-high active,
Input pin at VSS
IPH
IPD
Pull-high current
Pull-down current
60
20
75
35
90
50
µA
µA
Pull-down active,
Input pin at VDD
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB1 Power down current
ISB2 Power down current
−
−
−
−
1
µA
µA
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
10
/RESET = 'High', FOSC=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
Operating supply current
ICC1
−
15
20
µA
at two clocks (VDD=3V)
WDT disabled
/RESET = 'High', FOSC=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
Operating supply current
ICC2
−
−
−
15
−
25
1.5
2.8
µA
mA
mA
at two clocks (VDD=3V)
WDT enabled
/RESET = 'High', FOSC=4 MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current at two
clocks (VDD=5.0V)
ICC3
/RESET = 'High',
FOSC = 10 MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current at two
clocks (VDD=5.0V)
ICC4
−
*
Note: These parameters are theoretical values and have not been tested.
36 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Internal RC Electrical Characteristics (TA = 25°C, VDD = 5 V, VSS = 0V)
Drift Rate
Temperature Operating Voltage
Internal RC
Selected Band
4 MHz
Min.
3.92 MHz
Typ.
Max.
25°C
25°C
25°C
25°C
5V
5V
5V
5V
4 MHz
4.08 MHz
16 MHz
15.68 MHz 16 MHz 16.32 MHz
8 MHz
7.84 MHz
0.98 MHz
8 MHz
1 MHz
8.16 MHz
1.02 MHz
1 MHz
Internal RC Electrical Characteristics (Process, Voltage and Temperature
Deviation)
Drift Rate (Process & Operating Voltage and Temperature Variation)
Internal RC
Selected Band
Temperature
-40 ~ 85°C
-40 ~ 85°C
-40 ~ 85°C
-40 ~ 85°C
Operating Voltage
2.1V ~ 5.5V
Min.
Typ.
Max.
4 MHz
16 MHz
8 MHz
1 MHz
3.76 MHz
4 MHz
4.24 MHz
4.0V ~ 5.5V
15.36 MHz 16 MHz 16.64 MHz
3.0V ~ 5.5V
7.60 MHz
0.94 MHz
8 MHz
1 MHz
8.40 MHz
1.06 MHz
2.1V ~ 5.5V
8.2 AC Characteristics
TA=25°C, VDD=5V, VSS=0V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
%
Dclk
Input CLK duty cycle
−
Crystal type
RC type
−
45
50
−
55
DC
DC
−
100
ns
Instruction cycle time
(CLKS="0")
Tins
500
−
ns
Ttcc
Tdrh
Trst
TCC input period
(Tins + 20)/N*
−
ns
Device reset hold time XTAL
/RESET pulse width
16.8 - 30%
16.8 16.8 + 30% ms
ns
16.8 16.8 + 30% ms
−
2000
−
−
Twdt
Tset
Thold
Watchdog timer period
Input pin setup time
−
16.8 - 30%
−
−
−
−
0
−
−
−
ns
ns
ns
Input pin hold time
−
20
50
Tdelay Output pin delay time
CLOAD = 20pF
Note: These parameters are theoretical values and have not been tested.
The Watchdog Timer duration is determined by Option Code (Bit 6, Bit 5)
*N = selected prescaler ratio
*Twdt: In Crystal mode the WDT time-out length is the same as the set-up time (18 ms).
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 37
EM78P156K
8-Bit Microcontroller with OTP ROM
8.3 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristics illustrated
herein are not guaranteed for its accuracy. In some graphs, the data may be out of the
specified warranted operating range.
Volt. to Freq. Curve (1MHz)
1060
1040
1020
1000
980
Chip
Package
960
940
2
2.5
3
3.5
4
4.5
5
5.5
Volt. (V)
38 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Volt. to Freq. Curve (4MHz)
4160
4110
4060
4010
3960
3910
3860
3810
3760
3710
Chip
Package
2
2.5
3
3.5
4
4.5
5
5.5
Volt. (V)
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 39
EM78P156K
8-Bit Microcontroller with OTP ROM
Volt. to Freq. Curve (8MHz)
8420
8320
8220
8120
8020
7920
7820
7720
7620
7520
Chip
Package
3
3.5
4
4.5
Volt. (V)
5
5.5
40 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
Volt. to Freq. Curve (16MHz)
16840
16640
16440
16240
16040
15840
15640
15440
15240
15040
Chip
Package
4
4.5
5
5.5
Volt. (V)
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 41
EM78P156K
8-Bit Microcontroller with OTP ROM
9 Timing Diagrams
AC Test Input / Output Waveform
Note: AC Testing: Input are driven at 2.4V for logic “1”, and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1”, and 0.8V for logic “0”
Figure 9-1a AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK = "0")
Figure 9-1b Reset Timing Diagram
TCC Input Timing (CLKS = "0")
Figure 9-1c TCC Input Timing Diagram
42 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
APPENDIX
A Ordering and Manufacturing Information
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 43
EM78P156K
8-Bit Microcontroller with OTP ROM
B Package Type
OTP MCU
EM78P156KD18J
EM78P156KSO18J
EM78P156KJSS20J
Package Type
DIP
Pin Count
Package Size
300 mil
18
18
20
SOP
300 mil
SSOP
209 mil
For product code "J".
These are Green products and comply with RoHS specifications
Part No.
Electroplate type
Ingredient (%)
EM78P156K
Pure Tin
Sn: 100%
°
°
Melting point ( C)
232 C
Electrical resistivity (µΩ-cm)
Hardness (hv)
11.4
8 ~ 10
> 50%
Elongation (%)
44 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
C Package Information
20-Lead Shrink Small Outline Package (SSOP) — 209 mil
Symbol
Min
Normal
Max
2.130
0.250
1.880
0.380
0.200
8.200
5.600
7.500
0.850
A
A1
A2
b
c
E
E1
D
L
0.050
1.620
0.220
0.090
7.400
5.000
6.900
0.650
1.750
7.800
5.300
7.200
0.750
1.250(REF )
0.650(TYP)
4
L1
e
0
8
θ
b
e
c
L1
File :
SSOP20
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-1a EM78P156K 20-Lead SSOP Package Type
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 45
EM78P156K
8-Bit Microcontroller with OTP ROM
18-Lead Plastic Dual In–line Package (DIP) — 300 mil
Symbol
A
Min Normal Max
4.450
0.381
3.175
A1
A2
c
3.302
3.429
0.203 0.254 0.356
22.610 22.860 23.110
D
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
E1
E
eB
B
B1
L
e
θ
0.356 0.457 0.559
1.143 1.524 1.778
3.048 3.302 3.556
2.540(TYP)
eB
0
15
File :
Edtion: A
D18
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-1c EM78P156K 18-Lead DIP Package Type
46 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
EM78P156K
8-Bit Microcontroller with OTP ROM
18-Lead Small Outline Package (SOP) — 300 mil
Symbol
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
0.230
7.400
0.320
7.600
c
E
10.000
11.350
0.406
10.650
11.750
1.270
H
D
L
0.838
1.27(TYP)
e
θ
0
8
b
e
c
File :
SO18
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-1d EM78P156K 18-Lead SOP Package Type
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
• 47
EM78P156K
8-Bit Microcontroller with OTP ROM
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature = 245 ± 5°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
–
Step 1: TCT, 65°C (15 min) ~ 150°C (15 min), 10 cycles
Step 2: Bake at 125°C, TD (endurance) = 24 hrs
Step 3: Soak at 30°C / 60%, TD (endurance) = 192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness ≥ 2.5 mm or
Pkg volume ≥ 350 mm3 ---- 225 ± 5°C)
(Pkg thickness ≤ 2.5 mm or
Pkg volume ≤ 350 mm3 ---- 240 ± 5°C)
Temperature cycle
test
-65°C (15 min) ~ 150°C (15 min), 200 cycles
–
–
–
–
TA = 121°C, RH = 100%, pressure = 2 atm,
TD (endurance) = 96 hrs
Pressure cooker test
High temperature /
High humidity test
TA = 85°C , RH = 85%, TD (endurance) = 168 , 500 hrs
TA = 150°C, TD (endurance) = 500, 1000 hrs
High-temperature
storage life
High-temperature
operating life
TA = 125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA = 25°C, VCC = Max. operating voltage, 800mA / 40V
ESD (HBM)
TA = 25°C, ≥∣± 4kV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (MM)
TA = 25°C, ≥ ∣± 400V∣
VDD-VSS(+),VDD_VSS
(-) mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
48 •
Product Specification (V1.3) 07.25.2012
(This specification is subject to change without further notice)
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