EM78P507NQ44 [ELAN]
8-Bit Microcontroller;
| 型号： | EM78P507NQ44 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总104页 (文件大小：2858K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P507N
8-Bit Microcontroller
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
April 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road Elan (HK) Microelectronics
Elan Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
General Description ...................................................................................... 1
Features ......................................................................................................... 1
Pin Assignment.............................................................................................. 2
Pin Description .............................................................................................. 4
4.2 EM78P507N LQFP/QFP 44 pins.......................................................................4
4.1 EM78P507N LQFP 48 Pins ..............................................................................6
5
6
Block Diagram ............................................................................................... 8
Function Description..................................................................................... 9
6.1 Operational Registers .......................................................................................9
6.1.1 R0 (Indirect Addressing Register) .......................................................................9
6.1.2 R1 (ROM Page and RAM Bank Select Register)................................................9
6.1.3 R2 (Program Counter) and Stack........................................................................9
6.1.4 R3 (Status Register)..........................................................................................12
6.1.5 R4 (RAM Select Register).................................................................................12
6.1.6 Bank 0 R5 TBLP (Low Byte of Table Pointer Register).....................................13
6.1.7 Bank 0 R6 TBHP (High Byte of Table Pointer Register) ...................................13
6 1.8 Bank 0 R7 ~ RB (Port 7 ~ Port B) .....................................................................13
6.1.9 Bank 0 RC SOCR (System Clock Control Register).........................................13
6.1.10 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)...........................14
6.1.11 Bank 0 RE IMR (Interrupt Mask Register).........................................................15
6.1.12 Bank 0 RF ISR (Interrupt Status Register)........................................................15
6.1.13 Bank 1 R5 ADCR1 (A/D Control Register 1).....................................................16
6.1.14 Bank 1 R6 ADCR2 (A/D Control Register)........................................................16
6.1.15 Bank 1 R7 ADDL (A/D Low 8-Bit Data Buffer)...................................................17
6.1.16 Bank 1 R8 ADDH (A/D High 8-Bit Data Buffer).................................................17
6.1.17 Bank 1 R9 ADIC1 (A/D Input Control Register 1) .............................................18
6.1.18 Bank 1 RAADIC2 (A/D Input Control Register 2) .............................................18
6.1.19 Bank 1 RB ADIC3 (A/D Input Control Register 3) .............................................18
6.1.20 Bank 1 RC COCR (Clock Output Control Register)..........................................18
6.1.21 Bank 1 RE EIMR (External Interrupt Mask Register)........................................19
6.1.22 Bank 1 RF EISR (External Interrupt Status Register) .......................................19
6.1.23 Bank 2 R5 T1CR (Timer 1 Control Register) ....................................................19
6.1.24 Bank 2 R6 TSR (Timer 1 Status Register) ........................................................20
6.1.25 Bank 2 R7 T1PD (Timer 1 Period Buffer)..........................................................21
6.1.26 Bank 2 R8 T1TD (Timer 1 Duty Buffer).............................................................21
6.1.27 Bank 2 R9 T2CR (Timer 2 Control Register) ....................................................21
6.1.28 Bank 2 RA T2PD (Timer 2 Period Buffer)..........................................................22
6.1.29 Bank 2 RB T2TD (Timer 2 Duty Buffer).............................................................22
Product Specification (V1.1) 04.08.2016
iii
Contents
6.1.30 Bank 2 RC T3CR1 (Timer 3 Control Register 1)...............................................22
6.1.31 Bank 2 RD T3CR2 (Timer 3 Control Register 2)...............................................23
6.1.32 Bank 2 RE T3PD (Timer 2 Period Buffer) .........................................................23
6.1.33 Bank 2 RF TCC (Timer Clock/Counter).............................................................23
6.1.34 Bank 3 R5 URC (UART Control Register) ........................................................24
6.1.35 Bank 3 R6 URS (UART Status).........................................................................24
6.1.36 Bank 3 R7 URRD (UART_RD Data Buffer) ......................................................25
6.1.37 Bank 3 R8 URTD (UART_TD Data Buffer) .......................................................25
6.1.38 Bank 3 R9 URC1 (UART Status).......................................................................25
6.1.39 Bank 3 RA SPIS (SPI Status Register) .............................................................26
6.1.40 Bank 3 RB SPIC (SPI Control Register) ...........................................................27
6.1.41 Bank 3 RC SPIR (SPI Read Buffer)..................................................................28
6.1.42 Bank 3 RD SPIW (SPI Write Buffer)..................................................................28
6.1.43 Bank 3 RE EIESH (External Interrupt Edge Select Control Register) ..............28
6.1.44 Bank 3 RF EIESL (External Interrupt Edge Select Control Register) ...............28
6.1.45 Bank 4 R7 IOC7 (Port 7 I/O Control Register) ..................................................29
6.1.46 Bank 4 R8 IOC8 (Port 8 I/O Control Register) ..................................................29
6.1.47 Bank 4 R9 IOC9 (Port 9 I/O Control Register) ..................................................29
6.1.48 Bank 4 RA IOCA (Port A I/O Control Register)..................................................29
6.1.49 Bank 4 RB IOCB (Port B I/O Control Register).................................................30
6.1.50 Bank 4 RC IOCC (Port C I/O Control Register) ................................................30
6.1.51 Bank 4 RF WKCR (Wake-up Control Register) ................................................30
6.1.52 Bank 5 R7 P7PHCR (Port 7 Pull-High Control Register)..................................30
6.1.53 Bank 5 R8 P8PHCR (Port 8 Pull-High Control Register)..................................30
6.1.54 Bank 5 R9 P9PHCR (Port 9 Pull-High Control Register)..................................31
6.1.55 Bank 5 RA PAPHCR (Port A Pull-High Control Register)..................................31
6.1.56 Bank 5 RB PBPHCR (Port B Pull-High Control Register).................................31
6.1.57 Bank 5 RC PCPHCR (Port C Pull-High Control Register) ................................31
6.1.58 Bank 6 R7 P7ODCR (Port 7 Open-Drain Control Register) .............................31
6.1.59 Bank 6 R8 P8ODCR (Port 8 Open-Drain Control Register) .............................32
6.1.60 Bank 6 R9 P9ODCR (Port 9 Open-Drain Control Register) .............................32
6.1.61 Bank 6 RA PAODCR (Port A Open-Drain Control Register) .............................32
6.1.62 Bank 6 RB PBODCR (Port B Open-Drain Control Register) ............................32
6.1.63 Bank 6 RC (Port C) ...........................................................................................32
6.1.64 Bank 7 R5 I2CCR1 (I2C Status and Control Register 1) ..................................33
6.1.65 Bank 7 R6 I2CCR2 (I2C Status and Control Register 2) ..................................34
6.1.66 Bank 7 R7 I2CSA (I2C Slave Address Register)...............................................34
6.1.67 Bank 7 R8 I2CDA (I2C Device Address Register) ............................................35
6.1.68 Bank 7 R9 I2CA (I2C Address Register) ...........................................................35
6.1.69 Bank 7 RA I2CDB (I2C Data Buffer) .................................................................35
6.1.70 Bank 7 RB DACDL (DA Conversion Low Data Buffer)......................................36
6.1.71 Bank 7 RC DACDH (DA Conversion High Data Buffer)....................................36
6.1.72 Bank 7 RD DACC (DA Conversion Control Register) .......................................36
6.1.73 Bank 7 RF I2CCR3 (I2C Control Register 3) ....................................................37
iv
Product Specification (V1.1) 04.08.2016
Contents
6.2 TCC/WDT and Prescaler ................................................................................37
6.3 I/O Port...........................................................................................................38
6.4 Reset and Wake-up ........................................................................................40
6.4.1 Reset and Wake-up Function............................................................................40
6.4.2 Wake-up and Interrupt Modes Operation Summary .........................................41
6.4.3 Status of T and P of the Status Register ...........................................................42
6.5 Interrupt ..........................................................................................................44
6.6 Analog-to-Digital Converter (ADC)..................................................................46
6.6.1 Registers for ADC Circuit ..................................................................................46
6.6.2 ADC Data Register............................................................................................47
6.6.3 A/D Sampling Time............................................................................................47
6.6.4 A/D Conversion Time ........................................................................................47
6.7 SPI (Serial Peripheral Interface) .....................................................................48
6.7.1 Registers for SPI Circuit....................................................................................48
6.7.2 Overview and Features .....................................................................................48
6.7.3 SPI Functional Block Diagrams.........................................................................50
6.7.4 SPI Signal and Pin Description .........................................................................51
6.7.5 SPI Mode Timing...............................................................................................53
6.8 I2C Function ...................................................................................................54
6.8.2 7-Bit Slave Address...........................................................................................57
6.8.2 10-Bit Slave Address.........................................................................................58
6.8.3 Master Mode .....................................................................................................61
6.8.4 Slave Mode .......................................................................................................61
6.9 Timer/Counter 1..............................................................................................61
6.9.1 Timer Mode .......................................................................................................62
6.9.2 T1OUT Mode.....................................................................................................62
6.9.3 Capture Mode....................................................................................................63
6.9.4 PWM Mode........................................................................................................64
6.10 Timer 2 ...........................................................................................................65
6.10.1 Timer Mode .......................................................................................................66
6.10.2 PWM Mode........................................................................................................66
6.11 Timer 3 ...........................................................................................................67
6.11.1 Timer Mode .......................................................................................................68
6.11.2 T3OUT Mode.....................................................................................................68
6.12 Universal Asynchronous Receiver Transmitter (UART)...................................68
6.12.1 UART MODE:....................................................................................................70
6.12.2 Transmitting.......................................................................................................70
6.12.3 Receiving...........................................................................................................70
6.12.4 Baud Rate Generator ........................................................................................71
6.12.5 UART Timing .....................................................................................................71
6.13 DA Conversion................................................................................................72
Product Specification (V1.1) 04.08.2018
v
Contents
6.14 Registers Initialized Values after Reset...........................................................73
6.15 Oscillator.........................................................................................................83
6.15.1 Oscillator Modes................................................................................................83
6.15.2 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................83
6.15.3 External RC Oscillator Mode.............................................................................84
6.15.4 Internal RC Oscillator Mode ..............................................................................85
6.16 Power-On Considerations...............................................................................87
6.16.1 External Power-on Reset Circuit.......................................................................87
6.16.2 Residue-Voltage Protection...............................................................................88
6.17 Code Option ...................................................................................................88
6.17.1 Code Option Register (Word 0).........................................................................89
6.17.2 Code Option Register (Word 1).........................................................................90
6.17.3 Code Option Register (Word 2).........................................................................91
6.18 Instruction Set.................................................................................................91
Absolute Maximum Ratings........................................................................ 93
Electrical Characteristics............................................................................ 94
7
8
8.1 DC Electrical Characteristics...........................................................................94
8.2 AC Electrical Characteristics...........................................................................95
9
Timing Diagrams ......................................................................................... 95
APPENDIX
A
B
Ordering and Manufacturing Information.................................................. 97
Package Type............................................................................................... 98
Specification Revision History
Doc. Version
Revision Description
Initial Offical Release Version
Date
1.0
2010/04/16
1. Modified the Package Type and Name
1.1
2016/04/08
2. Added Ordering and Manufacturing Information
vi
Product Specification (V1.1) 04.08.2016
EM78P507N
8-Bit Microcontroller
1 General Description
The EM78P507N is an 8-bit microprocessors designed and developed with low-power and
high-speed CMOS technology. Integrated onto a single IC are on-chip Watchdog Timer (WDT),
RAM, ROM, programmable real time clock counter (TCC), internal/external interrupt, power down
mode, four 8-bit timers, SPI, I2C, UART, Current type DAConverter,10 bits/24 channels AD , LVD,
and tri-state I/O. It is equipped with a 6K13-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM).
With its enhanced OTP-ROM features, the EM78P507N provides a convenient way of developing
and verifying user’s programs. Moreover, this OTP-ROM device offers the advantages of easy
and effective program updates, using development and programming tools. Users can avail of
the ELAN Writer to easily program their development codes.
2 Features
CPU Configuration
Special Features
Programmable free running watchdog timer
High ESD immunity
Power saving Sleep mode
Selectable Oscillation mode
6K13 bits on-chip ROM
2728 bits on-chip registers
8-level stacks for subroutine nesting
Dual clock operation mode
Four operation modes: Normal, Green, Idle, & Sleep
Two programmable Level Voltage Detector (LVD):
2.3V, 3.0V
Peripheral Configuration
One clock output pin can output the currently
working frequency
Power-on reset Level Voltage: 1.9 reset level,
2.0 release
Less than 2.0 mA at 3.3V / 4 MHz
Typically 15 A, at 3V / 32kHz
Typically 2 A, during Sleep mode
8-bit real time clock/counter (TCC)
24-channel Analog-to-Digital Converter (ADC) with
12-bit resolution in Vref mode
Three 8-bit timers
8-bit Timer 1, auto reload counter/timer which can be
an interrupt source. Function modes: Timer, Toggle
output, UART baud rate generator, Capture, & PWM
8-bit Timer 2, auto reload timer which can be an
interrupt source. Function modes: Timer, SPI baud
rate generator, & PWM
Two sets of 8 bits auto reload counter/timer which
can be cascaded to one 16-bit counter/timer
8-bit Timer 3 with external clock source, can
generate a 50% duty pulse output from T3OUT Pin.
Universal Asynchronous Receiver/Transmitter
(UART) available (operates at 16 MHz/2Mbps, 2.2V)
I2C-bus function, including 7-bit/10-bit address 8-bit
data transmit/ receive mode and 16 bytes buffer to
save the data.
I/O Port Configuration
6 bidirectional I/O ports: P7, P8, P9, PA, PB and PC
45 I/O pins & 1I pin
45 programmable pull-high I/O pins
39 programmable open-drain I/O pins
External interrupt with Wake-up : P74~P77, P82~P83,
PB0~PB3
Operating Voltage
2.2V~3.6V at -40C~85C (Industrial)
Operating Frequency
Crystal/IRC/ERC oscillation circuit selected by code
option for system clock
Serial Peripheral Interface (SPI)
Digital-to-Analog Converter (DAC) current type with
10-bit resolution
IRC oscillation circuit selected by code option or register
Main Clock
Crystal Mode:
Single instruction cycle commands
DC~20 MHz/2clks@3.3V;
DC~100ns inst. cycle @ 3.3V;
DC~16 MHz/2 clks @ 2.2V;
DC~250ns inst. cycle @ 2.2V
ERC mode:
22 available interrupts: 10 external, 12 internal
TCC overflow interrupt
Ten external interrupts (wake-up from sleep mode)
Three timer interrupts
A/D converter interrupt
SPI interrupt
Two I2C interrupts
IRC mode: DC~16 MHz/2 clks @ 2.2V ;
DC~400ns inst. cycle @ 2.2V
Three UART interrupts
Low voltage detect (LVD)
Sub Clock:
IRC mode : 16kHz
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
1
EM78P507N
8-Bit Microcontroller
Package Type:
44 pin QFP/LQFP 1010mm: EM78P507NQ/L44
48 pin LQFP 77mm: EM78P507NL48
NOTE
These are Green products which do NOT
contain hazardous substances.
3 Pin Assignment
43
37
44
42
41
40
39
38
36
35
34
P74/INT0
P75/INT1/T1OUT/PWM1
P76/INT2/T1CK
P77/INT3/T1CAP
VDD
1
2
3
4
5
6
7
33
32
31
30
PA6/SCK
PA5/SO
PA4/SI
PA3/SDA
PA2/SCL
PA1/AD17
PA0/AD18
P97/AD19
P96/AD20
P95/AD21
P94/AD22
29
28
27
EM78P507N-44Pin
PC1/OSCI
PC0/OSCO
26
25
8
VSS
P80/T3CLK
9
T3OUT/PC2
PC3/AD23
10
11
24
23
13
19
12
14
15
16
17
18
20
21
22
Figure 3-1a EM78P507N 44-pin QFP/LQFP Package
2
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
42 41 40
37
48 47 46 45 44 43
39 38
36
35
34
33
32
PB1/INT5/AD10
PB0/INT4/AD9
PA7//SS
P74/INT0
1
2
3
4
5
6
7
P75/INT1/T1OUT/PWM1
P76/INT2/T1CK
PA6/SCK
PA5/SO
P77/INT3/T1CAP
VDD
PC1/OSCI
PC0/OSCO
PA4/SI
31
30
29
EM78P507N-48Pin
PA3/SDA
PA2/SCL
PA1/AD17
PA0/AD18
P97/AD19
P96/AD20
VSS
8
P80/T3CLK
9
28
27
10
PC2/T3OUT
PC3/AD23
11
12
26
25
P81//RESET
13
19
14 15 16 17 18
20
21
22 23 24
Figure 3-1b EM78P507N 48-pin LQFP Package
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
3
EM78P507N
8-Bit Microcontroller
4 Pin Description
4.2 EM78P507N LQFP/QFP 44 pins
Symbol
Pin No. Type
Function
Crystal type: Crystal input terminal or external clock input
pin
OSCI
6
7
I
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin
OSCO
O
RC type:
Clock output with a period of 1 instruction
cycle time
External clock signal input
P70~P77 are bidirectional I/O pins
P70 can be used as AD13
P71 can be used as AD14
P72 can be used as AD15, DACO
P73 can be used as AD16
39~42
1~4
P70 ~ P77
I/O
P74 can be used as INT0
P75 can be used as INT1, T1OUT, and PWM1
P76 can be used as INT2 and T1CK
P77 can be used as INT3 and T1CAP
P80, P82~P87are bidirectional I/O pins
P81 only act as input pin
P80 can be used as T3CLK
P81 can be used as /RESET
P82 can be used as INT8 and AD8
P83 can be used as INT9 and AD7
P84 can be used as Vref
P80 ~ P87 9, 12 ~ 18 I/O
P85 can be used as AD6
P86 can be used as AD5
P87 can be used as AD4
P90~P97are bidirectional I/O pins
P90 can be used as AD3 and PWM2
P91 can be used as AD2 and CLKOUT
P92 can be used as AD1
P90 ~ P97
19 ~ 26
I/O
P93 can be used as AD0
P94 can be used as AD22
P95 can be used as AD21
P96 can be used as AD20
P97 can be used as AD19
4
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Symbol
Pin No. Type
Function
PA0~PA7are bidirectional I/O pins
PA0 can be used as AD18
PA1 can be used as AD17
PA2 can be used as SCL
PA3 can be used as SDA
PA4 can be used as SI
PA0 ~ PA7
27 ~ 34
I/O
PA5 can be used as SO
PA6 can be used as SCK
PA7 can be used as /SS
PB0~PB5are bidirectional I/O pins
PB0 can be used as INT4 and AD9
PB1 can be used as INT5 and AD10
PB2 can be used as INT6 and AD11
PB3 can be used as INT7 and AD12
PB4 can be used as RX
35 ~ 38
43 ~ 44
PB0 ~ PB5
I/O
PB5 can be used as TX
PC0~PC3 are bidirectional I/O pins
PC0 can be used as OSCO
PC1 can be used as OSCI
PC2 can be used as T3OUT
PC3 can be used as AD23
7 ~ 6
10 ~ 11
PC0 ~ PC3
/RESET
I/O
If it remains at logic low, the device will be reset.
Wakes-up from Sleep mode when pins status changes.
12
I
Voltage on /RESET must not be over VDD during Normal
mode.
Power supply for IC emulation. Can be adjusted as per
customer requirement.
VDD
VSS
5
6
-
-
Ground
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
5
EM78P507N
8-Bit Microcontroller
4.1 EM78P507N LQFP 48 Pins
Symbol
Pin No. Type
Function
Crystal type: Crystal input terminal or external clock input
pin
OSCI
6
7
I
RC type:
RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or external
clock input pin
OSCO
O
RC type:
Clock output with a period of 1 instruction cycle
time
External clock signal input
P70~P77 are bidirectional I/O pins
P70 can be used as AD13
P71 can be used as AD14
P72 can be used as AD15, DACO
P73 can be used as AD16
39~42
1~4
P70 ~ P77
I/O
I/O
I/O
P74 can be used as INT0
P75 can be used as INT1, T1OUT, and PWM1
P76 can be used as INT2 and T1CK
P77 can be used as INT3 and T1CAP
P80, P82~P87are bidirectional I/O pins
P81 only act as intupt pin
P80 can be used as T3CLK
P81 can be used as /RESET
P82 can be used as INT8 and AD8
P83 can be used as INT9 and AD7
P84 can be used as Vref
9
P80 ~ P87
12 ~ 18
P85 can be used as AD6
P86 can be used as AD5
P87 can be used as AD4
P90~P97are bidirectional I/O pins
P90 can be used as AD3 and PWM2
P91 can be used as AD2 and CLKOUT
P92 can be used as AD1
P90 ~ P97 19 ~ 26
P93 can be used as AD0
P94 can be used as AD22
P95 can be used as AD21
P96 can be used as AD20
P97 can be used as AD19
6
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Symbol
Pin No. Type
Function
PA0~PA7are bidirectional I/O pins
PA0 can be used as AD18
PA1 can be used as AD17
PA2 can be used as SCL
PA3 can be used as SDA
PA4 can be used as SI
PA0 ~ PA7
27 ~ 34
I/O
PA5 can be used as SO
PA6 can be used as SCK
PA7 can be used as /SS
PB0~PB7are bidirectional I/O pins
PB0 can be used as INT4 and AD9
PB1 can be used as INT5 and AD10
PB2 can be used as INT6 and AD11
PB3 can be used as INT7 and AD12
PB4 can be used as RX
35 ~ 38
43 ~ 46
PB0 ~ PB7
I/O
PB5 can be used as TX
PC0~PC5 are bidirectional I/O pins
PC0 can be used as OSCO
PC1 can be used as OSCI
PC2 can be used as T3OUT
PC3 can be used as AD23
7 ~ 6
10 ~ 11
47 ~ 48
PC0 ~ PC5
/RESET
I/O
If it remains at logic low, the device will be reset.
Wakes-up from Sleep mode when pin status changes
12
I
Voltage on /RESET must not be over VDD during Normal
mode
Power supply for IC emulation. Can be adjusted as per
customer requirement.
VDD
VSS
5
8
-
Ground
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
7
EM78P507N
8-Bit Microcontroller
5 Block Diagram
T1CLK,
T3CLK
P7
Start-up
timer
Ext.
OSC.
PC
ERC
ROM
P70
T1CAP
PWM1
P71
P72
P73
P74
P75
P76
P77
WDT
Timer1
(PWM1)
Oscillation
Generation
8-level
stack
(13 bit)
Instruction
Register
PWM2
T3OUT
Timer2
(PWM2)
Timer3
P8
IRC
Reset
SCL,SD
A
Instruction
Decoder
P80
P81
P82
P83
P84
P85
P86
P87
I2C
TCC
LVD
SPI
SCK,
SDO,
SDI, /SS
Mux.
ALU
Tx, Rx
P9
UART
R4
P90
P91
P92
P93
P94
P95
P96
P97
ADin0~23
ADC
DAC
RAM
DACO
Interrupt
control
circuit
R3(Status
Reg.)
ACC
PA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Ext INT0~9
Figure 5-1 EM78P507N Functional Block Diagram
8
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6 Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer.
Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select
Register (R4).
6.1.2 R1 (ROM Page and RAM Bank Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
PS2
PS1
PS0
0
BS2
BS1
BS0
Bit 7:
Not used bits, fixed to “0” all the time.
Bits 6~4 (PS2~PS0): Page Select Registers used to select Pages 0~15. These are
read only.
Bit 3:
Not used bits, fixed to “0” all the time.
Bits 2~0 (BS2~BS0): RAM Bank Select Registers used to select Banks 0~7 for
R20~R3F or Banks 0~7 for control register.
6.1.3 R2 (Program Counter) and Stack
R2 and hardware stacks are 10-bit wide. The structure is depicted in Figure 6-1.
Generates 6K13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
The contents of R2 are set to all "0"s upon a RESET condition.
"JMP" instruction allows the direct loading of the lower 10 program counter bits.
Thus, "JMP" allows PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"LJMP" instruction allows direct loading of the lower 12 program counter bits.
Therefore, "LJMP" allows PC to jump to any location within 6K (212).
"LCALL" instruction loads the lower 12 bits of the PC, and then PC+1 is pushed
onto the stack. Thus, the subroutine entry address can be located anywhere within
6K (212).
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top of stack.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
9
EM78P507N
8-Bit Microcontroller
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from "A" register to the lower 8 bits of the
PC, and the ninth and tenth bits (A8~A9) of the PC remain unchanged.
Any instruction except “ADD R2,A” that is written to R2 (e.g., "MOV R2, A", "BC R2,
6", etc.) will cause the ninth and the tenth bits (A8~A9) of the PC to remain
unchanged.
In the case of EM78P507N, the most significant bits (A12~A10) will be loaded with
the contents of PS2~PS0 in the status register (R1) upon the execution of a "JMP",
"CALL", or any other instruction set which are written to R2.
Program Counter Organization
000H
003H
Reset Vector
A12~A10
A9
~
A0
Interrupt Vector
CALL
RET
042H
RETL
RETI
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
000 PAGE0 0000~03FF
001 PAGE1 0400~07FF
010 PAGE2 0800~0BFF
011 PAGE3 0C00~0FFF
100 PAGE4 1000~13FF
101 PAGE5 1400~17FF
On-chip Program
Memory
FFFH
Figure 6-1 Program Counter Organization
10
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Data Memory Configuration
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Addr.
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
00
01
02
03
04
R0 (Indirect Addressing Register, IAR)
R1 (ROM Page and RAM Bank Select Register, RPBSR)
R2 (Program Counter, PC)
R3 (Status Register, SR)
R4 (Select Indirect Address Register, RSR)
R5
R5
R5
R5
R5
05
06
07
08
09
0A
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
(TBLP)
(ADCR1)
(T1CR)
(URC)
(I2CCR1)
R6
R6
R6
R6
R6
(TBHP)
(ADCR2)
(TSR)
(URS)
(I2CCR2)
R7
(Port 7)
R7
(ADDL)
R7
(T1PD)
R7
(URRD)
R7
(IOC7)
R7
(P7PHCR)
R7
(P7ODCR)
R7
(I2CSA)
R8
R8
R8
R8
R8
R8
R8
R8
(Port 8)
(ADDH)
(T1TD)
(URTD)
(IOC8)
(P8PHCR)
(P8ODCR)
(I2CDA)
R9
(Port 9)
R9
(ADIC1)
R9
(T2CR)
R9
(URC2)
R9
(IOC9)
R9
(P9PHCR)
R9
(P9ODCR)
R9
(I2CA)
RA
RA
RA
RA
RA
RA
RA
RA
(Port A)
(ADIC2)
(IOCA)
(PAPHCR)
PAODCR)
(I2CDB)
(T2PD)
(SPIS)
RB
(Port B)
RB
(ADIC3)
RB
(T2TD)
RB
(SPIC)
RB
(IOCB)
RB
(PBPHCR)
RB
PBODCR)
RB
(DACDL)
0B
0C
0D
0E
0F
RC
RC
RC
RC
RC
RC
RC
RC
(SCCR)
(COCR)
(T3CR1)
(SPIR)
(IOCC)
(PCPHCR)
(Port C)
(DACDH)
RD
(TWTCR)
RD
(T3CR2)
RD
(SPIW)
RD
(DACC)
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
RE
RE
RE
RE
Reserve
(IMR)
(EIMR)
(T3PD)
(EIESH)
RF
(ISR)
RF
(EISR)
RF
(TCC)
RF
(EIESL)
RF
(WKCR)
RF
I2CCR3)
10
:
General Registers (16x8 bits)
1F
20
:
General
General
General
General
General
General
General
General
Registers
Registers
Registers
Registers
Registers
Registers
Registers
Registers
(328 bits)
(328 bits)
(328 bits)
(328 bits)
(328 bits)
(328 bits)
(328 bits)
(328 bits)
3F
Figure 6-2 Data Memory Configuration
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
11
EM78P507N
8-Bit Microcontroller
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VDB
LVDEN
LVDS
T
P
Z
DC
C
Bit 7 (VDB):
Voltage Detector. This bit is read only. When VDD pin voltage is lower
than Vdet (selected by LVDS), this bit will be cleared.
0: Low voltage is detected
1: Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDEN): Voltage Detect Enable bit
0: No action
1: Voltage detect enabled
Bit 5 (LVDS): Detect Voltage select bits
LVDS
Detect Voltage
0
1
2.3V
3.0V
Bit 4 (T):
Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or
during power-on and reset to “0” by WDT time-out. This bit is read
only.
Event
T
0
0
1
1
P
0
1
0
1
Remark
WDT wake-up from Sleep mode
WDT time out (not Sleep mode)
/RESET wake-up from Sleep
Power up
Low pulse on /RESET
: d’on't care
Bit 3 (P):
Bit 2 (Z):
Power-down bit. Set to “1” during power-on or by a "WDTC" command
and reset to “0” by a "SLEP" command. This bit is read only.
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC):
Bit 0 (C):
Auxiliary carry flag
Carry flag
6.1.5 R4 (RAM Select Register)
Bits 7 ~ 6:
Bits 5~0:
Used to select Bank 0 ~ Bank 3
Used to select registers (Address: 00~3F) in indirect addressing
mode.
See the data memory configuration in Figure 6-2 above for details.
12
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.6 Bank 0 R5 TBLP (Low Byte of Table Pointer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit 7
RBit 6
RBit 5
RBit 4
RBit 3
RBit 2
RBit 1
RBit 0
Bits 7 ~ 0 (RBit 7 ~ RBit 0): Table Pointer Address Bits 0 ~7
6.1.7 Bank 0 R6 TBHP (High Byte of Table Pointer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBSHL
0
0
RBit 12
RBit 11
RBit 10
RBit 9
RBit 8
Bit 7 (TBSHL): Table address high and low bit selection
0: Take the low 8 bits of machine code to the “TBLP” register.
1: Take the high 5 bits of machine code to the “TBHP” register.
Bits 4 ~ 0 (RBit 12 ~ RBit 8): Table Pointer Address Bits 12 ~ 8.
6 1.8 Bank 0 R7 ~ RB (Port 7 ~ Port B)
R7 ~ RB:
These are all I/O registers.
6.1.9 Bank 0 RC SOCR (System Clock Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
IDLE
0
0
CPUS
Bits 7~4:
Not used bits, fixed to “0” all the time.
Bit 3 (IDLE): Idle Mode Enable bit. This bit will determine as to which mode to enter
after SLEP instruction.
IDLE=”0”+SLEP instruction Sleep mode.
IDLE=”1”+SLEP instruction Idle mode.
Bits 2 ~ 1:
Not used bits, fixed to “0” all the time.
Bit 0 (CPUS): CPU Oscillator Source select
0: sub-oscillator (Fs)
1: main oscillator (Fosc)
When CPUS=0, the CPU oscillator selects the sub-oscillator while the
main oscillator is stopped.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
13
EM78P507N
8-Bit Microcontroller
CPU Operation Mode
Code option
HLFS=1
RESET
Normal Mode
Code option
HLFS=0
Fm: oscillation
Fs: oscillation
Interrupt
or wake
up
wake up
CPU: using Fm
IDLE="0"
+ SLEP
CPUS="1"
CPUS="0"
IDLE="1"
+ SLEP
IDLE="1"
+ SLEP
Sleep Mode
Green Mode
Fm: stop
Idle Mode
wake up
Fm: stop
Fs: stop
Fm: stop
Fs: oscillation
Fs: oscillation
IDLE="0"
+ SLEP
Interrupt or
wake up
CPU: stop
CPU: using Fs
CPU: stop
Figure 6-3 CPU Operation Mode
6.1.10 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
WPSR2
WPSR1
WPSR0
TCCS
TPSR2
TPSR1
TPSR0
Bit 7 (WDTE): Watchdog Timer Enable bit. This control bit is used to enable the
watchdog timer.
0: Disable WDT function
1: Enable WDT function
Bits 6 ~ 4 (WPSR2 ~ WPSR0): WDT Prescaler bits
WPSR2
WPSR1
WPSR0
WDT Rate
1:1 (Default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (TCCS): TCC Clock Source select bit
0: Fm (main clock)
1: Fs (sub clock)
14
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bits 2 ~ 0 (TPSR2 ~ TPSR0): TCC Prescaler bits
TPSR2
TPSR1
TPSR0
TCC Rate
1:2 (Default)
1:4
110
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1:8
0
1:16
1
1:32
1
1:64
1
1:128
1:256
1
6.1.11 Bank 0 RE IMR (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1IE
LVDIE
ADIE
SPIE
URTIE
EXIE9
EXIE8
TCIE
NOTE
“1” means with interrupt request; “0” means no interrupt occurs.
Banks 0 ~ 1-RF can be cleared by instruction but cannot be set.
Banks 0 ~ 1-RE are the interrupt mask registers.
Reading Banks 0 ~ 1-RF will result to "logic AND" of Banks 0 ~ 1-RE and
Banks 0 ~ 1-RF.
Bits 7~0 (TCIE ~ T1IE) : Interrupt Enable bit. Enable interrupt source respectively.
0: Disable interrupt
1: Enable interrupt
6.1.12 Bank 0 RF ISR (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1IF
LVDIF
ADIF
SPIIF
URTIF
EXIF9
EXIF8
TCIF
NOTE
“1” means with interrupt request; “0” means no interrupt occurs.
Bank 0-RF can be cleared by instruction but cannot be set.
Bank 0-RE is the interrupt mask register.
Reading Bank 0-RF will result to "logic AND" of Bank 0-RE and Bank 0-RF.
Bit 7 (T1IF):
Timer 1 Interrupt Flag
Bit 6 (LVDIF): Low Voltage Detector Interrupt Flag
Bit 5 (ADIF): A/D Conversion Complete Interrupt Flag
Bit 4 (SPIIF): SPI Transfer Complete Interrupt Flag
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
15
EM78P507N
8-Bit Microcontroller
Bit 3 (URTIF): UART Transmit Interrupt Flag
Bit 2 (EXIF9): External Interrupt 9 Occur Flag
Bit 1 (EXIF8): External Interrupt 8 Occur Flag
Bit 0 (TCIF):
TCC Overflow Interrupt Flag
6.1.13 Bank 1 R5 ADCR1 (A/D Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADRUN
ADP
ADCK1
ADCK0
-
-
-
-
Bit 7 (ADRUN):Start AD Conversion
0: Reset on conversion completion by hardware. This bit cannot be
reset by software.
1: Start Conversion
Bit 6 (ADP):
A/D Power Control
Bits 5 ~ 4 (ADCK1~ADCK0): AD Conversion Time Select bits
ADCK1
ADCK0
Clock Source
Fc/4
Max. Operating Frequency (Fc)
0
0
1
1
0
1
0
1
1 MHz
4 MHz
8 MHz
16 MHz
Fc/16
Fc/32
Fc/64
Bit 3 ~ Bit 0: Not used bits, fixed to “0” all the time.
6.1.14 Bank 1 R6 ADCR2 (A/D Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
ADREF
0
ADIS4
ADIS3
ADIS2
ADIS1
ADIS0
Bit 7:
Not used bit, fixed to “0” all the time.
Bit 6 (ADREF): A/D Reference Voltage Input select.
0: Internal VDD, P84 is used as I/O
1: External reference pin, P84 is used as reference input pin.
Not used bit, fixed to “0” all the time.
Bit 5:
16
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bits 4~0 (ADIS4~ADIS0): A/D Input select bits
ADIS4
ADIS3
ADIS2
ADIS1
ADIS0
Analog Input Pin
AD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
6.1.15 Bank 1 R7 ADDL (A/D Low 8-Bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Bits 7~0 (ADD7~ADD0): AD Low 8-bit Data Buffer
6.1.16 Bank 1 R8 ADDH (A/D High 8-Bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
ADD11
ADD10
ADD9
ADD8
Bits 7~4:
Not used bits, fixed to “0” all the time
Bits 3~0 (ADD11~ADD8): AD High 4-bit Data Buffer
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
17
EM78P507N
8-Bit Microcontroller
6.1.17 Bank 1 R9 ADIC1 (A/D Input Control Register 1)
Bit 7
ADE7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bits 7~0 (ADE7~ADE0): AD Input pin enable control.
0: AD acts as I/O pin
1: AD acts as analog input pin
6.1.18 Bank 1 RA ADIC2 (A/D Input Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE15
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE8
Bits 7~0 (ADE15~ADE8): AD Input pin enable control.
0: Act as I/O pin
1: Act as analog input pin
6.1.19 Bank 1 RB ADIC3 (A/D Input Control Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE23
ADE22
ADE21
ADE20
ADE19
ADE18
ADE17
ADE16
Bits 7~0 (ADE23~ADE16): AD Input pin enable control.
0: Act as I/O pin
1: Act as analog input pin
6.1.20 Bank 1 RC COCR (Clock Output Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
RCM1
RCM0
CLKOE
CLKB1
CLKB0
Bits 7~5:
Not used bits, fixed to “0” all the time.
Bits 4~3 (RCM1~0): IRC Mode select bits
RCM1
RCM0
Frequency
1 MHz
0
0
1
1
0
1
0
1
8 MHz
16 MHz
4 MHz
Bit 2 (CLKOE): Port 9.1 used as CLK Output Pin
1: No action
0: Enable CLK output
18
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bits 1~0 (CLKB1~0): Clock Output Rate select bits.
CLKB1
CLKB0
CLK Rate
1:1
0
0
1
1
0
1
0
1
1:2
1:4
1:8
6.1.21 Bank 1 RE EIMR (External Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIE7
EXIE6
EXIE5
EXIE4
EXIE3
EXIE2
EXIE1
EXIE0
Bits 7~0 (EXIE7~EXIE0): Interrupt Enable bits. Enable interrupt source respectively.
6.1.22 Bank 1 RF EISR (External Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIF7
EXIF6
EXIF5
EXIF4
EXIF3
EXIF2
EXIF1
EXIF0
Bits 7~0 (EXIE7~EXIE0): Interrupt Flag of External Interrupts 0~7 occur
6.1.23 Bank 2 R5 T1CR (Timer 1 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIS1
TIS0
T1MS2
T1MS1
T1MS0
T1P2
T1P1
T1P0
Bits 7~6 (T1S1~0): Timer 1 and Timer 2 Interrupt Type select bits. These two bits are
used when the Timer operates in PWM mode.
TIS1
TIS0
Timer 1 and Timer 2 Interrupt Type Select
TXPD underflow
0
0
1
0
1
TXTD underflow
TXPD and TXTD underflow
Bit 5~ (T1MS2~T1MS0): Timer 1 Operation Mode select bits
T1MS2
T1MS1
T1MS0
Timer 1 Mode Select
Timer 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
T1OUT mode
Capture Mode Rising Edge
Capture Mode falling Edge
UART Baud Rate Generator
PWM1
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
19
EM78P507N
8-Bit Microcontroller
Bits 2~0 (T1CSS1~T1CSS0): Timer 1 Clock Source select bits
T1P2
T1P1
T1P0
Prescaler
1:2 (Default)
1:4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:8
1:16
1:32
1:64
1:128
1:256
6.1.24 Bank 2 R6 TSR (Timer 1 Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1MOD
TRCB
T1CSS1 T1CSS0
T2CSS
T1EN
0
T1OC
Bit 7 (T1MOD): Timer Operating Mode select bit
0: Two 8-bit Timers
1: Timer 1 and Timer 2 cascade to one 16-bit Timer
NOTE
By setting T1MOD to “1”, the Timer can cascade to one 16-bit Timer. This 16-bit Timer
is controlled by Timer 1, including enable clock source and prescaler. Timer 1 is MSB
and Timer 2 is LSB in period and duty values.
Bit 6 (TRCB): Timers 1, 2, & 3 Read Control bit
0: When this bit is set to “0”, read data from T1PD, T2PD or T3PD.
1: When this bit is set to “1”, read data from T1PD, T2PD or T3PD,
but the value is timer counter read value.
Bits 5~4 (T1CSS1~0): Timer 1 Clock Source select bits.
T1CSS1
T1CSS0
Timer 1 Clock Source Select
0
0
1
0
1
Fm
Fs
T1CK
Bit 3 (T2CSS): Timer 2 Clock Source select bit
0: Main clock with prescaler
1: Sub clock with prescaler
Bit 2 (T1EN): Timer 1 Start Bit
0: Timer 1 stop
1: Timer 1 start
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bit 1:
Not used bits, fixed to “0” all the time.
Bit 0 (T1OC): Timer 1 Output Flip-Flop Control bit
0: T-FF is low
1: T-FF is high
6.1.25 Bank 2 R7 T1PD (Timer 1 Period Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
Bits 7~0 (PRD1[7]~PRD1[0]): The content of this register is a period of Timer 1.
6.1.26 Bank 2 R8 T1TD (Timer 1 Duty Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TD1[7]
TD1[6]
TD1[5]
TD1[4]
TD1[3]
TD1[2]
TD1[1]
TD1[0]
Bits 7~0 (TD1[7]~TD1[0]): The content of this register is a period of Timer 1
6.1.27 Bank 2 R9 T2CR (Timer 2 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2IF
T2IE
T2EN
T2MS1
T2MS0
T2P2
T2P1
T2P0
Bit 7(T2IF):
Bit 6(T2IE):
Interrupt Flag of Timer 2 Interrupt
Timer 2 Interrupt Mask bit
0: Disable Timer 2 interrupt
1: Enable Timer 2 interrupt
Bit 5 (T2EN): Timer 2 Start Bit
0: Timer 2 stop
1: Timer 2 start
Bits 4~3 (T2MS1~T2MS0): Timer 2 Operation Mode select bits
T2MS1
T2MS0
Timer 2 Mode Select
Timer 2
0
0
1
1
0
1
0
1
SPI Baud Rate Generator
PWM2
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
21
EM78P507N
8-Bit Microcontroller
Bits 2~0 (T2P2~T2P0): Timer 2 Prescaler bits
T2P2
T2P1
T2P0
Prescaler
1:2 (Default)
1:4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:8
1:16
1 :32
1:64
1:128
1:256
6.1.28 Bank 2 RA T2PD (Timer 2 Period Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Bits 7~0 (PRD2[7] ~ PRD2[0]): The content of this register is a period of Timer 2.
6.1.29 Bank 2 RB T2TD (Timer 2 Duty Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TD2[7]
TD2[6]
TD2[5]
TD2[4]
TD2[3]
TD2[2]
TD2[1]
TD2[0]
Bits 7~0 (TD2[7] ~ TD2[0]): The content of this register is a duty of Timer 2.
6.1.30 Bank 2 RC T3CR1 (Timer 3 Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T3IF
T3IE
T3EN
T3CSS1 T3CSS0
T3P2
T3P1
T3P0
Bit 7 (T3IF): Interrupt Flag of Timer 3 Interrupt
Bit 6 (T3IE): Timer 3 Interrupt Mask bit
0: Disable Timer 3 interrupt
1: Enable Timer 3 interrupt
Bit 5 (T3EN): Timer 3 Start Bit
0: Timer 3 stop
1: Timer 3 start
Bits 4~3 (T3CSS1~T3CSS0): Timer 3 Clock Source selects bits
T3CSS1 T3CSS0
Timer 3 Clock Source Select
0
0
1
0
1
Fm
Fs
T3CK
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bits 2~0 (T3P2~T3P0): Timer 3 Pre-scaler Bits
T3P2
T3P1
T3P0
Prescaler
1:2 (Default)
1 : 4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
6.1.31 Bank 2 RD T3CR2 (Timer 3 Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
T3MS1
T3MS0
Bits 7~2:
Not used bits, fixed to “0” all the time.
Bits 1~0 (T3MS1~T3MS0): Timer 3 Operation Mode select bits
T3MS1
T3MS0
Timer 3 Mode Select
Timer 3
0
0
1
1
0
1
0
1
T3OUT Mode
Reserved
Reserved
6.1.32 Bank 2 RE T3PD (Timer 2 Period Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Bits 7~0 (PRD2[7] ~ PRD2[0]): The content of this register is a period of Timer 2
6.1.33 Bank 2 RF TCC (Timer Clock/Counter)
Increased by the main oscillator clock (Fm), or sub oscillator clock (Fs). Controlled by
TWTCR register.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
23
EM78P507N
8-Bit Microcontroller
6.1.34 Bank 3 R5 URC (UART Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0
UTBE
TXE
Bit 7 (URTD8): Transmission Data Bit 8
Bits 6~5 (UMODE1~UMODE0): UART Transmission Mode select bits.
UMODE1
UMODE0
UART Mode
Mode 1 : 7 bits
Mode 2 : 8 bits
Mode 3 : 9 bits
Reserved
0
0
1
1
0
1
0
1
Bits 4~2 (BRATE2~BRATE0): Transmit Baud Rate select (Tuart = Fc/16)
BRATE2
BRATE1
RRATE0
Baud Rate
Tuart/13
e.g. Fc = 8 MHz
38400
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tuart/26
19200
Tuart/52
9600
Tuart/104
Tuart/208
Tuart/416
4800
2400
1200
Timer 1
2M
Bit 1 (UTBE): UART transfer buffer empty flag. Set to “1” when transfer buffer is
empty. Reset to “0” automatically when in URTD register. The UTBE
bit should be cleared by hardware when transmission is enabled. The
UTBE bit is read-only. Therefore, writing to the URTD register is
necessary when you want to start transmit shifting.
Bit 0 (TXE):
Enable transmission
0: Disable transmission
1: Enable transmission
6.1.35 Bank 3 R6 URS (UART Status)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
EVEN
PRE
PRERR
OVERR
FMERR
URBF
RXE
Bit 7(URRD8): Receive Data Bit 8
Bit 6 (EVEN): Select Parity Check
0: Odd parity
1: EVEN parity
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bits 5 (PRE): Enable Parity Addition
0: Disable
1: Enable
Bit 4 (PRERR): Parity Error Flag
Set to “1” when parity error occurs and clear to “0” by software.
Bit 3 (OVERR): Overrun Error flag
Set to “1” when overrun error occurs and clear to “0” by software.
Bit 2 (FMERR): Framing Error Flag.
Set to “1” when framing error occurs and clear to “0” by software.
Bit 1 (URBF): UART Read Buffer Full Flag
Set to “1” when one character is received. Resets to “0” automatically
when read from URS register. URBF will be cleared by hardware
when Receive is enabled, and that URBF bit is read-only. Therefore,
read URS register is necessary to avoid overrun error.
Bit 0 (RXE):
Enable Receive
0: Disable Receive
1: Enable Receive
6.1.36 Bank 3 R7 URRD (UART_RD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
URRD6
URRD5
URRD4
URRD3
URRD2
URRD1
URRD0
Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only.
6.1.37 Bank 3 R8 URTD (UART_TD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD7
URTD6
URTD5
URTD4
URTD3
URTD2
URTD1
URTD0
Bits 7~0 (URTD7~URTD0): UART Transmit Data Buffer. Write only.
6.1.38 Bank 3 R9 URC1 (UART Status)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
UARTE
0
UINVEN
0
0
URRIF
Bits 7~6:
Not used bits, fixed to “0” all the time.
Bit 5 (UARTE): UART Function Enable.
0: UART function disabled, PB4, PB5 act as general I/O.
1: UART function enabled, PB4, PB5 act as UART Rx & Tx pins
respectively.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
25
EM78P507N
8-Bit Microcontroller
Bit 4:
Not used bit, fixed to “0” all the time.
Bit 3 (UINVEN):Enable UART Tx and Rx Port Inverse Output
0: Disable Tx and Rx port inverse output.
1: Enable Tx and Rx port inverse output.
Bits 2~1:
Not used bits, fixed to “0” all the time.
Bit 0 (URRIF): Interrupt flag of UART receive completed. Reset to “0” by software.
6.1.39 Bank 3 RA SPIS (SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
0
OD3
OD4
0
RBF
Bit 7 (DORD): Data Shift Control bit
0: Shift left (MSB first)
1: Shift right (LSB first)
Bits 5~6 (TD0~TD1): SDO Status Output Delay Times Options
TD1
0
TD0
0
Delay Time
8 clk
0
1
16 clk
1
0
24 clk
1
1
32 clk
Bit 4:
Not used bit, fixed to “0” all the time.
Open-drain Control bit
Bit 3 (OD3):
0: Open-drain disabled for SDO
1: Open-drain enabled for SDO
Bit 2 (OD4): Open-Drain Control bit
0: Open-drain disabled for SCK
1: Open-drain enabled for SCK
Not used bit, fixed to “0” all the time.
Read Buffer Full Flag
Bit 1:
Bit 0 (RBF):
0: Receive is not completed and SPIR has not fully exchanged data
1: Receive is completed and SPIR has fully exchanged data.
26
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.40 Bank 3 RB SPIC (SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIEN
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Bit 7 (CES):
Clock Edge Select Bit
0: Data shift out on a rising edge, and shifts in on a falling edge. Data
is on hold during low-level.
1: Data shift out on a falling edge, and shifts in on a rising edge. Data
is on hold during high-level.
Bit 6 (SPIEN): SPI Enable bit
0: Disable SPI mode
1: Enable SPI mode
Bit 5 (SRO):
SPI Read Overflow bit
0: No overflow
1: A new data is received while the previous data is still being held in
the SPIR register. In this situation, the data in SPIS register is
destroyed. To avoid setting this bit, you should read the SPIRB
register although only transmission is implemented. This can only
occur during Slave mode.
Bit 4 (SSE):
SPI Shift Enable bit
0: Reset as soon as the shift is completed, and the next byte is read to
shift.
1: Start to shift, and kept on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0: After the serial data is output, the SDO remains high.
1: After the serial data is output, the SDO remains low.
1
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate select bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Timer 2
/SS enable
/SS disable
Slave
1 If EM78P507N acts as the Master or Slave device to transmit and receive data, be sure to operate at Baud Rate
lower than 3MHz and ensure that the operating voltage is higher than 2.5V.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
27
EM78P507N
8-Bit Microcontroller
6.1.41 Bank 3 RC SPIR (SPI Read Buffer)
Bit 7
SRB7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Bits 7~0 (SRB7 ~ SRB0): SPI Read Data Buffer
6.1.42 Bank 3 RD SPIW (SPI Write Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Bits 7~0 (SWB7 ~ SWB0): SPI Read Data Buffer
6.1.43 Bank 3 RE EIESH (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIES7
EIES6
EIES5
EIES4
EIES3
EIES2
EIES1
EIES0
Bits 7~0 (EIES7 ~ EIES0): External Interrupts 0~7 Edge Select Bit
0: Falling edge interrupt
1: Rising edge interrupt
6.1.44 Bank 3 RF EIESL (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDWE
I2CWE
SPIWE
ADWK
INTWK9 INTWK8
EIES9
EIES8
Bit 7 (LVDWE): LVD Wake-up Function Enable bit
0: Disable
1: Enable
Bit 6 (I2CWE): I2C Receive Wake-up Function Enable bit
0: Disable
1: Enable
Bit 5 (SPIWE): SPI Receive Wake-up Function Enable bit
0: Disable
1: Enable
Bit 4 (ADWK): AD Converter Wake-up Function Enable bit
0: Disable
1: Enable
Bit 3 (INTWK9): External Interrupts 9 Wake-up Function Enable bit
0: Disable
1: Enable
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Bit 2 (INTWK8): External Interrupts 8 Wake-up Function Enable Bit
0: Disable
1: Enable
Bits 1~0 (EIES9 ~ EIES8): External Interrupts 9~8 Edge Select Bit
0: Falling edge interrupt
1: Rising edge interrupt
6.1.45 Bank 4 R7 IOC7 (Port 7 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC77
IOC76
IOC75
IOC74
IOC73
IOC72
IOC71
IOC70
Bits 7~0 (IOC77~IOC70): Port 7 8-Bit I/O Direction Control Register
0: Define Port 7 as output port
1: Define Port 7 as input port
6.1.46 Bank 4 R8 IOC8 (Port 8 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC87
IOC86
IOC85
IOC84
IOC83
IOC82
IOC81
IOC80
Bits 7~0 (IOC87~IOC80): Port 8 8-Bit I/O Direction Control Register. P8.1 only acts as
input pin.
0: Define Port 8 as output port
1: Define Port 8 as input port
6.1.47 Bank 4 R9 IOC9 (Port 9 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC97
IOC96
IOC95
IOC94
IOC93
IOC92
IOC91
IOC90
Bits 7~0 (IOC97~IOC90): Port 9 8-Bit I/O Direction Control Register
0: Define Port 9 as output port
1: Define Port 9 as input port
6.1.48 Bank 4 RA IOCA (Port A I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCA7
IOCA6
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
Bits 7~0 (IOCA7~IOCA0): Port A 8-Bit I/O Direction Control Register
0: Define Port A as output port
1: Define Port A as input port
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
29
EM78P507N
8-Bit Microcontroller
6.1.49 Bank 4 RB IOCB (Port B I/O Control Register)
Bit 7
IOCB7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
Bits 7~0 (IOCB7~IOCB0): Port B 8-Bit I/O Direction Control Register
0: Define Port B as output port
1: Define Port B as input port
6.1.50 Bank 4 RC IOCC (Port C I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
IOCC5
IOCC4
IOCC3
IOCC2
IOCC1
IOCC0
Bits 7~ 6: Not used fixed “0”
Bits 5~0 (IOCC5~IOCC0): Port C 6-Bit I/O Direction Control Register
0: Define Port C as output port
1: Define Port C as input port
6.1.51 Bank 4 RF WKCR (Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2
INTWK1 INTWK0
Bits 7~ 0 (INTWK7 ~ INTWK0): External Interrupts 7~0 Wake-up Function Enable Bits
0: Disable
1: Enable
6.1.52 Bank 5 R7 P7PHCR (Port 7 Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH77
PH76
PH75
PH67
PH73
PH72
PH71
PH70
Bits 7~0 (PH77~PH70): Port 7 8-bit I/O Pull-high Control Registers
0: Pull-high disabled
1: Pull-high enabled
6.1.53 Bank 5 R8 P8PHCR (Port 8 Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH87
PH86
PH85
PH84
PH83
PH82
0
PH80
Bits 7~0 (PH87~PH80): Port 8 8-bit I/O Pull-high Control Registers
0: Pull-high disable
1: Pull-high enable
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.54 Bank 5 R9 P9PHCR (Port 9 Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH97
PH96
PH95
PH94
PH93
PH92
PH91
PH90
Bits 7~0 (PH97~PH90): Port 9 8-bit I/O Pull-high Control Registers.
0: Pull-high disabled
1: Pull-high enabled
6.1.55 Bank 5 RA PAPHCR (Port A Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PHA7
PHA6
PHA5
PHA4
PHA3
PHA2
PHA1
PHA0
Bits 7~0 (PHA7~PHA0): Port A 8-bit I/O Pull-high Control Registers.
0: Pull-high disable
1: Pull-high enable
6.1.56 Bank 5 RB PBPHCR (Port B Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PHB7
PHB6
PHB5
PHB4
PHB3
PHB2
PHB1
PHB0
Bits 7~0 (PHB7~PHB0): Port B 8-bit I/O Pull high Control Registers.
0: Pull-high disabled
1: Pull-high enabled
6.1.57 Bank 5 RC PCPHCR (Port C Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
PHC5
PHC4
PHC3
PHC2
PHC1
PHC0
Bits 7~0 (PHC7~PHC0): Port C 8-bit I/O Pull-high Control Registers.
0: Pull-high disabled
1: Pull-high enabled
6.1.58 Bank 6 R7 P7ODCR (Port 7 Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD77
OD76
OD75
OD74
OD73
OD72
OD71
OD70
Bits 7~0 (OD77~OD70) : Port 7 8-bit I/O Open-drain Control Registers.
0: Open Drain disable
1: Open Drain enable
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
31
EM78P507N
8-Bit Microcontroller
6.1.59 Bank 6 R8 P8ODCR (Port 8 Open-Drain Control Register)
Bit 7
OD87
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD86
OD85
OD84
OD83
OD82
0
OD80
Bits 7~0 (OD87~OD80): Port 8 8-bit I/O Open Drain Control Registers
0: Open Drain disabled
1: Open Drain enabled
6.1.60 Bank 6 R9 P9ODCR (Port 9 Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD97
OD96
OD95
OD94
OD93
OD92
OD91
OD90
Bits 7~0 (OD97~OD90): Port 9 8-bit I/O Open-drain Control Registers
0: Open-drain disabled
1: Open-drain enabled
6.1.61 Bank 6 RA PAODCR (Port A Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ODA7
ODA6
ODA5
ODA4
ODA3
ODA2
ODA1
ODA0
Bits 7~0 (ODA7~ODA0) : Port A 8-bits I/O Open-drain Control Registers.
0: Open-drain disabled
1: Open-drain enabled
6.1.62 Bank 6 RB PBODCR (Port B Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
Bits 7~0 (ODB7~ODB0): Port B 8-bit I/O Open-drain Control Registers.
0: Open-drain Disable
1: Open-drain Enable
6.1.63 Bank 6 RC (Port C)
RC is an I/O register
32
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.64 Bank 7 R5 I2CCR1 (I2C Status and Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Strobe/Pend
IMS
ISS
STOP
SAR_EMPTY
ACK
FULL
EMPTY
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control the I2C
circuit to send SCL clock. Reset automatically after receiving or
transmitting handshake signal (ACK or nACK).
In Slave mode, it is used as pending signal. You should clear it
after writing data into the Tx buffer or reading data from Rx buffer
to inform Slave I2C circuit to release the SCL signal.
Bit 6 (IMS):
Bit 5 (ISS):
Bit 4 (STOP):
I2C Master/Slave mode select bit.
0: Slave
1: Master
I2C Fast/Standard mode select bit.
0: Standard mode (100K bit/s)
1: Fast mode (400K bit/s)
In Master mode, if STOP=1 and R/nW=1, then EM78P507N
must return a nACK signal to the Slave device before sending a
STOP signal. If STOP=1 and R/nW=0 then EM78P507N sends
a STOP signal after receiving an ACK signal. Reset when the
EM78P507N sends a STOP signal to the Slave device.
In Slave mode, if STOP=1 and R/nW=0 then the EM78P507N
must return a nACK signal to the master device.
Bit 3 (SAR_EMPTY): Set when the EM78P507N transmits a 1-byte data from the I2C
Slave Address Register and receive an ACK (or nACK) signal.
Reset when the MCU writes a 1-byte data to the I2C Slave
Address Register.
Bit 2 (ACK):
The ACK condition bit is set to “1” by hardware when the device
responds with an acknowledge (ACK). Resets when the device
responds with a not- acknowledge (nACK) signal.
Bit 1 (FULL):
Bit 0 (EMPTY):
Set by hardware when I2C Receive Buffer Register is full. Reset
by hardware when the MCU reads data from I2C Receive Buffer
Register.
Set by hardware when the I2C Transmit Buffer Register is empty
and receives an ACK (or nACK) signal. Reset by hardware
when the MCU writes new data to the I2C Transmit Buffer
Register.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
33
EM78P507N
8-Bit Microcontroller
6.1.65 Bank 7 R6 I2CCR2 (I2C Status and Control Register 2)
Bit 7
I2CRIF
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2CRIE
I2CTIF
I2CTIE
I2CTS1
I2CTS0
I2CCS
I2CEN
Bit 7 (I2CRIF): I2C Receive Interrupt Flag. Set when the I2C receives a 1 byte data
and responds with an ACK signal. Reset by firmware or I2C disabled.
Bits 6 (I2CRIE): I2C Interface Receive Interrupt Enable bit
0: Disable Interrupt
1: Enable Interrupt
Bit 5 (I2CTIF): I2C Transmit Interrupt Flag. Set when I2C transmits 1 byte data and
responds with an ACK signal. Reset by firmware or I2C disabled.
Bits 4 (I2CTIE): I2C Interface Tx Interrupt Enable bit
0: Disable Interrupt
1: Enable Interrupt
Bits 3~2 (I2CTS1~I2CTS0): I2C Transmit Clock Source Select bits (When I2CCS=0).
I2C source must be low 6 MHz.
I2CTS1
I2CTS0
Source
Fm/1
Max. Operating Fm(MHz)
0
0
1
0
1
4
8
Fm/2
Fm/4
16
Bit 1 (I2CCS): I2C Clock Source Select Bit
0: Fm (main clock)
1: Fs (sub clock)
Bit 0 (I2CEN): I2C Enable bit
0: Disable I2C mode
1: Enable I2C mode
6.1.66 Bank 7 R7 I2CSA (I2C Slave Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
IRW
Bits 7~1 (SA6~SA0): When EM78P507N functions as Master device for I2C
application, these bits are used as the Slave device address registers.
Bit 0 (IRW):
When EM78P507N functions as Master device for I2C application,
this bit is used as Read/Write transaction control bit.
0: Write
1: Read
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.67 Bank 7 R8 I2CDA (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Bits 7~0 (DA7~DA0): When the EM78P507N is used as a Slave device for I2C
application, these bits store the registers address of EM78P507N.
The address register is used to identify the data on the I2C bus to
extract the message delivered to the EM78P507N.
6.1.68 Bank 7 R9 I2CA (I2C Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
IBFULL
AMB
IBEN
I2CSPE
I2CSPF
DA9
DA8
Bit 7:
Not used, fixed to “0” all the time.
Bit 6 (IBFULL): Set by hardware when the I2C 16-byte buffer is full. Reset by
software when the MCU reads data from the I2C 16-byte buffer.
Bit 5 (AMB):
Don’t care MSB bit of Slave address. If this bit (in 7-bit and 10-bit
Address mode) is enabled and the two Slave devices have the same
address, i.e., Bit 1 ~ Bit 6 or Bit 1~ Bit 9 (excluding MSB); the data will
be received by the two Slave devices.
0: Disable AMB bit
1: Enable AMB bit
Bit 4 (IBEN):
I2C 16 bytes Buffer Enable bit. The EM78P507N I2C has a 16-byte
buffer which is distributed in Bank 7 0x30 ~ 0x3F to save the received
data. If this bit is disabled, the buffer will be a general purpose RAM
0: Disable the I2C Buffer
1: Enable the I2C Buffer
Bit 3 (I2CSPE): I2C Interface Stop Interrupt Enable bit
Bit 2 (I2CSPF): I2C Interface Interrupt Stop Flag. Set after the EM78P507N acting as
Slave device, has received the STOP signal from the Master device
and the I2CSPE bit has been enabled. Reset by software.
Bits 1~0 (DA9~8): Device Address bits
6.1.69 Bank 7 RA I2CDB (I2C Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Bits 7~0 (DB7~ DB0): I2C Receive/Transmit Data Buffer
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
35
EM78P507N
8-Bit Microcontroller
6.1.70 Bank 7 RB DACDL (DA Conversion Low Data Buffer)
Bit 7
DACD7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DACD6
DACD5
DACD4
DACD3
DACD2
DACD1
DACD0
Bits 7~0 (DACD7 ~ DACD0): DA Conversion Low Data Buffer
6.1.71 Bank 7 RC DACDH (DA Conversion High Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
DACD9
DACD8
Bits 7~2:
Not used, fixed to “0” all the time.
Bits 1~0 (DACD9 ~ DACD8): DA Convert high Data Buffer
6.1.72 Bank 7 RD DACC (DA Conversion Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DARUN
0
0
SEMCL
COF[3]
COF[2]
COF[1]
COF[0]
Bit 7 (DARUN): DA Conversion Start.
Bits 6~5: Not used, fixed to “0” all the time.
Bit 4 (SEMCL): Set the maximum output current
0: Output maximum current set at 3mA
1: Output maximum current set at 4mA
Bits 3~0 (COF[3]~COF[0]): Control output maximum current levels:
COF[3]
COF[2]
COF[1]
COF[0]
DA Max Level (Ic = 3mA)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ic/16
Ic/15
Ic/14
Ic/13
Ic/12
Ic/11
Ic/10
Ic/9
Ic/8
Ic/7
Ic/6
Ic/5
Ic/4
Ic/3
Ic/2
Ic/1
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.1.73 Bank 7 RF I2CCR3 (I2C Control Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
GCEN
I2CBF
Bits 7~2:
Not used, fixed to “0” all the time.
Bit 1 (GCEN): I2C General Call Function Enable bit. If this bit is enabled and the
Master device transmitted “0000000”, the connected Slave device will
respond with an acknowledgment.
0: Disable
1: Enable
Bit 0 (I2CBF): I2C Busy Flag. If the Slave receives the address from the Master, this
flag will be set. The flag is cleared after Slave receives the STOP
signal from Master or I2C Slave address does not match.
0: I2C does not operate
1: I2C is in operation
6.2 TCC/WDT and Prescaler
R_BANK Addr. Name Bit 7
Bank 0 0X0D TWTCR WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0
R/W R/W R/W R/W R/W R/W R/W R/W
TCC TCC[7] TCC[6] TCC[5] TCC[4] TCC[3] TCC[2] TCC[1] TCC[0]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2 0X0F
Bank 0 0x0E
Bank 0 0x0E
R/W
T1IE
R/W
T1IF
R/W
R/W
LVDIE
R/W
R/W
ADIE
R/W
R/W
R/W
R/W
R/W
R/W
TCIE
R/W
TCIF
R/W
IMR
ISR
SPIIE URTIE EXIE9 EXIE8
R/W
SPIIF
R/W
R/W
URTIF EXIF9 EXIF8
R/W R/W R/W
R/W
R/W
LVDIF
R/W
ADIF
R/W
There are two 8-bit counters available as prescalers for the TCC and WDT respectively.
The PST0~PST2 bits of the Bank 0 RD TWTCR register are used to determine the ratio
of the TCC prescaler, and the PWR0~PWR2 bits of the Bank 0 RD register are used to
determine the prescaler of WDT. The prescaler counter is cleared by instruction each
time they are written into TCC. The WDT and prescaler are cleared by the “WDTC” and
“SLEP” instructions. The following Figure 6-4 depicts the circuit diagram of TCC/WDT.
Bank 2 RF (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock
or external signal input (edge selectable from the TCC pin). If the TCC signal source is
from an internal clock, the TCC will be incremented by 1 at every oscillator cycle
(without prescaler). If the TCC signal source is from an external clock input, the TCC
will be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC
pin input time length (kept in high or low level) must be greater than 1CLK.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
37
EM78P507N
8-Bit Microcontroller
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep
running even if the oscillator driver has been turned off (i.e., in Sleep mode). During
normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to
reset. The WDT can be enabled or disabled any time during Normal mode through
software programming. Refer to the WDTE bit of the TWTCR register in the above
table. With no presacler, the WDT time-out period is approximately 18 ms2.
TCCS (TCCCR)
0
Fm
Fs
Data Bus
TCC
8-bit Counter
0
MUX
1
MUX
TCC Pin
1
8 to 1 MUX
Prescaler
TE
(TCCCR)
TS
(TCCCR)
TCC overflow
interrupt
PSTE PST2~0
(TCCCR) (TCCCR)
WDT
8-bit Counter
8 to 1 MUX
Prescaler
WDTE
(WDTCR)
PSWE PSW2~0
(WDTCR) (WDTCR)
WDT Time out
Figure 6-4 TCC and WDT Block Diagram
6.3 I/O Port
Port 7, Port 8, Port 9, Port A, Port B, and Port C the I/O registers are bidirectional
tri-state I/O ports. The function of Pull-high and Open-drain can be set internally by
Bank 5 R7, R8, R9, RA, RB, and RC, Bank 6 R7, R8, R9, RA, and RB respectively.
Port 7 [4:7], Port 8 [2:3], and Port B [0:3] feature an input status (Rising or Falling edge)
changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or
"output" pin by the I/O control register (Bank 4 R7~RD IOC7~IOCC). P81 cannot be
defined as pull-high and open drain. The I/O registers and I/O control registers are both
readable and writable.
The I/O interface circuits for Port 7, Port 8, Port 9, Port A, and Port C are illustrated in
the following figures.
2 Vdd = 3V, set up time period = 18ms ± 30%
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
PCRD
P
R
Q
D
D
CLK
PCWR
_
C
L
Q
P
R
PORT
IOD
Q
CLK
PDWR
_
C
L
Q
PDRD
M
U
X
0
1
Figure 6-5a I/O Port and I/O Control Register Interface Circuit for Port 7~Port C
NOTE
Pull-high and Open-drain are not shown in the figure.
PCRD
P
R
Q
D
CLK
PCWR
_
C
L
Q
INT
P
R
Q
D
PORT
IOD
CLK
_
PDWR
C
L
Q
IMR
M
U
X
0
1
P
R
D
Q
CLK
_
C
L
Q
PDRD
TI 0
INT
Figure 6-5b I/O Port and I/O Control Register for INT
NOTE
Pull-high and Open-drain are not shown in the figure.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
39
EM78P507N
8-Bit Microcontroller
6.4 Reset and Wake-up
6.4.1 Reset and Wake-up Function
A reset is initiated by one of the following events-
(1) Power-on reset
(2) /RESET pin input "low"
(3) WDT time-out (if enabled)
NOTE
The power-on reset circuit is always enabled. It will reset the CPU at 1.9V and
consumed about 0.5µA or lower less.
The device is kept in a reset condition for a period of approximately 18ms (one
oscillator start-up timer period) after the Power-on reset is detected. If the /Reset pin
goes “low” or WDT time-out is active, a reset is generated.
Once a Reset occurs, the following functions are performed:
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog Timer and prescaler are cleared.
When power is switched on, R1 is cleared.
The bits of the P7ODCR, P8ODCR, P9ODCR, PAODCR, PBODCR registers are
set to all "0".
The bits of the P7PHCR, P8PHCR, P9PHCR, PAPHCR, PBPHCR, PCPHCR
registers are set to all "0".
Bits 7~0 of Bank 0 RE, RF registers and Bank 1 RE, RF registers are cleared.
Executing the “SLEP” instruction will assert the Sleep (power down) mode. While
going into Sleep mode, the Oscillator, TCC, and Timers 2~1 are stopped. The WDT (if
enabled) is cleared but keeps on running.
The controller can be awakened by one of the following events:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) External Interrupt status changes (if INTWE is enabled)
4) Low Voltage Detector initiated (if LVDWE is enabled)
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
The first two events will cause the EM78P507N to reset. The T and P flags of R3 can
be used to determine the source of the reset (wake-up). Events 3 and 4 are considered
the continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the Address 0x3~0x42 at each interrupt vector after wake-up. If DISI is
executed before SLEP, the execution will restart from the instruction right next to SLEP
after wake-up. Only one of Events 2 to 4 can be enabled before entering into Sleep
mode. That is:
a) If WDT is enabled before SLEP, all of Bank 0, 1 RE bit is disabled. Hence, the
EM78P507 can be awakened only by Event 1 or 2. Refer to the section (Section 5)
on Interrupt for further details.
b) If External interrupt status change is used to wake-up the EM78P507N and INTWK
bit of Banks 3, 4 RF register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P507N can be awakened only by Event 3.
c) If Low voltage detector is used to wake-up the EM78P507N and LVDWE bit of
Bank 3-RF register is enabled before SLEP, the WDT must be disabled by software.
Hence, the EM78P507N can be awakened only with Event 4.
6.4.2 Wake-up and Interrupt Modes Operation Summary
All categories under Wake-up and relative Interrupt modes are summarized below:
Wake-up
Signal
Sleep Mode
Idle Mode
Wake-up
Green Mode Normal Mode
TCC time out
+ interrupt
+ next instruction
Interrupt
Interrupt
Interrupt
Interrupt
Wake-up
+ interrupt
(if interrupt is enabled)
Wake-up
+ interrupt
(if interrupt is enabled)
INT pin
+ next instruction
+ next instruction
Wake-up
Timer 1
Timer 2
Timer 3
+ interrupt
+ next instruction
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Wake-up
+ interrupt
+ next instruction
Wake-up
+ interrupt
+ next instruction
Wake-up
+ interrupt
(if interrupt is enabled)
UART
Interrupt
Interrupt
+ next instruction
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
41
EM78P507N
8-Bit Microcontroller
(Continuation)
Wake-up
Signal
Sleep Mode
Idle Mode
Green Mode Normal Mode
Wake-up
+ interrupt
(if interrupt is enabled) (if interrupt is enabled)
Wake-up
+ interrupt
LVD
I2C
SPI
A/D
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
+ next instruction
Wake-up
+ next instruction
Wake-up
+ interrupt
(if interrupt is enabled)
+ interrupt
+ next instruction
+ next instruction
Wake-up
Wake-up
+ interrupt
(if interrupt is enabled)
+ interrupt
+ next instruction
+ next instruction
Wake-up
Wake-up
+ interrupt
+ interrupt
(if interrupt is enabled) (if interrupt is enabled)
+ next instruction
WDT time out RESET
+ next instruction
RESET
RESET
RESET
NOTE
User must set the wake up register (Bank 3 RF Bits 2~7 and Bank 4 RF Bits
0~7).
Actions to be taken after Wake up through INT pin, A/D, UART, SPI, I2C, or LVD
from Sleep and Idle modes:
1. If interrupt is enabled interrupt+ next instruction
2. If interrupt is disabled next instruction.
6.4.3 Status of T and P of the Status Register
A reset condition is initiated by one of the following events:
1) Power-on condition
2) High-low-high pulse on the /RESET pin
3) Watchdog Timer time-out
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
The values of T and P, as listed in the table below, are used to check how the processor
wakes up.
Values of RST, T, and P after Reset
Reset Type
T
1
P
1
Power-on
/RESET during Operation mode
/RESET wake-up during Sleep mode
WDT during Operation mode
*P
1
*P
0
0
*P
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
*P: Previous status before reset
The following table shows the events which may affect the status of T and P.
Status of RST, T, and P affected by Events
Events
T
1
1
0
1
1
P
1
Power-on
WDTC instruction
WDT time-out
SLEP instruction
1
*P
0
Wake-up on pin changed during Sleep mode
0
*P: Previous value before reset
Controller Reset Block Diagram
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-On Reset
Voltage Detector
WTE
WDT Timeout
WDTE
WDT
Reset
Setup time
/RESET
Figure 6-6 Controller Reset Functional Block Diagram
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
43
EM78P507N
8-Bit Microcontroller
6.5 Interrupt
The EM78P507N has 21 interrupts as listed below:
1. Low Voltage Detector Interrupt
2. TCC Overflow Interrupt
3. External Interrupt (INT0~INT9) Pin
4. Timers 1~3 Underflow Interrupt
5. A/D Conversion Completed Interrupt
6. SPI Transmit/Receive Interrupt
7. UART Transmit/Receive/Error Completed Interrupt
8. I2C Transmit/Receive Interrupt
External interrupt can select the detector edge in Banks 3 RE and RF (EIESH, EIESL).
During a power source unsteady situation, such as external power noise interference
or EMS test condition, it will cause the power to vibrate fiercely. While VDD is still
erratic, the voltage supply may be below the required operational voltage. When this
condition occurs, the IC kernel must automatically keep all the register status.
ISR is the Interrupt Status Register that records the interrupt requests in the relative
flags/bits. IMR is an Interrupt Mask Register. The global interrupt is enabled by the ENI
instruction and is disabled by the DISI instruction. When one of the interrupts (if
enabled) occurs, the next instruction will be fetched from its address. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in ISR. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag in the Interrupt Status Register is set regardless of the status of its mask bit or
ENI execution. Note that the outcome of ISR will be the logic AND of ISR and IMR.
The RETI instruction ends the interrupt routine and enables the global interrupt (ENI
execution).
Interrupt
occurs
Interrupt sources
ACC
R1
STACKACC
ENI/DISI
STACKR1
STACKR2
STACKR3
R2
R3
RETI
Figure 6-7a Interrupt Backup Diagram
With EM78P507N, each individual interrupt source has its own interrupt vector as
depicted in the following table.
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(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Interrupt Vector
0003H
0006H
0009H
000CH
000FH
0012H
0015H
0018H
001BH
001EH
0021H
0024H
0027H
002AH
002DH
0030H
0033H
0036H
0039H
003CH
003FH
0042H
Interrupt Status
Low voltage detector interrupt
TCC overflow interrupt
External INT0 interrupt
External INT1 interrupt
External INT2 interrupt
External INT3 interrupt
External INT4 interrupt
External INT5 interrupt
External INT6 interrupt
External INT7 interrupt
External INT8 interrupt
External INT9 interrupt
Timer 1 overflow interrupt
Timer 2 overflow interrupt
Timer 3 overflow interrupt
A/D Converter complete interrupt
SPI transmti/receive complete interrupt
UART transmit complete interrupt
UART error complete interrupt
UART receive complete interrupt
I2C transmit/receive complete interrupt
I2C Slave stop interrupt
VDD
PR
IRQn
D
CLK
CL
Q
Q
.
.
/IRQn
INT
RFRD
IRQm
ISR
ENI / DISI
PR
D
IOD
Q
Q
CLK
CL
IOCFWR
IMR
/RESET
IOCFRD
RFWR
Figure 6-7b Interrupt Input Circuit
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
45
EM78P507N
8-Bit Microcontroller
6.6 Analog-to-Digital Converter (ADC)
6.6.1 Registers for ADC Circuit
R_BANK Addr. Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1 005 ADCR1 ADRUN ADP ADCK1 ADCK0
-
-
-
-
R/W
R/W
ADREF
R/W
R/W
R/W
-
-
-
-
Bank 1 006 ADCR2
-
ADIS4 ADIS3 ADIS2 ADIS1 ADIS0
-
R/W
ADD4
R
R/W
ADD3
R
R/W
ADD2
R
R/W
ADD1
R
R/W
ADD0
R
Bank 1 007 ADDL ADD7 ADD6
ADD5
R
R
R
Bank 1 008 ADDH
ADD11 ADD10 ADD9
ADD8
R/W
R/W
ADE3
R/W
R/W
ADE2
R/W
R/W
ADE1
R/W
Bank 1 009 ADIC1 ADE7
ADE6
ADE5
ADE4
ADE0
R/W
R/W
R/W
R/W
R/W
Bank 1 00A ADIC2 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9
R/W R/W R/W R/W R/W R/W R/W
ADE8
R/W
Bank 1 00B ADIC3 ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16
R/W
R/W
R/W
ADIE
R/W
R/W
R/W
R/W
R/W
R/W
Bank 0 00E
Bank 0 00F
IMR
ISR
ADIF
R/W
AD23 (PC2)
AD22 (P94)
AD21 (P95)
VDD
VREF
Power Down
ADC
(Successive Approximation)
Start to Convert
AD3 (P90)
Fosc/4
AD2 (P91)
AD1 (P92)
AD0 (P93)
Fosc/16
4 to 1
MUX
Fosc/32
Fosc/64
ADIC1
ADIC2
ADIC3
ADIC4
0~23
3
2
1
0
5
4
5
5
11 10
9
8
7
6
5
4
3
2
1
0
7
6
6
ADICH
ADCR
ADCR
ADCR
ISR
IMR
DATA BUS
Figure 6-8 ADC Functional Block Diagram
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(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
It is a 12-bit successive approximation type AD converter. The upper side of analog
reference voltage can select either internal VDD or external input pin P84 (VREF) by
setting the ADREF bit in ADCR2.
6.6.2 ADC Data Register
When the A/D conversion is complete, the result is loaded to the ADDH (4-bit) and
ADDL (8-bit). The START/END bit is cleared, and the ADIF is set.
6.6.3 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation by A/D converter
are dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample holding
capacitor. The application program controls the length of the sampling time to meet the
specified accuracy. Generally speaking, the program should wait for 2 µs for each K
of the analog source impedance and at least 2 µs for the low-impedance source. The
maximum recommended impedance for the analog source is 10K at Vdd =3.3V. After
the analog input channel is selected, this acquisition time must be done before A/D
conversion can be started.
6.6.4 A/D Conversion Time
ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles.
This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D
conversion. For the EM78P507N, the conversion time per bit is about 4µs. The table
below shows the relationship between Tct and the maximum operating frequencies.
Maximum
Conversion Rate
per Bit
Maximum
Frequency (Fc)
Maximum
Conversion Rate
ADCK1:0 Operation Mode
0 0
0 1
1 0
1 1
Fc/4
Fc/16
Fc/32
Fc/64
1 MHz
4 MHz
8 MHz
16 MHz
250kHz (4 µs)
250kHz (4 µs)
250kHz (4 µs)
250kHz (4 µs)
48 µs (20.83kHz)
48 µs (20.83kHz)
48 µs (20.83kHz)
48 µs (20.83kHz)
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(This specification is subject to change without prior notice)
47
EM78P507N
8-Bit Microcontroller
6.7 SPI (Serial Peripheral Interface)
6.7.1 Registers for SPI Circuit
R_BANK Addr. Name Bit 7
Bit 6
TD1
Bit 5
TD0
Bit 4
-
Bit 3
OD3
R/W
Bit 2
OD4
R/W
Bit 1
-
Bit 0
RBF
R
Bank 3 0X0A
Bank 3 0X0B
Bank 3 0X0C
Bank 3 0X0D
SPIS
SPIC
SPIR
SPIW
IMR
DORD
R/W
R/W
SPIE
R/W
R/W
SRO
R/W
CES
R/W
SSE
SDOC SBRS2 SBRS1 SBRS0
R/W R/W R/W R/W
R/W
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
R
R
R
R
R
R
R
R
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
R/W
R/W
R/W
R/W
SPIE
R/W
SPIF
R/W
R/W
R/W
R/W
R/W
Bank 0
Bank 0
0x0E
0x0F
ISR
6.7.2 Overview and Features
Overview:
Figures 7-9a and 7-9b below show how the EM78P507N communicates with other
devices through the SPI module. If the EM78P507N is a Master controller, it sends a
clock through the SCK pin. A couple of 8-bit data are transmitted and received at the
same time. However, if the EM78P507N is defined as a Slave, its SCK pin could be
programmed as an input pin. Data will continue to be shifted based on both the clock
rate and the selected edge. You can also set the SPIS Bit 7 (DORD) to determine the
SPI transmission order, the SPIC Bit 3 (SDOC) to control the SO pin after serial data
output status, and the SPIS Bit 6 (TD1) & Bit 5 (TD0) to determine the SO status output
delay times.
Features:
Operation in either Master mode or Slave mode
Full duplex, 3-wire synchronous communication
Programmable baud rates of communication
Programming clock polarity (RD Bit 7)
Interrupt flag available for the read buffer full
SPI transmission order
After serial data output SDO status select
SDO status output delay time
Up to 8 MHz bit frequency (maximum)
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
SDO
SPIW Reg
SPIW Reg
SPIR Reg
SPIR Reg
/SS
SDI
SPI Module
SPIS Reg
SCK
Master Device
Slave Device
Figure 6-9a SPI Master/Slave Communication
SDI
SDO
SCK
/SS
VDD
Master
P70
P71
P72
P73
Slave Device 1
Slave Device 2
Slave Device 4
Slave Device 3
Figure 6-9b SPI Single-Master and Multi-Slave Configurations
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
49
EM78P507N
8-Bit Microcontroller
6.7.3 SPI Functional Block Diagrams
Read
Write
RBF
SPIIF
SSE
SPIW
SPIR reg
reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
SI
SPIC reg
SO
Edge
Select
SBR0 ~SBR2
Noise
Filter
/SS
SBR2~SBR0
/
SS
Clock Select
Prescaler
2, 4, 8, 16, 32
Fosc
Edge
Select
SCK
TMR2
CES
Figure 6-9c SPI General Functional Block Diagram
SPI
SO
SI
Shift Clock
SPI Shift
Buffer
FOSC
2 1 0
SPIC
7 6 4 5 4
3
0
7~0
SPIW
7~0
SPIR
SPIC
ISR
SPIC
SPIS
DATA Bus
Figure 6-9d SPI Transmission Functional Block Diagram
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Listed below are the function descriptions of each block depicted in Figures 6-9c and
6-9d above. It also explains how to carry out the SPI communication with the relevant
signals.
PA4/SDI: Serial Data In
PA5/SDO: Serial Data Out
PA6/SCK: Serial Clock
PA7//SS: /Slave Select (Option). This pin (/SS) may be required in Slave mode
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to “1” when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift. The SSE bit will be kept
at “1“ if communication is still undergoing. This flag must be cleared as the shifting
is completed. Users can determine if the next write attempt is available.
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and
the SPIW registers are shifted at the same time. Once data are written, SPIS
starts transmission/reception. The data received will be moved to the SPIR
register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full)
flag and the SPIIF (SPI transmit/receive completed Interrupt flag) are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
SBRS2~SBRS03: Programming the clock frequency/rates and sources.
Clock Select: Selects either the internal or the external clock as the shifting clock.
Edge Select: Selects the appropriate clock edges by programming the CES bit.
6.7.4 SPI Signal and Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS are as follows:
PA4/SDI:
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last.
Defined as high-impedance, if not selected.
3 If EM78P507N acts as the Master or Slave device to transmit and receive data, be sure to operate at lower Baud
rate of less than 3MHz and ensure that the operating voltage higher than 2.5V.
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EM78P507N
8-Bit Microcontroller
Program the same clock rate and clock edge to latch on both the Master and
Slave devices.
The received byte will update the transmitted byte.
The RBF will be set when the SPI operation is completed.
Timing is as shown in Figures 6-10a and 6-10b below.
PA5/SDO:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last.
Program the same clock rate and clock edge to latch on both the Master and
Slave devices.
The received byte will update the transmitted byte.
The CES bit will be reset when the SPI operation is completed.
Timing is as shown in Figures 6-10a and 6-10b below.
PA6/SCK:
Serial Clock
Generated by a Master device
Synchronize the data communication on both the SDI and SDO pins.
The CES is used to select the edge to communicate.
The SBR0~SBR2 is used to determine the baud rate of communication.
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode.
Timing is as shown in Figures 6-10a and 6-10b below.
PA7//SS:
Slave Select; negative logic
Generated by a Master device to indicate the Slave(s) has to receive data.
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed.
Ignores the data on the SDI and SDO pins while /SS is high, because the SO is
no longer driven
Timing is as shown in Figures 6-10a and 6-10b below.
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EM78P507N
8-Bit Microcontroller
NOTE
1. The Priority of PA4/SDO Pin:
PA4/SDO Pin Priority
High
Low
PA4
SDO
2. The Priority of PA5/SCK Pin:
PA5/SCK Pin Priority
High
SCK
Low
PA5
3. The Priority of PA6/SDI Pin:
PA6/SDI Pin Priority
High
SDI
Low
PA6
4. The Priority of PA7 / /SS Pin :
PA7 / /SS Pin Priority
High
/SS
Low
PA7
6.7.5 SPI Mode Timing
Figure 6-10a SPI Mode with /SS Disabled Timing Diagram
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
53
EM78P507N
8-Bit Microcontroller
The SCK edge is selected by programming bit CES. The waveform shown in the above
figure (Figure 6-10a) is applicable regardless whether the EM78P507N is in Master or
Slave mode with /SS disabled. However, the waveform in the following Figure 6-10b
can only be implemented in Slave mode with /SS enabled.
Figure 6-10b SPI Mode with /SS Enabled Timing Diagram
6.8 I2C Function
Registers for I2C Circuit
R_BAN
Addr. Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
K
Bank 7 0X05 I2CCR1 Storbe/Pend IMS
ISS
STOP SAR_EMPTY ACK FULL EMPTY
R/W R/W R/W R/W
I2CT0 I2CCS I2CEN
R/W
I2CRIF
R/W
SA6
R/W
DA7
R/W
-
R/W
R/W
R/W
I2CTS1
R/W
SA2
R/W
DA3
R/W
I2CSPE
R/W
DB3
R/W
-
Bank 7 0X06 I2CCR2
Bank 7 0X07 I2CSA
Bank 7 0X08 I2CDA
Bank 7 0X09 I2CA
Bank 7 0x0A I2CDB
Bank 7 0x0F I2CCR3
I2CRIE I2CTIF I2CTIE
R/W
SA5
R/W
DA6
R/W
R/W
SA4
R/W
DA5
R/W
R/W
SA3
R/W
DA4
R/W
IBEN
R/W
DB4
R/W
-
R/W
SA1
R/W
DA2
R/W
R/W
SA0
R/W
DA1
R/W
R/W
IRW
R/W
DA0
R/W
DA8
R/W
DB0
R/W
IBFULL AMB
I2CSPF DA9
-
R/W
DB6
R/W
-
R/W
DB5
R/W
-
R/W
DB2
R/W
-
R/W
DB1
R/W
DB7
R/W
-
GCEN I2CBF
R/W R/W
-
-
-
-
-
-
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Read
Write
FULL
I2CRIF
I2CTIF
I2CDB reg
Buffer Full Detector
Control and
Status reg
SCL
I2CSR reg
MSb
LSb
SDA
Add Match
Match Detect
I2CDA reg
Start and Sotp
bit Detect
Figure 6-11a I2C Block Diagram
The EM78P507N supports a bidirectional, 2-wire bus, 7-bit/10-bit addressing and data
transmission protocol, and has 16 provisional buffers to save the received data. A
device that sends data onto the bus is defined as transmitter, while a device receiving
data is defined as a receiver. The bus has to be controlled by a Master device which
generates the Serial Clock (SCL), controls the bus access, and generates the Start and
Stop conditions. Both Master and Slave can operate as transmitter or receiver, but only
the Master device can determine which mode is activated.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a
pull-up resistor. When the bus is free, both lines are HIGH. The output stages of the
devices connected to the bus must have an open-drain or open-collector to perform the
wired-AND function. Data on the I2C bus can be transferred at the rates of up to
100kbit/s in the Standard-mode or up to 400kbit/s in the Fast-mode.
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the SCL
line is LOW.
Within the procedure of the I2C bus, unique situations could arise, which are defined as
START (S) and STOP (P) conditions. A HIGH to LOW transition on the SDA line while
SCL is HIGH, is one of such unique cases. This situation indicates a START condition.
Product Specification (V1.1) 04.08.2016
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55
EM78P507N
8-Bit Microcontroller
A LOW to HIGH transition on the SDA line while SCL is HIGH, defines a STOP
condition.
The EM78P507N has a 16-byte buffer (BANK 7 0X30 ~ 0X3F) for the received data in
I2C function. The 16-bit buffer characteristics requires that when you want to use this
buffer, the IBEN bit in BANK 7 R9 needs to be enabled. For example, after the buffer
has received data from one device and followed by another data received from another
device, the previously received data will be overwritten by the recently received data.
This is because the I2C receives the data from different devices address. However, if
the first and subsequently received data are from the same device address, all the data
will be saved in the 16-byte buffer. On the other hand, if the previously received data
were transmitted in the I2C format (including the START and STOP signals), followed
by subsequent data (from the same device) transmitted in other format (including
START signal); the previously received data will also be overwritten by the recently
received data. If the 16 bytes buffer is full, the IBFULL flag will be set by hardware and
cleared by software.
The following will discus the I2C interrupt procedure. When EM78P507N acts as the
Master device and transmits the data to Slave device, the Slave device address will
transmit first. After address transmission is completed, the transmit flag of the Master
device will set automatically. Likewise, when EM78P507N acts as the Slave device, its
receiver flag will also set automatically. In other circumstances where the Master
device wants to read or receive the data from the Slave device after the Slave device
has received the data transmitted by the Master device, the Master device transmit flag
will automatically set. Likewise, the Slave device transmit flag will also automatically be
set.
SCL
SDA
data line change
stable;
data valid allowed
of data
START
STOP
Figure 6-11b I2C Format Data Transfer Schematic
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.8.2 7-Bit Slave Address
The Master-transmitter transmits to Slave-receiver. The data transfer direction is not
subject to change. The Master reads the Slave immediately after the first byte. At the
moment of the first acknowledge, the Master-transmitter becomes a Master-receiver
and the Slave- receiver becomes a Slave-transmitter. This first acknowledge is still
generated by the Slave. The STOP condition is generated by the Master, which has
previously sent a not-acknowledge (A). The difference between Master-transmitter
with Master-receiver occurs only in R//W bit. If the R//W bit is “0”, the Master device is
a transmitter. Otherwise, the Master device would be a receiver (R//W bit is “1”). The
Master-transmitter operation is further described in Figure 6-11c, and that of
Master-receiver is described in Figure 6-11d below.
8 Bits
8 Bits
DATA
8 Bits
DATA
S
Slave Address
7 Bits
R//W
A
A
A//A
P
'0'
Write
data transferred
(n byte + acknowledge)
A = acknowledge (SDA low)
/A = not acknowledge (SDA high)
S = Start
Master to Slave
Slave to Master
P = Stop
Figure 6-11c Master-Transmitter Transmits to Slave-Receiver with 7-Bit Slave Address
8 Bits
S
Slave Address
7 Bits
R//W
A
DATA
A
DATA
/A
P
'1' Read
data transferred
(n byte + acknowledge)
Figure 6-11d Master-Receiver Reads from Slave-Transmitter with 7-Bit Slave Address
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(This specification is subject to change without prior notice)
57
EM78P507N
8-Bit Microcontroller
6.8.2 10-Bit Slave Address
In 10-Bit Slave address mode, using 10-bit for addressing exploits the reserved
combination 11110XX for the first 7 bits of the first byte following a START (S) or
repeated START (Sr) condition. The first 7 bits of the first byte are the combination
11110XX of which the last 2 bits (XX) are the two most-significant bits of the 10-bit
address. If the R//W bit were “0”, the second byte after acknowledge would be the 8
address bits of the10-bit Slave address. Otherwise, the second byte would just be the
next transmitted data from a Slave to Master device (R//W bit were “1”). The first bytes
11110XX are transmitted by using the Slave address register (I2CSA), and the second
bytes XXXXXXXX would be transmitted by using the data buffer (I2CDB).
The possible data transfer formats for 10-bit Slave address mode are described in the
following sub-sections:
Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave Address
When the Slave has received the first byte after the START bit from the Master, each
Slave device will compare the 7 bits of the first byte (11110XX) with their own address
and with the 8th bit (R//W). If the R//W bit is “0”, the Slave will return acknowledge (A1)
and it is possible that more than 1 Slave devices will return A1. The Slave devices will
continue to compare the second address (XXXXXXXX). If a Slave device has found a
match, that particular Slave device will be the only one to return the acknowledge (A1).
The matched Slave device will remain addressed by the Master until it receives a
STOP condition or a repeated START condition followed by a different Slave address.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
A//
A
S
A1
A2
A
DATA
DATA
P
R//W
Write
1st 7-Bits
2nd 8-Bits
Figure 6-12a Master-Transmitter Transmits to Slave-Receiver with 10-Bit Slave Address
Master-Receiver Read Slave-Transmitter with a 10-bit Slave Address
Up to, and including Acknowledge Bit A2; the procedure is the same as that of
Master-transmitter addressing the Slave-receiver as described above. After the
Acknowledge A2, a repeated START condition (Sr) takes place, followed by 7 bits
Slave address (11110XX) but with the 8th bit R//W=1. The addressed Slave device will
then return an Acknowledge A3. If the repeated START (Sr) condition occurs and the 7
bits of the first byte (11110XX) are received by the Slave device, all the Slave devices
will compare with their own address and test the 8th R//W. However, none of the Slave
devices can return an acknowledgement because R//W=1.
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EM78P507N
8-Bit Microcontroller
1 1 1 1 0 X X
0
1 1 1 1 0 X X 1
Slave
Address
A
1
Slave
Address
A
2
Slave
Address
A
3
/
A
S
Data
A
Data
P
Sr
R//W
Write
1st 7-Bits R//W
read
1st 7-Bits
2nd 8-Bits
Figure 6-12b Master-Receiver Reads from Slave-Transmitter with 10-bit Slave Address
Master Transmit and Receives Data to and from the Same Slave Device with
10-Bit Slave Address
The Initial operation of this data transfer format is the same as explained in the above
subsection on “Master- Transmitter Transmits to Slave-Receiver with 10-bit Slave
Address”. Then the Master device starts to transmit the data to the Slave device.
When the Slave device receives an Acknowledge or Not Acknowledge that is followed
by repeat START (Sr), the operation “Master-Receiver Reads from Slave-Transmitter
with 10-bit Slave Address” described in the preceding subsection, is then performed.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
Data
Data
R//W
Write
1st 7-Bits
2nd 8-Bits
1 1 1 1 0 X X
1
Slave
Address
/
A
Sr
A
A
Data
Data
P
R//W
Write
1st 7-Bits
Figure 6-12c Master Transmit and Receives Data to and from the Same Slave
Device with 10-Bit Address
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
59
EM78P507N
8-Bit Microcontroller
Master Device Transmits Data to Two or More Slave Devices with 10 & 7 Bits
Slave Address
For 10-bit Slave address transmittal, the Initial operation of this data transmit format is
the same as explained in the above subsection on “Master-Transmitter Transmits to
Slave-Receiver with 10-bit Slave Address” which describes how to transmit the data to
Slave device. After the Master device have finished the initial transmittal, and wants to
transmit the data to other devices, the Master needs to address each of the new Slave
devices by repeating the initial operation mentioned above.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
Data
Data
R//W
Write
1st 7-Bits
2nd 8-Bits
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
A
A
A
A//A
Data
Data
P
R//W
Write
1st 7-Bits
2nd 8-Bits
Figure 6-12d Master Transmitting to More than One Slaves with 10-Bit Slave Address
When the Master device wants to transmit data in 7-bit and 10-bit Slave address modes
successively, this could be done after the START or repeat START conditions as
illustrated in the following figure.
0
Slave
Address
S
A
A
A//A
Data
Data
R//W
Write
7-Bits
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
A
A
A
A//A
Data
Data
P
R//W
Write
1st 7-Bits
2nd 8-Bits
Figure 6-12e Master Successively Transmitting 7-Bit & 10-Bit Slave Addresses to Slave
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EM78P507N
8-Bit Microcontroller
6.8.3 Master Mode
In transmitting serial data, the I2C operates as follows:
1. Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C master function.
3. Write Slave address into the I2CSA register and IRW bit to select read or write.
4. Set strobe bit will start transmit and then Check SAR_EMPTY bit.
5. Write 1st data into the I2CDB register, set strobe bit and Check EMPTY bit.
6. Write 2nd data into the I2CDB register, set strobe bit, STOP bit and Check EMPTY
bit.
6.8.4 Slave Mode
In receiving, the I2C operates as follows:
1. Set I2CTS1~0, I2CCS and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C slave function.
3. Write device address into the I2CDA register.
4. Read I2CDB register (address) and then clear Pend bit.
5. Check Full bit, read I2CDB register (1st data) and then clear Pend bit.
6. Check Full bit, read I2CDB register (2nd data) and then clear Pend bit.
7. If the I2CSPE bit is enabled and the slave device has received a stop signal from
the master device, the flag of I2CSPF would be set automatic and the device be
into interrupt address.
6.9 Timer/Counter 1
Registers for Timer/Counter 1 Circuit
R_BANK Addr. Name
Bit 7
Bit 6
Bit 5
T1MS2 T1MS1 T1MS0
R/W R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2 0X06 T1CR
TIS1
TIS0
T1P2
R/W
T1P1
T1P0
R/W
R/W
R/W
R/W
Bank 2 0X07
TSR
T1MOD TRCB T1CSS1 T1CSS0 T2CSS
R/W R/W R/W R/W R/W
T1EN
R/W
-
T1OC
R/W
-
Bank 2 0X08 T1PD PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
R/W
TD1[7]
R/W
R/W
TD1[6]
R/W
R/W
TD1[5]
R/W
R/W
TD1[4]
R/W
R/W
TD1[3]
R/W
R/W
TD1[2]
R/W
R/W
TD1[1]
R/W
R/W
TD1[0]
R/W
Bank 2 0X09
Bank 1 0x0E
Bank 0 0x0F
T1TD
IMR
ISR
T1IE
R/W
LVDIE
R/W
ADIE
R/W
SPIIE
R/W
URTIE
R/W
EXIE9
R/W
EXIE8
R/W
TCIE
R/W
T1IF
R/W
LVDIF
R/W
ADIF
R/W
SPIIF
R/W
URTIF
R/W
EXIF9
R/W
EXIF9
R/W
TCIF
R/W
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
61
EM78P507N
8-Bit Microcontroller
TSR.2
T1CLK Pin
8-bit Counter
8-to-1 MUX
IMR.7
Fm
Fs
MUX
T1P0 ~ T1P2
One-shot
TSR.1
Timer1 Interrupt
TSR.4~5
Data Bus
Underflow
8-bit
Down-counter
F/F
PWM1,
T1OUT Pin
TSR.0
TSR.6
T1CR.3~5
T1CAP Pin
MUX
Match
T1PD
Timer1 Interrupt
T1CR.6~7
T1CR.3~5
Data Bus
T1CR.3~5
T1TD
Data Bus
T1PD
Data Bus Data Bus
T1TD
Figure 6-13 Timer/Counter 1 Configuration
6.9.1 Timer Mode
In Timer mode, count down is performed using the internal clock. The down-counter
value auto reloads from T1PD. When the contents of the down-counter underflows,
interrupt is the generated and the counter is cleared. Counting down resumes after the
counter is cleared.
6.9.2 T1OUT Mode
In Timer 1 underflow Output mode, count down is performed using the internal clock
with prescaler or External clock through T1CLK pin or Sub Frequency with prescaler.
The counter value is loaded from T1PD when the counter underflows. The F/F output
is toggled and the counter is auto-reloaded from T1PD each time an overflow is found.
The F/F output is inverted and output to /T1OUT pin. This mode can generate 50%
duty pulse output. The program can initialize the F/F and it is initialized to “0” during a
reset. A T1OUT interrupt is generated each time the /T1OUT output is toggled.
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(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Source Clock
Down-counter
n
n
n-2 n-3
n
n-1
n-2
n-1
n-1
1
0
1
0
n-1
1
0
n
n
T1PD
F/F
T1OUT Pin
Timer 1 Interrupt
Figure 6-14 T1OUT Mode Timing Diagram
6.9.3 Capture Mode
In Capture mode, the pulse width, period, and duty of the T1CAP input pin are
measured under this mode, which can be used in decoding the remote control signal.
The counter is free running by the internal clock. On the rising (falling) edge of T1CAP
pin input, the contents of the counter is loaded into T1PD, then the counter is cleared
and interrupt is generated. On the falling (rising) edge of T1CAP pin input, the contents
of the counter are loaded into T1TD. The counter continues counting on the next rising
edge of the T1CAP pin input and the contents of the counter are loaded into T1PD.
Then, counter is cleared and interrupt is generated again. If an overflow occurs before
the edge is detected, the 00H is loaded into T1PD and an underflow interrupt is
generated. During interrupt processing, it can be determined whether or not there is an
overflow by checking whether the T1PD value is 00H. After an interrupt (capture to
T1PD or overflow detection) is generated, capture and underflow detection are halted
until T1PD is read out.
Source Clock
Down-counter
m+1
m
m-1
n-1
FF
FE
K
n
FF FE FD
1
0
1
FE FD
FE
FF
FC
FF
K
T1CAP Pin Input
T1PD
n
00 (Underflow)
Underflow
m
T1TD
Capture
Capture
Timer 1 Interrupt
Reading T1PD
Figure 6-15 Capture Mode Timing Diagram
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
63
EM78P507N
8-Bit Microcontroller
6.9.4 PWM Mode
In Pulse Width Modulation (PWM) Output mode, counting down is performed using the
internal clock with prescaler or external clock through T1CLK Pin or Sub Frequency
with prescaler. The PWM1 duty cycle is controlled by T1TD, and the PWM1 period is
controlled by T1PD. The pulse at the PWM1 pin is held at high level as long as the
counter value of T1TD is greater than or equal to zero, while the pulse is held at low
level until the counter value of T1PD underflows. The F/F is toggled when counter
underflows. While the counter is still counting, the F/F is toggled again when the
counter underflows, then the counter is auto-reloaded from T1PD. The F/F output is
inverted and output to the /PWM pin. A Timer1 interrupt is generated each time an
underflow occurs. T1PD is configured as a 2-stage shift register and, during output, will
not switch until one output cycle is completed even if T1PD is overwritten. Therefore,
the output can be changed continuously. T1PD is also shifted for the first time by
setting T1S to “1” after data is loaded to T1PD.
Source Clock
Down-counter
T1TD
n
n-m+2 n-m+1
n-m+2
n-m
1
0
n
FF
FE
0
n-1 n-2
n-m
0
n
n-2
n-m+1
2
n-1
m
m
m
n
T1PD
n
n
F/F
/PWM
1 Period
Timer 1 Interrupt
Figure 6-16 PWM Mode Timing Diagram
NOTE
Under 16-bit timer mode, all Timer 1 function resolution becomes 16 bits.
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.10 Timer 2
Registers for Timer/Counter 2 Circuit
R_BANK Addr. Name
Bit 7
TIS1
R/W
Bit 6
TIS0
R/W
Bit 5
T1MS2 T1MS1 T1MS0
R/W R/W R/W
Bit 4
Bit 3
Bit 2
T1P2
R/W
Bit 1
T1P1
R/W
0
Bit 0
T1P0
R/W
Bank 2 0X06
Bank 2 0X07
Bank 2 0X0A
Bank 2 0X0B
Bank 2 0X0C
T1CR
TSR
T1MOD TRCB T1CSS1 T1CSS0 T2CSS
T1EN
R/W
T1OC
R/W
R/W
T2IF
R/W
R/W
T2IE
R/W
R/W
T2S
R/W
R/W
T2MS1 T2MS0
R/W R/W
R/W
-
T2CR
T2P2
R/W
T2P1
R/W
T2P0
R/W
T2PD PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0]
T2TD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T2CR.5
Fm
8-bit Counter
8-to-1 MUX
T2CR.6
MUX
Fs
T2P0 ~ T2P2
Timer 2 Interrupt
TSR.3
Underflow
8-bit
Down-counter
PWM2 Pin
T2CR.3~4
T2CR.6
TSR.6
Timer 2 Interrupt
Match
T2PD
T2CR.3~4
Data Bus
T2PD
T2TD
Data Bus Data Bus
Figure 6-17 Timer 2 Configuration
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
65
EM78P507N
8-Bit Microcontroller
6.10.1 Timer Mode
In Timer mode, count down is performed using the internal clock with prescaler. When
the counter value from T2PD underflows, interrupt is generated and the counter is
cleared. Count down resumes after the counter is cleared. The counter value will
automatically reload from T2PD.
Internal clock
Down-counter
n
n-1 n-2
n-3 n-4
3
2
1
0
n
n-1
n-2 n-3
n-5
n
T2PD
counter
clear
Underflow
Timer 2 interrupt
Figure 6-18 Timer Mode Timing Diagram
6.10.2 PWM Mode
In Pulse Width Modulation (PWM) Output mode, count down is performed using the
internal clock with prescaler or Fsub with frequency. The PWM2 duty cycle is
controlled by T2TD, and the PWM2 period is controlled by T2PD. The pulse at the
PWM2 pin is held to high level as long as the T2TD counter value is greater than or
equal to zero while the pulse is held to low level until the T2PD counter value
underflows.
Source Clock
Down-counter
FF
FE
0
n
n-1
n-2
n-m+2
n-m+1
n-m
1
0
n-1
m
n
n-m+2
n-m+1
n-m
1
0
n
n+1
n
T2TD
T2PD
/PWM
m
m
n
n
1 Period
Timer 2 Interrupt
Figure 6-19 PWM Mode Timing Diagram
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.11 Timer 3
Registers for Timer/Counter 3 Circuit
R_BANK Addr. Name Bit 7
Bit 6
T3IE
R/W
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T1P1
R/W
Bit 0
T1P0
R/W
Bank 2 0X0C T3CR1
T3IF
T3EN T3CSS1 T3CSS0 T1P2
R/W
R/W
R/W
R/W
R/W
Bank 2 0X0D T3CR2
-
-
-
-
-
-
-
-
-
T3MS1 T3MS0
R/W R/W
-
-
Bank 2 0X0E T3PD PRD3[7] PRD3[6] PRD3[5] PRD3[4] PRD3[3] PRD3[2] PRD3[1] PRD[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T3CLK Pin
T3CR.5
8-bit Counter
8-to-1 MUX
Fm
Fs
MUX
T3P0 ~ T3P2
T3CSS1~0
Unerflow
8-bit
Down-counter
T3OUT Pin
T3CR.6
Timer3 Interrupt
T3PD
Data Bus
Figure 6-20 Timer 2 Configuration
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
67
EM78P507N
8-Bit Microcontroller
6.11.1 Timer Mode
In Timer mode, count down is performed using the internal clock with prescaler. When
the counter value from T3PD underflows, interrupt is then generated and the counter is
cleared. Count down resumes after the counter is cleared. The counter value will
automatically reload from T3PD.
6.11.2 T3OUT Mode
In Timer 3 Underflow Output mode, count down is performed using the internal clock
with prescaler or external clock through T3CLK Pin or Sub Frequency with prescaler.
The counter value is loaded from T3PD. When the counter underflows, this mode can
generate 50% duty pulse output. A T3OUT interrupt is generated each time the
/T3OUT output is toggled.
Source Clock
n
n
n-2 n-3
n
n-1
n-2
n-1
n-1
1
0
1
0
n-1
1
0
Down-counter
T3PD
n
n
T3OUT Pin
Timer3 Interrupt
Figure 6-21 PWM Mode Timing Diagram
6.12 Universal Asynchronous Receiver Transmitter (UART)
Registers for UART Circuit
R_BANK Addr. Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXE
R/W
RXE
R/W
BANK 3 005 URC1 URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
W
R/W
URRD8 EVEN
R/W
R/W
PRE
R/W
R/W
R/W
R/W
R
BANK 3 006
URS
PRERR OVERR FMERR URBF
R
R
R
R
R
BANK 3 007 URRD URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
R
R
R
R
R
R
R
R
BANK 3 008 URTD URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0
W
W
W
W
W
W
W
W
BANK3 009 URC2
UARTE
R/W
UINVEN
R/W
URRIF
R/W
T1IE
LVDIE
ADIE
SPIE
URTIE EXIE9
EXIE8
TCIE
BANK 0 00E
BANK 0 00F
ISR
IMR
R/W
T1IF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LVDIF
ADIF
SPIF
URTIF
EXIF9
EXIF8
TCIF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
Timer1
Baud rate
generator
Fsystem
Interrupt
Control
TXE
RXE
RX Control
TX Control
RX
RX shift register
Parity control
TX
URRD
URTD8
URRD8
Error flag
Data Bus
URTD
UINVEN
UINVEN
Figure 6-22a UART Functional Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and stop bit.
Full duplex data transfer is possible since the UART has an independent transmit and
receive sections. Double buffering for both sections allows the UART to be
programmed for continuous data transfer.
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in
which the least significant bit (LSB) comes first. The data bits are followed by the parity
bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on the falling edge of the start bit. When two or
three “0” are detected during three samples, it is recognized as normal start bit and the
receiving operation is started.
Idle state
(mark)
START
bit
Parity STOP
D0
D1
D2
Dn
bit
bit
1 bit
7 or 8 bits
One character or frame
1 bit
1 bits
Figure 6-22b UART Data Format
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
69
EM78P507N
8-Bit Microcontroller
6.12.1 UART MODE:
Three UART modes are availble, i.e.; Mode 1 ~ Mode 3. Mode 1 (7 bits data) and Mode
2 (8 bits data) allow the addition of a parity bit. The parity bit addition is not available in
Mode 3. The figure below shows the data format of each mode.
1
2
3
4
5
6
7
8
9
10 11
UMODE PRE
7 bits DATA
7 bits DATA
STOP
0
0
0
START
Mode 1
0
0
1
Parity STOP
STOP
START
8 bits DATA
8 bits DATA
0
0
1
1
0
1
START
START
Mode 2
Mode 3
Parity STOP
9 bits DATA
STOP
1
0
X
START
Figure 6-23 UART Modes 1, 2, & 3 Data Format
6.12.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Set the TXE bit of the URC register to enable the UART transmission function.
2. Write data into the URTD register and the UTBE bit of the URC register will be set
by hardware.
3. Then start transmitting.
4. Serially transmit data in the following order from the TX pin:
a) Start bit: one “0” bit is output.
b) Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.
c) Parity bit: one parity bit (odd or even selectable) is output.
d) Stop bit: one “1” bit (stop bit) is output.
Mark state: output “1” continues until the start bit of the next transmitted data. After
transmitting the stop bit, UART generates a URTIF interrupt (if enabled).
6.12.3 Receiving
In receiving, the UART operates as follows:
1. Set RXE bit of the URS register to enable the UART receiving function. The UART
monitors the RX pin and synchronizes internally when it detects a start bit.
2. Received data are shifted into the URRD register in LSB to MSB order.
3. The parity bit and the stop bit are received. After one character is received, UBIF bit
of URC2 register is set to “1”. This means the UART receive interrupt will occur.
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EM78P507N
8-Bit Microcontroller
4. The UART performs the following checks:
a) Parity check: The number of 1 of the received data must match the even or odd
parity setting of the EVEN bit in the URS register.
b) Frame check: The start bit must be 0 and the stop bit must be 1.
c) Overrun check: The URBF bit of the URS register must be cleared (that means
the URRD register should be read out) before the next received data is loaded
into the URRD register.
If any checked item failed, an ERROR interrupt will be generated (if enabled). If
the UART has completely received data, the receive-complete interrupt is
generated (if enabled). The error flag and receive complete flag should be
cleared by software. The URTIE bit is the interrupt enable bit of ERROR, UBIF
and URTIF.
5. Read the received data from URRD register and the URBF bit will be cleared by
hardware.
6.12.4 Baud Rate Generator
The baud rate generator is comprised of a circuit that generates a clock pulse to
determine the transfer speed for transmission/reception in the UART.
The BRATE2~BRATE0 bits of the URC register can determine the desired baud rate.
6.12.5 UART Timing
Transmission Counter Timing:
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
TSYSTEM/16
One bit cycle
Start bit
Bit 0
TXD pin
Figure 6-24a UART Transmission Counter Timing Diagram
Receiving Counter Timing:
Synchronization
(Reset counter)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
12 13
TSYSTEM/16
One bit cycle
Start bit
Bit 0
Stop bit
RXD pin
Sampling
Timing
Figure 6-24b UART Receiving Counter Timing Diagram
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
71
EM78P507N
8-Bit Microcontroller
UART Transmit Operation (8 bits data with parity bit):
Figure 6-24c UART Transmit Operation Timing Diagram
6.13 DA Conversion
Registers for DAC Circuits
R_BANK Addr. Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7 0X0B DACDL DACD7 DACD6 DACD5 DACD4 DACD3 DACD2 DACD1 DACD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DACD9 DACD8
R/W R/W
R/W
Bank 7 0X0C DACDH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bank 7 0X0D DACC DARUN
SEMC COF[3] COF[2] COF[1] COF[0]
R/W R/W R/W R/W R/W
R/W
Perform the Following steps to control the output current of DA:
1. Load the data to the DA buffer DACDL and DACDH.
2. Set the SEMC bit to determine the maximum level (3 or 4mA) of the output current.
3. Set the COF [3:0] to determine the range and resolution of the output current.
4. Set DARUN bit to “1” and clear by software.
The DA module is provided in the MCU internal circuit. When the register is set to
enable the DA module, the output current of the DA pin DACO is 0~3 or 4mA.
The maximum level of the DA output current is determined by the SEMC bit. If the
SEMCL is enabled, the maximum level of the DA output current is 4mA. The COF [3:0],
COAC [3:0], and SEMC are used to control the DA Conversion output current.
Examples: If SEMC is disabled and COF [3:0] are all “1”, the output current range of
DA Conversion would be between 0 and 3mA. In this case, the output
current of DA Conversion can be adjusted to 3mA1/16, 3mA2/16,
3mA3/16…3mA16/16, by COF[3:0].
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(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.14 Registers Initialized Values after Reset
Legend: -: Not used U: Unknown or don’t care, P: Previous value before wake-up,
T: Check “Reset Type” in Section 6.4.2.
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
R0
(IAR)
000
/RESET and WDT
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
PS2
0
PS1
0
PS0
0
0
0
0
BS2
0
BS1
0
BS0
0
Power-on
R1
(RPBSR)
001
002
003
/RESET and WDT
0
0
0
0
0
0
Wake-up from
Sleep & Idle mode
0
0
P
P
0
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
(PC)
/RESET and WDT
Wake-up from
Sleep & Idle mode
Continue to execute next instruction
Bit Name
VDB LVDEN LVDS
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-on
0
0
0
0
0
0
R3
(SR)
/RESET and WDT
P
Wake-up from
Sleep & Idle mode
0
0
P
t
t
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
U
P
U
P
U
P
U
P
U
P
U
P
R4
(RSR)
004
/RESET and WDT
Wake-up from
Sleep & Idle mode
0
0
P
P
P
P
P
P
Bit Name
Rbit7
Rbit6
Rbit5
Rbit4
Rbit3
Rbit2
Rbit1
Rbit0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
005 (TBLP)
R5
/RESET and WDT
Wake-up from
Sleep & Idle mode
0
0
0
P
P
P
P
P
Bit Name
TBSHL
0
0
0
0
0
0
Rbit12 Rbit11 Rbit10 Rbit9
Rbit8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R6
/RESET and WDT
006 (TBHP)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
P77
0
P76
0
P75
0
P74
0
P73
0
P72
0
P71
0
P70
0
Power-on
R7
Bank 0
007
/RESET and WDT
0
0
0
0
0
0
0
0
(Port 7)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
73
EM78P507N
8-Bit Microcontroller
(Continuation)
Reset Type
Bit Name
Addr.
Name
Bit 7
P87
0
Bit 6
P86
0
Bit 5
P85
0
Bit 4
P84
0
Bit 3
P83
0
Bit 2
P82
0
Bit 1
P81
0
Bit 0
P80
0
Power-on
R8
Bank 0
/RESET and WDT
0
0
0
0
0
0
0
0
008
(Port 8)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
P97
0
P96
0
P95
0
P94
0
P93
0
P92
0
P91
0
P90
0
Power-on
R9
Bank 0
/RESET and WDT
0
0
0
0
0
0
0
0
009
(Port 9)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PA7
0
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
Power-on
RA
Bank 0
/RESET and WDT
0
0
0
0
0
0
0
0
00A
(Port A)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PB7
0
PB6
0
PB5
0
PB4
0
PB3
0
PB2
0
PB1
0
PB0
0
Power-on
RB
Bank 0
/RESET and WDT
0
0
0
0
0
0
0
0
00B
(Port B)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
IDLE
0
0
0
0
0
0
CPUS
Power-on
1
1
1
1
RC
Bank 0
/RESET and WDT
00C
(SCCR)
Wake-up from
Sleep & Idle mode
0
0
P
P
P
0
P
P
Bit Name
WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0 RD
/RESET and WDT
00D (TWTCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
T1IE
LVDIE ADIE
SPIE URTIE EXIE9 EXIE8
TCIE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
RE
/RESET and WDT
00E
(IMR)
Wake-up from
Sleep & Idle mode
0
0
0
P
P
P
P
P
Bit Name
T1IF
LVDIF
ADIF
SPIF URTIF EXIF9 EXIF8
TCIF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
RF
/RESET and WDT
00F
(ISR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
74
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
010
~
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R10~R3F
/RESET and WDT
03F
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
ADRUN ADP ADCK1 ADCK0
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
Bank 1
R5
/RESET and WDT
005 (ADCR1)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
0
0
0
ADREF
0
0
0
ADIS4 ADIS3 ADIS2 ADIS1 ADIS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
R6
/RESET and WDT
006 (ADCR2)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
R7
/RESET and WDT
007
(ADDL)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
ADD11 ADD10 ADD9 ADD8
Power-on
0
0
0
0
0
0
0
0
Bank 1
R8
/RESET and WDT
008
(ADDH)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
R9
/RESET and WDT
009 (ADIC1)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
RA
/RESET and WDT
00A (ADIC2)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
RB
/RESET and WDT
00B (ADIC3)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
75
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
RCM1 RCM0 CLKOE CLKB1 CLKB0
Power-on
1
1
1
1
1
1
0
0
0
0
Bank 1
RC
/RESET and WDT
00C (COCR)
Wake-up from
Sleep & Idle mode
P
0
P
P
P
P
0
0
Bit Name
EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
RE
/RESET and WDT
00E
(EIMR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
RF
/RESET and WDT
00F
(EISR)
Wake-up from
Sleep & Idle mode
P
P
P
0
P
0
0
0
Bit Name
TIS1
TIS0 T1MS2 T1MS1 T1M0
T1P2
T1P1
T1P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
R5
/RESET and WDT
005
(T1CR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
T1MOD TRCB T1CSS1 T1CSS0 T2CSS T1EN
0
0
0
T1OC
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
0x06
R6
/RESET and WDT
(TSR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
R7
/RESET and WDT
007
(T1PD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
TD1[7] TD1[6] TD1[5] TD1[4] TD1[3] TD1[2] TD1[1] TD1[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
R8
/RESET and WDT
008
(T1TD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
T2IF
T2IE
T2EN T2MS1 T2MS0 T2P2
T2P1
T2P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
R9
/RESET and WDT
009 (T2CR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
76
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
RA
/RESET and WDT
00A (T2PD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
RB
/RESET and WDT
00B (T2TD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
T3IF
T3IE
T3EN T3CSS1 T3CSS0 T3P2
T3P1
T3P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
RC
/RESET and WDT
00C (T3CR1)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T3MS1 T3MS0
Power-on
0
0
0
0
Bank 2
RD
/RESET and WDT
00D (T3CR2)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
RE
/RESET and WDT
00E (T3PD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
TCC[7] TCC[6] TCC[5] TCC[4] TCC[3] TCC[2] TCC[1] TCC[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2
RF
/RESET and WDT
00F
(TCC)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
URTD8 UMODE1UMODE0BRATE2 BRATE1 BRATE0 UTBE
TXE
0
Power-on
U
P
0
0
0
0
0
0
0
0
0
0
1
1
Bank 3
R5
/RESET and WDT
0
005
(URC)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
URRD8 EVEN
PRE PRERR OVERR FMERR URBF
RXE
Power-on
U
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 3
R6
/RESET and WDT
006
(URS)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
77
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 3
R7
/RESET and WDT
007 (URRD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 3
R8
/RESET and WDT
008 (URTD)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
UARTE
0
0
0
UINVEN
0
0
0
0
0
0
URRIF
Power-on
0
0
0
0
0
0
Bank 3
R9
/RESET and WDT
009 (URC2)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
DORD
TD1
0
TD0
0
0
0
0
OD3
OD4
0
0
0
RBF
Power-on
0
0
0
0
0
0
0
0
Bank 3
RA
/RESET and WDT
0
0
00A (SPIS)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
CES
SPIEN SRO
SSE
SDOC SBRS2 SBRS1 SBRS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 3
RB
/RESET and WDT
00B (SPIC)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Bank 3
RC
/RESET and WDT
00C (SPIR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Bank 3
RD
/RESET and WDT
00D (SPIW)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
EIES7 EIES6 EIES5 EIES4 EIES3 EIES2 EIES1 EIES0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 3
RE
/RESET and WDT
00E (EIESH)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
78
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDWE I2CWE SPIWE ADWK INTWK9 INTWK8 EIES9 EIES8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 3
RF
/RESET and WDT
00F (EIESL)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
R7
/RESET and WDT
007
(IOC7)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
R8
/RESET and WDT
008
(IOC8)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
R9
/RESET and WDT
009
(IOC9)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
R9
/RESET and WDT
00A
(IOCA)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
RB
/RESET and WDT
00B
(IOCB)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
IOCC5 IOCC4 IOCC3 IOCC2 IOCC1 IOCC0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
Bank 4
RC
/RESET and WDT
00C (IOCC)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2 INTWK1 INTWK0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 4
RF
/RESET and WDT
00F (WKCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
79
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
PH77
0
Bit 6
PH76
0
Bit 5
PH75
0
Bit 4
PH74
0
Bit 3
PH73
0
Bit 2
PH72
0
Bit 1
Bit 0
PH71 PH70
Power-on
0
0
0
0
Bank 5
R7
/RESET and WDT
0
0
0
0
0
0
007 (P7PHCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PH87
PH86
PH85
PH84
PH83
PH82
0
0
0
PH80
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 5
R8
/RESET and WDT
008 (P8PHCR)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
PH97
PH96
PH95
PH94
PH93
PH92
PH91 PH90
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 5
R9
/RESET and WDT
009 (P9PHCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PHA7 PHA6 PHA5 PHA4 PHA3
PHA2 PHA1 PHA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 5
RA
/RESET and WDT
00A (PAPHCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
PHB7 PHB6 PHB5 PHB4 PHB3
PHB2 PHB1 PHB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 5
RB
/RESET and WDT
00B (PBPHCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
PHC5 PHC4 PHC3 PHC2 PHC1 PHC0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 5
RC
/RESET and WDT
00C (PCPHCR)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
OD77 OD76 OD75 OD74 OD73 OD72 OD71 OD70
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 6
R7
/RESET and WDT
007 (P7ODCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
OD87 OD86 OD85 OD84 OD83 OD82
0
0
0
OD80
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 6
R8
/RESET and WDT
008 (P8ODCR)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
80
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD97 OD96 OD95 OD94 OD93 OD92 OD91 OD90
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 6
R9
/RESET and WDT
009 (P9ODCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 6
RA
/RESET and WDT
00A (PAODCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 6
RB
/RESET and WDT
00B (PBODCR)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
PC5
0
PC4
0
PC3
0
PC2
0
PC1
0
PC0
0
Power-on
Bank 6
RC
/RESET and WDT
0
0
0
0
0
0
00C (Port C)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Strobe/
Pend
SAR_
EMPTY
IMS
ISS
Stop
ACK
FULL EMPTY
Bit Name
Power-on
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
Bank 7
R5
005 (I2CCR1)
/RESET and WDT
Wake-up from
Sleep & Idle mode
0
P
P
P
P
P
P
P
Bit Name
I2CRIF I2CRIE I2CTIF I2CTIE I2CTS1 I2CTS0 I2CCS I2CEN
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 7
R6
/RESET and WDT
006 (I2CCR2)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
SA6
0
SA5
0
SA4
0
SA3
0
SA2
0
SA1
0
SA0
0
IRW
0
Power-on
Bank 7
R7
/RESET and WDT
0
0
0
0
0
0
0
0
007 (I2CSA)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
DA7
0
DA6
0
DA5
0
DA4
0
DA3
0
DA2
0
DA1
0
DA0
0
Power-on
Bank 7
R8
/RESET and WDT
0
0
0
0
0
0
0
0
008 (I2CDA)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
81
EM78P507N
8-Bit Microcontroller
(Continuation)
Addr.
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DA9
0
Bit 0
DA8
0
0
0
0
IBFULL AMB
IBEN I2CSPE I2CSPF
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 7
R9
/RESET and WDT
0
0
009
(I2CA)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
Power-on
Bank 7
RA
/RESET and WDT
0
0
0
0
0
0
0
0
00A (I2CDB)
Wake-up from
Sleep & Idle mode
P
P
P
P
P
P
P
P
Bit Name
DACD7 DACD6 DACD5 DACD4 DACD3 DACD2 DACD1 DACD0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 7
RB
/RESET and WDT
00B (DACDL)
Wake-up from
Sleep & Idle mode
P
0
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DACD9 DACD8
Power-on
0
0
0
0
Bank 7
RC
/RESET and WDT
00C (DACDH)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
Bit Name
DARUN
0
0
0
0
0
0
SEMC COF[3] COF[2] COF[1] COF[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 7
RD
/RESET and WDT
00D (DACC)
Wake-up from
P
P
0
P
P
P
P
P
Sleep & Idle mode
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GCEN I2CBF
Power-on
0
0
0
0
Bank 7
RF
/RESET and WDT
00F (I2CCR3)
Wake-up from
P
P
P
P
P
P
P
P
Sleep & Idle mode
82
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.15 Oscillator
6.15.1 Oscillator Modes
The EM78P507N can be operated in five different oscillator modes, such as High
Crystal oscillator mode (HXT), Crystal oscillator mode (XT), Low Crystal oscillator
mode, External RC oscillator mode (ERC), and Internal RC oscillator mode (IRC). You
can select one of the five modes by programming the Code Option. The up-limited
operation frequency of crystal/resonator on the different VDD is listed in the following
table.
Summary of Maximum Operating Speeds
Conditions
VDD
2.2
Fxt Max. (MHz)
16
20
Two clocks
3.3
6.15.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P507N can be driven by an external clock signal through the OSCI pin as
shown in the following figure.
OSCI
Ext. Clock
OSCO
Figure 6-25a External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure below depicts such a circuit. The
same applies to the HXT1, HXT2, XT, and LXT mode.
C1
OSCI
Crystal
OSCO
C2
RS
Figure 6-25b Crystal/Resonator Circuit
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
83
EM78P507N
8-Bit Microcontroller
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, you should refer to their specifications for appropriate
values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or
low frequency mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator Type
Frequency Mode
Frequency
100kHz
200kHz
455kHz
1 MHz
C1 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
30pF
30pF
30pF
30pF
30pF
20pF
15pF
C2 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
30pF
30pF
30pF
30pF
30pF
20pF
15pF
LXT
(100K~1 MHz)
Ceramic Resonators
1.0 MHz
2.0 MHz
4.0 MHz
100kHz
200kHz
455Hz
XT
(1M~6 MHz)
LXT
(100K~1 MHz)
1 MHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
12.0 MHz
12.0 MHz
16 MHz
20 MHz
XT
(1M~6 MHz)
Crystal Oscillator
HXT1
(6M~12 MHz)
HXT2
(12M~20 MHz)
6.15.3 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
oscillator (right figure) could offer users
with an effective cost savings.
VDD
Rext
Nevertheless, it should be noted that the
frequency of the RC oscillator is
OSCI
influenced by the supply voltage, the
resistor values (Rext), the capacitor
(Cext), and even by the operation
temperature. Moreover, the frequency
also changes slightly from one chip to
another due to manufacturing process
Cext
Figure 6-26 External RC Oscillator Mode
Circuit
variations.
84
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 M. If they
cannot be kept under this range, the frequency can be affected easily by noise,
humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the way the PCB is layout, will have certain effects on the system frequency.
ERC Oscillator Frequencies
Cext
Rext
3.3k
5.1k
10k
Average Fosc 3.3V, 25C
2.9 MHz
Average Fosc 2.4V, 25C
2.855 MHz
1.92 MHz
1.1 MHz
2.1 MHz
20 pF
1.1 MHz
100k
3.3k
5.1k
10k
135kHz
140kHz
1.08 MHz
727kHz
1.05 MHz
722kHz
100 pF
300 pF
387kHz
392kHz
100k
3.3k
5.1k
10k
43kHz
45kHz
457kHz
455kHz
307kHz
307kHz
162kHz
165kHz
100k
17.7kHz
19kHz
NOTE
1. Data measured and obtained from DIP packages
2. The frequency drift is about ± 30%
3. Data is provided design reference use only
6.15.4 Internal RC Oscillator Mode
The EM78P507N offers a versatile internal RC mode with default frequency value of 4
MHz. In Internal RC oscillator mode, it has other frequencies (16 MHz, 8 MHz and
1 MHz) that can be set by Code Option (Word 1), RCM1 and RCM0, and Bank 1 RC.
The following table describes the EM78P507N internal RC drift with variation of
temperature, voltage, and process.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
85
EM78P507N
8-Bit Microcontroller
Internal RC Drift Rate (Ta=25C, VDD=3.3V±5%, VSS=0V)
Drift Rate
Internal RC
Frequency
Temperature
(-40C~+85C)
Voltage
(2.0V~3.6V)
Process
Total
4 MHz
1 MHz
16 MHz
8 MHz
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±2.5%
±2.5%
±2.5%
±2.5%
±12.35%
±12.35%
±12.35%
±12.35%
NOTE
These are theoretical values and are provided for reference only. Actual values may
vary according to the actual process involved.
All the four main frequencies can be calibrated by programming the Option bits, C4~C0.
Table below describes a typical instance of the calibration.
Calibration Selection for Internal RC Mode
C4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
Frequency (MHz)
(1-28.6%) x F
(1-27.3%) x F
(1-25.9%) x F
(1-24.5%) x F
(1-23.1%) x F
(1-21.6%) x F
(1-20.0%) x F
(1-18.4%) x F
(1-16.7%) x F
(1-14.9%) x F
(1-13.0%) x F
(1-11.1%) x F
(1-9.09%) x F
(1-6.98%) x F
(1-4.76%) x F
(1-2.44%) x F
F (default)
(1+2.56%) x F
(1+5.26%) x F
(1+8.11%) x F
(1+11.1%) x F
(1+14.3%) x F
(1+17.6%) x F
86
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
(Continuation)
C4
1
C3
1
C2
0
C1
0
C0
0
Frequency (MHz)
(1+21.2%) x F
(1+25.0%) x F
(1+29.0%) x F
(1+33.3%) x F
(1+37.9%) x F
(1+42.9%) x F
(1+48.2%) x F
(1+53.8%) x F
(1+60.0%) x F
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
NOTE
These are theoretical values and are provided for reference only. Actual values may
vary according to the actual process involved.
6.16 Power-On Considerations
Any microcontroller is not guaranteed to start operating properly before the power
supply stabilizes in steady state. The EM78P507N is equipped with Power-on Voltage
Detector (POVD) with detection level range of 1.8V to 1.9V. The circuitry eliminates
any extra external reset circuit. It will work well if VDD rises fast enough. However,
under critical applications, extra devices are still required to assist in solving power-on
problems.
6.16.1 External Power-on Reset Circuit
The circuit shown at right figure
VDD
implements an external RC to
produce a reset pulse. The
pulse width (time constant)
should be kept long enough to
allow the VDD to achieve
/RESET
R
D
Rin
C
minimum operation voltage.
Apply this circuit when the
power supply has a slow rise
time. As the current leakage
from the /RESET pin is about
Figure 6-27a External Power on Reset Circuit
5A, it is recommended that R should not be greater than 40K in order for the /RESET
pin voltage to remain at below 0.2V. The diode (D) acts as a short circuit at
power-down. The capacitor C will discharge rapidly and fully. The current-limited
resistor Rin, prevents high current discharge or ESD (electrostatic discharge) from
flowing into /RESET pin.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
87
EM78P507N
8-Bit Microcontroller
6.16.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) takes off but residue-voltage remains.
The residue-voltage may trips below VDD minimum, but not to zero. This condition may
cause a poor power on reset. Figures 6-27b and 6-27c below illustrate how
residue-voltage protection circuit is constructed.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-27b Residue Voltage Protection Circuit 1
VDD
VDD
R1
Q1
/RESET
R2
R3
Figure 6-27c Residue Voltage Protection Circuit 2
6.17 Code Option
The EM78P507N has three Code Option words and one Customer ID word that are not
a part of the normal program memory.
Word 0
Word 1
Word 2
Bit 12~Bit 0
Bit 12~Bit 0
Bit 12~Bit 0
88
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.17.1 Code Option Register (Word 0)
Word 0
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSC2 OSC1 OSC0 PR2 PR1 PR0
COBS TYPE RESETB ENWDTB
-
-
-
Bit 12 (COBS): Code Option bit selection
0: Select internal Bank 1 RC Bit 2 as code option input. The other
code option depends on the H/W definition.
1: Select H/W code option input (default)
Not used bit, fixed to “0” all the time.
Bit 11:
Bit 10 (TYPE):
TYPE bit selection for differential package
EM78P507N TYPE:
TYPE
Type Selection
44 Pins
0
1
48 Pins
Bit 9 (RESETB): Reset Pin Enable Bit
0: Enabled, P81//RESET RESET pin.
1: Disabled, P81//RESET P81 (default)
Bit 8 (ENWDTB): Watchdog Timer Enable Bit.
0: Enabled
1: Disabled (default)
Bit 7:
Bit 6:
Not used bit, fixed to “1” all the time.
Not used bit, fixed to “0” all the time.
Bits 5~3 (OSC2~OSC0): Oscillator Modes select bits
Mode
OSC2 OSC1 OSC0
ERC (External RC oscillator mode); PC0/OSCO acts as PC0
ERC (External RC oscillator mode); PC0/OSCO acts as OSCO
IRC (Internal RC oscillator mode); PC0/OSCO acts as PC0 (default)
IRC (Internal RC oscillator mode); PC0/OSCO acts as OSCO
LXT (Low Crystal oscillator mode)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HXT2 (High Crystal 2 oscillator mode)
HXT1 (High Crystal 1 oscillator mode)
XT (Crystal oscillator mode)
NOTE
1. Frequency range of HXT2 mode is 20MHz ~ 12MHz.
2. Frequency range of HXT1 mode is 12MHz ~ 6MHz.
3. Frequency range of XT mode is 6MHz ~ 1MHz.
4. Frequency range of LXT mode is 1MHz ~ 100kHz.
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
89
EM78P507N
8-Bit Microcontroller
Bits 2~0 (PR2~PR0): Protect Bits
PR2~PR0 are protect bits, protect type are as follows:
PR2
0
PR1
0
PR0
0
Protect
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
6.17.2 Code Option Register (Word 1)
Word 1
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C4 C3 C2 C1 C0 RCM1 RCM0 HLFS
CLKOEB RCOUT EFTIM
-
-
Bit 12 (CLKOEB):P9.1 act as CLK output pin
0: P9.1 act as CLK output Pin
1: P9.1 act as General I/O Pin (default)
Bit 11 (RCOUT): System Clock Output Enable Bit in IRC or ERC mode
0: OSCO pin is open drain
1: OSCO output system clock (default)
Bit 10 (EFTIM): EFT Improvement
0: Low EFT improvement (default) (2.2V, 16 MHz)
1: High EFT improvement (1.8V, 4MHz)
Bit 9:
Not used bit, fixed to “0” all the time.
Bits 8~4 (C4~C0):Calibrator of Internal RC Mode. For IRC calibration value, refer to
table under Section 6.15.4, Internal RC Oscillator Mode.
Bits 3~2 (RCM1~RCM0): RC Mode Selection Bits
RCM 1
RCM 0
*Frequency (MHz)
0
0
1
1
0
1
0
1
1M
8M
16M
4M
Bits 1 (HLFS):
Bit 0:
Reset to Normal or Green Mode Select Bit
0: CPU is selected as Green mode when a reset occurs.
1: CPU is selected as Normal mode when a reset occurs (default).
Not used bit, fixed to “0” all the time.
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Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
6.17.3 Code Option Register (Word 2)
Word 2
Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Customer ID
6.18 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consisting of 2 oscillator periods), unless the program counter is
changed by instructions “MOV R2,A”, “ADD R2,A”, or by instructions of arithmetic or
logic operation on R2 (e.g., “SUB R2,A”, “BSI R2,6”, “CLR R2”, etc.). In this case,
execution takes one or two instruction cycles as determined by Code Option Register
CYES bit.
In addition, the instruction set has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O registers can be regarded as general registers. That is, the same instruction
can operate on I/O registers.
EM78P507N Instruction Set Table
In the following Instruction Set table, the following symbols are used:
"R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the
register "R", and affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Binary Instruction
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0011
0 0000 0000 0100
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
HEX Mnemonic
0000 NOP
0001 DAA
0003 SLEP
0004 WDTC
0010 ENI
Operation
No Operation
Status Affected
None
C
Decimal Adjust A
0 WDT, Stop oscillator
0 WDT
T, P
T, P
None
None
None
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
0011 DISI
0012 RET
[Top of Stack] PC,
Enable Interrupt
0 0000 0001 0011
0013 RETI
None
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
00rr
MOV R,A
A R
None
Z
0080 CLRA
0 A
00rr
01rr
01rr
CLR R
0 R
Z
SUB A,R
SUB R,A
R-A A
R-A R
Z, C, DC
Z, C, DC
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91
EM78P507N
8-Bit Microcontroller
(Continuation)
Binary Instruction
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
HEX Mnemonic
Operation
R-1 A
Status Affected
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
DECA R
DEC R
Z
R-1 R
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A VR A
A VR R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
R A
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
R R
Z
Z
/R A
/R R
Z
INCA R
INC R
R+1 A
Z
R+1 R
Z
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R(n) A(n-1),R(0) C,
C A(7)
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
R(n) R(n-1),R(0) C,
C R(7)
R(n) A(n+1),R(7) C,
C A(0)
RLCA R
RLC R
C
R(n) R(n+1),R(7) C,
C R(0)
C
R(0-3) A(4-7),
R(4-7) A(0-3)
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
07rr
07rr
07rr
SWAP R
JZA R
JZ R
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
None
None
0xxx BC R,b
0xxx BS R,b
0xxx JBC R,b
0xxx JBS R,b
None
1 R(b)
None <Note1>
None
if R(b)=0, skip
if R(b)=1, skip
None
PC+1 [SP],
(Page, k) PC
1 00kk kkkk kkkk
1kkk CALL k
None
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EM78P507N
8-Bit Microcontroller
(Continuation)
Binary Instruction
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1 1110 1001 kkkk
HEX Mnemonic
1kkk JMP k
Operation
(Page, k) PC
Status Affected
None
18kk MOV A,k
19kk OR A,k
1Akk AND A,k
1Bkk XOR A,k
1Ckk RETL k
1Dkk SUB A,k
1E9k BANK K
k A
None
A k A
A & k A
A k A
Z
Z
Z
k A,[Top of Stack] PC
k-A A
None
Z, C, DC
None
KR4(7:6)
Next instruction: k kkkk
kkkk kkkk;
1 1110 1010 kkkk
1EAK LCALL
None
PC+1 [SP], k->PC
Next instruction: k kkkk
kkkk kkkk;
1 1110 1011 kkkk
1 1111 kkkk kkkk
1EBK LJMP
None
kPC
1Fkk ADD A,k
k+A A
Z, C, DC
If R6, machine
code(0:7)R
1 1110 11rr rrrr
1Err TBRD R
None
else R5 machine code
(12:8)R
NOTE
These instructions cannot operate under interrupt status register.
7 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
to
to
to
to
to
to
85C
-65C
150C
Vss-0.3V
Vss-0.3V
2.2V
Vdd+0.3V
Vdd+0.3V
3.6V
Output voltage
Working Voltage
Working Frequency
DC
20 MHz
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
93
EM78P507N
8-Bit Microcontroller
8 Electrical Characteristics
8.1 DC Electrical Characteristics
Ta= 25C, VDD= 3.3V, VSS= 0V
Symbol
Parameter
Condition
Min.
0.1
Typ.
Max.
20
Unit
Two cycles with two
clocks
FXT
Crystal: VDD to 3.6V
-
MHz
ERC
IRC1
ERC: VDD to 3.3V
IRC:VDD to 3.3V
R: 5.1K, C: 100 pF
505
760
4
945
kHz
RCM0:RCM1=1:1
MHz
Internal RC oscillator error
per stage
IRCE
-
±2.5
%
IRC2
IRC3
IRC4
IRC:VDD to 3.3V
IRC:VDD to 3.3V
IRC:VDD to 3.3V
RCM0:RCM1=1:0
RCM0:RCM1=0:1
RCM0:RCM1=0:0
16
8
MHz
MHz
MHz
1
Input Leakage Current for
input pins
IIL
VIN = VDD, VSS
Ports 7, 8, 9, A, B, C
Ports 7, 8, 9, A, B, C
/RESET
-1
0
-
1
A
V
Input High Voltage
(Schmitt trigger)
VIH1
VIL1
0.7VDD
VSS
-
Input Low Voltage
(Schmitt trigger)
-
0.3VDD
-
V
Input High Threshold Voltage
(Schmitt trigger)
VIHT1
VILT1
0.7VDD
VSS
-
V
Input Low Threshold Voltage
(Schmitt trigger)
/RESET
-
0.3VDD
V
VIHX1
VILX1
Clock Input High Voltage
Clock Input Low Voltage
OSCI in crystal mode
OSCI in crystal mode
0.8VDD
-
-
-
-
V
V
0.3VDD
Output High Voltage
(Ports 5, 6, 7, 8, 9, A)
IOH
IOL
IPH
VOH = VDD-0.1VDD
VOL = GND+0.1VDD
-
-
-3.6
6
-
-
mA
mA
A
Output Low Voltage
(Ports 5, 6, 7, 8, 9, A)
Pull-high active, input pin
at VSS
Pull-high current
-20
-25
-30
All input and I/O pins at
VDD, output pin floating,
WDT disabled
ISB1
ISB2
Power down current
-
-
1
5
A
A
All input and I/O pins at
VDD, output pin floating,
WDT enabled
Power down current
/RESET= 'High',
Operating supply current
at two clocks
Fosc=4MHz (Crystal
type), output pin floating,
WDT disabled
ICC1
-
1.5
mA
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EM78P507N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
/RESET= 'High',
Operating supply current
at two clocks
Fosc=16 MHz (Crystal
type), output pin floating,
WDT enabled
ICC2
-
6
mA
/RESET= 'High', In Green
mode, output pin floating,
WDT enabled
Operating supply current
at two clocks
ICC3
ICC4
-
-
10
6
A
A
/RESET= 'High', in idle
mode, output pin floating,
WDT enabled
Operating supply current
at two clocks
8.2 AC Electrical Characteristics
Ta= -40C ~ 85C, VDD=3.3V 5%, VSS=0V
Symbol
Parameter
Conditions
Min
Typ
50
-
Max
55
DC
DC
30
-
Unit
%
Dclk
Input CLK duty cycle
-
45
Crystal type
RC type
Ta = 25C
Ta = 25C
Ta = 25C
-
125
ns
Instruction cycle time
(CLKS="0")
Tins
500
-
ns
Tdrh
Trst
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
9
18
-
ms
ns
2000
Twdt
Tset
Thold
9
-
18
0
30
-
ms
ns
-
-
20
50
-
ns
Tdelay Output pin delay time
Cload=20pF
-
-
ns
9 Timing Diagrams
AC Timing
AC Test Input/Output Waveform
VDD-0.1VDD
GND+0.1VDD
0.75VDD
0.75VDD
TEST POINTS
0.25VDD
0.25VDD
AC Testing: Input is driven at VDD-0.1VDD for logic “1”, and GND+0.1VDD for logic “0”.
Timing measurements are made at 0.75VDD for logic “1” and 0.25VDD for logic “0”.
Figure 9-1a AC Timing Diagram
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
95
EM78P507N
8-Bit Microcontroller
Reset Timing
RESET Timing (CLK="0")
Instruction 1
Executed
NOP
CLK
/RESET
Tdrh
Figure 9-1b Reset Timing Diagram
TCC Input Timing
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
Figure 9-1c TCC Input Timing Diagram
96
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
EM78P507N
8-Bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P507NL48S
Material Type
J
: RoHS complied
S
: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
L
:LQFP
Q :QFP
Check the following section for details
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P507NL48S
is EM78P507N with OTP program memory, industrial grade product,
in 48-pin LQFP 7x7mm package with SONY SS-00259 complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number
Batch Number
EM78Paaaaaa
1041c bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
c is Alphabetical suffix code for Elan use only
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
97
EM78P507N
8-Bit Microcontroller
Ordering Code
EM78P507NL48S
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
Flash MCU
Package Type
Pin Count
Package Size
10*10 mm
10*10 mm
7*7 mm
EM78P507NL44
EM78P507NQ44
EM78P507NL48
LQFP
QFP
44
44
48
LQFP
NOTE
These are Green products which do not contain hazardous substances.
These products comply with the 3rd edition of Sony SS-00259 Standard.
Pb contents of these products are less than 100ppm and comply with Sony
specifications.
98
Product Specification (V1.1) 04.08.2016
(This specification is subject to change without prior notice)
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