EM78P528NL44 [ELAN]
8-Bit Microprocessor with OTP ROM;
| 型号： | EM78P528NL44 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microprocessor with OTP ROM OTP只读存储器 外围集成电路 |
| 文件： | 总164页 (文件大小：4428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P528N
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
March 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Pin Configuration (Package)................................................................................... 2
Pin Description........................................................................................................ 4
Functional Block Diagram .................................................................................... 10
Functional Description.......................................................................................... 11
6.1 Operational Registers ..................................................................................... 11
6.1.1 R0 IAR (Indirect Addressing Register).............................................................. 11
6.1.2 R1 BSR (Bank Selection Control Register) ...................................................... 11
6.1.3 R2 PCL (Program Counter Low)....................................................................... 11
6.1.4 R3 SR (Status Register) ...................................................................................17
6.1.5 R4 RSR (RAM Select Register)........................................................................17
6.1.6 Bank 0 R5 ~ RA Port 5 ~ Port A........................................................................17
6.1.7 Bank 0 RB~RD IOCR5 ~ IOCR7 ......................................................................18
6.1.8 Bank 0 RE OMCR (Operating Mode Control Register) ....................................18
6.1.9 Bank 0 RF EIESCR (External Interrupt Edge Select Control Register)............20
6.1.10 Bank 0 R10 WUCR1 (Wake-up Control Register 1) .........................................21
6.1.11 Bank 0 R11 WUCR2 (Wake-up Control Register 2) .........................................21
6.1.12 Bank 0 R12 WUCR3 (Wake-up Control Register 3) .........................................22
6.1.13 Bank 0 R14 SFR1 (Status Flag Register 1)......................................................22
6.1.14 Bank 0 R15 SFR2 (Status Flag Register 2)......................................................23
6.1.15 Bank 0 R17 SFR4 (Status Flag Register 4)......................................................23
6.1.16 Bank 0 R18 SFR5 (Status Flag Register 5)......................................................24
6.1.17 Bank 0 R1B IMR1 (Interrupt Mask Register 1) .................................................24
6.1.18 Bank 0 R1C IMR2 (Interrupt Mask Register 2).................................................25
6.1.19 Bank 0 R1E IMR4 (Interrupt Mask Register 4) .................................................26
6.1.20 Bank 0 R1F IMR5 (Interrupt Mask Register 5) .................................................27
6.1.21 Bank 0 R21 WDTCR (Watchdog Timer Control Register) ................................27
6.1.22 Bank 0 R22 TCCCR (TCC Control Register)....................................................28
6.1.23 Bank 0 R23 TCCD (TCC Data Register) ..........................................................29
6.1.24 Bank 0 R24 TC1CR1 (Timer/Counter 1 Control Register 1).............................29
6.1.25 Bank 0 R25 TC1CR2 (Timer/Counter 1 Control Register 2).............................30
6.1.26 Bank 0 R26 TC1DA (Timer/Counter 1 Data Buffer A).......................................31
6.1.27 Bank 0 R27 TC1DB (Timer/Counter 1 Data Buffer B) ......................................32
6.1.28 Bank 0 R28 TC2CR1 (Timer/Counter 2 Control Register 1).............................32
6.1.29 Bank 0 R29 TC2CR2 (Timer/Counter 2 Control Register 2).............................33
6.1.30 Bank 0 R2A TC2DA (Timer/Counter 2 Data Buffer A).......................................34
6.1.31 Bank 0 R2B TC2DB (Timer/Counter 2 Data Buffer B)......................................34
Product Specification (V1.4) 03.31.2016
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Contents
6.1.32 Bank 0 R2C TC3CR1 (Timer/Counter 3 Control Register 1) ............................35
6.1.33 Bank 0 R2D TC3CR2 (Timer/Counter 3 Control Register 2) ............................36
6.1.34 Bank 0 R2E TC3DA (Timer/Counter 3 Data Buffer A) ......................................37
6.1.35 Bank 0 R2F TC3DB (Timer/Counter 3 Data Buffer B) ......................................37
6.1.36 Bank 0 R30 I2CCR1 (I2C Status and Control Register 1)................................37
6.1.37 Bank 0 R31 I2CCR2 (I2C Status and Control Register 2)................................38
6.1.38 Bank 0 R32 I2CSA (I2C Slave Address Register) ............................................39
6.1.39 Bank 0 R33 I2CDB (I2C Data Buffer Register).................................................39
6.1.40 Bank 0 R34 I2CDAL (I2C Device Address Register) ........................................39
6.1.41 Bank 0 R35 I2CDAH (I2C Device Address Register) .......................................40
6.1.42 Bank 0 R36 SPICR (SPI Control Register).......................................................40
6.1.43 Bank 0 R37 SPIS (SPI Status Register) ...........................................................41
6.1.44 Bank 0 R38 SPIR (SPI Read Buffer Register)..................................................42
6.1.45 Bank 0 R39 SPIW (SPI Write Buffer Register) .................................................42
6.1.46 Bank 0 R3E ADCR1 (Analog-to-Digital Converter Control Register 1).............42
6.1.47 Bank 0 R3F ADCR2 (Analog-to-Digital Converter Control Register 2).............43
6.1.48 Bank 0 R40 ADISR (Analog-to-Digital Converter Input
Channel Select Register) ..................................................................................44
6.1.49 Bank 0 R41 ADER1 (Analog-to-Digital Converter Input Control Register 1) ....45
6.1.50 Bank 0 R42 ADER2 (Analog-to-Digital Converter Input Control Register 2) ....46
6.1.51 Bank 0 R43 ADDL (Low Byte of Analog-to-Digital Converter Data)..................47
6.1.52 Bank 0 R44 ADDH (High Byte of Analog-to-Digital Converter Data)................47
6.1.53 Bank 0 R45 ADCVL (Low Byte of Analog-to-Digital Converter
Compare Value) ................................................................................................47
6.1.54 Bank 0 R46 ADCVH (High Byte of Analog-to-Digital Converter
Compare Value) ................................................................................................48
6.1.55 Bank 0 R48 LCDCR1 (LCD Driver Control Register 1) ....................................48
6.1.56 Bank 0 R49 LCDCR2 (LCD Driver Control Register 2) ....................................49
6.1.57 Bank 0 R4A LCDCR3 (LCD Driver Control Register 3) ....................................50
6.1.58 Bank 0 R4B LCDADDR (Address of LCD RAM) ..............................................50
6.1.59 Bank 0 R4C LCDDB (Data of LCD RAM) .........................................................50
6.1.60 Bank 0 R4D LCDSCR0 (LCD COM/SEG Pin Control Register 0)....................51
6.1.61 Bank 0 R4E LCDSCR1 (LCD SEG Pin Control Register 1) .............................52
6.1.62 Bank 0 R4F LCDSCR2 (LCD Segment Control Register 2).............................52
6.1.63 Bank 1 R5~R7 IOCR8~IOCA............................................................................52
6.1.64 Bank 1 R8 P5PHCR (Port 5 Pull-high Control Register) ..................................53
6.1.65 Bank 1 R9 P6PHCR (Port 6 Pull-high Control Register) ..................................53
6.1.66 Bank 1 RA P789APHCR (Port 7~A Pull-high Control Register) .......................53
6.1.67 Bank 1 RB P5PLCR (Port 5 Pull-low Control Register)....................................54
6.1.68 Bank 1 RC P6PLCR (Port 6 Pull-low Control Register)....................................54
6.1.69 Bank 1 RD P789APLCR (Port 7~A Pull-low Control Register).........................54
6.1.70 Bank 1 RE P5HDSCR (Port 5 High Drive/Sink Control Register) ....................55
6.1.71 Bank 1 RF P6HDSCR (Port 6 High Drive/Sink Control Register).....................55
6.1.72 Bank 1 R10 P789AHDSCR (Port 7~A High Drive/Sink Control Register) ........55
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Product Specification (V1.4) 03.31.2016
Contents
6.1.73 Bank 1 R11 P5ODCR (Port 5 Open-drain Control Register) ............................55
6.1.74 Bank 1 R12 P6ODCR (Port 6 Open-drain Control Register)............................56
6.1.75 Bank 1 R13 P789AODCR (Port 7~A Open-drain Control Register) .................56
6.1.76 Bank 1 R33 URCR (UART Control Register)....................................................57
6.1.77 Bank 1 R34 URS (UART Status Register)........................................................58
6.1.78 Bank 1 R35 URTD (UART Transmit Data Buffer Register)...............................58
6.1.79 Bank 1 R36 URRDL (UART Receive Data Low Buffer Register) .....................59
6.1.80 Bank 1 R37 URRDH (UART Receive Data High Buffer Register)....................59
6.1.81 Bank 1 R40 WCR (Watch Timer Control Register)...........................................59
6.1.82 Bank 1 R45 TBPTL (Table Pointer Low Register).............................................59
6.1.83 Bank 1 R46 TBPTH (Table Pointer High Register) ...........................................60
6.1.84 Bank 1 R47 STKMON (Stack Monitor) .............................................................60
6.1.85 Bank 1 R48 PCH (Program Counter High) .......................................................60
6.1.86 Bank 1 R49 LVDCR (Low Voltage Detector Control Register) .........................60
6.1.87 Bank 1 R4A~R4C: (Reserve)............................................................................61
6.1.88 Bank 0 R50~R7F, Bank 0~3 R80~RFF.............................................................61
6.2 TCC/WDT and Prescaler ................................................................................61
6.3 I/O Ports .........................................................................................................62
6.4 Reset and Wake-up ........................................................................................65
6.4.1 Reset.................................................................................................................65
6.4.2 Status of RST, T, and P of the Status Register .................................................70
6.5 Interrupt ..........................................................................................................85
6.6 A/D Converter.................................................................................................87
6.6.1 ADC Data Register ...........................................................................................88
6.6.2 A/D Sampling Time ...........................................................................................88
6.6.3 A/D Conversion Time........................................................................................89
6.6.4 ADC Operation during Sleep Mode ..................................................................90
6.6.5 Programming Process/Considerations .............................................................90
6.6.6 Programming Process for Detecting Internal VDD ...........................................91
6.6.7 Sample Demo Programs...................................................................................93
6.7 Timer ..............................................................................................................95
6.7.1 Timer/Counter Mode .........................................................................................96
6.7.2 Window Mode ...................................................................................................97
6.7.3 Capture Mode ...................................................................................................98
6.7.4 Programmable Divider Output Mode and Pulse Width Modulation Mode ........99
6.7.5 Buzzer Mode...................................................................................................100
6.8 UART (Universal Asynchronous Receiver/Transmitter).................................101
6.8.1 UART Mode.....................................................................................................102
6.8.2 Transmitting.....................................................................................................103
6.8.3 Receiving ........................................................................................................103
6.8.4 Baud Rate Generator......................................................................................104
6.8.5 UART Timing...................................................................................................104
Product Specification (V1.4) 03.31.2016
v
Contents
6.9 SPI (Serial Peripheral Interface) ...................................................................104
6.9.1 Overview and Feature.....................................................................................105
6.9.2 SPI Functional Description..............................................................................106
6.9.3 SPI Signal and Pin Description.......................................................................108
6.9.4 SPI Mode Timing.............................................................................................109
6.10 I2C Function.................................................................................................. 110
6.10.1 Master Mode ................................................................................................... 117
6.10.2 Slave Mode ..................................................................................................... 117
6.11 Liquid Crystal Display Driver (LCD Driver) .................................................... 117
6.12 LVD (Low Voltage Detector)..........................................................................126
6.13 Oscillator.......................................................................................................128
6.13.1 Oscillator Modes .............................................................................................128
6.13.2 Crystal Oscillator/Ceramic Resonators (XTAL)...............................................129
6.13.3 Internal RC Oscillator Mode............................................................................131
6.14 Power-on Considerations..............................................................................131
6.15 External Power-on Reset Circuit...................................................................131
6.16 Residue-Voltage Protection...........................................................................132
6.17 Code Option .................................................................................................133
6.17.1 Code Option Register (Word 0) ......................................................................133
6.17.2 Code Option Register (Word 1) ......................................................................134
6.17.3 Code Option Register (Word 2) ......................................................................136
6.17.4 Code Option Register (Word 3) ......................................................................137
6.18 Instruction Set...............................................................................................138
Absolute Maximum Ratings................................................................................ 140
DC Electrical Characteristics.............................................................................. 140
7
8
8.1 AD Converter Characteristics........................................................................142
8.2 VREF 2V/3V/4V Characteristics....................................................................143
9
AC Electrical Characteristics.............................................................................. 144
10 Timing Diagrams ................................................................................................. 145
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Product Specification (V1.4) 03.31.2016
Contents
APPENDIX
A
B
C
Ordering and Manufacturing Information .......................................................... 146
Package Type....................................................................................................... 147
Package Information ........................................................................................... 148
C.1 EM78P528NQ44...........................................................................................148
C.2 EM78P528NL44 ...........................................................................................149
C.3 EM78P528NL48 ...........................................................................................150
D
Quality Assurance and Reliability ...................................................................... 151
D.1 Address Trap Detect.....................................................................................151
EM78P528N Program Pin List............................................................................. 152
ICE 400 Oscillator Circuit (JP3) .......................................................................... 152
E
F
F.1 Mode 1 .........................................................................................................152
F.2 Mode 2 .........................................................................................................153
F.3 Mode 3 .........................................................................................................153
F.4 Mode 4 .........................................................................................................153
Product Specification (V1.4) 03.31.2016
vii
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial released version
2011/03/18
1. Modified the CPU change operating mode description.
2. Modified the ADC description.
1.1
2012/02/08
3. Modified Figure 6-3. CPU Operation Mode.
4. Modified the LVD power consumption.
1.2
1.3
Added LVR specifications
2013/03/29
2016/01/15
1. Modified the Code Option default for Word 1_Bit 4 and
Word 2_Bit 3
2. Added the remarks on P50
1. Added User Application Note
2. Modified the package type in the Features section
1.4
2016/03/31
3. Modified Appendix A “Ordering and Manufacturing
Information”
viii
Product Specification (V1.4) 03.31.2016
Contents
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.)
1.
2.
We strongly recommend that you have to place an external pull-down or pull-high resistor on P50
no matter what the pin function is. The purpose of this is to prevent P50 from floating.
The value in the dead-time register must be less than the value in the duty cycle register in order
to prevent unexpected behavior on both of the PWM outputs.
3.
4.
The PWM output will not be set, if the duty cycle is “0”.
The internal TCC will stop running when in sleep mode. However, during AD conversion, when
TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, TCC will keep on
running.
5.
6.
During ADC conversion, do not perform output instruction to maintain precision for all of the pins.
In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during
AD conversion
The noise rejection function is turned off in the LXT2 and sleep mode
Product Specification (V1.4) 03.31.2016
ix
Contents
x
Product Specification (V1.4) 03.31.2016
EM78P528N
8-Bit Microprocessor with OTP ROM
1 General Description
The EM78P528N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS
technology. It is used for 15 bits kernel simulation and it simulates the 8K15-bit programmable ROM.
Using the UIT400N, user can develop their program for ELAN’s several OTP types of IC.
2 Features
Peripheral configuration
CPU configuration
8-bit Real Time Clock/Counter (TCC) with
selective signal sources and trigger edges
Supports 8K15 bits program ROM
(48+512) bytes general purpose register
32 bytes LCD RAM
15+1 channels Analog-to-Digital Converter with
12-bit resolution + 1 internal reference for Vref
8-level stacks for subroutine nesting
Less than 1mA at 5V/4MHz
LCD: 823 dots, bias (1/2, 1/3), duty (static, 1/3,
1/4, 1/8)
Three 8-bit timers (TC1/TC2/TC3) with six modes:
Timer/Counter/Capture/Window/Buzzer/PWM/
PDO (Programmable Divider Output) modes.
Timers 1 and 2 can be cascaded to one 16-bit
counter/timer
Typically 15 A at 3V/16kHz
Typically 22 A, at 3V/32kHz
Typically 2 A during sleep mode
Four CPU operation modes: Normal, Sleep, Green,
Idle
Universal Asynchronous Receiver/Transmitter
(UART)
I/O port configuration
Six bidirectional I/O ports: P5~P9, PA
Serial transmitter/receiver interface (SPI): 3-wire
synchronous communication
I2C function with 7/10-bit address and 8-bit data
Four programmable pin change wake-up ports :
P5~P8
transmit/receive mode
Six programmable pull-down I/O ports: P5~P9, PA
Six programmable pull-high I/O ports: P5~P9, PA
Six programmable open-drain I/O ports: P5~P9, PA
Four programmable watch timer: 1.0 sec, 0.5 sec,
0.25 sec, 3.91 ms
Four programmable Level Voltage Detector
LVD: 4.5V, 4.0V, 3.3V, 2.2V
Six programmable high-sink/drive I/O ports: P5~P9,
PA
Power-on reset and three programmable level
voltage reset POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
High EFT immunity
10 external interrupt pins
Operating voltage range:
2.1V~5.5V at 0C~70C (commercial)
2.3V~5.5V at -40C~85C (industrial)
25 available interrupts (12 external, 13 internal)
10 external interrupts
Operating frequency range (base on 2 clocks):
Input-port status changed interrupt (wake up from
sleep mode)
Main oscillator:
LVD interrupt
Crystal mode:
DC~16 MHz at 5V; DC~8 MHz at 3V; DC~4 MHz at 2.1V
TCC overflow interrupt
Three timer interrupt
ADC completion interrupt
I2C transfer/receive interrupt
UART TX, RX , RX error interrupt
SPI interrupt
IRC mode:
DC~16 MHz at 5V; DC~8 MHz at 3V; DC~4 MHz at 2.1V
Drift Rate
Internal RC
Frequency
Temperature
Voltage
Process Total
(-40C ~+85C) (2.5V~5.5V)
Watch timer interrupt
1 MHz
4 MHz
8 MHz
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
Single instruction cycle commands
Package Type:
44-pin QFP 10x10mm
44-pin LQFP 10x10mm : EM78P528NL44
48-pin LQFP 7x7mm EM78P528NL48
:
EM78P528NQ44
16 MHz
±2%
±1%
±1%
±4%
Sub oscillator:
:
Crystal mode: 32.768kHz
IRC mode: 16k/32kHz
Note: These are Green Products which do not contain
hazardous substances.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
1
EM78P528N
8-Bit Microprocessor with OTP ROM
3 Pin Configuration (Package)
*: Optional selection
44 43 42 41 40 39 38 37 36 35 34
33
PA2/SEG18/INT0
CLK/P50/INT1/TC1OUT
DATA/P51/INT2/TC1IN
P52/INT3/TCC
VDD/VDD
1
2
P86/SEG6/SCK/SCL
P85/SEG5/SO
P84/SEG4/SI/SDA
P83/SEG3
32
31
30
29
28
27
26
25
24
23
3
4
5
P82/SEG2
EM78P528N
44-PIN
VSS/VSS
6
P81/SEG1
P53/OSCO
7
P80/SEG0
P54/OSCI/RCOUT
VPP//RESET2
P55/Xin
8
P77/COM0
9
P76/COM1
10
P75/COM2
P56/Xout
11
P74/COM3
12 13 14 15 16 17 18 19 20 21 22
Figure 3-1 44-pin QFP 10x10mm EM78P528NQ44/L44
2
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
*: Optional selection
48 47 46 45 44 43 42 41 40 39 38 37
PA2/SEG18/INT0
CLK/P50/INT1/TC1OUT
DATA/P51/INT2/TC1IN
P52/INT3/TCC
VDD/VDD
1
36
35
34
33
32
31
30
29
28
27
26
25
P91/SEG9/INT5/AD10
P90/SEG8/INT4/AD9
P87/SEG7//SS
P86/SEG6/SCK/SCL
P85/SEG5/SO
P84/SEG4/SI/SDA
P83/SEG3
2
3
4
5
VSS/VSS
6
EM78P528N
48-PIN
P53/OSCO
7
P54/OSCI/RCOUT
VPP//RESET2
P55/Xin
8
P82/SEG2
9
P81/SEG1
10
11
12
P80/SEG0
P56/Xout
P77/COM0
P57//RESET
P76/COM1
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3-2 48-pin LQFP 7x7mm EM78P528NL48
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
3
EM78P528N
8-Bit Microprocessor with OTP ROM
4 Pin Description
Input
Type
Output
Type
Name
Function
Description
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P50
ST
CMOS
-
Remark: Off-chip pull-down or pull-high
P50/INT1/
TC1OUT/
(CLK)
External interrupt pin
INT1
ST
Remark: Off-chip pull-down or pull-high
Timer 1 output (PDO/PWM/Buzzer)
T1OUT
(CLK)
P51
-
CMOS
-
Remark: Off-chip pull-down or pull-high
ST
ST
Clock pin for Writer programming
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
CMOS
P51/INT2/
TC1IN/
(DATA)
INT2
T1IN
ST
ST
ST
-
-
External interrupt pin
Timer 1 input (Counter/Capture/Window)
(DATA)
CMOS DATA pin for Writer programming
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P52
ST
open-drain, high-sink/drive and pin change wake-up.
P52/INT3/
TCC
INT3
TCC
ST
ST
-
-
External Interrupt pin
Real Time Clock/Counter clock input
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P53
OSCO
P54
ST
-
CMOS
XTAL
CMOS
-
P53/OSCO
Clock output of crystal/resonator oscillator
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
P54/OSCI/
RCOUT
OSCI
XTAL
-
Clock input of crystal/resonator oscillator
RCOUT
CMOS Clock output of internal RC oscillator
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P55
Xin
ST
XTAL
ST
open-drain, high-sink/drive and pin change wake-up.
P55/Xin
Clock input of crystal/resonator oscillator only for
32.768kHz
-
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P56
Xout
open-drain, high-sink/drive and pin change wake-up.
P56/Xout
Clock output of crystal/resonator oscillator only for
32.768kHz
-
XTAL
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P57
ST
ST
P57/
/RESET1
open-drain, high-sink/drive and pin change wake-up.
/RESET1
-
Internal pull-high (set P57 pull-high) reset pin
4
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P60
ST
CMOS
P60/INT8/AD8
INT8
AD8
ST
AN
-
-
External interrupt pin
ADC Input 8
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P61
ST
CMOS
P61/COM7/INT9/
AD7
-
COM7
INT9
AD7
AN
LCD Common 7 output
External interrupt pin
ADC Input 7
-
-
ST
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P62
VREF
P63
ST
AN
ST
CMOS
-
P62/VREF
Voltage reference for ADC
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
CMOS
P63/COM6/AD6
-
COM6
AD6
AN
-
LCD Common 6 output
ADC Input 6
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P64
ST
CMOS
P64/COM5/AD5
P65/COM4/AD4
-
COM5
AD5
AN
-
LCD Common 5 output
ADC Input 5
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P65
ST
CMOS
-
COM4
AD4
AN
-
LCD Common 4 output
ADC Input 4
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P66
AD3
TC2
ST
AN
ST
CMOS
-
ADC Input 3
P66/AD3/TC2
P67/AD2/TC3
Timer 2 input (Counter/Capture/Window)
Timer 2 output (PDO/PWM/Buzzer)
CMOS
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P67
AD2
TC3
ST
AN
ST
CMOS
-
ADC Input 2
Timer 3 input (Counter/Capture/Window)
Timer 3 output (PDO/PWM/Buzzer)
CMOS
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P72
AD1
P73
AD0
ST
AN
ST
AN
CMOS
-
P72/AD1
P73/AD0
ADC Input 1
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
CMOS
-
ADC Input 0
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
5
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
ST
-
Type
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P74
COM3
P75
CMOS
P74/COM3
AN
CMOS
AN
LCD Common 3 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
P75/COM2
P76/COM1
P77/COM0
P80/SEG0
P81/SEG1
P82/SEG2
P83/SEG3
COM2
P76
LCD Common 2 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
COM1
P77
LCD Common 1 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
COM0
P80
LCD Common 0 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
SEG0
P81
LCD Segment 0 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
SEG1
P82
LCD Segment 1 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
SEG2
P83
LCD Segment 2 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
-
CMOS
AN
SEG3
P84
LCD Segment 3 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
ST
CMOS
P84/SEG4/SI/
SDA
-
SEG4
SI
AN
-
LCD Segment 4 output
SPI serial data input
ST
ST
SDA
CMOS I2C serial data line. It is open-drain
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P85
ST
open-drain, high-sink/drive and pin change wake-up.
P85/SEG5/SO
-
-
SEG5
SO
AN
LCD Segment 5 output
CMOS SPI serial data output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain, high-sink/drive and pin change wake-up.
P86
ST
CMOS
AN
P86/SEG6/SCK/
SCL
-
SEG6
SCK
SCL
LCD Segment 6 output
ST
ST
CMOS SPI serial clock input/output
CMOS I2C serial clock line. It is open-drain.
Bidirectional I/O pin with programmable pull-low, pull-high,
CMOS
P87
ST
open-drain, high-sink/drive and pin change wake-up.
P87/SEG7//SS
-
SEG7
/SS
AN
-
LCD Segment 7 output
SPI Slave select pin
ST
6
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P90
ST
CMOS
P90/SEG8/INT4/
AD9
-
SEG8
INT4
AD9
AN
LCD Segment 8 output
External interrupt pin
ADC Input 9
-
-
ST
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P91
ST
CMOS
P91/SEG9/INT5/
AD10
-
SEG9
INT5
AN
LCD Segment 9 output
External interrupt pin
ADC Input 10
-
-
ST
AN
AD10
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P92
ST
CMOS
P92/SEG10/INT6/
AD11
-
SEG10
INT6
AN
LCD Segment 10 output
External interrupt pin
ADC Input 11
-
-
ST
AN
AD11
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P93
ST
CMOS
P93/SEG11/INT7/
AD12
-
SEG11
INT7
AN
LCD Segment 11 output
External interrupt pin
ADC Input 12
-
-
ST
AN
AD12
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P94
ST
CMOS
P94/SEG12/AD13
P95/SEG13/AD14
-
SEG12
AD13
AN
-
LCD Segment 12 output
ADC Input 13
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P95
ST
CMOS
-
SEG13
AD14
AN
-
LCD Segment 13 output
ADC Input 14
AN
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
P96
SEG14
P97
ST
-
CMOS
AN
P96/SEG14
P97/SEG15
LCD Segment 14 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
ST
-
CMOS
AN
SEG15
PA0
LCD Segment 15 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
ST
CMOS
PA0/SEG16/RX/
SDA
-
SEG16
RX
AN
-
LCD Segment 16 output
UART RX input
ST
ST
SDA
CMOS I2C serial data line. It is open-drain.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
7
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
PA1
ST
CMOS
-
-
SEG17
TX
AN
LCD Segment 17 output
PA1/SEG17/TX/
SCL
CMOS UART TX output
SCL
ST
CMOS I2C serial clock line. It is open-drain.
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
PA2
ST
CMOS
PA2/SEG18/INT0
-
SEG18
INT0
AN
-
LCD Segment 18 output
External interrupt pin
ST
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
PA3
SEG19
PA4
ST
-
CMOS
AN
PA3/SEG19
PA4/SEG20
PA5/SEG21
PA6/SEG22
LCD Segment 19 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
ST
-
CMOS
AN
SEG20
PA5
LCD Segment 20 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
ST
-
CMOS
AN
SEG21
PA6
LCD Segment 21 output
Bidirectional I/O pin with programmable pull-low, pull-high,
open-drain and high-sink/drive.
ST
CMOS
-
SEG22
VDD
AN
LCD Segment 22 output
Power
-
-
-
-
-
-
Power
Power
Power
Power
ST
VDD/(VDD)
(VDD)
VSS
VDD pin for Writer programming
Ground
VSS/(VSS)
(VSS)
/RESET2
(VPP)
Ground pin for Writer programming
Reset pin. It is open-drain
VPP pin for Writer programming
/RESET2/(VPP)
Power
Legend: ST : Schmitt Trigger input
AN : Analog pin
XTAL : Oscillation pin for crystal/resonator
CMOS : CMOS output
NOTE
It is strongly recommended that user must place an external pull-down or pull-high
resistor on P50 no matter what the pin function is.
The purpose of this is to prevent P50 from floating.
8
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Pin control condition repeat function starting capability
I/O Status
Pin Control
Pull Low
Pin Function
I/O Direction Pin Change WK/Int. Pull High
O.D.
General Input
General Output
PWM
Input
Output
Output
Input
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Enable
Enable
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
S/W
TCC
S/W
TC-IN
Input
S/W
TC-OUT
RSTB (VPP pin)
RSTB
Output
Input
S/W
S/W
Input
Init: Enable
S/W
S/W
EX_INT
Input
S/W
I2C-SDA
I2C-SCL
Input/Output
Input/Output
Input
S/W
S/W
S/W
S/W
SPI-SDI
S/W
S/W
SPI-SDO
SPI-SCK-IN
SPI-SCK-OUT
UART-TX
UART-RX
LCD Driver
AD
Output
Input
S/W
S/W
S/W
S/W
Output
Output
Input
S/W
S/W
S/W
S/W
S/W
S/W
Input
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Input
OP/VO
Input
CMP/IN
Input
CMP/CO
OSCI
Output
Input
OSCO
Input
INMODE
WRITER PIN
Input
Output: *
Enable High
drive/sink
DUMPROM
Disable forced to shutoff
Enable forced to open
S/W The initial value in the control register is set as “Disable”.
1. For non-I/O function, the Pin Change Wake-up/Interrupt function should be disabled
2. Priority: INMODE PIN > Analog function > I2C, SPI, UART > Output Digital Function > Input
Digital Function > General I/O Function
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
9
EM78P528N
8-Bit Microprocessor with OTP ROM
5 Functional Block Diagram
PA
PA6
PA5
PA4
PA3
PA2
PA1
PA0
WDT
ROM
PC
XTAL
IRC
Reset
Watch
Timer
TCC
TC1
TC2
TC3
TCC
Oscillator generator
8 level
stack
Instruction
register
P9
TC1IN
TC1OUT
P97
P96
P95
P94
P93
P92
P91
P90
Sub
IRC
Sub
XTAL
TC2
TC3
Instruction
decoder
LVD
MUX
P8
LVR
ADC
UART
SPI
P87
P86
P85
P84
P83
P82
P81
P80
ALU
ADC
0~15
R4
TX, RX
RAM
SO, SI,
SCK, /SS
P7
SCL,
SDA
I2C
P77
P76
P75
P74
P73
P72
Interrupt
control reg.
ACC
Status reg.
P6
Interrupt
circuit
P67
P66
P65
P64
P63
P62
P61
P60
Ext INT
P5
Figure 5-1 EM78P528N Functional Block Diagram
10
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6 Functional Description
6.1 Operational Registers
6.1.1 R0 IAR (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
6.1.2 R1 BSR (Bank Selection Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SBS0
R/W
GBS1
R/W
GBS0
R/W
Bits 7~5: Not used, set to “0” all the time.
Bit 4 (SBS0): Special register bank select bit. It is used to select Bank 0/1 of Special
Registers R5~R4F.
0: Bank 0
1: Bank 1
Bits 3~2: Not used, fixed to 0 all the time.
Bits 1~0 (GBS1~GBS0): General register bank select bit. It is used to select
Banks 0~3 of General Registers R80~RFF.
GBS1 GBS0
RAM Bank
0
0
1
1
0
1
0
1
0
1
2
3
6.1.3 R2 PCL (Program Counter Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC7
R/W
PC6
R/W
PC5
R/W
PC4
R/W
PC3
R/W
PC2
R/W
PC1
R/W
PC0
R/W
Bits 7~0 (PC7~PC0): Low byte of program counter.
Depending on the device type, R2 and hardware stack are 13-bit wide. The
structure is depicted in Figure 6-1.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
11
EM78P528N
8-Bit Microprocessor with OTP ROM
Generates 8K15 bits on-chip OTP ROM addresses to the relative programming
instruction codes. One program page is 4096 words long.
R2 is set as all "0"s when under reset condition.
"JMP" instruction allows direct loading of the lower 12-bit program counter. Thus,
"JMP" allows the PC to go to any location within a page.
"CALL" instruction loads the lower 12 bits of the PC, and the present PC value will
be incremented by 1 and is pushed onto the stack. Thus, the subroutine entry
address can be located anywhere within a page.
"LJMP" instruction allows direct loading of the lower 13-bit program counter.
Therefore, "LJMP" allows the PC to jump to any location within 8K (213).
"LCALL" instruction loads the lower 13 bits of the PC and PC+1 are pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within 8K
(213).
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and above bits of the PC will remain unchanged.
Any instruction except “ADD R2,A” that is written to R2 (e.g. "MOV R2, A", "BC
R2, 6",etc.) will cause the ninth bit and the above bits (A8~A12) of the PC to
remain unchanged.
All instructions are single instruction cycle (Fsys/2) except “LCALL” and “LJMP”
instructions. The “LCALL” and “LJMP” instructions need two instruction cycles
12
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
A12
A11
~
A0
PC
0000h
0002h
0004h
0006h
0008h
000Ch
0010h
0012h
001Ah
001Ch
001Eh
0022h
0028h
002Eh
0030h
0032h
0038h
Reset vector
INT interrupt vector
Pin change interrupt vector
TCC interrupt vector
LVD interrupt vector
SPI interrupt vector
AD interrupt vector
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
TC1 interrupt vector
I2C Tx overfolw
I2C Rx interrupt vector
I2C stop interrupt vector
TC2 interrupt vector
TC3 interrupt vector
UART Rx error interrupt vector
UART Rx interrupt vector
UART Tx interrupt vector
WT interrupt vector
On-chip Program Memory
1FFFh
Figure 6-1 EM78P528N Program Counter Organization
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
13
EM78P528N
8-Bit Microprocessor with OTP ROM
Data Memory Configuration
Address
0X00
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X08
0X09
0X0A
0x0B
0X0C
0X0D
0X0E
Bank 0
Bank 1
IAR (Indirect Addressing Register)
BSR (Bank Select Control Register)
PC (Program Counter)
SR (Status Register)
RSR (RAM Select Register)
Port 5
IOCR8
Port 6
IOCR9
Port 7
IOCRA
Port 8
P5PHCR
P6PHCR
P789APHCR
P5PLCR
P6PLCR
P789APLCR
P5HDSCR
Port 9
Port A
IOC5
IOC6
IOC7
OMCR (Operating Mode Control Register)
EIESCR1 (External Interrupt Edge Select
Control Register)
0X0F
P6HDSCR
0X10
0X11
0X12
0X13
0X14
0X15
0X16
0X17
0X18
0X19
0X1A
0X1B
0X1C
0X1D
0X1E
0X1F
0X20
0X21
WUCR1
WUCR2
WUCR3
P789AHDSCR
P5ODCR
P6ODCR
P789AODCR
SFR1 (Status Flag Register 1)
SFR2 (Status Flag Register 2)
SFR3 (Status Flag Register 3)
SFR4 (Status Flag Register 4)
SFR5 (Status Flag Register 5)
IMR1 (Interrupt Mask Register 1)
IMR2 (Interrupt Mask Register 2)
IMR3 (Interrupt Mask Register 3)
IMR4 (Interrupt Mask Register 4)
IMR5 (Interrupt Mask Register 5)
WDTCR
14
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Address
0X22
0X23
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0x2B
0X2C
0X2D
0X2E
0X2F
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3A
0x3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0X42
0X43
Bank 0
TCCCR
TCCD
TC1CR1
TC1CR2
TC1DA
TC1DB
TC2CR1
TC2CR2
TC2DA
TC2DB
TC3CR1
TC3CR2
TC3DA
TC3DB
I2CCR1
I2CCR2
I2CSA
I2CDB
I2CDAL
I2CDAH
SPICR
SPIS
Bank 1
URCR
URS
URTD
URRDL
URRDH
SPIR
SPIW
ADCR1
ADCR2
ADISR
ADER1
ADER2
ADDL
WCR
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
15
EM78P528N
8-Bit Microprocessor with OTP ROM
Address
0X44
0X45
0X46
0X47
0X48
0X49
0X4A
0x4B
0X4C
0X4D
0X4E
0X4F
0X50
0X51
:
Bank 0
ADDH
Bank 1
ADCVL
TBPTL
TBPTH
STKMON
PCH
ADCVH
LCDCR1
LCDCR2
LCDCR3
LCDADDR
LCDCCR
LCDSCR0
LCDSCR1
LCDSCR2
LVDCR
COBS1
COBS2
COBS3
General Purpose Register
:
0X7F
0X80
0X81
:
:
:
0XFE
0XFF
Figure 6-2 Data Memory Configuration
16
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 SR (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT
F
T
P
Z
DC
C
R/W
R/W
R/W
R/W
R/W
Bit 7 (INT): Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/DISI instructions
Bits 6~5: Not used, set to “0” all the time.
Bit 4 (T): Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up
and reset to “0” by WDT time-out.
Bit 3 (P): Power down bit.
Set to ”1” during power on or by a "WDTC" command and reset to ”0” by
a "SLEP" command.
Bit 2 (Z): Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 RSR (RAM Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSR7
R/W
RSR6
R/W
RSR5
R/W
RSR4
R/W
RSR3
R/W
RSR2
R/W
RSR1
R/W
RSR0
R/W
Bits 7~0 (RSR7~RSR0): these bits are used to select registers (Address: 00~FF) in
indirect addressing mode. For more details refer to Figure 6-2 Data
Memory Configuration.
6.1.6 Bank 0 R5 ~ RA Port 5 ~ Port A
R5, R6, R7, R8, R9 and RA are I/O data registers.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
17
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.7 Bank 0 RB~RD IOCR5 ~ IOCR7
These registers are used to control the I/O port direction. They are both readable and
writable.
0: Put the relative I/O pin as output
1: Put the relative I/O pin into high impedance (input)
6.1.8 Bank 0 RE OMCR (Operating Mode Control Register)
Bit 7
CPUS
R/W
Bit 6
IDLE
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCM1
R/W
Bit 0
RCM0
R/W
Bit 7 (CPUS): CPU Oscillator Source Select.
0: Fs: sub-oscillator
1: Fm: main-oscillator
When CPUS=0, the CPU oscillator selects the sub-oscillator and the
main oscillator is stopped.
Bit 6 (IDLE): Idle Mode Enable Bit. This bit will determine as to which mode to go to or
be activated after SLEP instruction.
0: “IDLE=0”+SLEP instruction sleep mode
1: “IDLE=1”+SLEP instruction idle mode
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
Code option
HLFS=0
CPU: using Fm
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
+ SLEP
wakeup
Sleep mode
Fm: stop
Green mode
Fm: stop
Idle mode
Fm: stop
(*)
Fs: stop
CPU: stop
Fs: oscillation
CPU: using Fs
Fs: oscillation
CPU: stop
Interrupt or
wakeup
IDLE=0
+ SLEP
Figure 6-3 CPU Operation Mode
Note
(*) Switching Operation Mode from Idle Normal, Idle Green
If the clock source of the timer is Fs, the timer/counter will continue to count in Idle
mode. When the matching condition of the timer/counter occurs during Idle mode, the
interrupt flag of the timer/counter will be active. The MCU will jump to the interrupt
vector when the corresponding interrupt is enabled.
18
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Oscillation Characteristics
HLFS=1
Pin-Reset / WDT
Power-on
LVR
Fmain Fsub
N / G / I
S
RC 16ms + WSTO + 8*1/Fmain
XT
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 510*1/Fsub
RC
XT
16ms + WSTO + 510*1/Fsub WSTO + 8*1/Fmain
RC 16ms + WSTO + 510*1/Fmain WSTO + 510*1/Fmain WSTO + 510*1/Fmain
XT 16ms + WSTO + 510*1/Fsub WSTO + 510*1/Fmain WSTO + 510*1/Fsub
HLFS=0
Pin-Reset / WDT
N / G / I
Power-on
LVR
Fmain Fsub
S
RC 16ms + WSTO + 8*1/Fsub
XT 16ms + WSTO + 510*1/Fsub
RC 16ms + WSTO + 8*1/Fsub
XT 16ms + WSTO + 510*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 510*1/Fsub
WSTO + 8*1/Fsub
WSTO + 510*1/Fsub
RC
XT
Fmain Fsub
G N
I N
S N
RC WSTO + 8*1/Fmain
XT WSTO + 8*1/Fmain
RC WSTO + 510*1/Fmain
XT WSTO + 510*1/Fmain
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 8*1/Fmain
WSTO + 510*1/Fsub
RC
XT
WSTO + 510*1/Fmain WSTO + 510*1/Fmain
WSTO + 510*1/Fmain WSTO + 510*1/Fsub
Fmain Fsub
I G
S G
RC
XT
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 8*1/Fsub
WSTO + 510*1/Fsub
RC
XT
N: Normal mode
G: Green mode
WSTO: Waiting Time from Start-to-Oscillation
I: Idle mode S: Sleep mode
Bits 5~2: Not used, set to “0” all the time
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
19
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 1~0 (RCM1~RCM0): Internal RC mode select bits
*RCM1
*RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4
Note *: The initial value of RCM1~0 is the same as setting in Code Option Word 0. According to
the control bit “COBS” in Code Option Word 0, the IRC frequencies can be switched by
the control register or only by code option after the IC power is on.
6.1.9 Bank 0 RF EIESCR (External Interrupt Edge Select Control
Register)
Bit 7
EIES98
R/W
Bit 6
EIES76 EIES54
R/W R/W
Bit 5
Bit 4
EIES32
R/W
Bit 3
EIES1
R/W
Bit 2
EIES0
R/W
Bit 1
Bit 0
Bit 7 (EIES98): External Interrupt Edge Select Bit (while controlling INT9 and INT8)
0: Falling edge interrupt
1: Rising edge interrupt
Bit 6 (EIES76): External Interrupt Edge Select Bit (while controlling INT7 and INT6)
0: Falling edge interrupt
1: Rising edge interrupt
Bit 5 (EIES54): External Interrupt Edge Select Bit (while controlling INT5 and INT4)
0: Falling edge interrupt
1: rising edge interrupt
Bit 4 (EIES32): External Interrupt Edge Select Bit (while controlling INT3 and INT2)
0: Falling edge interrupt
1: Rising edge interrupt
Bits 3~2 (EIES1~0): External Interrupt Edge Select Bit
0: Falling edge interrupt
1: Rising edge interrupt
Bits 1~0: Not used, set to “0” all the time
20
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.10 Bank 0 R10 WUCR1 (Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
LVDWK
R/W
Bit 4
ADWK
R/W
Bit 3
INTWK1 INTWK0
R/W R/W
Bit 2
Bit 1
Bit 0
Bits 7~6: Not used, set to “0” all the time
Bit 5 (LVDWK): Low Voltage Detect Wake-up Enable Bit
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
Bit 4 (ADWK): A/D Converter Wake-up Function Enable Bit
0: Disable AD converter wake-up
1: Enable AD converter wake-up
When the AD Complete status is used to enter an interrupt vector or to wake-up the IC
from sleep/idle mode with AD conversion running, the ADWK bit must be set to
“Enable“.
Bits 3~2 (INTWK1~0): External Interrupt (INT pin) Wake-up Function Enable Bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status changed is used to enter an interrupt vector or to
wake-up the IC from sleep/idle mode, the INTWK bits must be set to “Enable“.
Bits 1~0: Not used, set to “0” all the time
6.1.11 Bank 0 R11 WUCR2 (Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2CWK
R/W
SPIWK
R/W
Bits 7~4: Not used, set to “0” all the time.
Bit 3 (SPIWK): SPI wake-up enable bit. Functions when SPI works in Slave mode.
0: Disable SPI wake-up
1: Enable SPI wake-up
Bit 2 (I2CWK): I2C wake-up enable bit. It is available when I2C works in Slave mode.
0: Disable
1: Enable
Bits 1~0: Not used, set to “0” all the time
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
21
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.12 Bank 0 R12 WUCR3 (Wake-up Control Register 3)
Bit 7
ICWKP8 ICWKP7 ICWKP6 ICWKP5 INTWK98 INTWK76 INTWK54 INTWK32
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~4 (ICWKP8~5): (Port 8~5) Pin-change Wake-up Function Enable Bit
0: Disable pin change wake-up function
1: Enable pin change wake-up function
Bits 3~0 (INTWK98/INTWK76/INTWK54/INTWK32): External Interrupt (INT pin)
Wake-up Function Enable Bit (INTWK98 while controlling INT9 and
INT8. INTWK76, INTWK54 and INTWK32 are similar)
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status change is used to enter an interrupt
vector or to wake-up the IC from sleep/idle mode, the INTWK bits must
be set to “Enable“.
6.1.13 Bank 0 R14 SFR1 (Status Flag Register 1)
Bit 7
Bit 6
Bit 5
LVDSF
F
Bit 4
ADSF
F
Bit 3
EXSF1
F
Bit 2
EXSF0
F
Bit 1
WTSF
F
Bit 0
TCSF
F
Each corresponding status flag is set to “1” when interrupt condition is triggered.
Bits 7~6: Not used, set to “0” all the time.
Bit 5 (LVDSF): Low Voltage Detector status flag.
LVDEN
LVDS2~0
011
LVD Voltage Interrupt Level
LVDSF
1
1
1
1
0
2.2V
3.3V
4.0V
4.5V
NA
1*
1*
1*
1*
0
010
001
000
XXX
* If VDD crossovers at the LVD voltage interrupt level as VDD varies, then LVDSF = 1.
Bit 4 (ADSF): Status flag for Analog-to-Digital conversion. Set when AD conversion is
completed, reset by software.
Bits 3~2 (EXSF1~0): External interrupt status flag.
Bit 1 (WTSF): Watch timer status flag. Set when the Watch timer overflows, reset by
software.
Bit 0 (TCSF): TCC overflow status flag. Set when TCC overflows, reset by software.
NOTE
22
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
If a function is enabled, the corresponding status flag would be active whether the
interrupt mask is enabled or not.
6.1.14 Bank 0 R15 SFR2 (Status Flag Register 2)
Bit 7
Bit 6
Bit 5
UERRSF
F
Bit 4
URSF
F
Bit 3
UTSF
F
Bit 2
TC3SF
F
Bit 1
TC2SF
F
Bit 0
TC1SF
F
Each corresponding status flag is set to “1” when interrupt condition is triggered.
Bits 7~6: Not used, set to “0” all the time
Bit 5 (UERRSF): UART receiving error Status flag. This flag is cleared by software or
when UART is disabled.
Bit 4 (URSF): UART receive mode data buffer full Status flag. This flag is cleared by
software.
Bit 3 (UTSF): UART transmit mode data buffer empty flag. This flag is cleared by
software.
Bit 2 (TC3SF): 8-bit Timer/Counter 3 Status flag. This flag is cleared by software.
Bit 1 (TC2SF): 8-bit Timer/Counter 2 Status flag. This flag is cleared by software.
Bit 0 (TC1SF): 8-/16-bit Timer/Counter 1 Status flag. This flag is cleared by software.
6.1.15 Bank 0 R17 SFR4 (Status Flag Register 4)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P8ICSF
F
P7ICSF
F
P6ICSF
F
P5ICSF
F
SPISF I2CSTPSF I2CRSF
I2CTSF
F
F
F
F
Bit 7 (P8ICSF): Port 8 Status flag. This flag is cleared by software.
Bit 6 (P7ICSF): Port 7 Status flag. This flag is cleared by software.
Bit 5 (P6ICSF): Port 6 Status flag. This flag is cleared by software.
Bit 4 (P5ICSF): Port 5 Status flag. This Flag is cleared by software.
Bit 3 (SPISF): SPI mode Status flag. This flag is cleared by software.
Bit 2 (I2CSTPSF): I2C Stop Status flag. Set when I2C occurs at a stop signal.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
23
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 1 (I2CRSF): I2C Receive Status flag. Set when I2C receives 1 byte data and
responds with an ACK signal. Reset by firmware or when I22C is
disabled.
Bit 0 (I2CTSF): I2C Transmit Status flag. Set when I2C transmits 1 byte data and
receives handshake signal (ACK or NACK). Reset by firmware or
when I2C is disabled
NOTE
If a function is enabled, the corresponding Status flag would be active whether the
interrupt mask is enabled or not.
6.1.16 Bank 0 R18 SFR5 (Status Flag Register 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXSF9
F
EXSF8
F
EXSF7
F
EXSF6
F
EXSF5
F
EXSF4
F
EXSF3
F
EXSF2
F
Each corresponding Status flag is set to “1” when interrupt condition is triggered.
Bits 7~0 (EXSF9~2): External Interrupt Status flag.
NOTE
If a function is enabled, the corresponding status flag would be active regardless
whether the interrupt mask is enabled or not.
6.1.17 Bank 0 R1B IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
LVDIE
R/W
Bit 4
ADIE
R/W
Bit 3
EXIE1
R/W
Bit 2
EXIE0
R/W
Bit 1
WTIE
R/W
Bit 0
TCIE
R/W
Bits 7~6: Not used, set to “0” all the time.
Bit 5 (LVDIE): LVDSF interrupt enable bit.
0: Disable LVDSF interrupt
1: Enable LVDSF interrupt
Bit 4 (ADIE): ADSF interrupt enable bit.
0: Disable ADSF interrupt
1: Enable ADSF interrupt
24
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 3 (EXIE1): EXSF1 interrupt enable bit.
0: Disable EXSF1 interrupt
1: Enable EXSF1 interrupt
Bit 2 (EXIE0): EXSF0 interrupt enable bit.
0: Disable EXSF0 interrupt
1: Enable EXSF0 interrupt
Bit 1 (WTIE): WTSF interrupt enable bit.
0: Disable WTSF interrupt
1: Enable WTSF interrupt
Bit 0 (TCIE): TCSF interrupt enable bit.
0: Disable TCSF interrupt
1: Enable TCSF interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter would
jump into the corresponding interrupt vector when the corresponding status flag is
set.
6.1.18 Bank 0 R1C IMR2 (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
UERRIE
R/W
Bit 4
URIE
R/W
Bit 3
UTIE
R/W
Bit 2
TC3IE
R/W
Bit 1
TC2IE
R/W
Bit 0
TC1IE
R/W
Bits 7~6: Not used, set to “0” all the time.
Bit 5 (UERRIE): UART receive error interrupt enable bit.
0: Disable UERRSF interrupt
1: Enable UERRSF interrupt
Bit 4 (URIE): UART receive mode Interrupt enable bit.
0: Disable URSF interrupt
1: Enable URSF interrupt
Bit 3 (UTIE): UART transmit mode interrupt enable bit.
0: Disable UTSF interrupt
1: Enable UTSF interrupt
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
25
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 2 (TC3IE): Interrupt enable bit.
0: Disable TC3SF interrupt
1: Enable TC3SF interrupt
Bit 1 (TC2IE): Interrupt enable bit.
0: Disable TC2SF interrupt
1: Enable TC2SF interrupt
Bit 0 (TC1IE): Interrupt enable bit.
0: Disable TC1SF interrupt
1: Enable TC1SF interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter would
jump to the corresponding interrupt vector when the corresponding status flag is set.
6.1.19 Bank 0 R1E IMR4 (Interrupt Mask Register 4)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P8ICIE
R/W
P7ICIE
R/W
P6ICIE
R/W
P5ICIE
R/W
SPIIE
R/W
I2CSTPIE
R/W
I2CRIE
R/W
I2CTIE
R/W
Bits 7~4 (P8ICIE ~P5ICIE): Ports 8~5 pin-change Interrupt Enable bit.
0: Disable P8ICSF ~ P5ICSF interrupt
1: Enable P8ICSF ~ P5ICSF interrupt
Bit 3 (SPIIE): Interrupt enable bit.
0: Disable SPISF interrupt
1: Enable SPISF interrupt
Bit 2 (I2CSTPIE): I2C stop interrupt enable bit.
0: Disable interrupt
1: Enable interrupt
Bit 1 (I2CRIE): I2C Interface Rx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
Bit 0 (I2CTIE): I2C Interface Tx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
26
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter would
jump to the corresponding interrupt vector when the corresponding status flag is set.
6.1.20 Bank 0 R1F IMR5 (Interrupt Mask Register 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIE9
R/W
EXIE8
R/W
EXIE7
R/W
EXIE6
R/W
EXIE5
R/W
EXIE4
R/W
EXIE3
R/W
EXIE2
R/W
Bits 7~0 (EXIE9~2): EXSF9~2 interrupt enable bit.
0: Disable EXSF9~2 interrupt
1: Enable EXSF9~2 interrupt
INT Pin
Enable Condition
Edge
Digital Noise Reject
INTX
EXIEX
Rising or Falling
8/Fc or 32/Fc
NOTE
1. The compound pin used as INT pin determines whether the interrupt
mask is enabled or not.
2. If the interrupt mask and instruction “ENI” are enabled, the program counter would
jump to the corresponding interrupt vector when the corresponding Status flag is
set.
6.1.21 Bank 0 R21 WDTCR (Watchdog Timer Control Register)
Bit 7
WDTE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
PSWE
R/W
Bit 2
WPSR2
R/W
Bit 1
WPSR1
R/W
Bit 0
WPSR0
R/W
Bit 7 (WDTE): Watchdog Timer Enable Bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bits 6~4: Not used, set to “0” all the time.
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit. WDT rate is 1:1
1: Prescaler enable bit. WDT rate is set at Bits 2~0.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
27
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (WPSR2~ WPSR 0): WDT Prescaler Bits
WPSR2
WPSR1 WPSR0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.22 Bank 0 R22 TCCCR (TCC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCCS
R/W
TS
TE
PSTE
R/W
TPSR2
R/W
TPSR1
R/W
TPSR0
R/W
R/W
R/W
Bit 7: Not used, set to “0” all the time.
Bit 6 (TCCS): TCC Clock Source Select Bit
0: Fs (sub clock) (default)
1: Fm (main clock)
Bit 5 (TS): TCC Signal Source
0: Internal oscillator cycle clock. If P77 is used as I/O pin, TS must be 0.
1: Transition on the TCC pin, TCC period must be larger than internal
instruction clock period.
Bit 4 (TE): TCC Signal Edge
0: Increment if the transition from low to high takes place on the TCC pin
1: Increment if the transition from high to low takes place on the TCC pin
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. The TCC rate is 1:1.
1: Prescaler enable bit. The TCC rate is set at Bit 2 ~ Bit 0.
28
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (TPSR2~TPSR0): TCC Prescaler Bits
TPSR2
TPSR1
TPSR0
TCC Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.23 Bank 0 R23 TCCD (TCC Data Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCC7
R/W
TCC6
R/W
TCC5
R/W
TCC4
R/W
TCC3
R/W
TCC2
R/W
TCC1
R/W
TCC0
R/W
Bits 7~0 (TCC7~TCC0): TCC data
It is incremented by an external signal edge through the TCC pin or by the instruction
cycle clock. The external signal of the TCC trigger pulse width must be greater than
one instruction. The signals to increment the counter are determined by Bit 4 and Bit 5
of the TCCCR register. Writable and readable as any other registers. Whenever
overflow is happened, the TCC circuit will continue to count signal edge from 0
repeatedly.
6.1.24 Bank 0 R24 TC1CR1 (Timer/Counter 1 Control Register 1)
Bit 7
Bit 6
Bit 5
TC1SS1 TC1MOD
R/W R/W
Bit 4
Bit 3
Bit 2
TC1OMS TC1IS1
R/W R/W
Bit 1
Bit 0
TC1S
R/W
TC1RC
R/W
TC1FF
R/W
TC1IS0
R/W
Bit 7 (TC1S): Timer/Counter 1 start control (main switch for all modes)
0: Stop and clear the counter (default)
1: Start Timer/Counter 1
Bit 6 (TC1RC): Timer 1 Read Control Bit
0: When this bit is set to “0”, data from TC1DB cannot be read (default).
1: When this bit is set to “1”, data is read from TC1DB. The read data is
the enumerated counting number.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
29
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 5 (TC1SS1): Timer/Counter 1 clock source select Bit 1
0: Select internal clock as counting source (Fc) Fs/Fm (default)
1: Select external TC1 pin as counting source (Fc). It is used only for
timer/counter mode.
Bit 4 (TC1MOD): Timer Operation Mode Select Bit
0: Two 8-bit timers
1: Timers 1 and 2 are cascaded as one 16-bit timer. The corresponding
control register of the 16-bit timer is from Timer 1. TC1DAand TC1DB
are high byte. TC2DA and TC2DB are low byte.
Bit 3 (TC1FF): Inversion for Timer/Counter 1 as PWM or PDO mode
0: Duty is Logic 1 (default)
1: Duty is Logic 0
Bit 2 (TC1OMS): Timer Output Mode Select Bit
0: Repeating mode (default)
1: One-shot mode
NOTE
One-shot mode means the timer only counts a cycle.
Bits 1~0 (TC1IS1~ TC1IS0): Timer 1 Interrupt Type Select Bits. These two bits are
used when the Timer operates in PWM mode.
TC1IS1
TC1IS0
Timer 1 Interrupt Type Select
TC1DA (period) matching
0
0
1
0
1
TC1DB (duty) matching
TC1DA and TC1DB matching
6.1.25 Bank 0 R25 TC1CR2 (Timer/Counter 1 Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
R/W R/W R/W R/W R/W
Bit 3
Bit 2
Bit 1
Bit 0
TC1M2
R/W
TC1M1
R/W
TC1M0
R/W
30
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 7~5 (TC1M2~TC1M0): Timer/Counter 1 operation mode select.
TC1M2
TC1M1
TC1M0
Operating Mode Select
Timer/Counter Rising Edge
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer (output timer/counter clock source. The
duty cycle of the clock source must be 50/50)
1
1
1
Bit 4 (TC1SS0): Timer/Counter 1 clock source select bit
0: Fs is used as counting source (Fc) (default)
1: Fm is used as counting source (Fc)
Bits 3~0 (TC1CK3~TC1CK0): Timer/Counter 1 clock source prescaler select
Max. Time
8 MHz
Max. Time
16kHz
Clock
Source
Resolution
8 MHz
Resolution
16kHz
TC3CK3 TC3CK2 TC3CK1 TC3CK0
Normal
FC
FC=8M
125ns
250ns
500ns
1 μs
FC=8M
32 μs
FC=16K
62.5 μs
125 μs
250 μs
500 μs
1ms
FC=16K
16ms
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
FC/2
64 μs
32ms
FC/22
FC/23
FC/24
FC/25
FC/26
FC/27
FC/28
128 μs
256 μs
512 μs
1024 μs
2048 μs
4096 μs
8192 μs
64ms
128ms
256ms
512ms
1024ms
2048ms
4096ms
2 μs
4 μs
2ms
8 μs
4ms
16 μs
32 μs
8ms
16ms
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
64 μs
128 μs
16384 μs
32768 μs
65536 μs
131072 μs
262144 μs
524.288ms
1.048s
32ms
64ms
8192ms
16384ms
32768ms
65536ms
131072ms
262144ms
524288ms
256 μs
128ms
256ms
512ms
1.024s
2.048s
512 μs
1.024ms
2.048ms
4.096ms
6.1.26 Bank 0 R26 TC1DA (Timer/Counter 1 Data Buffer A)
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
31
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7~0 (TC1DA7~0): Data Buffer A of 8-bit Timer/Counter 1
6.1.27 Bank 0 R27 TC1DB (Timer/Counter 1 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7~0 (TC1DB7~0): Data Buffer B of 8-bit Timer/Counter 1
NOTE
1. When Timer / Counter x is used in PWM mode, the duty value stored at register
TCxDB must be smaller than or equal to the period value stored at register
TCxDA.,i.e. duty≦period. Then the PWM waveform is generated. If the duty is
larger than the period, the PWM output waveform is kept at a high voltage level.
2. The period value set by users is extra plus 1 in inner circuit.
For example:
When the period value is set as 0x4F, the PWM waveform will actually generate 0x50
period length.
When the period value is set as 0xFF, the PWM waveform will actually generate
0x100 period length.
6.1.28 Bank 0 R28 TC2CR1 (Timer/Counter 2 Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TC2OMS TC2IS1
R/W R/W
Bit 1
Bit 0
TC2S
R/W
TC2RC
R/W
TC2SS1
R/W
TC2FF
R/W
TC2IS0
R/W
Bit 7 (TC2S): Timer/Counter 2 start control (main switch for all modes)
0: Stop and clear the counter (default)
1: Start Timer/Counter 2
Bit 6 (TC2RC): Timer 2 Read Control Bit
0: When this bit is set to “0”, data from TC2DB cannot be read (default).
1: When this bit is set to “1”, data is read from TC2DB. The read data is
the enumerated counting number.
32
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 5 (TC2SS1): Timer/Counter 2 clock source select Bit 1
0: Internal clock as counting source (Fc) - Fs/Fm (default)
1: External TC2 pin as counting source (Fc). It is used only for
timer/counter mode.
Bit 4: Not used, set to “0” all the time.
Bit 3 (TC2FF): Inversion for Timer/Counter 2 as PWM or PDO mode
0: Duty is Logic 1 (default).
1: Duty is Logic 0.
Bit 2 (TC2OMS): Timer Output Mode Select Bit
0: Repeating mode (default)
1: One-shot mode
NOTE
One-shot mode means the timer only counts a cycle.
Bits 1~0 (TC2IS1~ TC2IS0): Timer 2 Interrupt Type Select Bits. These two bits are
used when the Timer operates in PWM mode.
TC2IS1
TC2IS0
Timer 2 Interrupt Type Select
TC2DA (period) matching
0
0
1
0
1
TC2DB (duty) matching
TC2DA and TC2DB matching
6.1.29 Bank 0 R29 TC2CR2 (Timer/Counter 2 Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
TC2SS0 TC2CK3 TC2CK2 TC2CK1 TC2CK0
R/W R/W R/W R/W R/W
Bit 3
Bit 2
Bit 1
Bit 0
TC2M2
R/W
TC2M1
R/W
TC2M0
R/W
Bits 7~5 (TC2M2~TC2M0): Timer/Counter 2 operation mode select
TC2M2
TC2M1
TC2M0
Operating Mode Select
Timer/Counter Rising Edge
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer(output timer/counter clock source. The duty cycle
of the clock source must be 50/50)
1
1
1
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
33
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 4 (TC2SS0): Timer/Counter 2 Clock Source Select Bit 0
0: Fs is used as counting source (Fc) (default)
1: Fm is used as counting source (Fc)
Bits 3~0 (TC2CK3~TC2CK0): Timer/Counter 2 Clock Source Prescaler Select.
Max. Time
8 MHz
Max. Time
16kHz
Clock
Source
Resolution
8 MHz
Resolution
16kHz
TC2CK3 TC2CK2 TC2CK1 TC2CK0
Normal
FC
FC=8M
125ns
250ns
500ns
1 μs
FC=8M
32 μs
FC=16K
62.5 μs
125 μs
250 μs
500 μs
1ms
FC=16K
16ms
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FC/2
64 μs
32ms
FC/22
FC/23
FC/24
FC/25
FC/26
FC/27
FC/28
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
128 μs
64ms
256 μs
128ms
2 μs
512 μs
256ms
4 μs
1024 μs
2048 μs
4096 μs
8192 μs
16384 μs
32768 μs
65536 μs
131072 μs
262144 μs
524.288ms
1.048s
2ms
512ms
8 μs
4ms
1024ms
2048ms
4096ms
8192ms
16384ms
32768ms
65536ms
131072ms
262144ms
524288ms
16 μs
8ms
32 μs
16ms
64 μs
32ms
128 μs
256 μs
512 μs
1.024ms
2.048ms
4.096ms
64ms
128ms
256ms
512ms
1.024s
2.048s
6.1.30 Bank 0 R2A TC2DA (Timer/Counter 2 Data Buffer A)
Bit 7
TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1
R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2DA0
R/W
Bits 7~0 (TC2DA7~ TC2DA0): Data Buffer A of 8-bit Timer/Counter 2
6.1.31 Bank 0 R2B TC2DB (Timer/Counter 2 Data Buffer B)
Bit 7
TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1
R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC2DB0
R/W
Bits 7~0 (TC2DB7~ TC2DB0): Data Buffer B of 8-bit Timer/Counter 2
34
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.32 Bank 0 R2C TC3CR1 (Timer/Counter 3 Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TC3OMS TC3IS1
R/W R/W
Bit 1
Bit 0
TC3S
R/W
TC3RC
R/W
TC3SS1
R/W
TC3FF
R/W
TC3IS0
R/W
Bit 7 (TC3S): Timer/Counter 3 start control (main switch for all modes)
0: Stop and clear the counter (default)
1: Start Timer/Counter 3
Bit 6 (TC3RC): Timer 3 Read Control Bit
0: When this bit is set to “0”, data from TC3DB cannot be read (default).
1: When this bit is set to “1”, data is read from TC3DB. The read data is
the enumerated counting number.
Bit 5 (TC3SS1): Timer/Counter 3 Clock Source Select Bit 1
0: Internal clock as counting source (Fc) - Fs/Fm (default)
1: External TC3 pin as counting source (Fc). It is used only for
timer/counter mode.
Bit 4: Not used, set to “0” all the time.
Bit 3 (TC3FF): Inversion for Timer/Counter 3 as PWM or PDO mode.
0: Duty is Logic 1 (default).
1: Duty is Logic 0.
Bit 2 (TC3OMS): Timer Output Mode Select Bit
0: Repeating mode (default)
1: One-shot mode
NOTE
One-shot mode means the timer only counts a cycle.
Bits 1~0 (TC3IS1~ TC3IS0): Timer 3 Interrupt Type Select Bits. These two bits are
used when the Timer operates in PWM mode.
TC3IS1
TC3IS0
Timer 3 Interrupt Type Select
TC3DA (period) matching
0
0
1
0
1
TC3DB (duty) matching
TC3DA and TC3DB matching
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
35
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.33 Bank 0 R2D TC3CR2 (Timer/Counter 3 Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3M2
R/W
TC3M1
R/W
TC3M0
R/W
TC3SS0 TC3CK3 TC3CK2 TC3CK1 TC3CK0
R/W
R/W
R/W
R/W
R/W
Bits 7~5 (TC3M2~TC3M0): Timer/Counter 3 operation mode select.
TC3M2 TC3M1 TC3M0 Operating Mode Select
Timer/Counter Rising Edge
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer (output timer/counter clock source. The
duty cycle of the clock source must be 50/50)
1
1
1
Bit 4 (TC3SS0): Timer/Counter 3 Clock Source Select Bit 0
0: Fs is used as counting source (Fc) (default)
1: Fm is used as counting source (Fc)
Bits 3~0 (TC3CK3~TC3CK0): Timer/Counter 3 clock source prescaler select.
Max. Time
8 MHz
Clock
Source
Resolution
8 MHz
Resolution Max. Time
16kHz
FC=16K
62.5 μs
125 μs
250 μs
500 μs
1ms
16kHz
FC=16K
16ms
TC3CK3 TC3CK2 TC3CK1 TC3CK0
Normal
FC
FC=8M
125ns
250ns
500ns
1 μs
FC=8M
32 μs
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FC/2
64 μs
32ms
FC/22
FC/23
FC/24
FC/25
FC/26
FC/27
FC/28
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
128 μs
64ms
256 μs
128ms
2 μs
512 μs
256ms
4 μs
1024 μs
2048 μs
4096 μs
8192 μs
16384 μs
32768 μs
65536 μs
131072 μs
262144 μs
524.288ms
1.048s
2ms
512ms
8 μs
4ms
1024ms
2048ms
4096ms
8192ms
16384ms
32768ms
65536ms
131072ms
262144ms
524288ms
16 μs
8ms
32 μs
16ms
64 μs
32ms
128 μs
256 μs
512 μs
1.024ms
2.048ms
4.096ms
64ms
128ms
256ms
512ms
1.024s
2.048s
36
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.34 Bank 0 R2E TC3DA (Timer/Counter 3 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7~0 (TC3DA7~ TC3DA0): Data Buffer A of 8-bit Timer/Counter 3
6.1.35 Bank 0 R2F TC3DB (Timer/Counter 3 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7~0 (TC3DB7~ TC3DB0): Data Buffer B of 8-bit Timer/Counter 3
6.1.36 Bank 0 R30 I2CCR1 (I2C Status and Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
STOP SAR_EMPTY
R/W
Bit 3
Bit 2
Bit 1
Bit 0
Strobe/Pend
R/W
IMS
R/W
ISS
ACK
R
FULL
R
EMPTY
R
R/W
R
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control the I2C
circuit from sending SCL clock. Automatically resets after receiving or
transmitting a handshake signal (ACK or NACK).
In Slave mode, it is used as pending signal. User should clear it after
writing data into the Tx buffer or retrieving data from the Rx buffer to
inform the Slave I2C circuit to release an SCL signal.
Bit 6 (IMS): I2C Master/Slave mode select bit.
0: Slave
1: Master
Bit 5 (ISS): I2C Fast/Standard mode select bit. (If Fm is 4 MHz and I2CTS1~0<0,0>)
0: Standard mode (100kbit/s)
1: Fast mode (400kbit/s)
Bit 4 (STOP): In Master mode, if STOP=1 and R/nW=1 then the MCU must return a
nACK signal to the Slave device before sending a STOP signal. If
STOP=1 and R/nW=0 then the MCU sends a STOP signal after
receiving an ACK signal. Reset when the MCU sends a STOP signal to
the Slave device.
In Slave mode, if STOP=1 and R/nW=0 then the MCU must return a
nACK signal to the Master device.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
37
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 3 (SAR_EMPTY): Set when the MCU transmits a “1” byte data from the I2C Slave
Address Register and receives an ACK (or nACK) signal. Reset when
the MCU writes a “1” byte data to the I2C Slave Address Register.
Bit 2 (ACK): The ACK condition bit is set to “1” by hardware when the device responds
with an “acknowledge” (ACK) signal. Reset when the device responds
with a “not-acknowledge” (nACK) signal.
Bit 1 (FULL): Set by hardware when the I2C Receive Buffer Register is full. Reset by
hardware when the MCU reads data from the I2C Receive Buffer
Register.
Bit 0 (EMPTY): Set by hardware when I2C Transmit Buffer Register is empty and
receives ACK (or nACK) signal. Reset by hardware when the MCU
writes new data to I2C Transmit Buffer Register.
6.1.37 Bank 0 R31 I2CCR2 (I2C Status and Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I2CTS1
R/W
Bit 2
I2CTS0
R/W
Bit 1
Bit 0
I2CEN
R/W
I2CBF
R
GCEN
R/W
BBF
R
Bit 7 (I2CBF): I2C Busy Flag Bit
0: Clear to “0” in Slave mode, if the received STOP signal or the I2C
Slave address does not match.
1: Set when I2C communicates with Master in Slave mode.
Bit 6 (GCEN): I2C General Call Function Enable Bit
0: Disable General Call Function
1: Enable General Call Function
Bit 5: Not used, set to “0” all the time.
Bit 4 (BBF): Busy Flag Bit. I2C detection is busy in the Master mode. Read only.
Bits 3~2 (I2CTS1~I2CTS0): I2C Transmit Clock Select Bits. When using different
operating frequency (Fm), these bits must be set correctly in order for
the SCL clock to be consistent in Standard/Fast mode.
I2CCR1 Bit 5 = 1, Fast mode
I2CTS1
I2CTS0
SCL CLK
Fm/10
Operating Fm (MHz)
0
0
1
1
0
1
0
1
4
8
Fm/20
Fm/30
12
16
Fm/40
38
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
I2CCR1 Bit 5 = 0, Standard mode
I2CTS1
I2CTS0
SCL CLK
Fm/40
Operating Fm (MHz)
0
0
1
1
0
1
0
1
4
8
Fm/80
Fm/120
Fm/160
12
16
Bit 1: Not used, set to "0" all the time.
Bit 0 (I2CEN): I2C Enable Bit
0: Disable I2C mode
1: Enable I2C mode
6.1.38 Bank 0 R32 I2CSA (I2C Slave Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SA6
R/W
SA5
R/W
SA4
R/W
SA3
R/W
SA2
R/W
SA1
R/W
SA0
R/W
IRW
R/W
Bits 7~1 (SA6~SA0): When the MCU is used as Master device for I2C application,
these bits are the Slave device address register.
Bit 0 (IRW): When the MCU is used as Master device for I2C application, this bit is a
Read/Write transaction control bit.
0: Write
1: Read
6.1.39 Bank 0 R33 I2CDB (I2C Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DB7
R/W
DB6
R/W
DB5
R/W
DB4
R/W
DB3
R/W
DB2
R/W
DB1
R/W
DB0
R/W
Bits 7~0 (DB7~DB0): I2C Receive/Transmit Data Buffer.
6.1.40 Bank 0 R34 I2CDAL (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DA7
R/W
DA6
R/W
DA5
R/W
DA4
R/W
DA3
R/W
DA2
R/W
DA1
R/W
DA0
R/W
Bits 7~0 (DA7~DA0): When the MCU is used as Slave device for I2C application, this
register stores the address of the MCU. It is used to identify the data on
the I2C bus to extract the message delivered to the MCU.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
39
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.41 Bank 0 R35 I2CDAH (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DA9
R/W
DA8
R/W
Bits 7~2: Not used, set to “0” all the time.
Bits 1~0 (DA9~DA8): Device Address bits.
6.1.42 Bank 0 R36 SPICR (SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
R/W
SPIE
R/W
SRO
R/W
SSE
R/W
SDOC
R/W
SBRS2
R/W
SBRS1
R/W
SBRS0
R/W
Bit 7 (CES): Clock Edge Select Bit
0: Data shifts out on a rising edge, and shifts in on a falling edge. Data is
on hold during a low-level.
1: Data shifts out on a falling edge, and shift in on a rising edge. Data is
on hold during a high-level.
Bit 6 (SPIE): SPI Enable Bit
0: Disable SPI mode
1: Enable SPI mode
Bit 5 (SRO): SPI Read Overflow Bit
0: No overflow
1: A new data is received while the previous data is still being held in the
SPIR register. In this situation, the data in the SPIS register will be
destroyed. To avoid setting this bit, user is required to read the SPIR
register although only transmission is implemented. This can only
occur in Slave mode.
Bit 4 (SSE): SPI Shift Enable Bit
0: Reset as soon as shifting is completed, and the next byte is ready to
be shifted.
1: Start to shift, and remain on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0: After the serial data output, the SDO remains high.
1: After the serial data output, the SDO remains low.
40
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
/SS enable
/SS disable
Slave
6.1.43 Bank 0 R37 SPIS (SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
R/W
TD1
R/W
TD0
R/W
OD3
R/W
OD4
R/W
RBF
R
Bit 7 (DORD): Data Shift of Type Control Bit
0: Shift left (MSB first)
1: Shift right (LSB first)
Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options. When CPU oscillator
source use Fs from 1 CLK delay time.
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
1
0
24 CLK
1
1
32 CLK
Bit 4: Not used, set to “0” all the time.
Bit 3 (OD3): Open drain control bit
0: Open drain disable for SDO
1: Open drain enable for SDO
Bit 2 (OD4): Open drain control bit
0: Open drain disable for SCK
1: Open drain enable for SCK
Bit 1: Not used, set to “0” all the time.
Bit 0 (RBF): Read Buffer Full Flag
0: Receiving not completed, and SPIR has not fully exchanged.
1: Receiving completed, and SPIR is fully exchanged.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
41
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.44 Bank 0 R38 SPIR (SPI Read Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
R
SRB6
R
SRB5
R
SRB4
R
SRB3
R
SRB2
R
SRB1
R
SRB0
R
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.1.45 Bank 0 R39 SPIW (SPI Write Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
R/W
SWB6
R/W
SWB5
R/W
SWB4
R/W
SWB3
R/W
SWB2
R/W
SWB1
R/W
SWB0
R/W
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
6.1.46 Bank 0 R3E ADCR1 (Analog-to-Digital Converter Control
Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKR2
R/W
CKR1
R/W
CKR0
R/W
ADRUN
R/W
ADP
R/W
ADOM
R/W
SHS1
R/W
SHS0
R/W
Bits 7~5 (CKR2~0): Clock Rate Selection of ADC
System
Mode
Operating Clock
of ADC (FAD = 1 / TAD
Max. FMain
(VDD = 2.5V ~ 3V)
Max. FMain
(VDD = 3V ~ 5.5V)
CKR2~0
)
000
001
010
011
100
101
110
111
FMain/16
FMain/8
FMain/4
FMain/2
FMain/64
FMain/32
FMain/1
FSub
8 MHz
4 MHz
16 MHz
16 MHz
2 MHz
8 MHz
1 MHz
4 MHz
Normal
Mode
16 MHz
16 MHz
500kHz
32.768kHz
16 MHz
16 MHz
2 MHz
32.768kHz
Green
Mode
xxx
FSub
32.768kHz
32.768kHz
Bit 4 (ADRUN): ADC Starts to Run
In Single mode:
0: Reset on completion of the conversion by hardware, this bit cannot be
reset by software.
1: A/D conversion starts. This bit can be set by software
42
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
In Continuous mode:
0: ADC is stopped
1: ADC is running unless this bit is reset by software
Bit 3 (ADP): ADC Power
0: ADC is in power down mode.
1: ADC is operating normally.
Bit 2 (ADOM): ADC Operation Mode Select
0: ADC operates in single mode.
1: ADC operates in continuous mode.
Bits 1~0 (SHS1~0): Sample and Hold Timing Select (Recommend at least 4 µs,
TAD: Period of ADC Operating Clock)
SHS1~0
Sample and Hold Timing
00
01
10
11
2 x TAD
4 x TAD
8 x TAD
12 x TAD
6.1.47 Bank 0 R3F ADCR2 (Analog-to-Digital Converter Control
Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADIM
R/W
ADCMS
R/W
VPIS1
R/W
VPIS0
R/W
VREFP
R/W
Bits 7~6: Not used, set to “0” all the time.
Bit 5 (ADIM): ADC Interrupt Mode
0: Normal mode. Interrupt occurred after AD conversion is completed.
1: Compare mode. Interrupt occurred when comparison result conforms
to the setting of ADCMS bits. Using continuous mode is
recommended.
Bit 4 (ADCMS): ADC Compare Mode Select.
Compare mode:
0: Interrupt occurs when AD conversion data is equal to or greater than
data in ADCD register (which means when ADD＞=ADCD, interrupt
occurs).
1: Interrupt occurs when AD conversion data is equal to or less than the
data in ADCD register (which means when ADD＜=ADCD, interrupt
occurs).
Normal mode: No effect
Bits 3 ~ 2 (VPIS1~0): Internal Positive Reference Voltage Select
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
43
EM78P528N
8-Bit Microprocessor with OTP ROM
VPIS1~0
Reference Voltage
00
01
10
11
AVDD
4 V
3 V
2 V
Bit 1 (VREFP): Positive Reference Voltage Select
0: Internal positive reference voltage. The actual voltage is set by
VPIS1~0 bits
1: From VREF pin.
Bit 0: Not used, set to “0” all the time.
NOTE
1. When using the internal voltage reference and the Code Option Word 2<6>
(IRCIRS) sets to “1”, users need to wait for at least 50 µs when the first time to
enable and stabilize the voltage reference. Un-stabilized reference makes
conversion result inaccurate. After that, users only need to wait for at least 6 μs
whenever switching voltage references.
2. When using the internal voltage reference and the Code Option Word 2<6>
(IRCIRS) sets to “0”, users only need to wait for at least 6 μs for the internal
voltage reference circuit stabilized whenever switching voltage references.
6.1.48 Bank 0 R40 ADISR (Analog-to-Digital Converter Input
Channel Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
ADIS4
R/W
Bit 3
ADIS3
R/W
Bit 2
ADIS2
R/W
Bit 1
ADIS1
R/W
Bit 0
ADIS0
R/W
Bits 7~5: Not used, set to “0” all the time.
Bits 4~0 (ADIS4~0): ADC input channel select bits
ADIS4~0
Selected Channel
ADIS4~0
Selected Channel
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
N/A
1/4 VDD Power Detect
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
*
Used for internal signal source. Users only need to set ADIS4~0=10000.
These AD input channels are instantly active.
44
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.49 Bank 0 R41 ADER1 (Analog-to-Digital Converter Input
Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
R/W
ADE6
R/W
ADE5
R/W
ADE4
R/W
ADE3
R/W
ADE2
R/W
ADE1
R/W
ADE0
R/W
Bit 7 (ADE7): ADC enable bit of P61 pin.
0: Disable AD7, P61 acts as I/O pin.
1: Enable AD7 to act as analog input pin.
Bit 6 (ADE6): ADC enable bit of P63 pin.
0: Disable AD6, P63 acts as I/O pin
1: Enable AD6 to act as analog input pin
Bit 5 (ADE5): ADC enable bit of P64 pin.
0: Disable AD5, P64 acts as I/O pin
1: Enable AD5 to act as analog input pin
Bit 4 (ADE4): ADC enable bit of P65 pin.
0: Disable AD4, P65 acts as I/O pin
1: Enable AD4 to act as analog input pin
Bit 3 (ADE3): ADC enable bit of P66 pin.
0: Disable AD3, P66 act as I/O pin
1: Enable AD3 to act as analog input pin
Bit 2 (ADE2): ADC enable bit of P67 pin.
0: Disable AD2, P67 acts as I/O pin
1: Enable AD2 to act as analog input pin
Bit 1 (ADE1): ADC enable bit of P72 pin.
0: Disable AD1, P72 acts as I/O pin
1: Enable AD1 to act as analog input pin
Bit 0 (ADE0): ADC enable bit of P73 pin.
0: Disable AD0, P73 acts as I/O pin
1: Enable AD0 to act as analog input pin
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
45
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.50 Bank 0 R42 ADER2 (Analog-to-Digital Converter Input
Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE14
R/W
ADE13
R/W
ADE12
R/W
ADE11
R/W
ADE10
R/W
ADE9
R/W
ADE8
R/W
Bit 7: Not used, set to “0” all the time.
Bit 6 (ADE14): ADC enable bit of P95 pin.
0: Disable AD14, P95 acts as I/O pin
1: Enable AD14 to act as analog input pin
Bit 5 (ADE13): ADC enable bit of P94 pin.
0: Disable AD13, P94 acts as I/O pin
1: Enable AD13 to act as analog input pin
Bit 4 (ADE12): ADC enable bit of P93 pin.
0: Disable AD12, P93 acts as I/O pin
1: Enable AD12 to act as analog input pin
Bit 3 (ADE11): ADC enable bit of P92 pin.
0: Disable AD11, P92 acts as I/O pin
1: Enable AD11 to act as analog input pin
Bit 2 (ADE10): ADC enable bit of P91 pin.
0: Disable AD10, P91 acts as I/O pin
1: Enable AD10 to act as analog input pin
Bit 1 (ADE9): ADC enable bit of P90 pin.
0: Disable AD9, P90 acts as I/O pin
1: Enable AD9 to act as analog input pin
Bit 0 (ADE8): ADC enable bit of P60 pin.
0: Disable AD8, P60 acts as I/O pin
1: Enable AD8 to act as analog input pin
46
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.51 Bank 0 R43 ADDL (Low Byte of Analog-to-Digital Converter
Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADD2
R
Bit 1
ADD1
R
Bit 0
ADD0
R
ADD7
R
ADD6
R
ADD5
R
ADD4
R
ADD3
R
Bits 7~0 (ADD7~ ADD0): Low Byte of AD Data Buffer
6.1.52 Bank 0 R44 ADDH (High Byte of Analog-to-Digital
Converter Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADD10
R
Bit 1
ADD9
R
Bit 0
ADD8
R
ADD15
R
ADD14
R
ADD13
R
ADD12
R
ADD11
R
Bits 7~0 (ADD15~ ADD8): High Byte of AD Data Buffer.
The format of AD data is dependent on Code Option ADFM. The following table shows
how the data justify the different ADFM settings.
ADFM1~0
ADDH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADD11 ADD10 ADD9 ADD8
-
-
-
-
0
ADDL ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
ADDH ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
12 bits
1
ADDL
-
-
-
-
ADD3 ADD2 ADD1 ADD0
6.1.53 Bank 0 R45 ADCVL (Low Byte of Analog-to-Digital
Converter Compare Value)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCV2
ADCV1
ADCV0
ADCV7
R/W
ADCV6
R/W
ADCV5
R/W
ADCV4
R/W
ADCV3
R/W
R/W
R/W
R/W
Bits 7~0 (ADCV7~ ADCV0): Low Byte Data for AD Compare Value.
User should use the data format as with ADDH and ADDL register. Otherwise faulty
values will result after AD comparison.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
47
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.54 Bank 0 R46 ADCVH (High Byte of Analog-to-Digital
Converter Compare Value)
Bit 7
ADCV15 ADCV14 ADCV13 ADCV12 ADCV11
R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCV10
ADCV9
ADCV8
R/W
R/W
R/W
Bits 7~0 (ADCV15~ ADCV8): High Byte Data for AD Compare Value
User should use the data format as with ADDH and ADDL registers. Otherwise, faulty
values will result after AD comparison.
6.1.55 Bank 0 R48 LCDCR1 (LCD Driver Control Register 1)
Bit 7
LCDEN LCDTYPE
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BS
DS1
R/W
DS0
R/W
LCDF1
R/W
LCDF0
R/W
R/W
Bit 7 (LCDEN): LCD enable bit
0: Disable LCD driver Power-on during COM/SEG initial pull-low
1: Enable LCD driver
Bit 6 (LCDTYPE): LCD type select bit
0: A type waveform
1: B type waveform
Bit 5: Not used, set to “0” all the time.
Bit 4 (BS): bias select bit
BS
0
LCD bias
1/2 bias
1/3 bias
1
Bits 3~2 (DS1~DS0): LCD duty select bits
DS1
DS0
LCD duty
1/2 duty
1/3 duty
1/4 duty
1/8 duty
0
0
1
1
0
1
0
1
48
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 1~0 (LCDF1~LCDF0): LCD frame rate select bits
LCD Frame Frequency (Fs=32.768kHz from Cystal Osciilator)
1/2 duty 1/3 duty 1/4 duty 1/8 duty
Fs/(3*8*11*2)=62.0 Fs/(4*8*8*2)=64.0
Fs/(3*8*12*2)=56.8
LCDF1 LCDF0
0
0
1
1
0
1
0
1
Fs/(2*8*8*4)=64.0
Fs/(2*8*9*4)=56.8
Fs/(8*8*8)=64.0
Fs/(8*8*9)=56.8
Fs/(8*8*10)=51.2
Fs/(8*8*7)=73.1
Fs/(4*8*9*2)=56.8
Fs/(4*8*10*2)=51.2
Fs/(4*8*7*2)=73.1
Fs/(2*8*10*4)=51.2 Fs/(3*8*13*2)=52.5
Fs/(2*8*7*4)=73.1
Fs/(3*8*10*2)=68.2
LCD Frame Frequency (*Fs≒32kHz from IRC)
LCDF1 LCDF0
1/2 duty
1/3 duty
1/4 duty
1/8 duty
0
0
1
1
0
1
0
1
Fs/(2*8*8*4)=62.5
Fs/(2*8*9*4)=55.6
Fs/(3*8*11*2)=60.6
Fs/(3*8*12*2)=55.6
Fs/(4*8*8*2) =62.5
Fs/(4*8*9*2) =55.6
Fs/(4*8*10*2) =50.0
Fs/(4*8*7*2) =71.4
Fs/(8*8*8)=62.5
Fs/(8*8*9)=55.6
Fs/(8*8*10)=50.0
Fs/(8*8*7)=71.4
Fs/(2*8*10*4)=50.0 Fs/(3*8*13*2)=51.3
Fs/(2*8*7*4)=71.4 Fs/(3*8*10*2)=66.7
Note: *The 32kHz frequency from the internal RC is dedicated for LCD application, not for the MCU kernel.
6.1.56 Bank 0 R49 LCDCR2 (LCD Driver Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBS1
R/W
RBS0
R/W
DYMEN
R/W
Bit 7: Not used, set to “0” all the time.
Bits 6~5 (RBS1~ RBS0): Resistor for Resistive Bias Selection
Bias
RBS1~0
00
Ohms ()
270k
150k
90k
01
10
1/2
11
30k
00
01
10
180k
100k
60k
1/3
11
20k
Bit 4 (DYMEN): Dynamic Mode Enable
0: Disable
1: Enable
When Dynamic mode is enabled, 1/8 Clock LCD resistance of 20kΩ will
switch to fast charging and 7/8 Clock LCD selection of LCD bias stalls
resistance (RBS1 ~ 0 ≠ 11). If selected RBS1 ~ 0 = 11 (20kΩ) do not
perform switching action.
Bits 3~0: Not used, set to “0” all the time.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
49
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.57 Bank 0 R4A LCDCR3 (LCD Driver Control Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LCDCC2 LCDCC1 LCDCC0
R/W R/W R/W
Bit 1
Bit 0
Bits 7~3: Not used, set to “0” all the time.
Bits 2~0 (LCDCC2~ LCDCC0): LCD Contrast Control (Only for R-Type LCD)
LCDCC2~0
000
VLCD
1 x VDD
001
0.96 x VDD
0.93 x VDD
0.87 x VDD
0.82 x VDD
0.74 x VDD
0.66 x VDD
0.60 x VDD
010
011
100
101
110
111
6.1.58 Bank 0 R4B LCDADDR (Address of LCD RAM)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDA4
R/W
LCDA3
R/W
LCDA2
R/W
LCDA1
R/W
LCDA0
R/W
Bits 7~5: Not used, set to “0” all the time.
Bits 4~0 (LCDA4~ LCDA0): Address of LCD RAM. This register is used for 00H~16H
corresponding to SEG0~SEG22.
6.1.59 Bank 0 R4C LCDDB (Data of LCD RAM)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDD7
R/W
LCDD6
R/W
LCDD5
R/W
LCDD4
R/W
LCDD3
R/W
LCDD2
R/W
LCDD1
R/W
LCDD0
R/W
Bits 7~0 (LCDD7~ LCDD0): LCD RAM data register
50
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
The following table shows the organization of the LCD RAM and the relation between
the Data RAM and the LCD signal
Data of LCD RAM
Bit 4 Bit 3
(LCDD7) (LCDD6) (LCDD5) (LCDD4) (LCDD3) (LCDD2) (LCDD1) (LCDD0)
Address
of LCD
RAM
SEG
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
0x00h
0x01h
0x02h
|
-
-
-
-
-
-
-
-
SEG0
SEG1
SEG2
|
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
|
|
|
|
|
|
|
|
0x14h
0x15h
0x16h
COM
-
-
-
-
-
-
-
-
SEG20
SEG21
SEG22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
6.1.60 Bank 0 R4D LCDSCR0 (LCD COM/SEG Pin Control Register 0)
Bit 7
Bit 6
LCDSM2 LCDSM1 LCDSM0
R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
LCDCM2 LCDCM1 LCDCM0
R/W R/W R/W
Bit 1
Bit 0
Bit 7: Not used, set to 0 all the time
Bits 6~4 (LCDSM2~ LCDSM0): LCD pin switch for SEG16~SEG22
LCDSM
2~0
Number of
SEG signals
Description
16 segments
mode max.
(default)
SEG0~SEG15 pins are switched individually.
SEG16~SEG22 pins are switched to general purpose I/O ports.
x00
001
SEG0~SEG15 pins are switched individually.
SEG16~SEG17 pins are switched to LCD segment signals.
SEG18~SEG22 pins are switched to general purpose I/O ports.
18 segments
mode max.
SEG0~SEG15 pins are switched individually.
SEG16~SEG19 pins are switched to LCD segment signals.
SEG20~SEG22 pins are switched to general purpose I/O ports.
20 segments
mode max.
010
x11
101
23 segments
mode max.
SEG0~SEG15 pins are switched individually.
SEG16~SEG22 pins are switched to LCD segment signals.
SEG0~SEG15 pins are switched individually.
SEG16~SEG21 pins are switched to general purpose I/O ports.
SEG22 pin is switched to LCD segment signals.
17 segments
mode max.
SEG0~SEG15 pins are switched individually.
SEG16~SEG19 pins are switched to general purpose I/O ports.
SEG20~SEG22 pins are switched to LCD segment signals.
18 segments
mode max.
110
Bit 3: Not used, set to “0” all the time.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
51
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (LCDCM2~ LCDCM0): LCD port switch for COM0~COM7.
LCDCM
2~0
Number of
COM signals
Description
No common mode
(default)
COM0~COM7 pins are switched to general purpose I/O ports.
0xx
COM0~COM1 pins are switched to LCD common signals.
COM2~COM7 pins are switched to general purpose I/O ports.
COM0~COM2 pins are switched to LCD common signals.
COM3~COM7 pins are switched to general purpose I/O ports.
COM0~COM3 pins are switched to LCD common signals.
COM4~COM7 pins are switched to general purpose I/O ports.
COM0~COM7 pins are switched to LCD common signals.
2 common modes
3 common modes
100
101
4 common modes
8 common modes
110
111
6.1.61 Bank 0 R4E LCDSCR1 (LCD SEG Pin Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG7
R/W
SEG6
R/W
SEG5
R/W
SEG4
R/W
SEG3
R/W
SEG2
R/W
SEG1
R/W
SEG0
R/W
Bits 7~0 (SEG7~ SEG0): LCD Pin Switch for SEG7~SEG0
0: Function as normal I/O or other functions (default)
1: Function as LCD segment pins
6.1.62 Bank 0 R4F LCDSCR2 (LCD Segment Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG15
R/W
SEG14
R/W
SEG13
R/W
SEG12
R/W
SEG11
R/W
SEG10
R/W
SEG9
R/W
SEG8
R/W
Bits 7~0 (SEG15~ SEG8): LCD Pin Switch for SEG15~SEG8
0: Function as normal I/O or other functions (default)
1: Function as LCD segment pins
6.1.63 Bank 1 R5~R7 IOCR8~IOCA
These registers are used to control I/O port direction. They are both readable and
writable.
0: Put the relative I/O pin as output
1: Put the relative I/O pin into high impedance
52
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.64 Bank 1 R8 P5PHCR (Port 5 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH57
R/W
PH56
R/W
PH55
R/W
PH54
R/W
PH53
R/W
PH52
R/W
PH51
R/W
PH50
R/W
Bits 7~0 (PH57~PH50): Control bit used to enable pull-high of the P57~P50 pins
0: Enable internal pull-high
1: Disable internal pull-high
6.1.65 Bank 1 R9 P6PHCR (Port 6 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH67
R/W
PH66
R/W
PH65
R/W
PH64
R/W
PH63
R/W
PH62
R/W
PH61
R/W
PH60
R/W
Bits 7~0 (PH67~PH60): Control bit used to enable pull-high of the
P67~P60 pins
0: Enable internal pull-high
1: Disable internal pull-high
6.1.66 Bank 1 RA P789APHCR (Port 7~A Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAHPH
R/W
PALPH
R/W
P9HPH
R/W
P9LPH
R/W
P8HPH
R/W
P8LPH
R/W
P7HPH
R/W
P7LPH
R/W
Bit 7 (PAHPH): Control bit used to enable pull-high of Port A high nibble (PA7~PA4) pin
Bit 6 (PALPH): Control bit used to enable pull-high of Port A low nibble (PA3~PA0) pin
Bit 5 (P9HPH): Control bit used to enable pull-high of Port 9 high nibble (P97~P94) pin
Bit 4 (P9LPH): Control bit used to enable pull-high of Port 9 low nibble (P93~P90) pin
Bit 3 (P8HPH): Control bit used to enable pull-high of Port 8 high nibble (P87~P84) pin
Bit 2 (P8LPH): Control bit used to enable pull-high of Port 8 low nibble (P83~P80) pin
Bit 1 (P7HPH): Control bit used to enable pull-high of Port 7 high nibble (P77~P74) pin
Bit 0 (P7LPH): Control bit used to enable pull-high of Port 7 low nibble (P73~P72) pin
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
53
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.67 Bank 1 RB P5PLCR (Port 5 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL57
R/W
PL56
R/W
PL55
R/W
PL54
R/W
PL53
R/W
PL52
R/W
PL51
R/W
PL50
R/W
Bits 7~0 (PL57~PL50): Control bit used to enable pull-low of P57~P50 pins
0: Enable internal pull-low
1: Disable internal pull-low
6.1.68 Bank 1 RC P6PLCR (Port 6 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL67
R/W
PL66
R/W
PL65
R/W
PL64
R/W
PL63
R/W
PL62
R/W
PL61
R/W
PL60
R/W
Bits 7~0 (PL67~PL60): Control bit used to enable pull-low of P67~P60 pins
0: Enable internal pull-low
1: Disable internal pull-low
6.1.69 Bank 1 RD P789APLCR (Port 7~A Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAHPL
R/W
PALPL
R/W
P9HPL
R/W
P9LPL
R/W
P8HPL
R/W
P8LPL
R/W
P7HPL
R/W
P7LPL
R/W
Bit 7 (PAHPL): Control bit used to enable pull-low of Port A high nibble (PA7~PA4) pin
Bit 6 (PALPL): Control bit used to enable pull-low of Port A low nibble (PA3~PA0) pin
Bit 5 (P9HPL): Control bit used to enable pull-low of Port 9 high nibble (P97~P94) pin
Bit 4 (P9LPL): Control bit used to enable pull-low of Port 9 low nibble (P93~P90) pin
Bit 3 (P8HPL): Control bit used to enable pull-low of Port 8 high nibble (P87~P84) pin
Bit 2 (P8LPL): Control bit used to enable pull-low of Port 8 low nibble (P83~P80) pin
Bit 1 (P7HPL): Control bit used to enable pull-low of Port 7 high nibble (P77~P74) pin
Bit 0 (P7LPL): Control bit used to enable pull-low of Port 7 low nibble (P73~P72) pin
54
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.70 Bank 1 RE P5HDSCR (Port 5 High Drive/Sink Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H57
R/W
H56
R/W
H55
R/W
H54
R/W
H53
R/W
H52
R/W
H51
R/W
H50
R/W
Bits 7~0 (H57~H50): P57~P50 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.1.71 Bank 1 RF P6HDSCR (Port 6 High Drive/Sink Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H67
R/W
H66
R/W
H65
R/W
H64
R/W
H63
R/W
H62
R/W
H61
R/W
H60
R/W
Bits 7~0 (H67~H60): P67~P60 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.1.72 Bank 1 R10 P789AHDSCR (Port 7~A High Drive/Sink
Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAHHDS PALHDS P9HHDS P9LHDS P8HHDS P8LHDS P7HHDS P7LHDS
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 (PAHHDS): Control bit used to enable high drive/sink of Port A high nibble
(PA7~PA4) pin
Bit 6 (PALHDS): Control bit used to enable high drive/sink of Port A low nibble
(PA3~PA0) pin
Bit 5 (P9HHDS): Control bit used to enable high drive/sink of Port 9 high nibble
(P97~P94) pin
Bit 4 (P9LHDS): Control bit used to enable high drive/sink of Port 9 low nibble
(P93~P90) pin
Bit 3 (P8HHDS): Control bit used to enable high drive/sink of Port 8 high nibble
(P87~P84) pin
Bit 2 (P8LHDS): Control bit used to enable high drive/sink of Port 8 low nibble
(P83~P80) pin
Bit 1 (P7HHDS): Control bit used to enable high drive/sink of Port 7 high nibble
(P77~P74) pin
Bit 0 (P7LHDS): Control bit used to enable high drive/sink of Port 7 low nibble
(P73~P72) pin
6.1.73 Bank 1 R11 P5ODCR (Port 5 Open-drain Control Register)
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
55
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD57
R/W
OD56
R/W
OD55
R/W
OD54
R/W
OD53
R/W
OD52
R/W
OD51
R/W
OD50
R/W
Bits 7~0 (OD57~OD50): P57~P50 Open-drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.74 Bank 1 R12 P6ODCR (Port 6 Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
R/W
OD66
R/W
OD65
R/W
OD64
R/W
OD63
R/W
OD62
R/W
OD61
R/W
OD60
R/W
Bits 7~0 (OD67~OD60): P67~P60 Open-drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.75 Bank 1 R13 P789AODCR (Ports 7~A Open-drain Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAHOD
R/W
PALOD
R/W
P9HOD
R/W
P9LOD
R/W
P8HOD
R/W
P8LOD
R/W
P7HOD
R/W
P7LOD
R/W
Bit 7 (PAHOD): Control bit used to enable open-drain of Port Ahigh nibble (PA7~PA4) pin
Bit 6 (PALOD): Control bit used to enable open-drain of Port Alow nibble (PA3~PA0) pin
Bit 5 (P9HOD): Control bit used to enable open-drain of Port 9 high nibble (P97~P94) pin
Bit 4 (P9LOD): Control bit used to enable open-drain of Port 9 low nibble (P93~P90) pin
Bit 3 (P8HOD): Control bit used to enable open-drain of Port 8 high nibble (P87~P84) pin
Bit 2 (P8LOD): Control bit used to enable open-drain of Port 8 low nibble (P83~P80) pin
Bit 1 (P7HOD): Control bit used to enable open-drain of Port 7 high nibble (P77~P74) pin
Bit 0 (P7LOD): Control bit used to enable open-drain of Port 7 low nibble (P73~P72) pin
56
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.76 Bank 1 R33 URCR (UART Control Register)
Bit 7
UINVEN UMODE1 UMODE0 BRATE2 BRATE1 BRATE0
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UTBE
R
TXE
R/W
Bit 7 (UINVEN): Enable UART TXD and RXD Port Inverse Output Bit
0: Disable TXD and RXD port inverse output.
1: Enable TXD and RXD port inverse output.
Bits 6~5 (UMODE1~UMODE0): UART mode select bits
UMODE1
UMODE0
UART Mode
7-bit
0
0
1
1
0
1
0
1
8-bit
9-bit
Reserved
Bits 4~2 (BRATE2~BRATE0): Transmit Baud rate select
BRATE2
BRATE1
BRATE0
Baud Rate
Fc/13
8 MHz
38400
19200
9600
4800
2400
1200
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fc/26
Fc/52
Fc/104
Fc/208
Fc/416
TC3
Reserved
Bit 1 (UTBE): UART transfer buffer empty flag. Set to “1” when transfer buffer is empty.
Reset to “0” automatically when writing to the URTD register. The UTBE bit will be
cleared by hardware when enabling transmission. The UTBE bit is read-only.
Therefore, writing to the URTD register is necessary in starting transmission shifting.
Bit 0 (TXE): Enable transmission
0: Disable
1: Enable
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
57
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.77 Bank 1 R34 URS (UART Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD8
W
EVEN
R/W
PRE
R/W
PRERR
R/W
OVERR
R/W
FMERR
R/W
URBF
R
RXE
R/W
Bit 7 (URTD8): UART Transmit Data Bit 8. Write only.
Bit 6 (EVEN): Select parity check
0: Odd parity
1: Even parity
Bit 5 (PRE): Enable parity addition
0: Disable
1: Enable
Bit 4 (PRERR): Parity error flag. Set to 1 when parity error occurred, clear to 0 by
software.
Bit 3 (OVERR): Over running error flag. Set to 1 when overrun error occurred, clear to
0 by software.
Bit 2 (FMERR): Framing error flag. Set to 1 when framing error occurred, clear to 0 by
software.
Bit 1 (URBF): UART read buffer full flag. Set to 1 when one character is received.
Reset to 0 automatically when read from the URS register. URBF will
be cleared by hardware when enabling receiving. The URBF bit is
read-only. Therefore, reading the URS register is necessary to avoid
overrun error.
Bit 0 (RXE): Enable receiving
0: Disable
1: Enable
6.1.78 Bank 1 R35 URTD (UART Transmit Data Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD7
W
URTD6
W
URTD5
W
URTD4
W
URTD3
W
URTD2
W
URTD1
W
URTD0
W
Bits 7~0 (URTD7~URTD0): UART transmit data buffer. Write only.
58
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.79 Bank 1 R36 URRDL (UART Receive Data Low Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
R
URRD6
R
URRD5
R
URRD4
R
URRD3
R
URRD2
R
URRD1
R
URRD0
R
Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only.
6.1.80 Bank 1 R37 URRDH (UART Receive Data High Buffer Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
R
Bit 7 (URRD8): UART Receive Data Bit 8. Read only.
Bits 6~0: Not used, set to “0” all the time.
6.1.81 Bank 1 R40 WCR (Watch Timer Control Register)
Bit 7
Bit 6
WTSSB1 WTSSB0
R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WTE
R/W
Bit 7 (WTE): Watch Timer Enable Bit
0: Disable
1: Enable
Bits 6~5 (WTSSB1~ WTSSB0): Watch Timer Interval Select Bits
Timer Interval Select
(LXT2=32.768kHz)
WTSSB1 WTSSB0
Timer Interval Select
0
0
1
1
0
1
0
1
32768/Fs
16384/Fs
8192/Fs
128/Fs
1.0s
0.5s
0.25s
3.91ms
Bits 4~0: Not used, set to “0” all the time.
6.1.82 Bank 1 R45 TBPTL (Table Pointer Low Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TB7
R/W
TB6
R/W
TB5
R/W
TB4
R/W
TB3
R/W
TB2
R/W
TB1
R/W
TB0
R/W
Bits 7~0 (TB7~TB0): Table Pointer Address Bits 7~0.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
59
EM78P528N
8-Bit Microprocessor with OTP ROM
6.1.83 Bank 1 R46 TBPTH (Table Pointer High Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLB
R/W
GP1
R/W
GP0
R/W
TB12
R/W
TB11
R/W
TB10
R/W
TB9
R/W
TB8
R/W
Bit 7 (HLB): Take MLB or LSB at machine code
Bits 6~5 (GP1~GP0): General Purpose read/write bits
Bits 4~0 (TB12~TB8): Table Pointer Address Bits 12~8.
6.1.84 Bank 1 R47 STKMON (Stack Monitor)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STOV
R
STL3
R
STL2
R
STL1
R
STL0
R
Bit 7 (STOV): Stack pointer overflow indication bit. Read only.
Bits 6~4: Not used, set to “0” all the time.
Bits 3~0 (STL3~ STL0): Stack pointer number. Read only.
6.1.85 Bank 1 R48 PCH (Program Counter High)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC12
R/W
PC11
R/W
PC10
R/W
PC9
R/W
PC8
R/W
Bits 7~5: Not used, set to “0” all the time.
Bits 4~0 (PC12~PC8): Program Counter high byte.
6.1.86 Bank 1 R49 LVDCR (Low Voltage Detector Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDEN
R/W
LVDS2
R/W
LVDS1
R/W
LVDS0
R/W
LVDB
R
Bit 7 (LVDEN): Low Voltage Detector Enable Bit
0: Disable low voltage detector
1: Enable low voltage detector
60
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 6~4 (LVDS2~LVDS0): Low Voltage Detector Level Bits
LVDEN
LVDS2~0
LVD Voltage Interrupt Level
VDD < 2.2V
VDD > 2.2V
VDD < 3.3V
VDD > 3.3V
VDD < 4.0V
VDD > 4.0V
VDD < 4.5V
VDD > 4.5V
NA
LVDB
0
1
0
1
0
1
0
1
1
1
011
1
1
010
001
1
0
000
XX
Bit 3 (LVDB): Low Voltage Detector State Bit. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by LVDS2
~ LVDS0), this bit will be cleared.
0: Low voltage is detected.
1: Low voltage is not detected or LVD function is disabled.
Bits 2~0: Not used, set to “0” all the time.
6.1.87 Bank 1 R4A~R4C: (Reserve)
6.1.88 Bank 0 R50~R7F, Bank 0~3 R80~RFF
All of these are 8-bit general-purpose registers.
6.2 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT
respectively. The TPSR0~ TPSR2 bits of the TCCCR register (Bank 0 R22) are used to
determine the ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the
WDTCR register (Bank 0 R21) are used to determine the prescaler of WDT. The
prescaler counter will be cleared by the instructions each time they are written into
TCC. The WDT and prescaler counter will be cleared by the “WDTC” and “SLEP”
instructions. Figure 6-3 depicts the Block Diagram of TCC/WDT.
The clock source of TCC can be internal clock or external signal input (edge selectable
from the TCC pin). If the TCC signal source is from an internal clock, the TCC will be
incremented by 1 at Fc clock (without prescaler). If the TCC signal source is from an
external clock input, the TCC will be incremented by 1 at every falling edge or rising
edge of the TCC pin. The TCC pin input time length (kept in High or low level) must be
greater than 1/Fc. The TCC will stop running when sleep mode occurs.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
61
EM78P528N
8-Bit Microprocessor with OTP ROM
The Watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e. in sleep mode). During
normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to
reset. The WDT can be enabled or disabled at any time during normal mode by
software programming. Refer to WDTE bit of WDTCR (Bank 0 R21) register. With no
prescaler, the WDT time-out period is approximately 16 ms1 (one oscillator start-up
timer period).
0
8 Bit Counter
Data Bus
Fc (Fm/Fs)
MUX
1
TCC Pin
TE (R22)
8 to 1 MUX
Prescaler
TCC(R23)
TCC overflow
interrupt
TS (R22)
TPSR2~TPSR0
(R22)
8 Bit Counter
WDT
8 to 1 MUX
Prescaler
WDTE (R21)
WDT time out
WPSR2~WPSR0
(R21)
Figure 6-3 TCC and WDT Block Diagram
6.3 I/O Ports
The I/O registers, Port 5~Port A are bidirectional tri-state I/O ports. All can be
pulled-high and pulled-low internally by software. In addition, they can also have
open-drain output and high sink/drive setting by software. Ports 5~8 have wake up and
interrupt function. Furthermore, Ports 5~8 also have input status change interrupt
function. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOCA).
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 ~ Port A are shown in Figures 6-4 ~ 6-7.
1
VDD=2.1~5.5V, Temp= -40C~85C, WDT Time-out period = 16ms ± 10%.
62
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
R
IOD
PORT
Q
D
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-4 Circuit of I/O Port and I/O Control Register for Port 9~A
PCRD
P
R
Q
D
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
0
1
P
D
R
Q
M
U
X
_
Q
CLK
C
L
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-5 Circuit of I/O Port and I/O Control Register for /INT
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
63
EM78P528N
8-Bit Microprocessor with OTP ROM
PCRD
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
P61~P67
PORT
IOD
P
R
Q
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-6 Circuit of I/O Port and I/O Control Register for Ports 5~8
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.
1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-7 Block Diagram of I/O Port 5~8 with Input Change Interrupt/Wake-up
64
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Table 1 Usage of Ports 5~8 Input Changed Wake-up/Interrupt Function
Usage of Ports 5~8 Input Status Changed Wake-up/Interrupt
(II) Wake-up and interrupt
(I) Wake-up
(a) Before Sleep
1. Disable WDT
(a) Before Sleep
1. Disable WDT
2. Read I/O Port (MOV R6,R6)
3. Execute "ENI" or "DISI"
2. Read I/O Port (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set WUE6H=1, WUE6L=1)
5. Execute "SLEP" instruction
(b) After wake-up
4. Enable wake-up bit (Set WUE6H=1, WUE6L=1)
5. Enable interrupt (Set ICIE =1)
6. Execute "SLEP" instruction
(b) After wake-up
Next instruction
1. IF "ENI" Interrupt vector (0006H)
2. IF "DISI" Next instruction
6.4 Reset and Wake-up
6.4.1 Reset
A reset is initiated by one of the following events-
(1) Power-on reset
(2) /RESET pin input "low"
(3) WDT time-out (if enabled)
(4) LVR (if enabled)
The device is kept in a reset condition for a period of approx. 16ms2 (one oscillator
start-up timer period) after the reset is detected. If the /Reset pin goes “low” or WDT
time-out is active, a reset is generated, in IRC mode the reset time is WSTO and 8
clocks, High XTAL mode reset time is WSTO and 510 clocks. In low XTAL mode, the
reset time is WSTO and 510 clocks (Fsub). Once a reset occurs, the following functions
are performed. Refer to Figure 6-8.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
The control register bits are set according to the entries shown in Table 2 Summary
of Register Initial Values after Reset.
2 VDD=2.1~5.5V, Temp=-40C~85C, WDT time-out period = 16ms ± 10%.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
65
EM78P528N
8-Bit Microprocessor with OTP ROM
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. After wake-up
is generated, in IRC mode the wake-up time is WSTO and 8 clocks, High XTAL mode
wake-up time is WSTO and 510 clocks. In low XTAL mode, the wake-up time is WSTO
and 510 clocks (Fsub). The controller can be awakened by :
(1) External reset input on /RESET pin.
(2) WDT time-out (if enabled).
(3) External (/INT) pin changes (if INTWKX is enabled).
(4) Port input status changes (if ICWKPX is enabled).
(5) SPI received data when SPI acts as a Slave device (if SPIWK is enabled).
(6) I2C received data when I2C acts as a Slave device (if I2CWK is enabled).
(7) Low Voltage Detector (if LVDWK enable).
(8) A/D conversion completed (if ADWK is enabled).
The first two cases will cause the EM78P528N to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). Case 3~8 are considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the Address 0X02~0X38 by each interrupt vector after wake-up. If DISI is
executed before SLEP, the execution will restart from the instruction right next to SLEP
after wake-up.
Only one of Cases 3 to 8 can be enabled before entering into sleep mode. That is,
[a] If WDT is enabled before SLEP, the EM78P528N can be waken-up only by Case 1
or Case 2. For further details refer to Section 6.5, Interrupt.
[b] If the External (INT9~0) pin change is used to wake-up the EM78P528N and the
INTWKX bit is enabled before SLEP, WDT must be disabled. Hence, the
EM78P528N can be waken-up only by Case 3.
[c] If Port Input Status Change is used to wake-up the EM78P528N and the
corresponding wake-up setting is enabled before SLEP, WDT must be disabled.
Hence, the EM78P528N can be waken-up only by Case 4.
[d] When SPI acts as Slave device, after receiving data the EM78P528N will wake-up
and the SPIWK bit of Bank 0 R11 register is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P528N can be waken-up only by Case 5.
66
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
[e] When I2C acts as Slave device, after receiving data, the EM78P528N will wake-up
and the I2CWK bit of Bank 0 R11 register is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P528N can be waken-up only by Case 6.
[f] If Low voltage detector is used to wake-up the EM78P528N and the LVDWK bit of
Bank 0 R10 register is enabled before SLEP, WDT must be disabled by software.
Hence, the EM78P528N can be wake-up only by Case 7.
[g] If AD conversion completed is used to wake-up the EM78P528N and the ADWK bit
of Bank 0 R10 register is enabled before SLEP, WDT must be disabled by software.
Hence, the EM78P528N can be waken-up only by Case 8.
Table 2 All kinds of Wake-up modes and Interrupt modes are shown below:
Sleep Mode
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
Wake-up
Signal
Condition
Signal
DISI
ENI
DISI
ENI
TCIE=0
TCIE=1
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
TCC
(Used as
Timer)
Wake up Wake up
Wake-up is invalid
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
TCIE=0
Wake-up is invalid
Wake-up is invalid
TCC
Wake up Wake up Wake up Wake up
(Used as
Counter)
+
Next
+
+
Next
+
Next
+
Next
+
TCIE=1
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
TC1/2/3IE=0
TC1/2/3IE=1
TC1/2/3IE=0
TC1/2/3IE=1
WTIE=0
Wake-up is invalid
TC1/2/3
Interrupt
(Used as
Timer)
Wake up Wake up
Wake-up is invalid
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake-up is invalid
Wake-up is invalid
TC1/2/3
Interrupt
(Used as
Counter)
Wake up Wake up Wake up Wake up
+
+
+
Next
+
Next
+
Next
+
Next
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
Wake-up is invalid.
Watch
Timer
Wake up
Wake-up is invalid
+
Next
+
Next
+
WTIE=1
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector Vector
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
67
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Sleep Mode
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
DISI
ENI
INTWKx = 0,
EXIEx = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt is invalid
Interrupt +
Next
Interrupt +
Next
INTWKx = 0,
EXIEx = 1
Wake-up is invalid
Interrupt
Interrupt
Instruction
Vector
Instruction
Vector
External
INT
INTWKx = 1,
EXIEx = 0
Wake up +
Next Instruction
Wake up +
Next Instruction
Interrupt is invalid
Interrupt is invalid
Wake up Wake up Wake up Wake up
Interrupt
Interrupt
INTWKx = 1,
EXIEx = 1
+
Next
+
+
Next
+
Next
+
Next
+
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ICWKPx = 0,
PxICIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
ICWKPx = 0,
PxICIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Pin change
Wake up
+
Next Instruction
Wake up
+
Next Instruction
ICWKPx = 1,
PxICIE = 0
Wake up Wake up Wake up Wake up
ICWKPx = 1,
PxICIE = 1
+
Next
+
+
Next
+
Next
+
Next
+
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ADWK = 0,
ADIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
ADWK = 0,
ADIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
AD
Conversion
complete
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ADWK = 1,
ADIE = 0
Wake up +
Next Instruction
Wake up +
Next Instruction
Wake up Wake up Wake up Wake up
ADWK = 1,
ADIE = 1
+
Next
+
+
Next
+
Next
+
Next
+
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
SPIWK = 0,
SPIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
SPIWK = 0,
SPIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
SPI
(Slave
mode)
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
SPIWK = 1,
SPIE = 0
Wake up +
Next Instruction
Wake up +
Next Instruction
Wake up Wake up Wake up Wake up
SPIWK = 1,
SPIE = 1
+
Next
+
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector
+
Next
+
Interrupt
Instruction Vector Instruction Vector
68
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Sleep Mode
DISI ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
I2CWK=0
I2CRIE=0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
I2CWK=0
I2CRIE=1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
I2C
(Slave
mode)
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake up
+
Next Instruction
Wake up
+
Next Instruction
I2CWK=1
I2CRIE=0
Wake up Wake up Wake up Wake up
I2CWK=1
I2CRIE=1
+
+
+
+
Next
+
Next
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
UTIE = 0
UTIE = 1
UART
Transmit
complete
Interrupt
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
URIE = 0
UART
Receive
data
Buffer full
Interrupt
Next
+
Next
+
URIE = 1
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
UERRIE = 0
UERRIE = 1
UART
Receive
Error
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
LVDWK = 0,
LVDIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
LVDWK = 0,
LVDIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Low
Voltage
Detector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake up
+
Next Instruction
Wake up
+
Next Instruction
LVDWK = 1,
LVDIE = 0
Wake up Wake up Wake up Wake up
LVDWK = 1,
LVDIE = 1
+
Next
+
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector
+
Next
+
Interrupt
Instruction Vector Instruction Vector
Low
Voltage
Reset
Wake up + Reset
Wake up + Reset
Wake up + Reset
Wake up + Reset
Reset
Reset
Reset
WDT
Timeout
Reset
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
69
EM78P528N
8-Bit Microprocessor with OTP ROM
6.4.2 Status of RST, T, and P of the Status Register
A reset condition is initiated by the following events:
1. Power-on condition,
2. High-low-high pulse on /RESET pin
3. Watchdog timer time-out
4. When LVR occurs
The values of T and P, listed in Table 4 are used to check how the processor wakes up.
Table 4 shows the events that may affect the status of T and P.
Table 4 Values of RST, T and P after reset
Reset Type
T
1
P
1
Power on
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
*P
1
0
0
1
*P
0
*P
0
0
*P: Previous status before reset
Table 5 Status of T and P Being Affected by Events
Event
T
1
1
0
1
1
P
1
Power on
WDTC instruction
1
WDT time-out
*P
0
SLEP instruction
Wake-up on pin change during Sleep mode
0
*P: Previous value before reset
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-On Reset
Low Voltage Reset
Setup time
WDTE
WDT
WDT Timeout
Reset
/RESET
Figure 6-8 Block Diagram of Controller Reset
70
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Table 3 Summary of Register Initial Values after Reset
Legend: U: Unknown or don’t care
C: Same with Code option
P: Previous value before reset
t: Check Table 4
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bank 0/1
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0x00
0x01
0x02
0x03
0x04
0X05
R0
/RESET and WDT
IAR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
-
-
-
SBS0
-
-
GBS1 GBS0
Bank 0/1
R1
Power-on
U
U
U
U
U
U
0
0
U
U
U
U
0
0
0
0
/RESET and WDT
BSR
Wake-up from
Sleep/Idle
U
U
U
P
U
U
P
P
Bit Name
PC7
0
PC6
0
PC5
0
PC4
0
PC3
0
PC2
0
PC1
0
PC0
0
Bank 0/1
R2
Power-on
/RESET and WDT
0
0
0
0
0
0
0
0
PCL
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
INT
0
-
-
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Bank 0/1
R3
Power-on
U
U
U
U
/RESET and WDT
0
P
SR
Wake-up from
Sleep/Idle
P
U
U
t
t
P
P
P
Bit Name
RSR7 RSR6 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
1
1
1
1
1
1
1
1
Bank 0/1
R4
Power-on
P
P
P
P
P
P
P
P
/RESET and WDT
RSR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
P57
0
P56
0
P55
0
P54
0
P53
0
P52
0
P51
0
P50
0
Bank 0
R5
Power-on
/RESET and WDT
0
0
0
0
0
0
0
0
Port 5
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
71
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
P67
0
Bit 6
P66
0
Bit 5
P65
0
Bit 4
P64
0
Bit 3
P63
0
Bit 2
P62
0
Bit 1
P61
0
Bit 0
P60
0
Power-on
Bank 0
0x06
0x07
0x08
0x09
0x0A
0X0B
0x0C
R6
/RESET and WDT
0
0
0
0
0
0
0
0
Port 6
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
P77
0
P76
0
P75
0
P74
0
P73
0
P72
0
-
-
Power-on
U
U
U
U
Bank 0
R7
/RESET and WDT
0
0
0
0
0
0
Port 7
Wake-up from
Sleep/Idle
P
P
P
P
P
P
U
U
Bit Name
P87
0
P86
0
P85
0
P84
0
P83
0
P82
0
P81
0
P80
0
Power-on
Bank 0
R8
/RESET and WDT
0
0
0
0
0
0
0
0
Port 8
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
P97
0
P96
0
P95
0
P94
0
P93
0
P92
0
P91
0
P90
0
Power-on
Bank 0
R9
/RESET and WDT
0
0
0
0
0
0
0
0
Port 9
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
PA6
0
PA5
0
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
Bit Name
-
Power-on
U
U
Bank 0
RA
0
0
0
0
0
0
0
/RESET and WDT
PortA
Wake-up from
Sleep/Idle
P
P
P
P
U
P
P
P
IOC56
IOC54
IOC52
IOC50
Bit Name
IOC57
IOC55
IOC53
IOC51
1
1
1
1
1
1
1
1
Power-on
1
1
1
1
1
1
1
1
Bank 0
RB
/RESET and WDT
IOCR5
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
Bit Name
IOC67
1
1
1
1
1
1
1
1
Power-on
1
1
1
1
1
1
1
1
Bank 0
RC
/RESET and WDT
IOCR6
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
72
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
IOC77
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC76 IOC75 IOC74 IOC73 IOC72
-
-
1
1
1
1
1
1
U
U
Power-on
1
1
1
1
U
U
Bank 0
0X0D
0x0E
0x0F
0x10
0x11
RD
/RESET and WDT
1
IOCR7
Wake-up from
Sleep/Idle
P
P
P
P
P
U
U
P
-
-
-
-
Bit Name
CPUS
IDLE
RCM1 RCM0
U
U
U
U
Power-on
1
1
1
1
U
U
U
U
C
C
C
C
Bank 0
RE
/RESET and WDT
OMCR
Wake-up from
Sleep/Idle
U
U
U
U
P
P
P
P
-
-
Bit Name
EIES98 EIES76 EIES54 EIES32 EIES1 EIES0
1
1
1
1
1
1
U
U
Power-on
1
1
1
1
1
1
U
U
Bank 0
RF
/RESET and WDT
EIESCR
Wake-up from
Sleep/Idle
P
P
P
U
U
P
P
P
-
-
-
-
Bit Name
LVDWK ADWK INTWK1 INTWK0
U
U
0
0
0
0
U
U
Power-on
U
U
0
0
0
0
U
U
Bank 0
R10
/RESET and WDT
WUCR1
Wake-up from
Sleep/Idle
U
U
P
P
U
U
P
P
Bit Name
SPIWK I2CWK
-
-
-
-
-
-
U
U
U
U
U
U
Power-on
U
U
U
U
0
0
0
0
U
U
Bank 0
R11
/RESET and WDT
WUCR2
Wake-up from
Sleep/Idle
U
U
U
U
U
U
P
P
INTWK INTWK INTWK INTWK
Bit Name
ICWKP8 ICWKP7 ICWKP6 ICWKP5
98
76
54
32
Bank 0
R12
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0x12
0X14
/RESET and WDT
0
0
0
0
WUCR3
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
Bit Name
LVDSF ADSF EXSF1 EXSF0 WTSF TCSF
U
U
Power-on
U
U
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R14
/RESET and WDT
SFR1
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
73
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
UERRSF URSF UTSF TC3SF TC2SF TC1SF
U
U
Power-on
U
U
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
0X15
0X17
0X18
0X1B
0X1C
0X1E
0X1F
R15
/RESET and WDT
SFR2
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Bit Name
SPISF I2CSTPSF I2CRSF I2CTSF
P8ICSF P7ICSF P6ICSF P5ICSF
U
U
U
U
Power-on
U
U
U
U
0
0
0
0
0
0
0
0
Bank 0
R17
/RESET and WDT
SFR4
Wake-up from
Sleep/Idle
U
U
U
U
P
P
P
P
Bit Name
EXSF9 EXSF8 EXSF7 EXSF6 EXSF5 EXSF4 EXSF3 EXSF2
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R18
/RESET and WDT
SFR5
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
Bit Name
LVDIE
ADIE
EXIE1
EXIE0
WTIE TCIE
U
U
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
U
U
Bank 0
R1B
/RESET and WDT
IMR1
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
-
-
Bit Name
UERRSF URIE
UTIE
TC3IE TC2IE TC1IE
U
U
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
U
U
Bank 0
R1C
/RESET and WDT
IMR2
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Bit Name
SPIIE I2CSTPIE I2CRIE I2CTIE
P8ICIE P7ICIE P6ICIE P5ICIE
U
U
U
U
0
0
0
0
0
0
0
0
Power-on
U
U
U
U
Bank 0
R1E
/RESET and WDT
IMR4
Wake-up from
Sleep/Idle
U
U
U
U
P
P
P
P
Bit Name
EXIE9 EXIE8 EXIE7 EXIE6 EXIE5
EXIE4 EXIE3 EXIE2
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0
R1F
/RESET and WDT
IMR5
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
74
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
WDTE
PSWE WPSR2 WPSR1 WPSR0
U
U
0
0
Power-on
0
0
U
U
U
U
0
0
0
0
0
0
Bank 0
0X21
0X22
0X23
0X24
0X25
0X26
0X27
R21
/RESET and WDT
WDTCR
Wake-up from
Sleep/Idle
U
U
U
P
P
P
P
P
-
Bit Name
TCCS
TS
0
TE
0
PSTE TPSR2 TPSR1 TPSR0
U
U
0
0
Power-on
0
0
0
0
0
0
0
0
Bank 0
R22
/RESET and WDT
0
0
TCCR
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
TCC0
Bit Name
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R23
/RESET and WDT
TCCD
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1S TC1RC TC1SS1 TC1MOD TC1FF TC1OMS TC1IS1 TC1IS0
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R24
/RESET and WDT
TC1CR1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R25
/RESET and WDT
TC1CR2
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R26
/RESET and WDT
TC1DA
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R27
/RESET and WDT
TC1DB
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
75
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TC2S TC2RC TC2SS1
TC2FF TC2OMS TC2IS1 TC2IS0
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
0X28
0X29
0X2A
0X2B
0X2C
0X2D
0X2E
R28
/RESET and WDT
TC2CR1
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
Bit Name
TC2M2 TC2M1 TC2M0 TC2SS0 TC2CK3 TC2CK2 TC2CK1 TC2CK0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R29
/RESET and WDT
TC2CR2
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1 TC2DA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R2A
/RESET and WDT
TC2DA
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1 TC2DB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R2B
/RESET and WDT
TC2DB
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
Bit Name
TC3S TC3RC TC3SS1
TC3FF TC3OMS TC3IS1 TC3IS0
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R2C
/RESET and WDT
TC3CR1
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
Bit Name
TC3M2 TC3M1 TC3M0 TC3SS0 TC3CK3 TC3CK2 TC3CK1 TC3CK0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R2D
/RESET and WDT
TC3CR2
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R2E
/RESET and WDT
TC3DA
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
76
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
0X2F
0X30
R2F
/RESET and WDT
TC3DB
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Strobe/
Pend
SAR_
EMPTY
Bit Name
IMS
ISS
STOP
ACK
FULL EMPTY
Bank 0
R30
I2CCR1
Power-on
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
I2CBF GCEN
BBF
0
I2CTS1 I2CTS0
I2CEN
-
-
Bit Name
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0
R31
I2CCR2
0X31
0X32
0X33
0X34
0X35
/RESET and WDT
0
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Bit Name
SA6
0
SA5
0
SA4
0
SA3
0
SA2
0
SA1
0
SA0
0
IRW
0
Power-on
Bank 0
R32
I2CSA
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
Power-on
Bank 0
R33
I2CDB
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
DA7
1
DA6
1
DA5
1
DA4
1
DA3
1
DA2
1
DA1
1
DA0
1
Power-on
Bank 0
R34
I2CDAL
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
-
-
-
-
Bit Name
DA9
1
DA8
1
U
U
U
U
U
U
U
U
U
U
U
U
Power-on
Bank 0
R35
/RESET and WDT
1
1
I2CDAH
Wake-up from
Sleep/Idle
U
U
U
U
U
U
P
P
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
77
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
CES
0
Bit 6
SPIE
0
Bit 5
SRO
0
Bit 4
SSE
0
Bit 3
Bit 2
Bit 1
Bit 0
SDOC SBRS2 SBRS1 SBRS0
Power-on
0
0
0
0
0
0
0
0
Bank 0
0X36
0X37
0X38
0X39
0X3E
0X3F
0X40
R36
/RESET and WDT
0
0
0
0
SPICR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
Bit Name
DORD
TD1
0
TD0
0
OD3
OD4
RBF
0
U
U
U
U
Power-on
0
0
0
0
0
0
Bank 0
R37
/RESET and WDT
0
0
0
SPIS
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Bit Name
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 0
R38
/RESET and WDT
SPIR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 0
R39
/RESET and WDT
SPIW
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
CKR2
CKR1
CKR0 ADRUN ADP
ADOM SHS1
SHS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R3E
/RESET and WDT
ADCR1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
-
Bit Name
ADIM ADCMS VPIS1 VPIS0 VREFP
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0
R3F
/RESET and WDT
ADCR2
Wake-up from
Sleep/Idle
U
U
U
P
P
P
P
P
-
-
-
Bit Name
ADIS4 ADIS3 ADIS2 ADIS1 ADIS0
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0
R40
/RESET and WDT
ADISR
Wake-up from
Sleep/Idle
U
U
U
P
P
P
P
P
78
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
ADE7
0
Bit 6
ADE6
0
Bit 5
ADE5
0
Bit 4
ADE4
0
Bit 3
ADE3
0
Bit 2
ADE2
0
Bit 1
ADE1
0
Bit 0
ADE0
0
Power-on
Bank 0
0X41
0X42
0X43
0X44
0X45
0X46
0X48
R41
/RESET and WDT
0
0
0
0
0
0
0
0
ADER1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
Bit Name
ADE14 ADE13 ADE12 ADE11 ADE10 ADE9
ADE8
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R42
/RESET and WDT
ADER2
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
Bit Name
ADD7
U
ADD6
U
ADD5
U
ADD4
U
ADD3
U
ADD2
U
ADD1
U
ADD0
U
Power-on
Bank 0
R43
/RESET and WDT
U
U
U
U
U
U
U
U
ADDL
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9
ADD8
U
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Bank 0
R44
/RESET and WDT
U
ADDH
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R45
/RESET and WDT
ADCVL
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
ADCV15 ADCV14 ADCV13 ADCV12 ADCV11 ADCV10 ADCV9 ADCV8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R46
/RESET and WDT
ADCVH
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
Bit Name
LCDEN LCDTYPE
BS
0
DS1
0
DS0
0
LCDF1 LCDF0
U
U
Power-on
0
0
0
0
0
0
0
0
Bank 0
R48
/RESET and WDT
0
0
0
LCDCR1
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
79
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
RBS1
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
RBS0 DYMEN
-
-
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
Bank 0
0X49
0X4A
0X4B
0X4C
0X4D
0X4E
0X4F
R49
/RESET and WDT
0
LCDCR2
Wake-up from
Sleep/Idle
U
U
U
P
P
P
P
P
-
-
-
-
-
Bit Name
LCDCC2 LCDCC1 LCDCC0
U
U
U
U
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
Bank 0
R4A
/RESET and WDT
LCDCR3
Wake-up from
Sleep/Idle
U
U
U
U
U
P
P
P
-
-
-
Bit Name
LCDA4 LCDA3 LCDA2 LCDA1 LCDA0
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0
R4B
/RESET and WDT
LCDADDR
Wake-Up from
Sleep/Idle
U
U
U
P
P
P
P
P
Bit Name
LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 0
R4C
/RESET and WDT
LCDCDB
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
Bit Name
LCDSM2 LCDSM1 LCDSM0
LCDCM2 LCDCM1 LCDCM0
U
U
U
U
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R4D
/RESET and WDT
LCDSCR0
Wake-up from
Sleep/Idle
U
U
P
P
P
P
P
P
Bit Name
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R4E
/RESET and WDT
LCDSCR1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0
R47
/RESET and WDT
LCDSCR2
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
80
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
0X05
0X06
0X07
0X08
0X09
0X0A
0X0B
R5
/RESET and WDT
IOCR8
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
R6
/RESET and WDT
IOCR9
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
-
IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
Power-on
U
U
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
R7
/RESET and WDT
IOCRA
Wake-up from
Sleep/Idle
U
P
P
P
P
P
P
P
Bit Name
PH57
PH56
PH55
PH54
PH53
PH52
PH51
PH50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
R8
/RESET and WDT
P5PHCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
PH67
PH66
PH65
PH64
PH63
PH62
PH61
PH60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
R9
/RESET and WDT
P6PHCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
PAHPH PALPH P9HPH P9LPH P8HPH P8LPH P7HPH P7LPH
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
RA
/RESET and WDT
P789APHCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
PL57
PL56
PL55
PL54
PL53
PL52
PL51
PL50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1
RB
/RESET and WDT
P5PLCR
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
81
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
PL67
1
Bit 6
PL66
1
Bit 5
PL65
1
Bit 4
PL64
1
Bit 3
PL63
1
Bit 2
PL62
1
Bit 1
PL61
1
Bit 0
PL60
1
Bank 1
Power-on
0X0C
0X0D
0X0E
0X0F
0X10
0X11
0X12
RC
/RESET and WDT
1
1
1
1
1
1
1
1
P6PLCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
PAHPL PALPL P9HPL P9LPL P8HPL P8LPL P7HPL P7LPL
Bank 1
RD
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P789APLCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
HDS57 HDS56 HDS55 HDS54 HDS53 HDS52 HDS51 HDS50
Bank 1
RE
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P5HDSCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
HDS67 HDS66 HDS65 HDS64 HDS63 HDS62 HDS61 HDS60
Bank 1
RF
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P6HDSCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
PAHHDS PALHDS P9HHDS P9LHDS P8HHDS P8LHDS P7HHDS P7LHDS
Bank 1
R10
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P789AHDSCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
OD57 OD56
OD55 OD54 OD53 OD52 OD51 OD50
Bank 1
R11
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P5ODCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
OD67 OD66
OD65 OD64 OD63 OD62 OD61 OD60
Bank 1
R2
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P6ODCR
Wake-up from
P
P
P
P
P
P
P
P
Sleep/Idle
82
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAHOD PALOD P9HOD P9LOD P8HOD P8LOD P7HOD P7LOD
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
0X13
0X33
0X34
0X35
0X36
0X37
0X40
R13
/RESET and WDT
P789AODCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
UINVEN UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
TXE
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bank 1
R33
/RESET and WDT
0
URCR
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
URTD8 EVEN
PRE PRERR OVERR FMERR URBF
RXE
Power-on
U
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1
R34
/RESET and WDT
URS
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 1
R35
/RESET and WDT
URTD
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 1
R36
/RESET and WDT
URRDL
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
Bit Name
URRD8
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Power-on
U
P
Bank 1
R37
/RESET and WDT
URRDH
Wake-up from
Sleep/Idle
U
U
U
U
U
U
U
P
-
-
-
-
-
Bit Name
WTE WTSSB1 WTSSB0
U
U
U
U
U
U
U
U
U
U
Power-on
0
0
0
0
0
0
Bank 1
R40
/RESET and WDT
WCR
Wake-up from
Sleep/Idle
U
U
U
U
U
P
P
P
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
83
EM78P528N
8-Bit Microprocessor with OTP ROM
(Continuation)
Address Bank Name
Reset Type
Bit Name
Bit 7
TB7
0
Bit 6
TB6
0
Bit 5
TB5
0
Bit 4
TB4
0
Bit 3
TB3
0
Bit 2
TB2
0
Bit 1
TB1
0
Bit 0
TB0
0
Power-on
Bank 1
0X45
0X46
0X47
0X48
0X49
R45
/RESET and WDT
0
0
0
0
0
0
0
0
TBPTL
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
HLB
0
GP1
0
GP0
0
TB12
TB11
TB10
TB9
0
TB8
0
Power-on
0
0
0
0
0
0
Bank 1
R46
/RESET and WDT
0
0
0
0
0
TBPTH
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
STOV
-
-
-
STL3
STL2
STL1
STL0
Power-on
0
0
U
U
U
U
U
U
0
0
0
0
0
0
0
0
Bank 1
R47
/RESET and WDT
STKMON
Wake-up from
Sleep/Idle
P
U
U
U
P
P
P
P
Bit Name
-
-
-
PC12
PC11
PC10
PC9
0
PC8
0
Power-on
U
U
U
U
U
U
0
0
0
0
0
0
Bank 1
R48
/RESET and WDT
0
0
PCH
Wake-up from
Sleep/Idle
U
U
U
P
P
P
P
P
Bit Name
LVDEN LVDS2 LVDS1 LVDS0 LVDB
-
-
-
Power-on
0
0
0
0
0
0
0
0
1
1
U
U
U
U
U
U
Bank 1
R49
/RESET and WDT
LVDCR
Wake-up from
P
P
P
P
P
U
U
U
Sleep/Idle
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0X50
~
0X7F
Bank 0
/RESET and WDT
R50~R7F
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0X80
~
0XFF
Bank 0~3
R80~RFF
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
84
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.5 Interrupt
The EM78P528N has 25 interrupts (11 external, 14 internal) as listed below:
Interrupt Source
Enable Condition
-
Int. Flag
-
Int. Vector Priority
Internal/External
Reset
INT
0
2
4
6
High 0
External
External
Internal
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
EXSF
ICSF
TCSF
1
2
3
Pin change
TCC
ENI+LVDEN &
LVDIE=1
Internal
LVD
LVDSF
8
4
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
SPI
AD
ENI + SPIIE=1
ENI + ADIE=1
ENI + TC1IE=1
ENI+ I2CTIE
SPISF
ADSF
C
5
6
10
12
1A
1C
1E
22
28
2E
30
32
38
TC1(TCXDA)
I2C Transmit
I2C Receive
I2CSTOP
TC1SF
I2CTSF
I2CRSF
I2CSTPSF
TC2SF
TC3SF
UERRSF
URSF
7
8
ENI+ I2CRIE
9
ENI+ I2CSTPIE
ENI + TC2IE=1
ENI + TC3IE=1
ENI+UERRIE=1
ENI + URIE=1
ENI + UTIE=1
ENI+WTIE=1
10
11
12
13
14
15
16
TC2(TCXDA)
TC3(TCXDA)
UART Receive error
UART Receive
UART Transmit
Watch timer
UTSF
WTSF
Bank 0 R14~R18 are the interrupt status registers that record the interrupt requests in
relative flags/bits. Bank 0 R1B~R1F is the Interrupt Mask register. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. When one of
the enabled interrupts occurs, the next instruction will be fetched from their individual
address. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICSF bit delete) in the Interrupt Status Register is set regardless of the
status of its mask bit or the execution of ENI. The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
External interrupt is equipped with digital noise rejection circuit (input pulse of less than
4 system clock time is eliminated as noise), but in Low XTAL oscillator (LXT)
mode, the noise rejection circuit is disabled. When an interrupt (Falling edge) is
generated by the External interrupt (when enabled), the next instruction will be fetched
from Address 0X02H.
Before the interrupt subroutine is executed, the contents of ACC, R3 (Bit 0~Bit 4) and R4
registers are saved by hardware. If another interrupt occurs, the ACC, R3 (Bit 0~Bit 4)
and R4 registers will be replaced by the new interrupt. After the interrupt service routine
is finished, ACC, R3 (Bit 0~Bit 4) and R4 are restored.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
85
EM78P528N
8-Bit Microprocessor with OTP ROM
VDD
PR
IRQn
.
.
D
Q
Q
/IRQn
INT
CLK
CL
RFRD
IRQm
ISR
ENI / DISI
PR
D
IOD
Q
Q
CLK
CL
IOCFWR
IMR
/RESET
IOCFRD
RFWR
Figure 6-9a Interrupt Input Circuit
Interrupt
occurs
Interrupt
sources
ACC
R1
STACKACC
ENI/DISI
STACKR1
STACKR3
STACKR4
R3 (bits 0~4)
R4
RETI
Figure 6-9b Interrupt Backup Diagram
86
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.6 A/D Converter
R_BANK Address Name
Bit 7
Bit 6
Bit 5
CKR0 ADRUN
R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKR2
CKR1
ADP
ADOM
SHS1
SHS0
R/W
-
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x10
0x15
0x1B
ADCR1
ADCR2
ADISR
ADER1
ADER2
ADDL
R/W
R/W
R/W
R/W
R/W
-
-
ADIM ADCMS VPIS1
VPIS0 VREFP
-
-
R/W
R/W
ADIS4
R/W
R/W
ADIS3
R/W
R/W
ADIS2
R/W
R/W
ADIS1
R/W
-
-
-
-
-
-
ADIS0
R/W
ADE0
R/W
ADE8
R/W
ADD0
R
-
ADE7
ADE6
R/W
ADE5
R/W
ADE4
R/W
ADE3
R/W
ADE2
R/W
ADE1
R/W
R/W
-
ADE14 ADE13 ADE12 ADE11 ADE10
ADE9
R/W
-
ADD7
R
R/W
ADD6
R
R/W
ADD5
R
R/W
ADD4
R
R/W
ADD3
R
R/W
ADD2
R
ADD1
R
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10
ADD9
R
ADD8
R
ADDH
R
R
R
R
R
R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
R/W R/W R/W R/W R/W R/W R/W R/W
ADCV15 ADCV14 ADCV13 ADCV12 ADCV11 ADCV10 ADCV9 ADCV8
ADCVL
ADCVH
WUCR2
SFR1
R/W
R/W
R/W
R/W
ADWK
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADSF
R/W
ADIE
R/W
IMR1
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
87
EM78P528N
8-Bit Microprocessor with OTP ROM
¼ VDD
PowerDet.
AVDD / 4V
/ 3V / 2V
VREFP
AD14
ADC
Power Down
(Successive Approximation)
Start to Convert
Fsub
Fmain/1
Fmain/2
Fmain/4
8 to 1
MUX
Fmain/8
Fmain/16
Fmain/32
AD0
Fmain/64
7 - 0
14 - 8
4~0
7
6
5
4
4
11 10 9 8 7 6 5 4 3 2 1 0
4
3
1
ADER1
ADER2
ADIS
ADCR1
IMR1
ADDH
ADDL
ADCR1
ADCR2
ISR1
DATA BUS
Figure 6-10 AD Converter Functional Block Diagram
This is a 12-bit successive approximation register analog-to-digital converter (SAR
ADC). There are two reference voltages for SAR ADC. The positive reference voltage
can select internal AVDD, internal voltage sources or external input pin by setting the
VREFP and VPIS1~0 bits in ADCR2. Connecting to external positive reference voltage
provides more accuracy than using internal AVDD.
6.6.1 ADC Data Register
When the AD conversion is completed, the result is loaded to the ADDH and ADDL.
And the ADSF is set if ADIE is enabled.
6.6.2 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation AD converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample and hold
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. The maximum recommended impedance for the analog source is
10k at VDD = 5V. After the analog input channel is selected; this acquisition time
must be done before AD conversion can be started.
88
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.6.3 A/D Conversion Time
CKR2~0 select the conversion time (TAD). This allows the MCU to run at maximum
frequency without sacrificing the accuracy of AD conversion. The following tables
show the relationship between TAD and the maximum operating frequencies. The TAD
is 0.5 µs for 3V~5.5V and TAD is 2 µs for 2.5V~3V.
1. VDD = 3V ~ 5.5V (TAD is 0.5 µs)
Conversion Time
of One Word
Operating Clock
of ADC
System
Mode
Max. FMain
(VDD = 3V ~ 5.5V)
CKR[2:0]
(FAD = 1 / TAD
FMain / 16
FMain / 8
FMain / 4
FMain / 2
FMain / 64
FMain / 32
FMain / 1
FSub
)
(SHS1~0 = 10*)
21 s
000
001
010
011
100
101
110
111
xxx
16 MHz
16 MHz
10.5 s
10.5 s
10.5 s
84 s
8 MHz
4 MHz
Normal
Mode
16 MHz
16 MHz
42 s
2 MHz
10.5 s
640 s
32.768 kHz
32.768 kHz
Green Mode
FSub
640 s
* Conversion Time = Sample and Hold (SHS[1:0]=10, 8 * TAD) + 12 * Bit Conversion Time (12 *
TAD) + Delay Time between setting ADSTART bit and starting first TAD
.
2. VDD = 2.5V ~ 3V (TAD is 2 µs)
Conversion Time
of One Word
Operating Clock
System
Mode
Max. FMain
(VDD = 2.5V ~ 3V)
CKR[2:0]
of ADC
(FAD = 1 / TAD
)
(SHS[1:0] = 10*)
42 s
000
001
010
011
100
101
110
111
xxx
FMain / 16
FMain / 8
FMain / 4
FMain / 2
FMain / 64
FMain / 32
FMain / 1
FSub
8 MHz
4 MHz
42 s
2 MHz
42 s
1 MHz
42 s
Normal
Mode
16 MHz
84 s
16 MHz
42 s
0.5 MHz
32.768 kHz
32.768 kHz
42 s
640 s
640 s
Green Mode
FSub
* Conversion Time = Sample and Hold (SHS[1:0]=10, 8 * TAD) + 12 * Bit Conversion Time (12 *
TAD) + Delay Time between setting ADSTART bit and starting first TAD (0.5 * TAD).
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
89
EM78P528N
8-Bit Microprocessor with OTP ROM
6.6.4 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, TC1~3 and
AD conversion.
The AD Conversion is considered completed as determined by:
1. The ADRUN bit of the Bank 0-R3E register is cleared to “0”.
2. The ADSF bit of the Bank 0-R15 register is set to “1”.
3. The ADWK bit of the Bank 0-R10 register is set to “1”. Wakes up from ADC
conversion (where it remains in operation during sleep mode).
4. Wake up and execution of the next instruction if the ADIE bit of the Bank 0-R1B is
enabled and the “DISI” instruction is executed.
5. Wake up and enters into Interrupt vector if the ADIE bit of Bank 0-R1B is enabled
and the “ENI” instruction is executed.
6. Enters into an Interrupt vector if the ADIE bit of the Bank 0-R1B is enabled and the
“ENI” instruction is executed.
The results are fed into the ADDL and ADDH registers when the conversion is
completed. If the ADWK is enabled, the device will wake up. Otherwise, the AD
conversion will be shut off, no matter what the status of the ADPD bit is.
6.6.5 Programming Process/Considerations
Follow these steps to obtain data from the ADC:
1. Write to the 15 bits (ADE14~0) on the Bank 0-R41~R42 (ADER1~2) register to
define the characteristics of P60~P61, P63~P67, P72~P73 and P90~P95 (digital
I/O, analog channels, or voltage reference pin)
2. Write to the Bank 0-R3E/ADCON register to configure the AD module:
a) Select the ADC input channel (ADIS4~0)
b) Define the AD conversion clock rate (CKR2~0)
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to “1” to begin sampling
3. Set the ADWK bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
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(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6. Set the ADRUN bit to “1”
7. Write “SLEP” instruction or Polling.
8. Wait for either Wake-up or for the ADRUN bit to be cleared to “0” , and the Status
flag (ADSF) is set “1”, or ADC interrupt occurs.
9. Read the ADDL and ADDH conversion data registers. If the ADC input channel
changes at this time, the ADDL and ADDH values can be cleared to “0”.
10. Clear the status flag (ADSF).
11. For next conversion, go to Step 1 or Step 2 as required. At least two TAD are
required before the next acquisition starts. On the other hand, the timing setting
ADRUN = 1 must be later than the timing setting ADPD=1, and the difference
between the two timing is also two TAD.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the
I/O pins during AD conversion
6.6.6 Programming Process for Detecting Internal VDD
VDD is detected within the operation, as described in the previous section the
difference is that before starting the ADC conversion, the first detection of VDD is
ready. Therefore in Detecting VDD:
It should be noted that before starting the AD conversion operation, the channel has to
be switched to 1/4VDD channel, the voltage divider is started, then AD can be
converted. Several points to note is that, precise conversion values can be added in
the VDD Pin capacitance, or more than twice the conversion, taking the average or the
last few strokes data in order to increase the reliability of the data.
Note that usually before VDD is detected, do not switch the channel to 1/4VDD
channel, as it has always been a DC current consumption, must be switched to another
channel analog multiplexer, and it will be shut out of the resistor divider, which requires
user attention.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
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EM78P528N
8-Bit Microprocessor with OTP ROM
External
Volt. Ref.
Internal
VDD
Int. VREF.
Internal
VDD
Analog
MUX
3R
R
Ref. In
Signal
In
Analog
MUX
12 bits
ADC
To
Kernel
ADC[0:14]
Pins
Figure 6-11 ADC and VDD Detection Block Diagram
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Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.6.7 Sample Demo Programs
A. Define System Control Registers
IAR
SR
== 0X00
== 0X03
; Indirect addressing register
; Status register
WUCR2 == 0x10
SFR1 == 0x15
IMR1 == 0x1B
; Wakeup Control Register 2
; Status Flag Register 1 of Interrupt
; Interrupt Mask Register 1
B. Define I/O Control Registers
PORT6 == 0X06
PORT7 == 0X07
PORT9 == 0X09
IOCR6 == 0x0C
IOCR7 == 0x0D
IOCR9 == 0x06
; I/O Control Register of Port 6
; I/O Control Register of Port 7
; I/O Control Register of Port 9(Bank 1)
C. ADC Control Register
ADCR1 == 0x3E
;
7
6
5
4
3
2
1
0
; CKR1 CKR1 CKR0 ADRUN ADP
; ADC input select register
ADOM SHS1 SHS0
ADISR == 0x40
ADDH == 0x44
ADDL == 0x45
; The contents are the results of ADC[11:8]
; The contents are the results of ADC[7:0]
D. Define Bits in ADCR1
ADP
== 0x3
; Power Mode of ADC
ADRUN == 0x4
; ADC is executed as the bit is set
E. Program Starts
ORG
0
; Initial address
JMP INITIAL
;
ORG 0x12
JMP CLRRE
;
; ADC Interrupt vector
;(User program section)
;
CLRRE:
MOV A, SFR1
AND A, @0BXXX0XXXX; To clear the ADSF bit, “X” by application
MOV SFR1, A
BS
ADCR1, ADRUN
; To start to execute the next AD conversion
; if necessary
RETI
INITIAL:
MOV A, @0B00000001; To define P73 as an analog input
MOV ADISR, A
MOV A, @0B00001000; To select P73 as an analog input channel, and
AD power on
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(This specification is subject to change without prior notice)
93
EM78P528N
8-Bit Microprocessor with OTP ROM
MOV ADCR1, A
En_ADC:
; To define P73 as an input pin and set clock
rate at fosc/16
MOV A, @0BXXXX1XXX; To define P73 as an input pin, and the others
; are dependent on applications
MOV IOCR7, A
MOV A, @0BXXX1XXXX; Enable the ADWE wake-up function of ADC, “X”
; by application
MOV WUCR2, A
MOV A, @0BXXX1XXXX; Enable the ADIE interrupt function of ADC,
; “X” by application
MOV IMR1, A
ENI
; Enable the interrupt function
; Start to run the ADC
BS ADCON, ADRUN
; If the interrupt function is employed, the following three lines
may be ignored
;If Sleep:
SLEP
;
;(User program section)
;
or
;If Polling:
POLLING:
JBC ADCR1, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
; is completed
;
;(User program section)
94
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.7 Timer
There are three Timers in the EM78P528N. Timer 2 and Timer 3 are 8 bits up-counter.
Timer 1 can be as one 8-bit up-counter or cascaded with Timer 2 as one 16-bit
up-counter. If Timer 1 is used as 16-bit up-counter, the circuit resource of Timer 2
would be used. At this time, Timer 2 cannot be used.
R_BANK Address Name
Bit 7
Bit 6
TC1RC TC1SS1 TC1MOD TC1FF TC1OMS TC1IS1 TC1IS0
R/W R/W R/W R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1S
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x24
0x25
0x26
0x27
0x28
0x29
0x3A
0x3B
TC1CR1
TC1CR2
TC1DA
TC1DB
TC2CR1
TC2CR2
TC2DA
TC2DB
R/W
R
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W
TC2S
R/W
R/W
TC2RC TC2SS1
R/W R/W
R/W
R/W
R/W
TC2FF TC2OMS TC2IS1 TC2IS0
R/W R/W R/W
TC2CK3 TC2CK2 TC2CK1 TC2CK0
R/W R/W R/W R/W
R/W
R/W
R/W
-
-
-
-
R
TC2M2 TC2M1 TC2M0
R/W R/W R/W
TC2DA7 TC2DA6 TC2DA5 TC2DA4 TC2DA3 TC2DA2 TC2DA1 TC2DA0
R/W R/W R/W R/W R/W R/W R/W R/W
TC2DB7 TC2DB6 TC2DB5 TC2DB4 TC2DB3 TC2DB2 TC2DB1 TC2DB0
R/W
TC3S
R/W
R/W
TC3RC TC3SS1
R/W R/W
R/W
R/W
R/W
TC3FF TC3OMS TC3IS1 TC3IS0
R/W R/W R/W
TC3CK3 TC3CK2 TC3CK1 TC3CK0
R/W R/W R/W R/W
R/W
R/W
R/W
-
-
-
-
0x3C TC3CR1
0x3D TC3CR2
R
TC3M2 TC3M1 TC3M0
R/W R/W R/W
TC3DA7 TC3DA6 TC3DA5 TC3DA4 TC3DA3 TC3DA2 TC3DA1 TC3DA0
0x3E
0x3F
0x16
0x1C
TC3DA
TC3DB
SFR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC3DB7 TC3DB6 TC3DB5 TC3DB4 TC3DB3 TC3DB2 TC3DB1 TC3DB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TC3DIF TC2DIF TC1DIF
F
F
F
TC3DIE TC2DIE TC1DIE
R/W R/W R/W
IMR2
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
95
EM78P528N
8-Bit Microprocessor with OTP ROM
6.7.1 Timer/Counter Mode
TCxM2~0
TCxM2~0=timer/counter mode
TCx pin
M
fc/215
MUX
clear
8-bit up counter
fc/20
TC1S
TCxCK
Comparator
TCx
interrupt
4
TCxCR
TCxDB
TCxDA
Data Bus
Figure 6-12a Timer/Counter Mode Block Diagram
In Timer/Counter mode, counting up is performed using internal clock or TCx pin.
When the contents of the up-counter are matched with the TCxDA, then interrupt is
generated and the counter is cleared. Counting up resumes after the counter is
cleared. The current contents of the up-counter are loaded into TCxDB by setting
TCxRC to “1”.
Internal clock
Up-counter
n
5
n-2
0
1
2
3
4
n-3
n-1
0
1
2
3
TCxDA
n
match
counter clear
TCx interrupt
TCx Pin
1
2
3
n 0
4
n-2
Up-counter
TCxDA
0
n-1
1
2
3
n
match
counter clear
TCx interrupt
Figure 6-12b Timer/Counter Mode Waveform
96
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.7.2 Window Mode
TCx pin
fc/215
Window
clear
8-bit up counter
MUX
fc/20
Comparator
TCx interrupt
TCxCK
TCxS
4
TCcCR2
TCxDA
Data Bus
Figure 6-13a Window Mode Block Diagram
In Window mode, counting up is performed on a rising edge of the pulse that is logical
AND of an internal clock and the TCx pin (window pulse). When the contents of the
up-counter are matched with the TCxDA, then interrupt is generated and the counter is
cleared. The frequency (window pulse) must be slower than the selected internal
clock.
TCx pin
Internal clock
Up-counter
TCxDA
n-1
n
0
n-2
0
1
2
n-3
1
2
3
n
match
counter clear
TCx interrupt
Figure 6-13b Window Mode Waveform
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
97
EM78P528N
8-Bit Microprocessor with OTP ROM
6.7.3 Capture Mode
Inhibit
Rising
Edge
detector
Capture
control
TCx
Falling
TCxM2~0
M
interrupt
TCxM2~0=010
TCx pin
fc/215
Overflow
8-bit up counter
MUX
fc/20
TC1S
CAP
TCxCK
4
Capture
Capture
TC1CR
TCxDB
TCxDA
Data Bus
Figure 6-14a Capture Mode Block Diagram
In Capture mode, the pulse width, period and duty of the TCx input pin are measured in
this mode, which can be used to decode the remote control signal. The counter is free
running by the internal clock. On a rising (falling) edge of TCx pin, the contents of the
counter is loaded into TCxDA, then the counter is cleared and interrupt is generated.
On a falling (rising) edge of TC1 pin, the contents of the counter are loaded into TCxDB.
At this time, the counter is still counting. Once the next rising edge of TCx pin is
triggered, the contents of the counter are loaded into TCxDA, the counter is cleared
and interrupt is generated again. If overflow before the edge is detected, the FFH is
loaded into TCxDA and an overflow interrupt is generated. During interrupt processing,
it can be determined whether or not there is an overflow by checking whether or not the
TCxDA value is FFH. After an interrupt (capture to TCxDA or overflow detection) is
generated, capture and overflow detection are halted until TCxDA is read out.
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EM78P528N
8-Bit Microprocessor with OTP ROM
Clock source
Up-counter
m
m+1
1
m-1
n
0
1
2
3
FE FF0
1
2
3
K-2
K-1
K
0
n-1
TCx pin input
TCxDA
K
n
FF (overflow)
overflow
m
FE
TCxDB
capture
capture
TCx Interrupt
Reading TCxDA
Figure 6-14b Capture Mode Waveform
6.7.4 Programmable Divider Output Mode and Pulse Width
Modulation Mode
TCxFF
TCxM2~0=101
TCx interrupt
F/F
PWMx,PDOx pin
Q
clear
TCxM2~0=10x
toggle
8-bit up counter
fc/215
fc/20
MUX
match
Comparator
TCxS
TCxCK2~0
match
Comparator
4
TCxCR
TCxDA_buffer2
TCxDA_buffer1
TCxDB_buffer2
TCxDB_buffer1
TCxDB
Write TCxDA[0]
TCxDA
Data Bus
Figure 6-15a PDO/PWM Mode Block Diagram
Programmable Divider Output (PDO)
In Programmable Divider Output (PDO) mode, counting up is performed using the
internal clock. The contents of TCxDA are compared with the contents of the up-
counter. The F/F output is toggled and the counter is cleared each time a match is
found. The F/F output is inverted and output to PDO pin. This mode can generate 50%
duty pulse output. The PDO pin is initialized to “0” during reset. A TCx interrupt is
generated each time the PDO output is toggled.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
99
EM78P528N
8-Bit Microprocessor with OTP ROM
Clock source
n
n
0
Up-counter
0
1
2
3
n-1
2
3
n-1
3
n
n-1 0
0
1
1
2
1
2
n
TCxDA
PDO pin
(TCxFF = 0)
PDO pin
(TCxFF = 1)
TCx Interrupt
Figure 6-15b PDO Mode Waveform
Pulse Width Modulation (PWM)
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock with prescaler. The Duty of PWMx control by TCxDB, and the period of
PWMx control by TCxDA. The pulse at the PWMx pin is held to high level as long as
TCxS=1 or timerx matches TCxDA, while the pulse is held to low level as long as
Timerx matches TCxDB. Once TCxFF is set to 1, the signal of PWMx is inverted. A TCx
interrupt is generated and defined by TCxIS. On the other hand, the TCxDA and
TCxDB can be written anytime, but the data of TCxDA and TCxDB are latched only at
writing TCxDA0. Therefore, the new duty and new period of PWM appear at the PMW
pin at the last period–match.
Clock source
Up-counter
n
p
p+2
p+1
n+1 n+2
p-1
q-1
q
0
1
n-1
n-1
n
m-1
m
0
m-1
m
0
n+2
n+1
1
n
p
Duty
duty-match
Writing duty register
period-match
duty-match
duty-match
period-match
period-match
m
q
Period
PWM
Writing period register
n
p
m+1
q+1
TCx Interrupt
Figure 6-15c PWM Mode Waveform
6.7.5 Buzzer Mode
The TCx pin outputs the clock after dividing the frequency.
100
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.8 UART (Universal Asynchronous Receiver/Transmitter)
Registers for UART Circuit
R_BAN Addr. Name
Bank 0 0x16 SFR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
UTSF
R/W
Bit 2
Bit 1 Bit 0
-
-
-
-
-
-
-
-
UERRSF URSF
-
-
-
-
-
-
-
-
-
-
-
-
R/W
UERRIE
R/W
R/W
URIE
R/W
UTIE
R/W
Bank 0 0x1C IMR2
Bank 1 0X33 URCR
UINVEN UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE TXE
R/W
URTD8 EVEN
R/W
R/W
R/W
PRE
R/W
R/W
PRERR OVERR FMERR URB RXE
R/W R/W R/W R/W
R/W
R/W
R/W R/W
Bank 1 0X34
URS
W
R
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URT URT
Bank 1 0x35 URTD
Bank 1 0X36 URRDL
Bank 1 0X37 URRDH
W
W
W
W
W
W
W
W
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URR URR
R
URRD8
R
R
-
R
-
R
-
R
-
R
-
R
-
R
-
-
-
-
-
-
-
-
TC3
Baud Rate
Generator
selector
Fsystem
Interrupt
Control
TXE
RXE
RX Control
TX Control
RX
RX Shift Register
Parity Control
TX
URRD8
URRD
Error Flag
Data Bus
URTD8
URTD
UINVEN
UINVEN
Figure 6-16 UART Functional Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and stop bit.
Full duplex data transfer is possible since the UART has independent transmit and
receive sections. Double buffering for both sections allows the UART to be
programmed for continuous data transfer.
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(This specification is subject to change without prior notice)
101
EM78P528N
8-Bit Microprocessor with OTP ROM
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in
which the least significant bit (LSB) comes first. The data bits are followed by the parity
bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on a falling edge of the start bit. When two or
three “0” are detected during three samples, it is recognized as normal start bit and the
receiving operation is started.
Idle state
(mark)
Parity
bit
Start
Bit
Stop
Bit
D0
D1
D2
Dn
1 bit
7 or 8 bits
1 bit
One character of frame
Figure 6-17 Data Format in UART
6.8.1 UART Mode
There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the
addition of a parity bit. The parity bit addition is not available in Mode 3. Figure 6-18a
below shows the data format in each mode.
UMODE PRE
1
2
3
5
6
7
8
9
10
11
4
Start
Stop
7 bits data
0
0
0
0
0
1
Mode 1
Start
Start
Start
Start
Parity
Stop
Stop
7 bits data
8 bits data
8 bits data
0
0
1
1
0
1
Mode 2
Mode 3
Parity
Stop
Stop
9 bits data
1
0
X
Figure 6-18a UART Model
102
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.8.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Set the TXE bit of the URCR1 register to enable the UART transmission function.
2. Write data into the URTD register and the UTBE bit of the URCR register will be
cleared by hardware.
3. Then start transmitting.
4. Serially transmitted data are transmitted in the following order from the TX pin.
5. Start bit: one “0” bit is output.
6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.
7. Parity bit: one parity bit (odd or even selectable) is output.
8. Stop bit: one “1” bit (stop bit) is output.
Mark state: output “1” continues until the start bit of the next transmitted data.
After transmitting the stop bit, the UART generates a UTSF interrupt (if enabled).
6.8.3 Receiving
In receiving, the UART operates as follows:
1. Set the RXE bit of the URS register to enable the UART receiving function. The
UART monitors the RX pin and synchronizes internally when it detects a start bit.
2. Receive data is shifted into the URRD register in the order from LSB to MSB.
3. The parity bit and the stop bit are received. After one character is received, the
URBF bit of the URS register will be set to “1”. This means UART interrupt will
occur.
4. The UART makes the following checks:
(a) Parity check: The number of “1” of the received data must match the even or
odd parity setting of the EVEN bit in the URS register.
(b) Frame check: The start bit must be “0” and the stop bit must be “1”.
(c) Overrun check: The URBF bit of the URS register must be cleared (that means
the URRD register should be read out) before the next received data is loaded
into the URRD register.
If any checks failed, the UERRSF interrupt will be generated (if enabled), and an
error flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be
cleared by software, otherwise, UERRSF interrupt will occur when the next byte is
received.
5. Read received data from URRD register. And URBF bit will be set by hardware.
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(This specification is subject to change without prior notice)
103
EM78P528N
8-Bit Microprocessor with OTP ROM
6.8.4 Baud Rate Generator
The baud rate generator is comprised of a circuit that generates a clock pulse to
determine the transfer speed for transmission/reception in the UART.
The BRATE2~BRATE0 bits of the URC register can determine the desired baud rate.
6.8.5 UART Timing
1. Transmission Counter Timing:
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
4
FUART*16
One bit cycle
TXD pin
Start bit
Bit 0
2. Receiving Counter Timing:
Synchronization
(reset counter)
15 16
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
4
FUART*16
One bit cycle
RXD pin
Stop bit
Start bit
Bit 0
Sampling timing
Figure 6-18b UART Timing Diagrams
6.9 SPI (Serial Peripheral Interface)
R_BANK Address Name Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1 Bit 0
CES
SPIE
R/W
TD1
R/W
SRO SSE SDOC SBRS2 SBRS1 SBRS0
Bank 0
Bank 0
Bank 0
Bank 0
0X36 SPICR
R/W
DORD
R/W
R/W R/W
R/W
OD3
R/W
R/W
OD4
R/W
R/W
R/W
RBF
R
TD0
-
-
0X37
0X38
0X39
SPIS
SPIR
SPIW
R/W
-
-
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
R
R
R
R
R
R
R
R
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
R/W
R/W
R/W R/W
R/W
SPISF
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bank 0
Bank 0
0X18
0X1E
SFR4
IMR4
SPIIE
R/W
104
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
6.9.1 Overview and Feature
Overview:
Figures 6-19 and 6-20 show how the EM78P528N communicates with other devices
through SPI module. If EM78P528N is a Master controller, it sends clock through the
SCK pin. A couple of 8-bit data are transmitted and received at the same time.
However, if the EM78P528N is defined as a Slave, its SCK pin could be programmed
as an input pin. Data will continue to be shifted based on both the clock rate and the
selected edge. User can also set SPIS Bit 7 (DORD) to determine the SPI transmission
order, SPICR Bit 3 (SDOC) to control SDO pin after serial data output status and SPIS
Bit 6 (TD1), Bit 5 (TD0) determines the SDO status output delay times.
Features:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Operation in either Master mode or Slave mode
Three-wire or four-wire full duplex synchronous communication
Programmable baud rates of communication
Programming clock polarity, (Bank 0 R36 Bit 7)
Interrupt flag available for the read buffer full
SPI transmission order
After serial data output SDO status select
SDO status output delay times
SPI handshake pin
10. Up to 4 MHz (maximum) bit frequency
SDO
SPIR Reg
SPIW Reg
SPIR Reg
SPIW Reg
/SS
SDI
SPIS Reg
SPIS Module
SCK
Master Device
Slave Device
Figure 6-19 SPI Master/Slave Communication
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
105
EM78P528N
8-Bit Microprocessor with OTP ROM
SDI
SDO
SCK
/SS
Vdd
Master
P60
P61
P62
P63
Slave Device 1
Slave Device 2
Slave Device 4
Slave Device 3
Figure 6-20 SPI Configuration of Single-Master and Multi-Slave
6.9.2 SPI Functional Description
Read
Write
RBF
SPIIF
SSE
SPIW
SPIR reg
reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
SI
SPIC reg
SO
Edge
Select
SBR0 ~SBR2
SBR2~SBR0
Noise
Filter
/SS
/ SS
Clock Select
Prescaler
2, 4, 8, 16, 32
Fosc
Edge
Select
SCK
TMR2
CES
Figure 6-21 SPI Block Diagram
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EM78P528N
8-Bit Microprocessor with OTP ROM
SPI
SO
SI
Shift Clock
SPI Shift
Buffer
FOSC
2 1 0
SPIC
7 6 4 5 4
SPIC
SPIC
3
0
7~0
SPIW
7~0
SPIR
ISR4
SPIS
DATA Bus
Figure 6-22 Functional Block Diagram of SPI Transmission
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Figures 6-21 and 6-22.
P84/SDA/SI/SEG4: Serial Data In
P85/SO/SEG5: Serial Data Out
P86/SCL/SCK/SEG6: Serial Clock
P87//SS/AD9/SEG8: /Slave Select (Option). This pin (/SS) may be required during
a Slave mode
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and the
SPIW registers are shift at the same time. Once data are written, SPIS starts
transmission / reception. The data received will be moved to the SPIR register as
the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
SPISF (SPI Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
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(This specification is subject to change without prior notice)
107
EM78P528N
8-Bit Microprocessor with OTP ROM
The SSE bit will be kept in “1” if the communication is still undergoing. This flag must
be cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select: Selecting either the internal or the external clock as the shifting clock.
Edge Select: Selecting the appropriate clock edges by programming the CES bit
6.9.3 SPI Signal and Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
P84/SDA/SI/SEG4:
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
Defined as high-impedance, if not selected
Program the same clock rate and clock edge to latch on both the Master and Slave
devices
The byte received will update the transmitted byte
The RBF will be set as the SPI operation is completed
Timing is shown in Figures 6-23 and 6-24.
P85/SO/SEG5:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last
Program the same clock rate and clock edge to latch on both the Master and Slave
devices
The received byte will update the transmitted byte
The CES bit will be reset, as the SPI operation is completed
Timing is shown in Figures 6-23 and 6-24.
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EM78P528N
8-Bit Microprocessor with OTP ROM
P86/SCL/SCK/SEG6:
Serial Clock
Generated by a Master device
Synchronize the data communication on both the SI and SO pins
The CES is used to select the edge to communicate.
The SBR0~SBR2 is used to determine the baud rate of communication
The CES, SBR0, SBR1, and SBR2 bits have no effect in Slave mode
Timing is shown in Figures 6-23 and 6-24.
P87//SS/AD9/SEG8:
Slave Select; negative logic
Generated by a Master device to signify the Slave(s) to receive data
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed
Ignores the data on the SI and SO pins while /SS is high, because the SO is no
longer driven
Timing is shown in Figures 6-23 and 6-24.
6.9.4 SPI Mode Timing
SCK
(CES=0)
SCK
(CES=1)
SDO
MSB
6
5
4
3
2
1
LSB
(DORD=0)
SDI
MSB
6
5
4
3
2
1
LSB
(DORD=0)
Delay
Time
RBF
Figure 6-23 SPI Mode with /SS Disabled
The SCK edge is selected by programming bit CES. The waveform shown in Figure
6-23 is applicable regardless of whether the EM78P528N is in Master or Slave mode
with /SS disabled. However, the waveform in Figure 6-24 can only be implemented in
Slave mode with /SS enabled.
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(This specification is subject to change without prior notice)
109
EM78P528N
8-Bit Microprocessor with OTP ROM
SCK
(CES=0)
SCK
(CES=1)
SDO
MSB
6
5
4
3
2
1
LSB
(DORD=0)
SDI
MSB
6
5
4
3
2
1
LSB
(DORD=0)
Delay
Time
RBF
/SS
Figure 6-24 SPI Mode with /SS Enabled
6.10 I2C Function
R_BANK Addr. Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
ACK
R
Bit 1
Bit 0
Strobe/Pend
IMS
R/W R/W R/W
ISS STOP SAR_EMPTY
FULL EMPTY
Bank 0 0x30 I2CCR1
Bank 0 0x31 I2CCR2
Bank 0 0x32 I2CSA
Bank 0 0x33 I2CDB
Bank 0 0x34 I2CDAL
Bank 0 0x35 I2CDAH
Bank 0 0x18 SFR4
Bank 0 0x1E IMR4
R/W
I2CBF GCEN
R
R
R
-
BBF
I2CTS1
I2CTS0
R/W
SA1
R/W
DB2
R/W
DA2
R/W
-
-
I2CEN
R/W
IRW
R/W
DB0
R/W
DA0
R/W
DA8
R/W
R
R/W
-
R
R/W
-
SA6
SA5 SA4 SA3
R/W R/W R/W
DB6 DB5 DB4
R/W R/W R/W
DA6 DA5 DA4
R/W R/W R/W
SA2
SA0
R/W
DB1
R/W
DA1
R/W
DA9
R/W
R/W
R/W
DB7
DB3
R/W
R/W
DA7
DA3
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2CSTPIF I2CRSF I2CTSF
R/W R/W R/W
I2CSTPIE I2CRIE I2CTIE
R/W R/W R/W
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Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Read
Write
FULL
I2CRIF
I2CTIF
I2CDB reg
I2CSA reg
Buffer Full Detector
Control and
Status reg
SCL
MSb
LSb
SDA
Add Match
Match Detect
I2CDA reg
Start and Stop
bit Detect
Figure 6-25 I2C Block Diagram
The EM78P528N supports a bidirectional, 2-wire bus, 7/10-bit addressing and data
transmission protocol. A device that sends data onto the bus is defined as transmitter,
while a device receiving data is defined as a receiver. The bus has to be controlled by
a Master device which generates the Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions. Both Master and Slave can operate as
transmitter or receiver, but the Master device determines which mode is activated.
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
pull-up resistor. When the bus is free, both lines are HIGH. The output stages of
devices connected to the bus must have an open-drain or open-collector to perform the
wired-AND function. Data on the I2C-bus can be transferred at the rates of up to
100Kbit/s in Standard mode or up to 400Kbit/sec. in Fast mode.
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the SCL
line is LOW.
Product Specification (V1.4) 03.31.2016
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111
EM78P528N
8-Bit Microprocessor with OTP ROM
The I2C Interrupt occurs as describe below:
Condition
Master/Slave Transmit Address
Transmit Data
Stop
Master
Slave
Transmit interrupt Transmit interrupt Stop interrupt
Master-transmitter
transmits to
Slave-receiver
Receive interrupt
Receive interrupt Stop interrupt
Master
Slave
Transmit interrupt
Transmit interrupt
Receive interrupt Stop interrupt
Transmit interrupt Stop interrupt
Master receiver read
Slave-transmitter
Within the procedure of the I2C bus, there can be unique situations which are defined
as START (S) and STOP (P) conditions.
A High to Low transition on the SDA line while SCL is High is one such unique case.
This situation indicates a START condition.
A Low to High transition on the SDA line while SCL is High defines a STOP condition.
SCL
SDA
data line change
stable;
data valid allowed
of data
START
STOP
Figure 6-26 I2C Transfer Condition
7-Bit Slave Address
Master-transmitter transmits to Slave-receiver. The transfer direction is not changed.
Master reads Slave immediately after the first byte. At the moment of the first
acknowledgement, the Master-transmitter becomes a Master-receiver and the
Slave-receiver becomes a Slave-transmitter. This first acknowledgement is still
generated by the Slave. The STOP condition is generated by the Master, which has
previously sent a not-acknowledge (A). The difference between Master transmitter
with Master receiver is only in R//W bit. If the R//W bit is “0”, the Master device is the
Transmitter. Otherwise, the Master device is the Receiver. The Master-Transmitter is
illustrated in Figure 6-27a “Master-Transmitter transmits to Slave–receiver with 7-Bit
Slave Address”, and that of the Master-Receiver is shown in Figure 6-27b “Master-
Receiver Reads Slave –Transmitter with 7-Bit Slave Address”.
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EM78P528N
8-Bit Microprocessor with OTP ROM
8 Bits
8 Bits
8 Bits
S
Slave Address
R//W
A
Data
A
Data
A//A
P
'0'
Write
7 Bits
data transferred
(n byte + acknowledge)
A = acknowledge (SDA low)
/A = not acknowledge (SDA high)
S = Start
Master to Slave
Slave to Master
P = Stop
Figure 6-27a Master-Transmitter Transmits to Slave-Receiver with 7-Bit Slave Address
8 Bits
S
Slave Address
R//W
A
Data
A
Data
/A
P
7 Bits
'1' Read
data transferred
(n byte + acknowledge)
Figure 6-27b Master-Receiver Reads Slave-Transmitter with 7-Bit Slave Address
10-Bit Slave Address
In 10-Bit Slave address mode, using 10 bits for addressing exploits the reserved
combination 11110XX for the first seven bits of the first byte following a START (S) or
repeated START (Sr) condition. The first seven bits of the first byte are the
combination 11110XX of which the last two bits (XX) are the two most-significant bits of
the 10-bit address. If the R//W bit is “0”, the second byte after acknowledgement would
be the eight address bits of the10-bit Slave address. Otherwise, the second byte would
just only be the next transmitted data from a Slave to Master device. The first bytes
11110XX are transmitted using the Slave address register (I2CSA), and the second
bytes XXXXXXXX are transmitted using the data buffer (I2CDB).
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(This specification is subject to change without prior notice)
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EM78P528N
8-Bit Microprocessor with OTP ROM
The following explains the possible data transfer formats for 10-bit Slave address
mode:
Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave Address
When the Slave receives the first byte after START bit from Master, each Slave devices
will compare the seven bits of the first byte (11110XX) with their own address and the
8th bit, R//W. If the R//W bit is “0”, the Slave will return the Acknowledge (A1). It is
possible that more than one Slave devices will return the Acknowledge (A1). Then all
Slave devices will continue to compare the second address (XXXXXXXX). If a Slave
device finds a match, that particular Slave will be the only one to return an
Acknowledge (A2). The matching Slave device will remain addressed by the Master
until it receives a STOP condition or a repeated START condition followed by the
different Slave address.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A1
A2
A
A//A
R//W
Data
Data
P
Write
1st 7-Bits
2nd 8-Bits
Figure 6-28a Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave Address
Master-Receiver Reads Slave-Transmitter with a 10-bit Slave Address
Up to and including acknowledge Bit A2, the procedure is the same as that described
for Master-transmitter addressing a Slave receiver. After the acknowledge A2, a
repeated START condition (Sr) followed by seven bits Slave address (11110XX) but
the 8th bit R//W is “1”, the addressed Slave device will return the acknowledge A3. If
the repeated START (Sr) condition and the seven bits of first byte (11110XX) received
by Slave device, all the Slave device would compare with their own address and test
the 8th R//W. However, none of the Slave devices can return an acknowledgement
because R//W=1.
1 1 1 1 0 X X
0
1 1 1 1 0 X X
1
Slave
Address
Slave
Address
Slave
Address
S
DATA
A1
A2 Sr
A3
A
DATA /A
P
R//W
R//W
1st 7-
Bits
1st 7-
Bits
2nd 8-Bits
read
Write
Figure 6-28b Master-Receiver Reads Slave-Transmitter with a 10-bit Slave Address
114
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EM78P528N
8-Bit Microprocessor with OTP ROM
Master Transmits and Receives Data to and from the Same Slave Device with
10-Bit Addresses
The initial operation of this data transfer format is the same as explained in the above
paragraph on “Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave
Address.” Then the Master device starts to transmit the data to Slave device. When
the Slave device receives the Acknowledge or None-Acknowledge that is followed by
repeat START (Sr), the above operation under “Master-Receiver Read Slave-
Transmitter with a 10-Bit Slave Address” is repeatedly performed.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
R//W
A
A
A
A//A
Data
Data
1st 7-Bits
Write
2nd 8-Bits
1 1 1 1 0 X X
1
Slave
Address
Sr
R//W
A
A
/A
Data
Data
P
1st 7-Bits
Read
Figure 6-28c Master Addresses a Slave with 10-Bit Addresses Transmits and Receives Data
with the Same Slave Device
Master Device Transmits Data to Two or More Slave Devices with 10 and
7 Bits Slave Address
For 10-bit address, the initial operation of this data transfer format is the same as
explained in the above paragraph on “Master-Transmitter Transmits to Slave-Receiver
with a 10-bit Slave Address,” which describes how to transmit data to Slave device.
After the Master device completes the initial transmittal, and wants to continue
transmitting data to another device, the Master needs to address each of the new Slave
devices by repeating the initial operation mentioned above. If the Master device wants
to transmit the data in 7-bit and 10-bit Slave address modes successively, this could be
done after the START or repeat START conditions as illustrated in the following figures.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
115
EM78P528N
8-Bit Microprocessor with OTP ROM
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
R//W
Data
Data
1st 7-
Bits
2nd 8-
Bits
Write
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-
Bits
2nd 8-
Bits
Write
Figure 6-28d Master Transmitting to More than One Slave Devices with 10-Bit Slave Address
0
Slave
Address
S
A
A
A//A
R//W
Data
Data
7-Bits
Write
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-
Bits
2nd 8-
Bits
Write
Figure 6-28e Master Successively Transmitting to 7-Bit and 10-Bit Slave Address
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EM78P528N
8-Bit Microprocessor with OTP ROM
6.10.1 Master Mode
In transmitting (receiving) serial data, the I2C operates as follows:
1. Set I2CTS1~0 and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C Master function.
3. Write Slave address into the I2CSA register and IRW bit to select read or write.
4. Set strobe bit will start transmit and then Check I2CTSF (I2CTSF) bit.
5. Write 1st data into the I2CDB register, set strobe bit and Check I2CTSF (I2CRSF) bit.
6. Write 2nd data into the I2CDB register, set strobe bit, Stop bit and Check I2CTSF
(I2CRSF) bit.
6.10.2 Slave Mode
In receiving (transmitting) serial data, the I2C operates as follows:
1. Set I2CTS1~0, I2CCS and ISS bits to select I2C transmit clock source.
2. Set I2CEN and IMS bits to enable I2C Slave function.
3. Write device address into the I2CDA register.
4. Check I2CRSF (I2CTSF) bit, read I2CDB register (address) and then clear Pend bit.
5. Check I2CRSF (I2CTSF) bit, read I2CDB register (1st data) and then clear Pend bit.
6. Check I2CRSF (I2CTSF) bit, read I2CDB register (2nd data) and then clear Pend bit.
7. Check I2CSTPSF bit, end transmission.
6.11 Liquid Crystal Display Driver (LCD Driver)
The EM78P528N supports two types of LCD (R-type) that can drive up to 23 segments
and 8 commons, which drive a total of 8×23 dots. The LCD block is made up of LCD
driver, display RAM, segment output pins, common output pins and LCD operating
power supply pins. This circuit can work in normal mode, green mode and idle mode.
The LCD duty, bias, the number of segment, the number of common and frame
frequency are determined by the LCD controller register.
The basic structure contains a timing control, which uses the main system clock or
subsystem clock to generate the proper timing for different duty and display access.
The Bank 1 R4B register is a command register for LCD driver that include LCD
enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4) and LCD frame frequency
control. The register Bank 1 R4C is LCD RAM address control register. The register
Bank 1 R4D is LCD RAM data buffer. The control register is explained as follows.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
117
EM78P528N
8-Bit Microprocessor with OTP ROM
Control Register
R_BANK Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
BS
Bit 3
Bit 2
DS0
R/W
-
Bit 1
Bit 0
LCDEN LCDTYPE
-
DS1
LCDF1 LCDF0
0x48
0x49
0x4A
LCDCR1
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
R/W
R/W
-
R/W
R/W
R/W
BF1
R/W
R/W
BF0
R/W
-
-
-
-
-
-
RBS1
RBS0 DYMEN
-
-
-
-
LCDCR2
LCDCR3
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
LCDCC2 LCDCC1 LCDCC0
R/W R/W R/W
-
LCDA4 LCDA3 LCDA2 LCDA1 LCDA0
R/W R/W R/W R/W R/W
0x4B LCDADDR
LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0
0x4C
LCDDB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
LCDSM2 LCDSM1 LCDSM0
-
-
LCDCM2 LCDCM1 LCDCM0
0x4D LCDCSCR
0x4E LCDSCR1
R/W
SEG6
R/W
R/W
EG5
R/W
R/W
SEG4
R/W
R/W
SEG2
R/W
R/W
SEG1
R/W
R/W
SEG0
R/W
SEG7
R/W
SEG3
R/W
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
SEG9
R/W
SEG8
R/W
0x4F
LCDSCR2
R/W
R/W
R/W
R/W
R/W
R/W
1 frame
VDD
COM 0
COM 1
SEG N
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
SEG N - COM0
ON
-VLCD3
-VDD
VDD
VLCD3
GND
SEG N - COM1
OFF
-VLCD3
-VDD
1/2 bias, 1/2 duty
A type
Figure 6-29a ½ Bias, ½ Duty A Type LCD Waveform
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EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
COM 0
COM 1
SEG N
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
SEG N - COM0
ON
-VLCD3
-VDD
VDD
VLCD3
GND
SEG N - COM1
OFF
-VLCD3
-VDD
1/2 bias, 1/2 duty
B type
Figure 6-29b ½ Bias, ½ Duty B Type LCD Waveform
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
119
EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
COM 0
VLCD3
GND
VDD
COM 1
COM 2
SEG N
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
COM0
ON
SEG N -
-VLCD3
-VDD
VDD
VLCD3
GND
SEG N -
COM1
OFF
-VLCD3
-VDD
1/2 bias, 1/3 duty
A type
Figure 6-29c ½ Bias, 1/3 Duty A Type LCD Waveform
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EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
COM 0
COM 1
COM 2
SEG N
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
VDD
VLCD3
GND
SEG N -COM0
ON
-VLCD3
-VDD
VDD
VLCD3
GND
SEG N -COM1
OFF
-VLCD3
-VDD
1/2 bias, 1/3 duty
B type
Figure 6-29d ½ Bias, 1/3 Duty B Type LCD Waveform
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(This specification is subject to change without prior notice)
121
EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
VLCD2
VLCD3
GND
COM 0
VDD
VLCD2
VLCD3
GND
COM 1
COM 2
VDD
VLCD2
VLCD3
GND
VDD
VLCD2
VLCD3
GND
SEG N
VDD
SEG N - COM0
ON
VLCD3
GND
-VLCD3
-VDD
VDD
SEG N - COM1
OFF
VLCD3
GND
-VLCD3
-VDD
1/3 bias, 1/3 duty
A type
Figure 6-29e ⅓ Bias, ⅓ Duty A Type LCD Waveform
122
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EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
VLCD2
VLCD3
GND
COM 0
VDD
VLCD2
VLCD3
GND
COM 1
COM 2
VDD
VLCD2
VLCD3
GND
VDD
VLCD2
VLCD3
GND
SEG N
VDD
SEG N - COM0
ON
VLCD3
GND
-VLCD3
-VDD
VDD
SEG N - COM1
OFF
VLCD3
GND
-VLCD3
-VDD
1/3 bias, 1/3 duty
B type
Figure 6-29f ⅓ Bias, ⅓ Duty B Type LCD Waveform
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
123
EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
VLCD2
VLCD3
GND
COM 0
VDD
VLCD2
VLCD3
GND
COM 1
COM 2
VDD
VLCD2
VLCD3
GND
VDD
VLCD2
VLCD3
GND
SEG N
VDD
VLCD3
GND
SEG N -COM0
ON
-VLCD3
-VDD
VDD
VLCD3
GND
SEG N -
COM1
OFF
-VLCD3
-VDD
1/3 bias, 1/4 duty
A type
Figure 6-29g ⅓ Bias, ¼ Duty A Type LCD Waveform
124
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
VLCD2
VLCD3
GND
COM 0
VDD
VLCD2
VLCD3
GND
COM 1
COM 2
VDD
VLCD2
VLCD3
GND
VLCD1
VLCD2
VLCD3
GND
SEG N
VLCD1
VLCD3
GND
SEG N -
COM0
ON
-VLCD3
-VLCD1
VLCD1
VLCD3
GND
SEG N -
COM1
OFF
-VLCD3
-VLCD1
1/3 bias, 1/4 duty
B type
Figure 6-29h ⅓ Bias, ¼ Duty B Type LCD Waveform
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(This specification is subject to change without prior notice)
125
EM78P528N
8-Bit Microprocessor with OTP ROM
6.12 LVD (Low Voltage Detector)
Under unstable power source condition, such as external power noise interference or
EMS test condition, a violent power vibration could occur. At the time, the VDD could
become unstable as it could be operating below working voltage. When the system
supply voltage (VDD) is below operating voltage, the IC kernel will automatically keep
all register status.
With LVD set at Bank 1 R45, the detailed LVD operation mode is as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDEN
R/W
LVDS2
R/W
LVDS1
R/W
LVDS0
R/W
LVDB
R
Bit 7 (LVDEN): Low Voltage Detector Enable Bit
0: Disable low voltage detector
1: Enable low voltage detector
Bits 6~4 (LVDS2~LVDS0): Low Voltage Detector Level Bits
LVDEN
LVDS2~0
011
LVD Voltage Interrupt Level
LVDSF
1
1
1
1
0
2.2V
3.3V
4.0V
4.5V
NA
1*
1*
1*
1*
0
010
001
000
XX
* If Vdd crossovers at the LVD voltage interrupt level as Vdd varies, LVDSF =1.
Bit 3 (LVDB): Low Voltage Detector State Bit. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by LVDS2
~ LVDS0), this bit will be cleared.
0: The low voltage is detected.
1: The low voltage is not detected or LVD function is disabled.
The following steps are needed to setup the LVD function:
1. Set the LVDEN to “1”, then use Bits 6~4 (LVDS2~LVDS0) of Register Bank 1 R45 to
set the LVD interrupt level
2. Wait for LVD interrupt to occur
3. Clear the LVD interrupt flag
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EM78P528N
8-Bit Microprocessor with OTP ROM
The internal LVD module uses the internal circuit to fit. When user set the LVDEN to
enable the LVD module, the current consumption will increase to 30 A.
During sleep mode, the LVD module continues to operate. If the device voltage drop
slowly and crosses the detect point. The LVDSF bit will be set and the device will not
wake up from Sleep mode. Until the other wake-up source to wake-up EM78P528N,
the LVD interrupt flag is still set as the prior status.
When the system resets, the LVD flag will be cleared.
The Figure 6-30 shows the LVD module to detect the external voltage situation.
When VDD drops not below VLVD, LVDSF keep at “0”.
When VDD drops below VLVD, LVDSF set to “1”. If global ENI enable, LVDSF will be
set to “1”, the next instruction will branch to the interrupt vector. The LVD interrupt flag
is cleared to “0” by software.
When VDD drops below VRESET and less than 5 s, the system will keep all the register
status and the system halts but oscillation is active. When VDD drops below VRESET
and more than 5 s, system RESET will occur, and for the following actions refer to
Section 6.5.1 Reset description.
LVDSF clear by software
Vdd
VLVD
VRESET
LVDSF
Internal
Reset
16ms
> LVR voltage drop time
< LVR voltage drop time
Vdd < Vreset not longer than 5us,system keep on
going
System occur
reset
Figure 6-30 LVD Waveform Characteristics Showing Detection Point in an External Voltage Condition
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(This specification is subject to change without prior notice)
127
EM78P528N
8-Bit Microprocessor with OTP ROM
6.13 Oscillator
6.13.1 Oscillator Modes
The EM78P528N can be operated in two different oscillator modes, such as Internal
RC oscillator mode (IRC) and XTAL oscillator mode (XT). User need to set the
main-oscillator modes by selecting the OSC2~OSC0, and set the sub-oscillator modes
by selecting the FSS1~FSS0 in the Code Option register to complete the overall
oscillator mode setting. Tables 6, 7, and 8 depict how these four modes are defined.
The up-limited operating frequency of crystal/resonator on the different VDD is listed in
Table 6
Table 6 Main-oscillator modes defined by OSC2 ~ OSC0
Main-oscillator Mode
HXT1 (High XTAL1 oscillator mode)
OSC2
OSC1
OSC0
1
1
1
1
0
0
1
1
0
0
X
X
1
0
1
0
1
0
Frequency range: 12~16 MHz
HXT2 (High XTAL2 oscillator mode)
Frequency range: 6~12 MHz
XT (XTAL oscillator mode)
Frequency range: 1~6 MHz
LXT1 (Low XTAL1 oscillator mode)
Frequency range: 100K~1 MHz
IRC (Internal RC oscillator mode) (default)
RCOUT (P54) acts as I/O pin
IRC (Internal RC oscillator mode)
RCOUT (P54) acts as clock output pin
Table 7 Sub-oscillator modes defined by FSS1 ~ FSS0
Sub-oscillator Mode
FSS1
FSS0
LXT2 (Low XTAL2) oscillator mode
Frequency range: 32.768kHz
0
x
Fs is 32kHz, Xin (P55) / Xout (P56) pin acts as I/O
1
1
0
1
Fs is 16kHz, Xin (P55) / Xout (P56) pin acts as I/O (default)
Note: WDT frequency is always 16kHz whatever the FSS1~0 bits are set.
Table 8 Combination of Main-oscillator and Sub-oscillator modes
Combination
Main Clock
Crystal
Crystal
IRC
Sub-clock
Crystal
IRC
1
2
3
4
Crystal
IRC
IRC
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Product Specification (V1.4) 03.31.2016
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EM78P528N
8-Bit Microprocessor with OTP ROM
Table 9 Summary of Maximum Operating Speeds
Conditions
VDD
2.2
Fxt max. (MHz)
4.0
8.0
Two cycles with two clocks
3.0
5.0
16.0
6.13.2 Crystal Oscillator/Ceramic Resonators (XTAL)
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation and such circuitry are depicted in the
following Figures. The same thing applies whether it is in HXT mode or in LXT mode.
Table 10 provides the recommended values of C1 and C2. Since each resonator has
its own attribute, user should refer to its specification for appropriate values of C1 and
C2. The serial resistor, RS, may be necessary for AT strip cut crystal or low frequency
mode.
C1
C1
OSC
I
Xin
XTAL
RS
XTAL
RS
OSCO
Xout
C2
C2
Figure 6-31 Crystal/Resonator Circuits
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129
EM78P528N
8-Bit Microprocessor with OTP ROM
Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode Frequency
C1 (pF)
C2 (pF)
100kHz
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
0F
60pF
60pF
40pF
30pF
0pF
200kHz
455kHz
1.0 MHz
1.0 MHz
2.0 MHz
4.0 MHz
100kHz
200kHz
455kHz
1.0 MHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MH
LXT
(100K~1 MHz)
Main-oscillator
(Ceramic Resonators)
HXT2
(1M~6 MHz)
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
20pF
LXT
(100K~1 MHz)
XT
Main-oscillator
(Crystal Oscillator)
(1M~6 MHz)
6.0 MHz
8.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
30pF
20pF
30pF
30pF
20pF
HXT2
(6M~12 MHz)
HX1
(12M~16 MHz)
LXT2
Sub-oscillator
(Crystal Oscillator)
32.768kHz
35pF
35pF
(32.768kHz)
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EM78P528N
8-Bit Microprocessor with OTP ROM
6.13.3 Internal RC Oscillator Mode
EM78P528N offer a versatile internal RC mode with default frequency value of 4MHz.
The Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz and 1 MHz)
that can be set by Code Option: RCM1 and RCM0. All these four main frequencies can
be calibrated by programming the Code Option bits: C5~C0. The table describes a
typical instance of the calibration.
Internal RC Drift Rate (Ta=25C, VDD=5V±5%, VSS=0V)
Drift Rate
Internal RC
Frequency
Temperature
(-40℃~+85℃)
Voltage
(2.5V~5.5V)
Process
Total
1 MHz
4 MHz
8 MHz
16 MHz
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
Note: These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
6.14 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes to a steady state. The EM78P528N is equipped with a built-in
Power-On Voltage Detector (POVD) with a detecting level of 2.0V. It will work well if
VDD rises fast enough (50ms or less). However, in many critical applications, extra
devices are still required to assist in solving power-up problems.
6.15 External Power-on Reset Circuit
The circuits shown in Figure 6-32 implement an external RC to generate a reset pulse.
The pulse width (time constant) should be kept long enough for VDD to reach minimum
operating voltage. Apply this circuit when the power supply has a slow rising time.
Since the current leakage from the /RESET pin is about 5 A, it is recommended that
R should not be greater than 40 KΩ in order for the /RESET pin voltage to remain at
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor (C) will discharge rapidly and fully. The current-limited resistor (Rin) will
prevent high current or ESD (electrostatic discharge) from flowing to Pin /RESET.
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131
EM78P528N
8-Bit Microprocessor with OTP ROM
VDD
D
VDD
/RESET
R
C
Rin
Figure 6-32 External Power-up Reset Circuit
6.16 Residue-Voltage Protection
When the battery is replaced, device power (VDD) is taken off but residue-voltage
remains. The residue-voltage may trip below VDD minimum, but not to zero. This
condition may cause a poor power-on reset. The following Figures 6-33a and 6-33b
show how to build and accomplish a proper residue-voltage protection circuit.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-33a Residue Voltage Protection Circuit 1
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EM78P528N
8-Bit Microprocessor with OTP ROM
VDD
VDD
R1
Q1
R3
/RESET
R2
Figure 6-33b Residue Voltage Protection Circuit 2
6.17 Code Option
6.17.1 Code Option Register (Word 0)
Word 0
Bit
Bit 14Bit 13Bit 12 Bit11 Bit10 Bit9 Bit8 Bit7
Bit6
Bit5
Bit4
Bit3 Bit2 Bit1 Bit0
Mnemonic
-
-
-
-
-
-
-
-
HLFS HLP LVR1 LVR0 RESETEN ENWDT NRHL NRE PR2 PR1 PR0
1
0
Normal High High High
P57
Disable 32/fc Enable
Disable
Enable
1
-
-
-
-
Green Low Low Low /RESET1 Enable 8/fc Disable
Default
1
1
1
1
1
0
1
1
1
1
1
1
Bits 14~11: Not used, set to "1" all the time.
Bit 10 (HLFS): Reset to Normal or Green Mode Select Bit
0: CPU is selected as Green mode when a reset occurs.
1: CPU is selected as Normal mode when a reset occurs (default)
Bit 9 (HLP): Power Consumption Selection
0: Low power consumption, apply to working frequency at 4 MHz or
below 4 MHz
1: High power consumption, apply to working frequency above 4 MHz
Bits 8~7 (LVR1~LVR0): Low voltage reset enable bit.
VDD Release Level
LVR1
LVR0
VDD Reset Level
0
0
4.0V
3.5V
2.7V
4.2V
3.7V
2.9V
0
1
1
0
1
1
NA ( Power-on Reset )
If VDD < 4.0V and is kept for about 5 µs, IC will be reset.
If VDD < 3.5V and is kept for about 5 µs, IC will be reset.
If VDD < 2.7V and is kept for about 5 µs, IC will be reset.
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133
EM78P528N
8-Bit Microprocessor with OTP ROM
Bit 6 (RESETEN): P57//RESET1 pin selection bit
0: Enable, /RESET1 pin. The initial value of Bank 1-R8<7> (PH57) will
be set to “0” (enable internal pull-high).
1: Disable, P57 pin (default)
Bit 5 (ENWDT): WDT enable bit
0: Enable
1: Disable (default)
Bit 4 (NRHL): Noise rejection high/low pulse define bit.
0: pulses equal to 8/fc is regarded as signal
1: pulses equal to 32/fc is regarded as signal (default)
NOTE
In Low XTAL oscillator (LXT) mode, the noise rejection high/low
pulses are always 8/Fm.
Bit 3 (NRE): Noise Rejection Enable bit
0: Disable
1: Enable (default). But in Green, Idle, and Sleep modes the noise
rejection circuit is always disabled.
Bits 2~0 (PR2~PR0): Protect Bits. Each protect status is as follows:
(only for real chip)
PR2
0
PR1
0
PR0
0
Protect
Enable
Disable
1
1
1
6.17.2 Code Option Register (Word 1)
Word 1
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic FSS1 FSS0 C5
C4
C3
C2
C1
C0 RCM1 RCM0
-
-
OSC2 OSC1 OSC0 RCOUT
1
0
High High High High High High High High High High
Low Low Low Low Low Low Low Low Low Low
High High High High
-
Low Low Low
Low
1
Default
1
1
1
1
1
1
1
1
1
1
1
0
1
1
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EM78P528N
8-Bit Microprocessor with OTP ROM
Bits 14~13 (FSS1~FSS0): Sub-oscillator mode select bits.
Sub-oscillator mode
FSS1
FSS0
LXT2 mode
Frequency range: 32.768kHz
0
x
Fs is 32kHz, Xin (P55) / Xout (P56) pin act as I/O
1
1
0
1
Fs is 16kHz, Xin (P55) / Xout (P56) pin act as I/O (default)
Note: WDT frequency is always 16kHz whatever the FSS1~0 bits are set.
Bits 12~7 (C5~C0): IRC trim bits. These are automatically set by the writer.
Bits 6~5 (RCM1~RCM0): IRC frequency select bits
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4 (default)
Bit 4: Not used, set to "1" all the time.
Bits 3~1 (OSC2~OSC0): Main-oscillator mode select bits.
Main-oscillator Mode
OSC2
OSC1
OSC0
HXT1 (High XTAL1 oscillator mode)
Frequency range: 16~12 MHz
1
1
1
HXT2(High XTAL2 oscillator mode)
Frequency range: 12~6 MHz
1
1
1
0
0
1
0
0
1
0
1
0
XT (XTAL oscillator mode)
Frequency range: 6~1 MHz
LXT1 (Low XTAL1 oscillator mode)
Frequency range: 1M~100kHz
0
IRC (Internal RC oscillator mode) (default)
RCOUT (P54) acts as I/O pin
X
X
IRC (Internal RC oscillator mode)
RCOUT (P54) acts as clock output pin
Bit 0 (RCOUT): System Clock Output Enable Bit in IRC mode
0: OSCI pin is open drain
1: OSCI output instruction cycle time (default)
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
135
EM78P528N
8-Bit Microprocessor with OTP ROM
6.17.3 Code Option Register (Word 2)
Word 2
Bit
Bit 14 Bit 13 Bit 12 Bit11 Bit10 Bit9 Bit8 Bit7
Bit6
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Mnemonic
-
-
-
-
-
-
SC3 SC2 SC1 SC0
High High High High
Low Low Low Low
-
-
IRCIRS
Regulator
Bandgap
1
-
-
I2COPT
High
Low
1
-
-
-
-
-
-
-
-
1
0
-
-
-
-
-
-
-
-
-
Default
0
1
1
1
1
1
1
1
0
0
0
1
0
Bit 14: Not used, set to “0” all the time.
Bits 13~12: Not used, set to “1” all the time.
Bits 11~8 (SC3~SC0): Trim bits of sub frequency IRC. These are automatically set by
the writer.
Bit 7: Not used, set to “1” all the time.
Bit 6 (IRCIRS): IRC Internal Reference Select
0: Bandgap
1: IRC regulator (default)
Bit 5: Not used, set to “0” all the time.
Bit 4 (I2COPT): I2C optional bit. It is used to switch the pin position of I2C function.
0: Placed I2C pins together with UART pins shown in the Pin Assignment
figure.
1: Placed I2C pins together with SPI pins shown in the Pin Assignment
figure (default)
Bit 3: Not used, set to “0” all the time.
Bit 2: Not used, set to “0” all the time.
Bit 1: Not used, set to “1” all the time.
Bit 0: Not used, set to “0” all the time.
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EM78P528N
8-Bit Microprocessor with OTP ROM
6.17.4 Code Option Register (Word 3)
Word 3
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic EFTIM
-
-
-
-
ADFM
High
Low
1
-
-
-
-
-
-
-
-
-
ID5 ID4 ID3 ID2 ID1 ID0
1
0
Light
Heavy
1
-
-
-
-
-
-
-
-
Customer ID
Default
1
1
1
1
1
1
1
Bits 14 (EFTIM): Low Pass Filter (0: Heavy, 1: Light)
0: Less than 10 MHz - pass (heavy LPS)
1: Less than 25 MHz - pass (light LPS, default)
Bits13~12: Not used. Set to “1” all the time.
Bit 11 (ADFM): These bits control the AD data buffer format (ADDH and ADDL).
Refer to the following table.
ADFM
ADDH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADD11ADD10 ADD9 ADD8
-
-
-
-
0
ADDL ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
ADDH ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
12
bits
1
ADDL
-
-
-
-
ADD3 ADD2 ADD1 ADD0
Note: Do not use if the hardware bits are set to “0”.
If ADFM=0, ADDH<7:4> = 0000.
Bits 10~6: Not used. Set to “1” all the time.
Bits 5~0 (ID5~ID0): Customer’s ID Code (only for real chip)
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137
EM78P528N
8-Bit Microprocessor with OTP ROM
6.18 Instruction Set
Each instruction in the instruction set is a 15-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case, the
execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
The conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were
tested to be true, are executed within two instruction cycles. The instructions that are
written to the program counter also take two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly (except read only)
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Instruction Set Convention:
R = Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which
affects the operation.
k = 8 or 12-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
None
C
DAA
DecimalAdjustA
0 WDT, Stop oscillator
0 WDT
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
A R
SLEP
T,P
WDTC
ENI
T,P
None
None
None
None
None
Z
DISI
RET
RETI
MOV R,A
CLRA
CLR R
SUBA,R
0 A
0 R
R-A A
Z
Z, C, DC
SUB R,A
R-A R
Z, C, DC
DECAR
DEC R
ORA,R
OR R,A
R-1 A
Z
Z
Z
Z
R-1 R
A R A
A R R
138
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Mnemonic
ANDA,R
AND R,A
XORA,R
XOR R,A
ADDA,R
ADD R,A
MOVA,R
MOV R,R
COMAR
COM R
Operation
Status Affected
A& R A
A& R R
A R A
A R R
A+ R A
A+ R R
R A
R R
/R A
/R R
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
INCAR
R+1 A
R+1 R
Z
INC R
Z
DJZAR
R-1 A, skip if zero
R-1 R, skip if zero
None
None
DJZ R
R(n) A(n-1),
RRCAR
RRC R
C
C
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
RLCAR
RLC R
C
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
C
R(0-3) A(4-7),
R(4-7) A(0-3)
SWAPAR
None
SWAP R
JZAR
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
None
None
None
None
None
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
PC+1 [SP],
(Page, k) PC
CALLk
None
JMP k
(Page, k) PC
k A
A k A
A& k A
A k A
None
None
Z
MOVA,k
ORA,k
ANDA,k
XORA,k
Z
Z
k A,
[Top of Stack] PC
RETLk
None
SUBA,k
k-A A
k+A A
K->R1(4)
K->R1(0)
Z, C, DC
Z, C, DC
None
ADDA,k
SBANK k
GBANK k
None
Next instruction : k kkkk kkkk kkkk
PC+1 [SP], k PC
LCALLk
None
Next instruction : k kkkk kkkk kkkk
K PC
ROM[(TABPTR)] R
LJMP k
None
None
TBRD R
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
139
EM78P528N
8-Bit Microprocessor with OTP ROM
7 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
to
to
to
to
to
to
-40C
-65C
85C
150C
VSS-0.3V
VSS-0.3V
2.1V
VDD+0.5V
VDD+0.5V
5.5V
Output voltage
Operating Voltage
Operating Frequency
DC
16 MHz
8 DC Electrical Characteristics
VDD=5.0V, VSS=0V, Ta=25C
Symbol
Parameter
XTAL: VDD to 3V
Condition
Min. Typ.
Max.
Unit
MHz
MHz
Hz
DC
8
16
F
Two cycles with two clocks
XTAL: VDD to 5V
DC
Fxt
IRC: VDD to 5V
4 MHz, 1 MHz, 8kHz, 16 MHz
Internal RC oscillator error per stage
IRCE
±1
4
%
RCM0:RCM1=1:1
IRC1 IRC:VDD to 5V
IRC2 IRC:VDD to 5V
IRC3 IRC:VDD to 5V
IRC4 IRC:VDD to 5V
MHz
MHz
MHz
MHz
RCM0:RCM1=1:0
RCM0:RCM1=0:1
RCM0:RCM1=0:0
8
16
1
IIL
Input Leakage Current for input pins VIN = VDD, VSS
-1
0
1
A
V
VIH1 Input High Voltage (Schmitt Trigger) Ports 5, 6, 7, 8, 9, A
VIL1 Input Low Voltage (Schmitt Trigger) Ports 5, 6, 7, 8, 9, A
Input High Threshold Voltage
0.7VDD
-0.3V
VDD+0.3V
0.3VDD
V
VIHT1
VILT1
VIHT2
VILT2
/RESET
/RESET
TCC, INT
TCC, INT
0.7VDD
-0.3V
VDD+0.3V
0.3VDD
V
V
V
(Schmitt Trigger )
Input Low Threshold Voltage
(Schmitt Trigger )
Input High Threshold Voltage
(Schmitt Trigger )
0.7VDD
VDD+0.3V
Input Low Threshold Voltage
(Schmitt Trigger )
-0.3V
0.3VDD
3.1
V
V
OSCI in crystal mode
OSCI in crystal mode
VIHX1 Clock Input High Voltage
VILX1 Clock Input Low Voltage
2.9
3.0
1.7
-2.7
-4.8
8.4
1.8
-4.5
-8
1.9
V
IOH1 High Drive Current 1 (Ports 5~9, A) VOH = VDD-0.1VDD
IOH2 High Drive Current 2 (Ports 5~9, A) VOH = VDD-0.1VDD
mA
mA
mA
mA
IOL1 Low Sink Current 1 (Ports 5~9, A)
IOL2 Low Sink Current 2 (Ports 5~9, A)
VOL = GND+0.1VDD
VOL = GND+0.1VDD
14
16.8
28
Pull-high active, input pin @
VSS
IPH Pull-high current
47
27
-72
97
77
A
A
Pull-low active, input pin @
VDD
IPL
Pull-low current
52
Symbol
Parameter
Condition
Min. Typ. Max. Unit
140
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Ta = 25C
Ta = -40C ~ 85C
Ta = 25C
Ta = -40C ~ 85C
Ta = 25C
Ta = -40C ~ 85C
2.41
2.14
3.1
2.7
2.7
3.5
3.5
4.0
4.0
2.99
3.25
3.92
4.25
4.43
4.81
V
V
V
V
V
V
Low voltage reset
Level 1 (2.7V)
LVR1
LVR2
LVR3
Low voltage reset
Level 2 (3.5V)
2.73
3.56
3.16
Low voltage reset
Level 3 (4.0V)
Ta=25C, /RESET= 'High', Fm & Fs off
All input and I/O pins at VDD,
Output pin floating, WDT disabled
1
2
2.5
A
A
A
A
A
A
Power down current
(Sleep mode)
ISB1
Ta=85C, /RESET= 'High', Fm & Fs off
All input and I/O pins at VDD,
Output pin floating, WDT disabled
2
/RESET= 'High', Fm & Fs off
All input and I/O pins at VDD,
Output pin floating, WDT enabled
Power down current
(Sleep mode)
ISB2
ISB3
ISB4
ISB5
4.2
5.6
19
22
/RESET= 'High', Fm off, Fs=16kHz
(IRC type), All input and I/O pins at VDD,
Output pin floating, WDT enabled
Power down current
(Idle mode)
/RESET= 'High', Fm off, Fs=32kHz
(IRC type), Output pin floating, WDT disabled,
LCD on (1/3 bias, RBS1~0=00)
Power down current
(Idle mode)
/RESET= 'High', Fm off, Fs=32.768kHz
(Crystal type), Output pin floating, WDT
disabled, LCD on (1/3 bias, RBS1~0=00)
Power down current
(Idle mode)
Operating supply current /RESET= 'High', Fm off, Fs=16kHz
ICC1
ICC2
12.8
17.6
A
A
(Green mode)
(IRC type), output pin floating, WDT enabled
Operating supply current
(Green mode)
/RESET= 'High', Fm off, Fs=32kHz
(IRC type), Output pin floating, WDT enabled
/RESET= 'High', Fm off, Fs=32.768kHz
(Crystal type), output pin floating, WDT
enabled
Operating supply current
(Green mode)
ICC3
24.5
A
Operating supply current /RESET= 'High', Fm=4 MHz (Crystal type), Fs
(Normal mode) on, output pin floating, WDT enabled
Operating supply current /RESET= 'High', Fm=4 MHz (IRC type), Fs on,
ICC4
ICC5
1.6
1.5
mA
mA
(Normal mode)
output pin floating, WDT enabled
/RESET= ‘High’, Fm=10 MHz
(Crystal type), Fs on, output pin floating,
WDT enabled
Operating supply current
(Normal mode)
ICC6
3.6
mA
Operating supply current /RESET= ‘High’, Fm=16 MHz (IRC type), Fs
(Normal mode) on, output pin floating, WDT enabled
Operating supply current /RESET= ‘High’, Fm=16 MHz (Crystal type),
ICC7
ICC8
4.6
5.7
12
mA
mA
A
A
A
A
(Normal mode)
Fs on, output pin floating, WDT enabled
VLCD=5V, exclude CPU core operation
current (no load), 1/3 bias, RBS1~0=00
ILCD1 All LCD lighting
ILCD2 All LCD lighting
ILCD3 All LCD lighting
ILCD4 All LCD lighting
VLCD=5V, exclude CPU core operation
current (no load), 1/3 bias, RBS1~0=01
20
VLCD=5V, exclude CPU core operation
current (no load), 1/3 bias, RBS1~0=10
33.5
100
VLCD=5V, exclude CPU core operation
current (no load), 1/3 bias, RBS1~0=11
* These parameters are characterize but not tested.
** Data in the Minimum, Typical, and Maximum (“Min.”, “Typ.”, “Max.”) columns are based on
characterization results at 25C. These data are for design reference only and have not been tested.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
141
EM78P528N
8-Bit Microprocessor with OTP ROM
8.1 AD Converter Characteristics
VDD=5V, VSS=0V, Ta=25 C
Symbol
VAREF
VASS
Parameter
Condition
Min.
2.5
Typ.
Max. Unit
VDD
VSS
V
V
V
Analog reference
voltage
VAREF-VASS ≧ 2.5V
VSS
VASS
VAI
Analog input voltage
VAREF
VAREF = VDD = 5.5V
VASS = VSS = 0V
Ivdd
IAI1
1400
10
A
A
A
A
Analog supply current
Analog supply current
FS=100kHz, FIN=1kHz
(VREF is internal VDD)
Ivref
VAREF = VDD = 5.5V
VASS = VSS = 0V
Ivdd
IAI2
900
500
FS=100kHz, FIN=1kHz
(VREF is external VREF pin)
Ivref
VAREF = VDD = 5V
VASS = VSS = 0V
INL
Integral nonlinearity
Differential nonlinear
±4
±1
LSB
LSB
FS=100kHz, FIN=1kHz
VAREF = VDD = 5V
VASS = VSS = 0V
DNL
FS=100kHz, FIN=1kHz
VAREF = VDD = 5V
FSE
OE
Full scale error
Offset error
±8
±4
LSB
LSB
VASS = VSS = 0V, Fs=100kHz
VAREF = VDD = 5V
VASS = VSS = 0V, Fs=100kHz
Recommended
ZAI
impedance of analog
voltage source
10
k
VDD = 3V~5.5V
0.5
2
s
s
VASS = VSS = 0V, FIN=1kHz
TAD
A/D clock duration
VDD = 2.5V~3V
VASS = VSS = 0V, FIN=1kHz
VDD = 3V~5.5V
VASS = VSS = 0V
4
s
TSH
TCN
Sample and Hold time
A/D conversion time
VDD = 2.5V~3V
VASS = VSS = 0V
16
s
VDD = 2.5V~5V
VASS = VSS = 0V
Tsh+12TAD
TAD
142
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
AD delay time between
TADD1 setting “ADRUN” and
starting 1st TAD
VDD=2.5~5.5V, VASS=0.0V
0.5
TAD
TAD
TAD
TAD
AD delay time between
TADD2 changing “ADOM” and VDD=2.5~5.5V, VASS=0.0V
setting “ADRUN”
2
2
2
AD delay time between
TADD3 changing “ADIS” and
setting “ADRUN”
VDD=2.5~5.5V, VASS=0.0V
AD delay time between
TADD4 changing “ADP” and
setting “ADRUN”
VDD=2.5~5.5V, VASS=0.0V
VDD = 2.5 ~ 5.5V, VAREF = 2.5V,
Power supply rejection
PSRR
ratio
2
LSB
%
VASS = VSS = 0V, Vin = 0 ~ 2.5V,
FS = 25kHz
A1/4VDD Accuracy for 1/4VDD
±3
Note:
1. FS is Sample Rate or conversion rate. FIN is freq. of input test sine wave
2. The parameters are theoretical values and have not been tested. Such parameters are for
design reference only.
3. There is no current consumption when ADC is off other than minor leakage current.
4. AD conversion result will not decrease when the input voltage is increased, and there is no
missing code.
5. These parameters are subject to change without further notice.
8.2 VREF 2V/3V/4V Characteristics
VDD=5V, VSS=0V, Ta=25C
Symbol
VDD
Parameter
Condition
Min.
2.1
Typ.
Max.
5.5
Unit
V
Power Supply
–
IVDD
DC Supply Current No load
250
µA
%
AVref
Accuracy for Vref Vref = 2V, 3V, 4V
VDD = VDDmin - 5.5V,
±1
±1.75
Warn up Time ready for
time
Cload = 19.2pf
Rload = 15.36K
30
50
µs
V
voltage reference
Minimum
Power Supply
VDDmin
Vref + 0.2
* VDDmin : Can also work at Vref+0.1V, but has a poor PSRR.
Note:
1. The parameters are theoretical values and have not been tested. Such parameters are for
design reference only.
2. These parameters are subject to change without prior notice.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
143
EM78P528N
8-Bit Microprocessor with OTP ROM
9 AC Electrical Characteristics
Ta=25C, VDD=5V ± 5%, VSS=0V
Symbol
Parameter
Input CLK duty cycle
Conditions
Min.
Typ.
Max. Unit
55
Dclk
Crystal type
IRC type
45
50
%
125
125
Tins
DC ns
DC ns
Tins
Ttcx
Tpor
Instruction Cycle Time
TCX Input Period
ns
Delay time after Power-on-Reset
16kHz
16±3%
ms
release
Crystal type, HLFS=1
IRC type, HLFS=1
Crystal type, HLFS=0
IRC type, HLFS=0
WSTO+510/Fm
WSTO+8/Fm
WSTO+510/Fs
WSTO+8/Fs
1
Delay time after /RESET,
WDT and LVR release
Trstrl
Hold time after /RESET and LVR reset
Watchdog timer period
Input pin setup time
Trsth
Twdt
Tset
s
16kHz
16±3%
ms
ns
0
Input pin hold time
Thold
15
20
25 ns
ns
Cload=20pF
Rload=1M
Tdelay Output pin delay time
20
Note: * Tpor and Twdt are16+/- 10% ms at Ta = -40 ~ 85C, and VDD = 2.1~5.5V
** WSTO: Waiting time of Start-to-Oscillation
1. These parameters are hypothetical (not tested) and are provided for design reference only.
2. Data under Minimum, Typical and Maximum (Min., Typ. and Max.) columns are based on
hypothetical results at 25C. These data are for design reference only and have not been
tested or verified.
144
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input / Output Waveform
VDD-0.5
0.75VDD
TEST POINTS
0.75VDD
0.25VDD
0.25VDD
GND+0.5
Note: AC Testing: Input are driven at VDD-0.5V for logic “1,” and VSS+0.5V for logic “0”
Timing measurements are made at 0.75VDD for logic “1,” and 0.25VDD for logic “0”
Figure 10-1a AC Test Input / Output Waveform Timing Diagram
Reset Timing
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 10-1b Reset Timing Diagram
TCC Input Timing
ins
CLK
TCC
tcc
Figure 10-1c TCC Input Timing Diagram
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
145
EM78P528N
8-Bit Microprocessor with OTP ROM
APPENDIX
A Ordering and Manufacturing Information
EM78P528NL48J
Material Type
J: RoHS complied
Pin Number
Package Type
Q: QFP
L: LQFP
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P528NL48J
is EM78P528N with OTP program memory, product,
in 48-pin LQFP 7x7mm package with RoHS complied
‧‧‧‧‧‧‧
Elan Product Number
EM78Paaaa
1041 bbbbbb
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
146
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
Ordering Code
EM78P528NL44J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
OTP MCU
EM78P528NQ44
Package Type
Pin Count
Package Size
QFP
LQFP
LQFP
44
44
48
10 mm 10 mm
10 mm 10 mm
7 mm 7 mm
EM78P528NL44
EM78P528NL48
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
Electroplate type
EM78P528NxJ / xS
Pure Tin
Ingredient (%)
Sn:100%
°
Melting point (°C)
Electrical resistivity ( μ-cm )
Hardness (hv)
232 C
11.4
8~10
>50%
Elongation (%)
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
147
EM78P528N
8-Bit Microprocessor with OTP ROM
C Package Information
C.1 EM78P528NQ44
Figure B-1 EM78P528N 44-pin QFP Package Type
148
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
C.2 EM78P528NL44
Figure B-2 EM78P528N 44-pin LQFP Package Type
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
149
EM78P528N
8-Bit Microprocessor with OTP ROM
C.3 EM78P528NL48
Figure B-3 EM78P528N 48-pin LQFP Package Type
150
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=2455C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
Step 1: TCT, 65C (15 min)~150C (15 min), 10 cycles
Step 2: Bake at 125C, TD (endurance)=24 hrs
Step 3: Soak at 30C/60% , TD (endurance)=192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5mm or
Pkg volume 350 mm3 ----2255C)
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ----2405C )
Temperature cycle test -65C (15mins)~150C (15min), 200 cycles
TA =121C, RH=100%, pressure = 2 atm,
Pressure cooker test
TD (endurance)= 96 hrs
High temperature /
TA=85C , RH=85% , TD (endurance)=168 , 500 hrs
High humidity test
High-temperature
TA=150C, TD (endurance)=500, 1000 hrs
storage life
High-temperature
operating life
TA=125C, VDD=Max. operating voltage,
TD (endurance) =168, 500, 1000 hrs
Latch-up
TA=25C, VDD=Max. operating voltage, 800mA/40V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
TA=25C, | ± 4KV |
ESD (MM)
TA=25C, | ± 400V |
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise caused address error is detected, the MCU will repeat execution of the program
until the noise is eliminated. The MCU will then continue to execute the next program.
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
151
EM78P528N
8-Bit Microprocessor with OTP ROM
E EM78P528N Program Pin List
UWTR is used to program the EM78P528N IC’s. The UWTR connector is selected by
UWTR-ADP050-C. The software is selected by EM78P528N.
L/QFP-44
LQFP-48
Program Pin Name
IC Pin Name
Pin Number
Pin Number
CLK
DATA
VDD
VSS
P50
P51
2
3
5
6
9
2
3
5
6
9
VDD
VSS
VPP
/RESET2
F ICE 400 Oscillator Circuit (JP3)
F.1 Mode 1
Main oscillator : Crystal mode
Sub oscillator : Crystal mode
C4
Y2
C5
Sub oscillator
GND Xout
Xout
Xout GND
Xin
Xin
Xin
GND GND
GND OSCO OSCO OSCO GND OSCI OSCI OSCI GND GND
Main oscillator
C1
Y1
C2
152
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
EM78P528N
8-Bit Microprocessor with OTP ROM
F.2 Mode 2
Main oscillator : IRC mode
Sub oscillator : Crystal mode
C4
Y2
C5
Sub oscillator
GND Xout
Xout
Xout GND
Xin
Xin
Xin
GND GND
GND OSCO OSCO OSCO GND OSCI OSCI OSCI GND GND
Main oscillator
F.3 Mode 3
Main oscillator : Crystal mode
Sub oscillator : IRC mode
Sub oscillator
GND Xout
Xout
Xout GND
Xin
Xin
Xin
GND GND
GND OSCO OSCO OSCO GND OSCI OSCI OSCI GND GND
Main oscillator
C1
Y1
C2
F.4 Mode 4
Main oscillator : IRC mode
Sub oscillator : IRC mode
Sub oscillator
GND Xout
Xout
Xout GND
Xin
Xin
Xin
GND GND
GND OSCO OSCO OSCO GND OSCI OSCI OSCI GND GND
Main oscillator
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
153
EM78P528N
8-Bit Microprocessor with OTP ROM
154
Product Specification (V1.4) 03.31.2016
(This specification is subject to change without prior notice)
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