EM6321FP32EW-10LF [EMLSI]
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM; 128K ×8位超低功耗和低电压全CMOS静态RAM
| 型号： | EM6321FP32EW-10LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Document Title
Low Power, 128Kx8 SRAM
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
Initial Draft
2’ nd Draft
May 9 , 2003
February 13 , 2004
Add Pb-free part number
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.18mm Full CMOS
• Organization : 128K x 8 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V(Min)
• Three state output and TTL Compatible
• Package Type : 32-TSOP1
The EM610FV8T families are fabricated by EMLSI’ s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
PKG
Type
Speed
Standby
(ISB1, Typ)
Operating
(ICC1.Max)
Industrial (-40 ~ 85oC)
2.7V~3.6V
551) / 70ns
0.5 mA2)
EM610FV8T
3 mA
32-TSOP1
1. The parameter is measured with 30pF test load.
2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
32
31
30
29
OE
A11
A9
A10
CS1
IO8
3
A8
Pre-charge Circuit
4
A13
5
28
IO7
IO6
WE
6
27
CS2
7
26
IO5
A15
32 - TSOP
Type1 - Forward
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
8
9
25
24
I O 4
VSS
VCC
NC
VCC
VSS
10
11
23
22
I/O3
I/O2
A16
A14
A12
Memory Array
12
13
21
20
I/O1
A0
A7
A6
1024 x 1024
14
15
19
A1
A5
A4
18
17
A2
A3
16
Data
Cont
I/O1 ~ I/O8
I/O Circuit
Column Select
Name
Function
Name
Function
A
A
14 15 16
A
A13
A10 A11
A
12
CS ,CS
Chip select inputs
WE Write Enable input
1
2
OE
Output Enable input
Address Inputs
Vcc Power Supply
Vss Ground
WE
OE
A ~A
0
16
Control Logic
CS1
CS2
I/O ~I/O
Data Inputs/outputs
NC
No Connection
1
8
2
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
Unit
V
-0.2 to Vcc+0.3 (Max. 4.0V)
-0.2 to 4.0V
1.0
V
PD
W
oC
Operating Temperature
TA
-40 to 85
* Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
H
X
L
L
L
X
L
X
X
H
L
X
X
H
H
L
High-Z
High-Z
Deselected
Deselected
Output Disabled
Read
Stand by
Stand by
Active
H
H
H
High-Z
Data Out
Data In
Active
X
Write
Active
Note: X means don’ t care. (Must be low or high state)
3
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Supply voltage
Symbol
Min
2.7
0
Typ
3.3
0
Max
3.6
0
Unit
V
VCC
VSS
VIH
VIL
Ground
V
VCC + 0.22)
0.6
Input high voltage
Input low voltage
2.2
-
-
V
V
-0.23)
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
VIO=0V
-
8
pF
pF
Input/Ouput capacitance
CIO
-
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
V
=V
to V
SS CC
Input leakage current
ILI
-1
-
-
-
1
1
3
mA
IN
Output leakage current
Operating power supply
ILO
ICC
CS =V , CS =V or OE=V or WE=V , V =V to V
-1
-
mA
1
IH
2
IL
IH
IL
IO
SS
CC
I
=0mA, CS =V , CS =WE=V , V =V or V
1 IL 2 IH IN IH IL
mA
IO
Cycle time=1ms, 100% duty, I =0mA,
IO
ICC1
-
-
3
mA
mA
CS <0.2V, CS >V -0.2V,
1
2
CC
V
<0.2V or V >V -0.2V
IN CC
IN
Average operating current
55ns
70ns
-
-
-
-
-
-
25
20
0.4
-
Cycle time = Min, I =0mA, 100% duty,
IO
ICC2
CS =V , CS =V
V =V or V
IH, IN IL IH
1
IL
2
I
I
= 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
VOL
VOH
ISB
-
V
V
OL
= -1.0mA
2.4
OH
CS =V , CS =V , Other inputs=V or V
IL
-
-
0.3
mA
1
IH
2
IL
IH
CS >V -0.2V, CS >V -0.2V (CS controlled)
1
CC
2
CC
1
or 0V<CS <0.2V (CS controlled),
2
2
LL
LF
Other inputs=0~V
0.51)
CC
ISB1
Standby Current (CMOS)
-
5
mA
o
(Typ. condition : V =3.3V @ 25 C)
CC
o
(Max. condition : V =3.6V @ 85 C)
CC
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
4
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=2.8V
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Read cycle time
Min
Max
Min
Max
tRC
tAA
tco1, tco2
tOE
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2
tOHZ
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
55
55
25
-
-
-
70
70
35
-
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
10
5
10
5
-
-
0
20
20
-
0
25
25
-
0
0
tOH
10
10
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW1, tCW2
tAs
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
60
0
-
Address valid to end of write
Write pulse width
tAW
45
40
0
-
60
50
0
-
tWP
-
-
Write recovery time
tWR
-
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tWHZ
tDW
0
20
0
20
25
0
30
0
tDH
-
-
-
-
tOW
5
5
5
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH
)
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS1
CS2
tHZ
tOE
OE
tOHZ
tOLZ
High-Z
Data Out
Data Valid
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW (2)
tWR(4)
CS1
CS2
tAW
tWP(1)
WE
tDH
tAS(3)
High-Z
tDW
High-Z
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
CS2
tAW
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) ( CS2 CONTROLLED)
tWC
Address
tCW(2)
tW R(4)
CS1
tAS(3)
CS2
tAW
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
when CS1 goes high, CS2 goes hagh and WE goes high. The tWP is measured from the beginning of write
to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE
going high.
8
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ2) Max
Unit
ISB1 Test Condition
1.5
-
3.6
-
V
1)
(Chip Disabled)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.25
mA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
2. Typical values are measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
CS1 Controlled
tRDR
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
1
CS1
GND
CS2 Controlled
Data Retention Mode
Vcc
2.7V
CS2
tRDR
tSDR
VDR
0.4V
CS < 0.2V
2
GND
9
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
Unit : millimeters/Inches
10
EM610FV8T Series
merging Memory & Logic Solutions Inc.
Low Power, 128Kx8 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
8. Version
Blank ----------------- Mother Die
2. Device Type
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------ 5.0V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free)
L ---------------------- Low Power
S ---------------------- Standard Power
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11
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