EM641FP8ET-12LF [EMLSI]
512K x8 bit Low Power Full CMOS Static RAM; 512K ×8位低功耗全CMOS静态RAM
| 型号： | EM641FP8ET-12LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 512K x8 bit Low Power Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM641FT8S Series
Low Power, 512Kx8 SRAM
Document Title
512K x8 bit Low Power Full CMOS Static RAM
Revision History
Revision No.
History
Initial Draft
0.1 Revision
Draft Date
Nov. 20, 2007
Dec. 5, 2007
Remark
0.0
0.1
Preliminary
IDR Current from 1.5uA to 7uA
tOE from 25nsec to 30nsec with 55ns part
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM641FT8S Series
Low Power, 512Kx8 SRAM
512K x8 Bit Low Power CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
- Very high speed : 45ns
- Process Technology : 0.15um Full CMOS
- Organization : 512K x8
The EM641FT8S is fabricated by EMLSI’s advanced full
CMOS process technology. The families support industrial
temperature range and Chip Scale Package for user flexi-
bility of system design. The families also supports low data
retention voltage for battery back-up operation with low
data retention current.
- Power Supply Voltage
=> EM641FT8S : 4.5V~5.5V
- Low Data Retention Voltage : 1.5V (MIN)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
- Package Type: 32L-STSOP
The EM641FT8S is available in KGD, JEDEC standard 32
pin 8.0mm x 13.4mm STSOP package.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
PKG Type
Standby
Operating
(ICC1.Max)
(ISB1, Typ.)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
EM641FT8S-45LF
EM641FT8S-55LF
EM641FT8S-70LF
4.5V~5.5V
4.5V~5.5V
4.5V~5.5V
45ns
55ns
70ns
1.5 µA
1.5 µA
1.5 µA
7mA
7mA
7mA
32-STSOP
32-STSOP
32-STSOP
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A
A
A
A
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
11
9
OE
A10
2
3
4
5
6
8
13
CS
A
0
I/O7
V
A
CC
1
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A
V
SS
WE
2
A
A
3
Memory Array
512K x 8
17
A
4
A15
7
A
5
V
A
8
CC
6
EM641FT8S
A
7
9
A
A
A
A
A
A
6
A
18
16
A
8
10
11
A
9
A
10
14
12
13
14
15
16
12
7
Data
Cont
I/O0 ~ I/O7
I/O Circuit
Column Select
5
A
4
A3
A
A
A
A
A
14 15 16
17
A
A
A
18
13
12
11
Name
CS
Function
Name
Function
Power Supply
Ground
WE
OE
CS
VCC
Chip select input
Output Enable input
Write Enable input
Address Inputs
Control Logic
VSS
OE
WE
A0~A18
I/O0~I/O7
Data Inputs/Outputs
2
EM641FT8S Series
Low Power, 512Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to VSS
Voltage on Vcc supply relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Minimum
-0.5 to 6.0V
-0.5 to 6.0V
1.0
Unit
V
V
PD
W
oC
Operating Temperature
TA
-40 to 85
Note : Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device.
Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
I/O0-7
Mode
Power
H
L
L
L
X
L
X
H
L
High-Z
Data Out
Data In
High-Z
Deselected/ Power down
Stand by
Active
Read
Write
X
H
Active
H
Selected, Output Disabled
Active
Note : X means don’t care. (Must be low or high state)
3
EM641FT8S Series
Low Power, 512Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Supply voltage
Symbol
Min
4.5
0
Typ
Max
Unit
2)
V
VCC
-
0
-
5.5
Ground
VSS
VIH
V
V
0
2.2
VCC + 0.53)
0.6
Input high voltage
-0.54)
Input low voltage
VIL
-
V
Notes :
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
Note : Capacitance is sampled, not 100% tested.
o
o
DC ELECTRICAL CHARACTERISTICS (T = -40 C to +85 C)
A
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
ILI
V
=V to V
SS CC
Input leakage current
-1
-1
-
-
-
-
-
1
1
5
7
uA
IN
CS=V or OE=V or WE=V
IL
IH
IH
ILO
ICC
Output leakage current
Operating power supply
uA
mA
mA
V
=V to V
SS CC
IO
I
=0mA, CS=V , V =V or V
IL
IO
IL
IN
IH
Cycle time=1µs, 100% duty, I =0mA,
CS<0.2V, V <0.2V or V >V -0.2V
IO
ICC1
-
IN
IN
CC
45ns
55ns
70ns
-
-
-
-
-
-
65
55
45
Average operating current
Cycle time = Min, I =0mA, 100% duty,
IO
ICC2
mA
CS=V , V =V or V
IH
IL
IN
IL
VOL
VOH
ISB
I
I
= 2.1mA
= -1.0mA
Output low voltage
Output high voltage
Standby Current (TTL)
-
2.4
-
-
-
-
0.4
-
V
V
OL
OH
CS=V , Other inputs=V or V
1
mA
IH
IH
IL
CS>V -0.2V
CC
Other inputs = 0~VCC
1)
ISB1
Standby Current (CMOS)
LF
-
20
uA
1.5
o
(Typ. condition : V =5V @ 25 C)
CC
o
(Max. condition : V =5.5V @ 85 C)
CC
NOTES :
1.Typical values are measured at Vcc=5V, TA=25oC and not 100% tested.
4
EM641FT8S Series
Low Power, 512Kx8 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
3)
VTM
Input Pulse Level : 0V to VCC
Input Rise and Fall Time : 1V/ns
Input and Output reference Voltage : 0.5VCC
Output Load (See right) : CL1) = 100pF + 1 TTL (70ns)
2)
R1
Output
CL1) = 30pF + 1 TTL (45ns/55ns)
Notes :
2)
CL1)
R2
1. Including scope and Jig capacitance
2. R1 = 1800 ohm,
3. VTM VCC
4. CL = 5pF + 1 TTL (measurement with tLZ, tOLZ, tHZ, tOHZ, tWHZ)
R2 = 990 ohm
=
o
o
READ CYCLE (V = 4.5V to 5.5V, GND = 0V, T = -40 C to +85 C)
cc
A
45ns
Max
55ns
Max
70ns
Max
Symbol
Parameter
Unit
Min
Min
Min
Read cycle time
tRC
tAA
45
-
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
45
45
25
-
-
-
55
55
30
-
-
-
70
70
35
-
Chip select to output
tCO
tOE
tLZ
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
-
10
5
10
5
10
5
tOLZ
tHZ
tOHZ
tOH
-
-
-
0
20
15
-
0
20
20
-
0
25
25
-
0
0
0
10
10
10
o
o
WRITE CYCLE (V = 4.5V to 5.5V, GND = 0V, T = -40 C to +85 C)
cc
Parameter
Write cycle time
A
45ns
55ns
Max
70ns
Unit
Symbol
Min
Max
Min
Min
Max
tWC
tCW
tAS
45
-
-
55
-
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
60
0
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
35
0
-
45
40
0
-
60
50
0
-
-
-
-
Write recovery time
-
-
-
Write to ouput high-Z
0
15
0
20
0
20
Data to write time overlap
Data hold from write time
End of write to output low-Z
25
0
25
0
30
0
-
-
-
-
-
-
tOW
5
5
5
5
EM641FT8S Series
Low Power, 512Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Transition Controlled)
tRC
Address
tAA
tOH
Previous Data Valid
Data Out
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (OE Controlled)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
High-Z
High-Z
Data Out
Data Valid
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM641FT8S Series
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled, OE High During WRITE)
tWC
Address
CS
2)
4)
tCW
tWR
tAW
tWP
1)
WE
3)
tAS
OE
tDH
tDW
High-Z
High-Z
Data in
Data Valid
tOHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
3)
2)
4)
tAS
tCW
tWR
CS
tAW
tWP
1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM641FT8S Series
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (WE Controlled, OE LOW)
tWC
Address
CS
4)
tWR
2)
tCW
tAW
3)
1)
tAS
tWP
WE
tDH
tDW
High-Z
High-Z
Data in
Data Valid
tWHZ
Data Undefined
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among
CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EM641FT8S Series
Low Power, 512Kx8 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ2)
Max
Unit
ISB1 Test Condition
(Chip Disabled) 1)
1.5
-
-
V
ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
1
7
µA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the ISB1 measurement condition of data sheet page 4.
2. Typical value is measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
tRDR
tSDR
Data Retention Mode
Vcc
5V
2.2V
VDR
V
1.5V
DR
CS > Vcc-0.2V
CS
GND
9
EM641FT8S Series
Low Power, 512Kx8 SRAM
PACKAGE DIMENSIONS
32Pin - sTSOP Type1
Unit : millimeters/Inches
13.40+/-0.20
0.528+/- 0.008
0.10
MAX
0.004
+0.10
0.20
0.008-0.002
#1
-0.05
+0.004
#32
0.25
(
)
0.010
8.40
0.331
8.00
0.315
MAX
0.50
0.0197
#16
#17
1.00 +/-0.10
0.039+/-0.004
0.05
MIN
0.25
TYP
11.80 +/-0.10
0.465+/- 0.004
0.002
0.010
+0.10
-0.05
+0.004
0.15
1.20
MAX
0.006-0.002 0.047
0~8
0.50
0.020
0.45~0.75
0.018~0.030
)
(
10
EM641FT8S Series
Low Power, 512Kx8 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Product Type
3. Density
11. Power
10. Speed
4. Function
9. Package
8. Generation
7. Organization
5. Technology
6. Operating Voltage
1. Memory Component
7. Organization
EM --------------------- Memory
8 ---------------------- x8 bit
16 ---------------------- x16 bit
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
9. Package
2 ----------------------- Multiplexed
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V --------------------- 32 SOP
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
5. Technology
F ------------------------- Full CMOS
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 ---------------------- 100ns
12 ---------------------- 120ns
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
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