EM680FU16A [EMLSI]
Low Power, 512Kx16 SRAM; 低功耗， 512Kx16 SRAM
| 型号： | EM680FU16A |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | Low Power, 512Kx16 SRAM |
| 文件： | 总11页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM680FU16A Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
Sep. 28 , 2007
Nov. 12, 2007
Remark
0.0
0.1
Initial Draft
0.1 Revision
Preliminary
Fix typo error
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM680FU16A Series
Low Power, 512Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.15µm Full CMOS
• Organization : 512K x 16 bit
• Power Supply Voltage : 2.7V ~ 3.3V
• Low Data Retention Voltage : 1.5V(Min.)
• Three state output and TTL Compatible
• Package Type : 48-FPBGA 8.0x10.0
The EM680FU16A families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
PKG
Type
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1.Max)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
EM680FU16A-45LF
EM680FU16A-55LF
EM680FU16A-70LF
2.7V~3.3V
2.7V~3.3V
2.7V~3.3V
45ns
55ns
70ns
2 µA
2 µA
2 µA
3mA
3mA
3mA
48-FPBGA
48-FPBGA
48-FPBGA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
1
2
3
4
5
6
Pre-charge Circuit
A
B
C
D
E
LB
I/O
OE
UB
A
A
A
A
A
A
A
A
2
CS2
0
3
5
1
4
6
7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VSS
CS1 I/O
9
1
3
Memory Array
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
2
4
5
6
2048 x 4096
V
V
I/O
I/O
I/O
A
V
CC
SS
17
Data
Cont
I/O1 ~ I/O8
DNU
A
A
A
A
V
SS
CC
16
15
13
10
I/O Circuit
Data
Cont
I/O9 ~ I/O16
Column Select
F
I/O
A
A
I/O
15
16
14
12
7
8
G
H
I/O
DNU
WE I/O
A11 A12 A13 A14 A15 A16
A
17 A18
A
A
A
A
11
DNU
18
8
9
WE
OE
48-FPBGA : Top view (ball down)
UB
Control Logic
LB
CS1
CS2
Name
Function
Name
Function
CS1,CS2 Chip select inputs
Vcc Power Supply
Vss Ground
OE
Output Enable input
Write Enable input
WE
UB Upper Byte (I/O9~16)
A0~A18 Address Inputs
LB Lower Byte (I/O1~8
DNU Do Not Use
)
I/O1~I/O16 Data Inputs/outputs
2
EM680FU16A Series
Low Power, 512Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
Unit
V
V , V
IN
OUT
V
V
CC
P
W
D
o
Operating Temperature
T
-40 to 85
A
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Func-
tional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
I/O
I/O
Mode
Power
1-8
9-16
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
H
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Stand by
Stand by
Stand by
Active
X
H
H
H
H
H
H
H
H
Deselected
Output Disabled
Output Disabled
Lower Byte Read
X
L
Active
H
L
Active
L
H
L
Data Out Upper Byte Read
Active
L
L
Data Out Data Out
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Active
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
Active
L
H
L
Active
L
L
Active
NOTE: X means don’t care. (Must be low or high state)
3
EM680FU16A Series
Low Power, 512Kx16 SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
V
2.7
3.0
3.3
V
CC
Ground
V
0
0
-
0
V
V
SS
2)
Input high voltage
V
2.2
IH
V
+ 0.2
CC
3)
Input low voltage
V
-
0.6
V
IL
-0.2
1. TA= -40 to 85oC, otherwise specified.
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
V =0V
Min
Max
Unit
C
-
-
8
pF
pF
IN
IO
IN
Input/Ouput capacitance
C
V =0V
10
IO
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
ILI
VIN=VSS to VCC
Input leakage current
-1
-1
-
-
-
-
1
1
3
uA
uA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
ILO
ICC
Output leakage current
Operating power supply
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
mA
Cycle time=1µs, 100% duty, IIO=0mA,
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN<0.2V or VIN>VCC-0.2V
ICC1
-
-
3
mA
mA
45ns
-
-
-
-
-
-
-
-
40
30
20
0.4
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
ICC2
55ns
70ns
VOL
VOH
ISB
IOL = 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
V
V
IOH = -1.0mA
2.2
-
-
-
-
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
0.3
mA
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~VCC
ISB1
Standby Current (CMOS)
LF
-
2
15
uA
o
(Typ. condition : VCC=3.0V @ 25 C)
o
(Max. condition : VCC=3.3V @ 85 C)
4
EM680FU16A Series
Low Power, 512Kx16 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
3)
VTM
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL (70ns)
1)
2)
CL = 30pF + 1 TTL (45ns/55ns)
R2
1)
CL
1. Including scope and Jig capacitance
2. R =3070 ohm,
R =3150 ohm
2
1
3. V =2.8V
TM
4. CL = 5pF + 1 TTL (measurement with t
, t
, t
, t
, t
)
LZ1,2 HZ12 OLZ OHZ WHZ
o
o
READ CYCLE (V =2.7 to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
55ns
70ns
Symbol
Parameter
Read cycle time
Unit
Min
Max
Min
Max
Min
Max
tRC
tAA
CO1, tCO2
tOE
45
-
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
45
45
30
45
-
-
-
55
55
35
55
-
70
70
35
70
-
Chip select to output
t
-
Output enable to valid output
UB, LB Access time
-
-
-
tBA
-
-
-
Chip select to low-Z output
tLZ1, tLZ2
tBLZ
5
5
5
0
0
0
10
5
5
5
0
0
0
10
5
5
5
0
0
0
10
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
-
tOLZ
-
-
-
tHZ1, tHZ2
tBHZ
20
20
20
-
20
20
20
-
25
25
25
-
tOHZ
tOH
o
o
WRITE CYCLE (V =2.7 to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
Min
Max
tWC
tCW1, tCW2
tAS
45
-
-
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
-
-
60
0
-
-
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
45
45
45
0
-
45
45
45
0
-
60
60
55
0
-
tBW
-
-
-
tWP
-
-
-
Write recovery time
tWR
-
-
-
Write to ouput high-Z
tWHZ
tDW
0
20
-
0
20
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
30
0
tDH
-
-
-
tOW
5
-
5
5
-
5
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V , CS2=WE=V )
IL
IL
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )
IH
t
RC
Address
t
AA
t
OH
t
CO1,2
CS1
CS2
t
HZ1,2
t
BA
UB,LB
t
t
BHZ
t
OE
OE
t
OHZ
OLZ
High-Z
Data Out
Data Valid
t
BLZ
t
LZ1,2
NOTES (READ CYCLE)
1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.
6
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
t
WC
Address
t
(4)
WR
t
(2)
CW1,2
CS1
CS2
t
AW
t
BW
UB,LB
WE
t
(1)
WP
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
t
WC
Address
t
(4)
WR
t
(3)
AS
t
(2)
CW1,2
CS1
CS2
t
AW
t
BW
UB,LB
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
t
WC
Address
CS1
t
(4)
WR
t
(2)
CW1,2
CS2
t
AW
t
BW
UB,LB
WE
t
(3)
t
(1)
AS
WP
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write
to the end of write.
2. tCW1 is measured from the CS1 going low or CS2 going high to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE
going high or CS2 going low.
8
EM680FU16A Series
Low Power, 512Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
CS1 ≥ Vcc-0.2V 1)
Min
Typ
Max
Unit
1.5
-
3.3
V
VCC=1.5V, CS1 ≥ Vcc-0.2V 1)
IDR
Data Retention Current
-
-
uA
ns
4
-
tSDR
tRDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
-
-
See data retention wave form
tRC
-
1. CS1 ≥ Vcc-0.2V , CS2 ≥ Vcc-0.2V (CS1 controlled) or CS2 < 0.2V (CS2 controlled)
DATA RETENTION WAVE FORM
t
t
RDR
Data Retention Mode
SDR
V
cc
2.7V
2.2V
V
DR
CS1 > Vcc-0.2V
Data Retention Mode
CS2 < 0.2V
CS1, LB / UB
GND
V
cc
2.7V
CS2
t
t
RDR
SDR
V
DR
0.4V
GND
9
EM680FU16A Series
Low Power, 512Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
Top View
A1 index Mark
B
B
B1
0.5
6
5
4
3
2
1
A
B
C
D
E
F
#A1
G
H
B/2
Side View
D
Detail A
A
Y
C
Min
Typ
0.75
8.00
3.75
10.00
5.25
0.35
1.04
0.79
0.25
-
Max
A
B
-
-
8.10
-
7.90
NOTES.
B1
C
-
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
9.90
10.10
-
C1
D
-
0.30
0.40
1.10
-
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
E
1.00
E1
E2
Y
-
-
-
-
0.08
10
EM680FU16A Series
Low Power, 512Kx16 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Product Type
3. Density
11. Power
10. Speed
4. Function
9. Package
8. Generation
7. Organization
5. Technology
6. Operating Voltage
1. Memory Component
7. Organization
EM --------------------- Memory
8 ---------------------- x8 bit
16 ---------------------- x16 bit
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
9. Package
2 ----------------------- Multiplexed
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V ---------------------- 32 SOP
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
5. Technology
10. Speed
F ------------------------- Full CMOS
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 ---------------------- 100ns
12 ---------------------- 120ns
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
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