EM7164SU16-90LF [EMLSI]
1M x 16 bit Single Transistor RAM; 1M ×16位的单晶体管RAM
| 型号： | EM7164SU16-90LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 1M x 16 bit Single Transistor RAM |
| 文件： | 总13页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
Document Title
1M x 16 bit Single Transistor RAM
Revision History
RevisionNo.
History
Initial Draft
1’st Revision
Draft Date
Jul. 11 , 2005
Nov. 24 , 2005
Remark
Preliminary
Preliminary
0.0
0.1
DNU pin location changed from E3 to H6.
Added Pb-free&Green part.
0.2
2’nd Revision Change tRC/tWC maximum from 40us to
10us.
Feb. 15 , 2006
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
1M x16 bit Single Transistor RAM
GENERAL DESCRIPTION
The EM7164SU16 is 16,777,216 bits of Single Transistor RAM which uses DRAM type memory cells, but
this device has refresh-free operation and extreme low power consumption technology. Furthermore the
interface is compatible to a low power Asynchronous type SRAM. The EM7164SU16 is organized as
1,048,576 Words x 16 bit.
FEATURES
- Organization :1M x16
- Power Supply Voltage : 2.7 ~ 3.3V
- Separated I/O power(VccQ) & Core power(Vcc)
- Three state outputs
- Byte read/write control by UB/LB
- Support Direct Deep Power Down control by ZZ and Auto TCSR for power saving
- Package type : 48-FPBGA 6.0x7.0
PRODUCT FAMILY
Power Dissipation
Speed
Part Number
Operating Temp.
Power Supply
(tRC
)
Standby
Operating
(ICC2, Max.)
(ISB1, Max.)
o
o
EM7164SU16
2.7V to 3.3V
70ns
80uA
25mA
-25 C to 85 C
FUNCTION BLOCK DIAGRAM
/ZZ
Self-Refresh
CONTROL
/CS
COLUMN SELECT
/UB
/LB
/WE
/OE
CONTROL
LOGIC
Memory Array
1M X 16
ADDRESS
DECODER
A0~A19
DQ0~
DQ15
Din/Dout BUFFER
I/O CIRCUIT
2
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
PIN DESCRIPTION ( 48-FBGA-6.00x7.00 )
1
2
3
4
5
6
A
B
A2
ZZ
LB
OE
A0
A1
DQ8
DQ0
A4
CS
UB
A3
DQ9
C
D
A6
A7
DQ1
DQ3
DQ4
DQ10
DQ11
A5
DQ2
VCC
A17
NC
VSSQ
VCCQ
DQ14
DQ12
DQ13
VSS
DQ6
A16
A15
E
F
A14
DQ5
DQ15
A18
A19
A8
WE
A11
A12
A9
A13
A10
DQ7
DNU
G
H
TOP VIEW (Ball Down)
Name
/CS
Function
Name
/LB
Function
Lower byte (DQ0~7
)
Chip select inputs
Upper byte (DQ8~15
)
/OE
Output enable input
Write enable input
Low Power Control
Data In-out
/UB
/WE
/ZZ
VCC
Power supply
VCCQ I/O Power supply
VSS(Q) Ground
DQ0-15
A0-19
DNU
Address inputs
Do Not Use
NC
No connection
3
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
1)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
Unit
V
V , V
-0.2 to V
+0.3V
IN
OUT
CCQ
2)
V
, V
CCQ
V
-0.2 to 3.6V
1.0
CC
P
W
D
o
T
Storage Temperature
-65 to 150
C
STG
o
T
Operating Temperature
-25 to 85
C
A
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
DQ
DQ
8~15
CS
H
X
X
L
ZZ
H
L
OE
X
X
X
H
H
L
WE
X
LB
X
X
H
L
UB
X
X
H
X
L
Mode
Power
Stand by
Deep Power Down
Stand by
Active
0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Deselected
X
Deselected
H
H
H
H
H
H
H
H
H
X
Deselected
H
H
H
H
H
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X
L
Active
L
H
L
Active
L
L
H
L
Active
L
L
L
Active
L
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
Active
L
L
L
Active
Note: X means don’t care. (Must be low or high state)
4
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
2.7
Typ
3.0
3.0
0
Max
3.3
3.3
0
Unit
V
V
CC
V
2.7
V
CCQ
Ground
V
, V
SS SSQ
0
V
2)
Input high voltage
V
0.8 * V
-
-
V
V
IH
IL
V
+ 0.2
CCQ
CCQ
3)
Input low voltage
V
0.2 * V
-0.2
CCQ
1. TA= -25 to 85oC, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
V =0V
Min
Max
Unit
C
-
8
8
pF
IN
IO
IN
Input/Ouput capacitance
C
V =0V
-
pF
IO
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ILI
VIN=VSS to VCCQ , VCC=VCCmax
Input leakage current
-1
-
1
uA
CS=VIH , /ZZ=VIH , OE=VIH or WE=VIL
VIO=VSS to VCCQ , VCC=VCCmax
,
ILO
Output leakage current
-1
-
-
-
1
uA
Cycle time=1µs, 100% duty, IIO=0mA,
CS<0.2V, ZZ=VIH , VIN<0.2V or VIN>VCCQ-0.2V
ICC1
ICC2
-
3
mA
mA
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL, ZZ=VIH, VIN=VIL or VIH
-
-
25
0.2*VCCQ
-
Output low voltage
Output high voltage
VOL
VOH
-
-
V
V
IOL = 0.5mA, VCC=VCCmin
0.8*VCCQ
IOH = -0.5mA, VCC=VCCmin
CS,ZZ>VCCQ-0.2V, Other inputs = 0 ~ VCCQ
o
ISB1
(Typ. condition : VCC=3.0V @ 25 C)
Standby Current (CMOS)
LL
-
-
80
uA
o
(Max. condition : VCC=3.3V @ 85 C)
1. Maximum Icc specifications are tested with VCC = VCCmax.
5
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Dout
Input Pulse Level : 0.2V to V
-0.2V
CCQ
Input Rise and Fall Time : 5ns
1)
Input and Output reference Voltage : V
/2
CL
CCQ
1)
Output Load (See right) : CL = 30pF
1. Including scope and Jig capacitance
o
AC CHARACTERISTICS (V = 2.7 to 3.3V, Gnd = 0V, T = -25C to +85 C)
cc
A
Speed
Symbol
Parameter List
Unit
Min
Max
Read Cycle Time
tRC
tAA
tCO
tOE
70
10k
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
70
70
25
70
-
Chip enable to data output
Output enable to valid output
UB, LB enable to data output
Chip enable to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from Address change
Write Cycle Time
-
tBA
-
tLZ
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
0
15
15
15
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
5
70
60
0
10k
-
Chip enable to end of write
Address setup time
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
60
60
50
0
-
-
-
Write
Write recovery time
-
Write to output high-Z
0
15
-
Data to write time overlap
Data hold from write time
End write to output low-Z
20
0
-
tOW
5
-
6
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
TIMING DIAGRAMS
READ CYCLE (1) (Address controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
t
RC
Address
t
AA
t
OH
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2) (ZZ=WE=VIH)
t
RC
Address
t
t
OH
AA
t
CO
CS
t
HZ
t
BA
LB, UB
t
BHZ
t
OE
OE
t
OHZ
t
t
OLZ
BLZ
High-Z
Data Out
Data Vaild
t
LZ
NOTES (READ CYCLE)
1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. Do not Access device with cycle timing shorter than tRC for continuous periods > 40us.
7
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
WRITE CYCLE (1) (WE controlled, ZZ=OE=VIH)
t
WC
Address
t
t
AW
CW
CS
t
BW
LB, UB
t
WR
t
WP
WE
t
DH
t
AS
t
DW
Data In
High-Z
Data Valid
t
WHZ
t
OW
Data Out
Data Undefined
WRITE CYCLE (2) (CS controlled, ZZ=OE=VIH)
t
WC
Address
t
tCW
WR
t
AS
CS
t
AW
t
BW
LB, UB
t
WP
WE
t
DH
t
DW
Data In
Data Valid
Data Out
High-Z
8
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
WRITE CYCLE (3) (UB, LB controlled, ZZ=OE=VIH)
t
WC
Address
t
tCW
WR
CS
t
AW
t
BW
LB, UB
t
AS
t
WP
WE
t
DH
t
DW
Data In
Data Valid
Data Out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS, low WE and low UB or LB. A write begins at the last transition
among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting
UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from CS going low to end od write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE
going high.
5. Do not Access device with cycle timing shorter than tWC for continuous periods > 40us.
9
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
LOW POWER MODES
Deep Power Down Mode Entry/Exit
CS
t
CSZZ
t
ZZCS
t
ZZP
ZZ
tR
Normal
operation
Deep Power Down Entry
Deep Power Down Exit
NOTES ( DEEP POWER DOWN )
During Deep Power Down mode, all referesh related activity are disabled.
Parameter
Description
ZZ low to CS low
CS high to ZZ high
Operation Recovery Time
ZZ pulse width
Min.
0
0
200
20
Max.
Units
t
-
-
-
-
ns
ns
us
ns
ZZCS
t
CSZZ
t
R
t
ZZP
Low Power Mode Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ZZ < 0.2V, Other inputs = 0 ~ VCCQ
Deep Power Down
Current
IZZ
-
-
10
uA
o
(Max. condition : VCC=3.3V @ 85 C)
10
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
TIMING WAVEFORM OF POWER UP
200us
V
(Min.)
CC
V
CC
CS
Power Up Mode
Normal Operation
NOTE . ( POWER UP )
1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation.
11
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
Top View
A1 index Mark
B
B1
B
0.5
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Side View
D
Detail A
A
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.04
0.79
0.25
-
Max
A
B
-
-
6.03
-
5.93
NOTES.
B1
C
-
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
6.93
7.03
-
C1
D
-
0.30
0.40
1.10
-
E
1.00
E1
E2
Y
-
-
-
-
0.08
12
Preliminary
EM7164SU16 Series
merging Memory & Logic Solutions Inc.
1Mx16 Single Transistor RAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Organization
7. Organization
1. Memory Component
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ---------------------- Low Power SRAM
7 ---------------------- STRAM
8. Version
Blank ----------------- Mother die
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
3. Density
1 ----------------------- 1M
2 ----------------------- 2M
4 ----------------------- 4M
8 ----------------------- 8M
16 --------------------- 16M
32 --------------------- 32M
64 --------------------- 64M
9. Package
Blank ---------------------- Package
W --------------------- Wafer
4. Function
0 ---------------------- Dual CS
10. Speed
1 ---------------------- Single CS
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
2 ---------------------- Multiplexed
3----------------------- Single CS with /ZZ
4----------------------- Single CS with /ZZ & Direct DPD
5 ---------------------- Multiplexed with Sync. mode
5. Technology
Blank ---------------- CMOS
F ----------------------- Full CMOS
S ----------------------- Single Transistor
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free&Green)
L ---------------------- Low Power
S ---------------------- Standard Power
6. Operating Voltage
Blank ---------------- 5V
V ----------------------- 3.3V
U ----------------------- 3.0V
S ----------------------- 2.5V
R ----------------------- 2.0V
P ----------------------- 1.8V
O ----------------------- 1.5V
13
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