EM7164SU16W-70LF [EMLSI]
1M x 16 bit Single Transistor RAM; 1M ×16位的单晶体管RAM
| 型号： | EM7164SU16W-70LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 1M x 16 bit Single Transistor RAM |
| 文件： | 总12页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
Document Title
1M x 16 bit Single Transistor RAM
Revision History
Revision No.
History
Initial Draft
2’nd Draft
Draft Date
Jun. 07 , 2005
Aug. 22 , 2005
Remark
0.0
0.1
Preliminary
Add net die and pad coordinates
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1M x16 bit Single Transistor RAM
GENERAL DESCRIPTION
The EM7164SU16 is 16,777,216 bits of Single Transistor RAM which uses DRAM type memory cells, but
this device has refresh-free operation and extreme low power consumption technology. Furthermore the
interface is compatible to a low power Asynchronous type SRAM. The EM7164SU16 is organized as
1,048,576 Words x 16 bit.
FEATURES
- Organization :1M x16
- Power Supply Voltage : 2.7 ~ 3.3V
- Separated I/O power(VccQ) & Core power(Vcc)
- Three state outputs
- Byte read/write control by UB/LB
- Support Direct Deep Power Down control by ZZ and Auto TCSR for power saving
PRODUCT FAMILY
Power Dissipation
Speed
Part Number
Operating Temp.
Power Supply
(tRC
)
Standby
Operating
(ICC2, Max.)
(ISB1, Max.)
-25oC to 85oC
EM7164SU16W
2.7V to 3.3V
70ns
80uA
25mA
FUNCTION BLOCK DIAGRAM
/ZZ
/CS
Self-Refresh
CONTROL
COLUMN SELECT
/UB
/LB
/WE
/OE
CONTROL
LOGIC
Memory Array
1M X 16
ADDRESS
DECODER
A0~A19
DQ0~
DQ15
Din/Dout BUFFER
I/O CIRCUIT
2
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1M x16 bit Single Transistor RAM
GENERAL WAFER SPECIFICATIONS
- Process Technology : 0.13um CMOS Deep trench process
- 3 Metal layers including local inter-connection
- Wafer thickness : 725 +/- 25um
- Minimum Pad Pitch : 100um
- Wafer diameter : 8-inch
PAD DESCRIPTION
Name
/CS
Function
Name
/LB
Function
Lower byte (DQ0~7
)
Chip select inputs
Upper byte (DQ8~15
)
/OE
Output enable input
Write enable input
Low Power Control
Data In-out
/UB
/WE
/ZZ
VCC
Power supply
VCCQ I/O Power supply
VSS(Q) Ground
DQ0-15
A0-19
Address inputs
NC
No connection
y
DEVICE CODE
(EM716XSU16)
x
+
(0.0)
3
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC, VCCQ
PD
Ratings
Unit
V
-0.2 to VCCQ+0.3V
-0.22) to 3.6V
1.0
V
W
oC
oC
TSTG
Storage Temperature
-65 to 150
TA
Operating Temperature
-25 to 85
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
DQ0~7
DQ8~15
CS
H
X
X
L
ZZ
H
L
OE
X
X
X
H
H
L
WE
X
LB
X
X
H
L
UB
X
X
H
X
L
Mode
Power
Stand by
Deep Power Down
Stand by
Active
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Deselected
X
Deselected
H
H
H
H
H
H
H
H
H
X
Deselected
H
H
H
H
H
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X
L
Active
L
H
L
Active
L
L
H
L
Active
L
L
L
Active
L
X
X
X
L
H
L
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
Active
L
L
L
Active
Note: X means don’t care. (Must be low or high state)
4
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
Typ
3.0
3.0
0
Max
3.3
3.3
0
Unit
V
VCC
2.7
VCCQ
VSS, VSSQ
VIH
2.7
0
V
Ground
V
VCCQ + 0.22)
0.2 * VCCQ
Input high voltage
0.8 * VCCQ
-
-
V
V
-0.23)
Input low voltage
VIL
1. TA= -25 to 85oC, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested
.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
CIO
VIN=0V
-
8
pF
Input/Ouput capacitance
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ILI
V
=V to V
, V V
CC= CCmax
Input leakage current
-1
-
1
uA
IN
SS
CCQ
CS=V , /ZZ=V , OE=V or WE=V
,
IH
IH
IH
IL
ILO
Output leakage current
-1
-
-
-
1
uA
V
=V to V
, V V
CC= CCmax
IO
SS
CCQ
Cycle time=1µs, 100% duty, I =0mA,
IO
ICC1
-
3
mA
mA
CS<0.2V, ZZ=V , V <0.2V or V >V
-0.2V
IH
IN
IN
CCQ
Average operating current
Cycle time = Min, I =0mA, 100% duty,
IO
ICC2
-
-
25
CS=V , ZZ=V , V =V or V
IL
IH
IN
IL
IH
0.2*V
Output low voltage
Output high voltage
VOL
VOH
-
-
V
V
I
I
= 0.5mA, V
V
CCQ
OL
CC= CCmin
0.8*V
-
= -0.5mA, V
V
CC= CCmin
CCQ
OH
CS,ZZ>V
-0.2V, Other inputs = 0 ~ V
o
CCQ
CCQ
ISB1
(Typ. condition : V =3.0V @ 25 C)
Standby Current (CMOS)
LL
-
-
80
uA
CC
o
(Max. condition : V =3.3V @ 85 C)
CC
1. Maximum Icc specifications are tested with VCC = VCCmax.
5
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Dout
CL1)
Input Pulse Level : 0.2V to VCCQ-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : VCCQ/2
Output Load (See right) : CL1) = 30pF
1. Including scope and Jig capacitance
o
AC CHARACTERISTICS (V = 2.7 to 3.3V, Gnd = 0V, T = -25C to +85 C)
cc
A
Speed
Symbol
Parameter List
Unit
Min
Max
Read Cycle Time
tRC
tAA
70
40k
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
70
70
25
70
-
Chip enable to data output
Output enable to valid output
UB, LB enable to data output
Chip enable to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from Address change
Write Cycle Time
tCO
tOE
tBA
-
-
tLZ
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
0
15
15
15
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
5
70
60
0
40k
-
Chip enable to end of write
Address setup time
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
60
60
50
0
-
-
-
Write
Write recovery time
-
Write to output high-Z
0
15
-
Data to write time overlap
Data hold from write time
End write to output low-Z
20
0
-
5
-
6
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
TIMING DIAGRAMS
READ CYCLE (1) (Address controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Previous Data Valid
Data Out
Data Valid
READ CYCLE (2) (ZZ=WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBHZ
tBA
tOE
LB, UB
OE
tOHZ
tOLZ
High-Z
Data Out
Data Vaild
tBLZ
tLZ
NOTES (READ CYCLE)
1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. Do not Access device with cycle timing shorter than tRC for continuous periods > 40us.
7
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
WRITE CYCLE (1) (WE controlled, ZZ=OE=VIH)
tWC
Address
tAW
t
CW
CS
tBW
tWP
LB, UB
tWR
WE
tDH
tAS
tDW
Data In
High-Z
Data Valid
tOW
tWHZ
Data Out
Data Undefined
WRITE CYCLE (2) (CS controlled, ZZ=OE=VIH)
tWC
Address
tWR
t
CW
tAS
CS
tAW
tBW
tWP
LB, UB
WE
tDH
tDW
Data In
Data Valid
Data Out
High-Z
8
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
WRITE CYCLE (3) (UB, LB controlled, ZZ=OE=VIH)
tWC
Address
CS
tWR
t
CW
tAW
tBW
tWP
LB, UB
WE
tAS
tDH
tDW
Data In
Data Valid
Data Out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS, low WE and low UB or LB. A write begins at the last transition
among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting
UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from CS going low to end od write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE
going high.
5. Do not Access device with cycle timing shorter than tWC for continuous periods > 40us.
9
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
LOW POWER MODES
Deep Power Down Mode Entry/Exit
CS
tCSZZ
tZZCS
tZZP
ZZ
t
R
Normal
operation
Deep Power Down Entry
Deep Power Down Exit
NOTES ( DEEP POWER DOWN )
During Deep Power Down mode, all referesh related activity are disabled.
Parameter
Description
Min.
Max.
Units
tZZCS
ZZ low to CS low
0
-
-
-
-
ns
ns
us
ns
tCSZZ
tR
CS high to ZZ high
Operation Recovery Time
ZZ pulse width
0
200
20
tZZP
Low Power Mode Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ZZ < 0.2V, Other inputs = 0 ~ V
CCQ
o
Deep Power Down
Current
IZZ
-
-
10
uA
(Max. condition : V =3.3V @ 85 C)
CC
10
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
TIMING WAVEFORM OF POWER UP
200us
V
CC(Min.)
VCC
CS
Power Up Mode
Normal Operation
NOTE . ( POWER UP )
1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation.
11
Preliminary
EM7164SU16W Series
1Mx16 Single Transistor RAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Organization
1. Memory Component
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
3. Density
Blank ----------------- Mother die
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- Package
W --------------------- Wafer
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3----------------------- Single CS with /ZZ
4----------------------- Single CS with /ZZ
for Direct DPD mode
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ----------------- CMOS
F ------------------------ Full CMOS
S ------------------------ Single Transistor
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free)
L ---------------------- Low Power
S ---------------------- Standard Power
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
O ------------------------- 1.5V
12
相关型号：
©2020 ICPDF网 联系我们和版权申明