EM742SP16-55L [EMLSI]
256K x 16Bit Multiplexed Single Transistor RAM; 256K X 16Bit的复用单晶体管RAM
| 型号： | EM742SP16-55L |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 256K x 16Bit Multiplexed Single Transistor RAM |
| 文件： | 总10页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM742SP16
256Kx16 Multiplexed STRAM
Document Title
256K x 16Bit Multiplexed Single Transistor RAM
Revision History
Revision No.
History
Initial Draft
Draft Date
Remark
0.0
December 21 , 2006
Preliminary
0.1
0.2
1’st Revision
2’nd Revision
Add to pad coordinate
March 07, 2007
March 20, 2007
Preliminary
Preliminary
Product code chang from
EM742SP16AW to EM742SP16
0.3
0.4
3’rd Revision
4’ th Revision
Valid address change from A18 to
A17
March 28, 2007
May 9, 2007
Priliminary
Priliminary
Remove configure register sets at
functional descripition table
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code: 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM742SP16
256Kx16 Multiplexed STRAM
256K x16 Bit Multiplexed Single Transistor RAM
FEATURES
- Process Technology : 0.13µm CMOS process
- Organization :256K x16
- Power Supply Voltage : 1.7~1.9V
- Multiplexed address and data bus
- Three state outputs
- Auto TCSR for power saving
GENERAL WAFER SPECIFICATIONS
- Deep trench process
- 3 Metal layers including local inter-connection
- Wafer diameter : 8-inch
PAD DESCRIPTION
Name
Function
Name
/LB
Function
Lower byte (ADQ
)
/CS
Chip select inputs
0~7
Upper byte (ADQ
)
/OE Output enable input
/WE Write enable input
/AVD Address valid input
/UB
8~15
VCC Power supply
VCCQ I/O Power supply
VSS(Q) Ground
ADQ
Address/Data In-out
Address inputs
i
A
NC
No connection
i
FUNCTION BLOCK DIAGRAM
/AVD
/CS
/UB
/LB
/WE
/OE
Self-Refresh
CONTROL
COLUMN SELECT
CONTROL
LOGIC
Memory Array
256K X 16
ADDRESS
DECODER
A16~A17
ADDRESS/DATA
Multiplexer
Din/Dout BUFFER
ADQ0~
ADQ15
I/O CIRCUIT
2
EM742SP16
256Kx16 Multiplexed STRAM
1)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC, VCCQ
PD
Minimum
Unit
V
-0.2 to VCCQ+0.3V
-0.22) to 2.5V
1.0
V
W
oC
oC
TSTG
Storage Temperature
-65 to 150
TA
Operating Temperature
-25 to 85
1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Undershoot at power-off : -1.0V in case of pulse width < 20ns
FUNCTIONAL DESCRIPTION
ADQ0~15
A16~A17
CS
H
L
OE
X
H
X
H
L
WE
X
LB
X
X
H
H
L
UB
X
X
H
H
H
L
AVD
X
Mode
Power
Stand by
Active
Active
Active
Active
Active
Active
Active
Active
Active
High-Z
High-Z
X
Deselected
H
X
H
X
Output Disabled
Output Disabled
Address Input
Lower Byte Read
Upper Byte Read
Word Read
L
X
High-Z
X
L
H
H
H
H
L
L
Add. Input
Data Out
Data Out
Data Out
Data In
Add. Input
L
H
X
X
X
X
X
X
L
L
H
L
H
L
L
L
H
L
H
H
H
L
H
L
H
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
H
Data In
L
L
L
H
Data In
Note: X means don’t care. (Must be low or high state)
3
EM742SP16
256Kx16 Multiplexed STRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
Typ
1.8
1.8
0
Max
1.9
1.9
0
Unit
V
VCC
1.7
VCCQ
VSS, VSSQ
VIH
1.7
0
V
Ground
V
VCCQ + 0.22)
0.4
Input high voltage
VCCQ - 0.4
-
-
V
V
-0.23)
Input low voltage
VIL
1. TA= -25 to 85oC, otherwise specified
2. Overshoot: VCC +1.0 V in case of pulse width < 20ns
3. Undershoot: -1.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested
.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
CIO
VIN=0V
-
8
pF
Input/Output capacitance
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ILI
V
=V to V
, V V
CC= CCmax
Input leakage current
-1
-
1
uA
IN
SS
CCQ
CS=V or OE=V or WE=V
,
IH
IH
IL
CC= CCmax
ILO
Output leakage current
-1
-
-
-
-
1
uA
V
=V to V , V
CCQ
V
IO
SS
Cycle time=1µs, 100% duty, I =0mA,
IO
ICC1
3
mA
mA
CS<0.2V, V <0.2V or V >V -0.2V
CCQ
IN
IN
Average operating current
Cycle time = Min, I =0mA, 100% duty,
IO
ICC2
-
25
CS=V , V =V or V
IH
IL
IN
IL
Output low voltage
Output high voltage
VOL
VOH
-
-
-
0.1
-
V
V
I
I
= 0.1mA, V
V
CC= CCmin
OL
V
CCQ-0.1
= -0.1mA, V
V
OH
CC= CCmin
CS>V
-0.2V, Other inputs = 0 ~ V
CCQ
CCQ
o
ISB1
(Typ. condition : V =1.8V @ 25 C)
Standby Current (CMOS)
LL
-
-
60
uA
CC
o
(Max. condition : V =1.9V @ 85 C)
CC
1. Maximum Icc specifications are tested with VCC = VCCmax.
4
EM742SP16
256Kx16 Multiplexed STRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Dout
Input Pulse Level : 0.2V to VCCQ-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : VCCQ/2
Output Load (See right) : CL1) = 30pF
CL1)
1. Including scope and Jig capacitance
o
AC CHARACTERISTICS (V = 1.7 to 1.9V, Gnd = 0V, T = -25C to +85 C)
cc
A
Speed
Symbol
Parameter List
Unit
Min
Max
AVD Low pulse
tAVD
tAVDS
tAVDH
tCSS
tACC1
tACC2
tACC3
tADOE
tOE
15
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup to AVD rising edge
Address hold from AVD rising edge
Chip enable setup to AVD rising edge
AVD low to data valid time
Address access time
15
5
-
-
Common
7
-
-
70
70
70
-
-
Chip enable to data output
Address disable to output enable
Output enable to valid output
UB, LB enable to data output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
AVD low to end of write
-
0
-
25
25
-
tUBLBA
tBLZ
-
Read
5
tOLZ
5
-
tHZ
-
15
15
15
-
tBHZ
-
tOHZ
tACW1
tACW2
tACW3
tWRL
tBW
-
70
70
70
45
50
25
0
Address valid to end of write
Chip enable to end of write
Write pulse low
-
-
-
Write
UB, LB valid to end of write
Data to write time overlap
-
tDW
-
Data hold from write time
tDH
-
5
EM742SP16
256Kx16 Multiplexed STRAM
Device Operaton
The access is performed in two stages. The first stage is address latching. The first stage take place between point A and
B in timing diagram. At this stage, the Chip Select(CS) to the device is asserted. The random access is enabled either
from the point the address becomes stable, the falling edge of the AVD signal or from the falling edge of the last chip
select signal. The second stage is the read or write access. This takes place between points B and C in timing diagram.
In case of a read access, the multiplexed address/data bus (ADQ0 ~ ADQ15) changes its direction. It is important to notice
tOE when it is dominant that the device gets into the read cycle since the address is available long before the device
output is enabled.
Read Access
The read access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15
(A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken
low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is
stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed.
At this point the read cycle is entered. The OE signal is set active low. This changes the direction of the bus. The status
of control signals UB and LB are set according to the access. Data is read at point C.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1) ( WE = VIH
)
C
A
B
tAVD
AVD
tACC1
tAVDH
tAVDS
Address/Data
Address Valid
Data Valid
tACC2
tOHZ
tADOE
tOLZ
tOE
OE
CS
tCSS
tHZ
tACC3
tBLZ
tUBLBA
tBHZ
UB, LB
6
EM742SP16
256Kx16 Multiplexed STRAM
TIMING WAVEFORM OF READ CYCLE (2) ( WE = VIH
)
C
A
B
tAVD
AVD
tAVDS
tAVDH
Address/Data
Address Valid
Data Valid
tACC2
tOHZ
tOLZ
tOE
OE
CS
tCSS
tHZ
tBLZ
tUBLBA
tBHZ
UB, LB
NOTES (READ CYCLE)
1. tHZ and tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
7
EM742SP16
256Kx16 Multiplexed STRAM
Write Access
The write access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15
(A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken
low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is
stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed.
At this point, the second stage of the write process is entered. Data is input to the multiplexed address/data bus. The WE
signal is set low and control signal UB and LB are set according to the access.
TIMING WAVEFORM OF WRITE CYCLE (1) (OE = V )
IH
C
A
B
tAVD
AVD
tACW1
tAVDS
tAVDH
Data Valid
Address/Data
Address Valid
tACW2
tDH
tDW
tWRL
WE
CS
tCSS
tACW3
tBW
UB, LB
TIMING WAVEFORM OF WRITE CYCLE (2) (OE = V )
IH
C
A
B
tAVD
AVD
tAVDS
tAVDH
Data Valid
Address/Data
Address Valid
tACW2
tDH
tDW
tWRL
WE
CS
tCSS
tBW
UB, LB
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWRL) of low CS, low WE and low UB or LB. A write begins at the last transition among low CS and
low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write
ends at the earliest transition among high CS and high WE. The tWRL is measured from the beginning of write to the end of write.
8
EM742SP16
256Kx16 Multiplexed STRAM
TIMING WAVEFORM OF POWER UP
200us
V
CC(Min.)
VCC
CS
Power Up Mode
Normal Operation
NOTE . ( POWER UP )
1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation.
TCSR (Temperature Cotrolled Self Refresh)
The 4M STRAM can be operated with temperature controlled self-refresh. The device internal self-refresh period is
controlled according as temperature change automatically.
9
EM742SP16
256Kx16 Multiplexed STRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Organization
1. Memory Component
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
3. Density
Blank ----------------- Mother die
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ----------------- Package
W ----------------------- Wafer
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ----------------- CMOS
F ------------------------ Full CMOS
S ------------------------ Single Transistor
6. Operating Voltage
Blank ------------------ 5V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
O ------------------------- 1.5V
11. Power
LL --------------------- Low Low Power
L ---------------------- Low Power
S ---------------------- Standard Power
10
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