EM7642FS16CT-85LL [EMLSI]
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM; 512K ×8位超低功耗和低电压全CMOS静态RAM
| 型号： | EM7642FS16CT-85LL |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总10页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Document Title
Low Power, 512Kx8 SRAM
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Initial Draft
2’ nd Draft
Draft Date
May 25 , 2003
Remark
0.0
0.1
Preliminary
Add Pb-free part number
February 13 , 2004
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.18mm Full CMOS
• Organization : 512K x 8 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V(Min)
• Three state output and TTL Compatible
• Package Type : 32-sTSOP1
The EM641FV8FS families are fabricated by EMLSI’ s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
Speed
PKG Type
Standby
(ISB1, Typ)
Operating
(ICC1.Max)
Industrial (-40 ~ 85oC)
2.7V~3.6V
551) / 70ns
1 mA2)
EM641FV8FS
3 mA
32- sTSOP1
1. The parameter is measured with 30pF test load.
2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
A11
A9
32
31
30
29
OE
A10
CS
3
A8
Pre-charge Circuit
4
A13
IO8
5
WE
28
27
IO7
IO6
6
A17
7
A15
26
IO5
32 - sTSOP
Type1 - Forward
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
8
9
VCC
A18
25
24
IO4
VCC
VSS
VSS
10
11
A16
A14
A12
23
22
21
I/O3
I/O2
I/O1
Memory Array
2048 x 2048
12
13
A7
A6
20
19
A0
14
15
A1
A5
A4
18
17
A2
A3
16
Data
Cont
I/O1 ~ I/O4
I/O Circuit
Data
Cont
I/O5 ~ I/O8
Column Select
Name
Function
Name
Function
A
11 A12 A13 A14 A15 A16 A17 A
18
CS
Chip select inputs
WE Write Enable input
OE
Output Enable input
Address Inputs
Vcc Power Supply
Vss Ground
A ~A
0
18
WE
OE
I/O ~I/O
Data Inputs/outputs
NC
No Connection
Control Logic
1
8
CS
2
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
Unit
V
-0.2 to Vcc+0.3(Max.4.0V)
-0.2 to 4.0V
1.0
V
PD
W
oC
Operating Temperature
TA
-40 to 85
* Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X
WE
X
I/O
Mode
Deselected
Output Disabled
Read
Power
Stand by
Active
High-Z
High-Z
Data Out
Data In
H
H
L
L
H
Active
L
X
L
Write
Active
Note: X means don’ t care. (Must be low or high state)
3
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.3
3.6
V
Ground
VSS
VIH
0
0
-
0
V
V
VCC + 0.22)
0.6
Input high voltage
2.2
-0.23)
Input low voltage
VIL
-
V
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
VIO=0V
-
-
8
pF
pF
Input/Ouput capacitance
CIO
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
V
=V
to V
SS CC
Input leakage current
ILI
-1
-
-
-
1
1
3
mA
IN
Output leakage current
Operating power supply
ILO
ICC
CS=V or OE=V or WE=V , V =V
to V
CC
-1
-
mA
IH
IH
IL
IO
SS
I
=0mA, CS =V , V =V or V
IL IN IH IL
mA
IO
Cycle time=1ms, 100% duty, I =0mA,
IO
ICC1
-
-
3
mA
mA
CS<0.2V, V <0.2V or V >V -0.2V
IN
IN
CC
Average operating current
55ns
70ns
-
-
-
-
-
-
25
20
Cycle time = Min, I =0mA, 100% duty,
IO
ICC2
CS=V
V =V or V
IL , IN IL IH
I
I
= 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
VOL
VOH
ISB
0.4
V
V
OL
= -1.0mA
2.4
-
-
-
-
OH
CS=V , Other inputs=V or V
IL
0.3
mA
IH
IH
CS>V -0.2V, Other inputs=0~V
CC
CC
LL
LF
o
11)
ISB1
Standby Current (CMOS)
(Typ. condition : V =3.3V @ 25 C)
-
12
mA
CC
o
(Max. condition : V =3.6V @ 85 C)
CC
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
4
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=2.8V
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Symbol
Parameter
Read cycle time
Unit
Min
Max
Min
Max
tRC
tAA
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
55
55
25
-
-
-
70
70
35
-
Chip select to output
tco
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
tOE
tLZ
-
-
10
5
10
5
tOLZ
tHZ
tOHZ
tOH
-
-
0
20
20
-
0
25
25
-
0
0
10
10
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW
tAs
55
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write recovery time
-
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
0
20
0
20
25
0
30
0
-
-
-
-
tOW
5
5
5
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=VIL, WE=VIH
)
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
High-Z
Data Out
Data Valid
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW (2)
tWR(4)
CS
tAW
tWP(1)
WE
tDH
tAS(3)
tDW
High-Z
Data in
High-Z
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and
WE goes low. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the
beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
7
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ2) Max
Unit
ISB1 Test Condition
1.5
-
3.6
-
V
1)
(Chip Disabled)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.5
mA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
2. Typical values are measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
CS Controlled
tRDR
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
CS
GND
8
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
PACKAGE DIMENSIONS
( 32-sTSOP1-0813.4F )
Unit : millimeters/Inches
+/-0.20
13.40
0.528+/- 0.008
0.10
0.004
+0.10
0.20
MAX
- 0.05
+0.004
- 0.002
0.008
#1
#32
0.25
0.010
(
)
8.40
0.331
8.00
0.315
MAX
0.50
0.0197
#16
#17
1.00 +/-0.10
0.039 +/- 0.004
0.05
0.002
MIN
0.25
0.010
11.80
0.465 +/- 0.004
+/-0.10
TYP
+0.10
- 0.05
+0.004
- 0.002
0.15
1.20
MAX
0.047
0.006
0~8
0.50
0.020
0.45~0.75
0.018~0.030
)
(
9
EM641FV8FS Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
7. Orginzation
8 ---------------------- x8 bit
2. Device Type
16 ---------------------- x16 bit
32 ---------------------- x32 bit
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
8. Version
3. Density
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
4. Mode Option
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
0 -------- Dual CS
1 -------- Single CS
2 -------- Multiplexed Address
3 -------- Single CS with LB,UB (tBA=tOE)
4 -------- Single CS with LB,UB (tBA=tCO)
5 -------- Dual CS with LB,UB (tBA=tOE)
6 -------- Dual CS with LB,UB (tBA=tCO)
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power (Pb-free)
L ---------------------- Low Power
S ---------------------- Standard Power
10
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