EMC326SP16AKU-85LF [EMLSI]
2Mx16 bit CellularRAM AD-MUX; 2Mx16位的CellularRAM AD- MUX
| 型号： | EMC326SP16AKU-85LF |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 2Mx16 bit CellularRAM AD-MUX |
| 文件： | 总52页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Document Title
2Mx16 bit CellularRAM AD-MUX
Revision History
Revision No. History
Draft Date
Remark
Initial Draft
0.0
July 18,2007
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
1
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will
answer to your questions about device. If you have any questions, please contact the EMLSI office.
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
x16 Burst, Multiplexed Address/Data
FEATURES
- 16-bit multiplexed address/data bus
- Sigle device supports asynchrous and burst operation
- Vcc, VccQ voltages:
1.7V~1.95V VCC
1.7V~1.95V VCCQ
- Random access time: 70ns
- Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 104 MHz (tCLK = 9.62ns) , 133MHz(tCLK = 7.5ns)
Burst initial latency: 38.5ns (4 clocks) @ 104 MHz ,
37.5ns(5 clocks) @ 133 MHz
tACLK: 7ns @ 104 MHz , 5.5ns @ 133 MHz
- Low power consumption:
Asynchronous READ: <25mA
Initial access, burst READ:
(38.5ns [4 clocks] @ 104 MHz) <35mA
Continuous burst READ: <30mA
Initial access, burst READ:
(37.5ns [5 clocks] @ 133 MHz) <40mA
Continuous burst READ: <35mA
- Low-power features
On-chip temperature compensated self refresh (TCSR)
Partial array refresh (PAR)
- Operating temperature range:
Wireless -30°C to +85°C
OPTIONS
- Configuration: 32Mb (2 megabit x 16)
- Vcc core / VccQ I/O voltage supply: 1.8V
- Timing: 70ns access
- Frequency: 83 MHz, 104 MHz, 133 MHz
- Standby current at 85°C
Low Low Power : 100µA(max)
Low Power
Standard
: 120µA(max)
: 140µA(max)
2
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table of Contents
Features.................................................................................................................................................................................. 2
Options............................................................................................................................................................................... 2
General Description................................................................................................................................................................. 6
Functional Description............................................................................................................................................................. 9
Power-Up Initialization........................................................................................................................................................ 9
Bus Operating Modes.............................................................................................................................................................. 10
Asynchronous Mode........................................................................................................................................................... 10
Burst Mode Operation......................................................................................................................................................... 12
Mixed-Mode Operation ....................................................................................................................................................... 15
WAIT Operation ................................................................................................................................................................. 15
LB# / UB# Operation........................................................................................................................................................... 15
Low-Power Operation......... .................................................................................................................................................... 16
Standby Mode Operation ................................................................................................................................................... 16
Temperature Compensated Refresh................................................................................................................................... 16
Partial Array Refresh .......................................................................................................................................................... 16
Registers................................................................................................................................................................................. 17
Access Using CRE ............................................................................................................................................................. 17
Software Access ................................................................................................................................................................ 21
Bus Configuration Register................................................................................................................................................. 23
Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................................... 24
Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................................ 24
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ........................................................................... 25
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH................................................................................................... 26
Initial Access Latency (BCR[14]) Default = Variable....................................................................................................... 26
Operating Mode (BCR[15]) Default = Asynchronous Operation..................................................................................... 28
Refresh Configuration Register........................................................................................................................................... 28
Device Identification Register.............................................................................................................................................. 29
Electrical Characteristics......................................................................................................................................................... 30
Timing Requirements.............................................................................................................................................................. 32
Timing Diagrams..................................................................................................................................................................... 36
3
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
List of Figures
Figure 1: Functional Block Diagram - 2 Meg x 16 .........................................................................................
6
Figure 2: Power-Up Initialization Timing .......................................................................................................... 9
Figure 3: READ Operation ............................................................................................................................... 11
Figure 4: WRITE Operation ............................................................................................................................. 11
Figure 5: Burst Mode READ (4-word burst)...................................................................................................... 12
Figure 6: Burst Mode WRITE (4-word burst).................................................................................................... 13
Figure 7: Refresh Collision During Variable-Latency READ Operation ........................................................... 14
Figure 8: Wired-OR WAIT Configuration ......................................................................................................... 15
Figure 9: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ......... 17
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ........... 18
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ................................. 19
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation ................................... 20
Figure 13: Load Configuration Register ............................................................................................................. 22
Figure 14: Read Configuration Register ............................................................................................................ 22
Figure 15: Bus Configuration Register Definition ............................................................................................... 23
Figure 16: WAIT Configuration During Burst Operation ..................................................................................... 26
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision) ...................................................... 27
Figure 18: Latency Counter (Fixed Latency) ..................................................................................................... 27
Figure 19: Refresh Configuration Register Mapping ......................................................................................... 28
Figure 20: AC Input / Output Reference Waveform ........................................................................................... 31
Figure 21: AC Output Load Circuit .................................................................................................................... 31
Figure 22: Initialization Period .......................................................................................................................... 36
Figure 23: Asynchronous READ ....................................................................................................................... 36
Figure 24: Single-Access Burst READ Operation - Variable Latency ................................................................ 37
Figure 25: 4-Word Burst READ Operation - Variable Latency ........................................................................... 38
Figure 26: Single-Access Burst READ Operation - Fixed Latency .................................................................... 39
Figure 27: 4-Word Burst READ Operation - Fixed Latency ............................................................................... 40
Figure 28: Burst READ Terminate at End-of-Row (Wrap off) ............................................................................. 41
Figure 29: Burst READ Row Boundary Crossing .............................................................................................. 42
Figure 30: Asynchronous WRITE ..................................................................................................................... 43
Figure 31: Burst WRITE Operation - Variable Latency Mode ............................................................................ 44
Figure 32: Burst WRITE Operation - Fixed Latency Mode ................................................................................ 45
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap off) ........................................................................... 46
Figure 34: Burst WRITE Row Boundary Crossing ............................................................................................ 47
Figure 35: Burst WRITE Followed by Burst READ ............................................................................................ 48
Figure 36: Asynchronous WRITE Followed by Burst READ .............................................................................. 49
Figure 37: Burst READ Followed by Asynchronous WRITE .............................................................................. 50
Figure 38: Asynchronous WRITE Followed by Asynchronous READ ............................................................... 51
4
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
List of Tables
Table 1: Signal Descriptions ........................................................................................................................................... 7
Table 2: Bus Operations ................................................................................................................................................. 8
Table 3: Sequence and Burst Length .............................................................................................................................. 24
Table 4: Drive Strength ................................................................................................................................................... 25
Table 5: Variable Latency Configuration Codes............................................................................................................... 26
Table 6: Fixed Latency Configuration Codes................................................................................................................... 27
Table 7: Address Patterns for PAR(RCR[4] =1)............................................................................................................... 29
Table 8: Device Identification Register Mapping ............................................................................................................. 29
Table 9: Absolute Maximum Ratings ............................................................................................................................... 30
Table 10: Electrical Characteristics and Operating Conditions ......................................................................................... 30
Table 11: Capacitance ...................................................................................................................................................... 31
Table 12: Asynchronous READ Cycle Timing Requirements ............................................................................................ 32
Table 13: Burst READ Cycle Timing Requirements ......................................................................................................... 33
Table 14: Asynchronous WRITE Cycle Timing Requirements .......................................................................................... 34
Table 15: Burst WRITE Cycle Timing Requirements ......................................................................................................... 35
Table 16: Initialization Timing Parameters ........................................................................................................................ 36
5
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
GENERAL DESCRIPTION
32Mb CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable
applications. The 32Mb CellularRAM device has a DRAM core organized as 2 Meg x 16 bits. These devices are a variation of the
industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality
dramatically reduce the required signal count, and increases read/write bandwidth. For seamless operation on a burst Flash bus,
32Mb CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device READ/WRITE performance. Two user accessible control
registers define device operation. The bus configuration register (BCR) defines how the 32Mb CellularRAM device interacts with the
system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is
used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during
power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption
during self refresh. 32Mb CellularRAM products include two mechanisms to minimize standby current. Partial array refresh (PAR)
enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated self
refresh (TCSR) uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower
temperatures to minimize current consumption during standby. The system configurable refresh mechanisms are accessed through
the RCR. This 32Mb CellularRAM specification defines the industry-standard CellularRAM1.5 x16 A/D Mux feature set established by
the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, a
variety of wrap options, and a device ID register (DIDR).
Figure 1: FUNTIONAL BLOCK DIAGRAM - 2 meg x 16
A[20:16]
Address Decode
Logic
Input
Output
MUX
and
Buffers
2,048K x 16
DRAM
MEMORY
ARRAY
A/DQ[7:0]
A/DQ[15:8]
Refresh Configuration
Register (RCR)
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
CLK
CE#
WE#
OE#
ADV#
CRE
LB#
Control
Logic
UB#
WAIT
Internal
External
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed
information.
6
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 1: SIGNAL DESCRIPTIONS
Symbol
Type
Descriptions
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally
latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded
into the BCR or the RCR.
A[20:16]
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations.
When configured for synchronous operation, the address is latched on the first rising CLK edge when
ADV# is active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE
operations when burst mode is enabled.
CLK
(note1)
Input
ADV#
(note1)
Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on
the rising edge of ADV# during asynchronous READ and WRITE operations.
Input
Input
Input
Input
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ
operations access the RCR, BCR, or DIDR.
CRE
CE#
OE#
WE#
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby mode.
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are
disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either
a configuration register or to the memory array.
LB#
Input
Input
Lower byte enable. DQ[7:0]
UB#
Upper byte enable. DQ[15:8]
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins
A/DQ[15:0] Input/Output behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address,
RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH.
Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate
WAIT
(note1)
collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless
wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z
when CE# is HIGH.
Output
RFU
VCC
-
Reserved for future use.
Supply
Supply
Supply
Supply
Device power supply: (1.70V.1.95V) Power supply for device core operation.
I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCCQ
VSS
VSSQ
VSSQ must be connected to ground.
Note:
1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.
7
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 2: BUS OPERATIONS
Asynchfonous Mode
BCR[15]=1
UB#/
LB#
Power
CLK ADV# CE# OE# WE# CRE
WAIT2
DQ[15:0]
Notes
Read
Write
Active
Active
Standby
Idle
X
X
L
L
L
X
X
X
H
L
L
L
L
L
L
Low-z
High-z
High-z
Low-z
Data out
Data in
High-z
X
4
L
4
Standby
No operation
H or L
X
X
X
H
L
X
X
X
5, 6
4, 6
X
Configuration register
write
Active
Active
Power
X
X
L
L
H
L
L
H
H
X
L
Low-z
Low-z
WAIT
High-z
Configuration register
read
Config.
Reg.out
H
Burst Mode
BCR[15]=0
UB#/
LB#
CLK ADV# CE# OE# WE# CRE
DQ[15:0]
Notes
Async read
Async write
Active
Active
Standby
Idle
H or L
H or L
H or L
H or L
L
L
H
L
L
L
L
X
X
X
X
H
H
L
L
L
L
L
L
L
L
L
Low-z
Low-z
High-z
Low-z
Low-z
Low-z
Data out
Data in
High-z
X
4, 7
4
Standby
X
X
L
X
X
H
L
X
X
L
5, 6
4, 6
4, 8
4, 8
No operation
Initial burst read
Initial burst write
Active
Active
Address
Address
L
X
Data out
or
Burst continue
Active
H
L
X
X
X
L
Low-z
4, 8
Data in
Configuration register
write
Active
Active
L
L
L
L
H
L
L
H
H
X
L
Low-z
Low-z
High-z
8, 9
8, 9
Configuration register
read
Config.
Reg.out
H
Note:
1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power
during standby mode.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is
in the select mode, DQ[15:8] are enabled.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.
7. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated
by WAIT).
8
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
FUNTIONAL DESCRIPTION
In general, 32Mb CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power,
portable applications. The 32Mb device contains a 33,554,432-bit DRAM core, organized as 2,097,152 addresses by 16 bits.The device
implement a multiplexed address/data bus. This multiplexed configuration supports greater bandwidth through the x16 data bus, yet still
reduces the required signal count. The 32Mb CellularRAM bus interface supports both asynchronous and burst mode transfers.
POWER-UP INITIALIZATION
32Mb CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will
configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied simultaneously. When they reach a stable
level at or above 1.7V, the device will require 150µs to complete its self-initialization process. Until the end of tPU, CE# should track
VccQ and remain HIGH. When initialization is complete, the device is ready for normal operation.
Figure 2: Power-Up Initialization Timing
Vcc=1.7V
tPU
Device ready for
normal operation
Vcc
VccQ
Device Initialization
9
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
BUS OPERATING MODES
32Mb CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This
bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value
loaded into the BCR.
Asynchronous Mode
Asynchronous mode uses the industry- standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations(Fig-
ure 3) are initiated by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address onto the A/
DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the I/Os after the specified
access time has elapsed. WRITE operations(Figure 4 ) occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW. with the address
on the A/DQ bus. ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous
WRITE operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE# must be HIGH while the address is
driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever occurs first). Dur-
ing asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be driven during
asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.
10
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 3: READ Operation
Valid
Address
A[20:16]
CE#
OE#
WE#
Valid
Data
Valid
Address
A/DQ[15:0]
High-Z
ADV#
LB#/UB#
Don’t Care
Figure 4: WRITE Operation
Valid
Address
A[20:16]
CE#
OE#
WE#
t
CEM
Valid
Data
Valid
Address
A/DQ[15:0]
ADV#
LB#/UB#
Undefined
Don’t Care
11
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock
sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of
the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE#
= HIGH, Figure 5) or WRITE (WE# = LOW, Figure 6).
Figure 5: Burst Mode READ (4-word burst)
CLK
A[20:16]
Address
Address
ADV#
CE#
Latency Code 2(3 clocks)
OE#
WE#
LB#/UB#
Address
A/DQ[15:0]
D0
D2
D3
Address
D1
WAIT
READ Burst Identified
(WE# = HIGH)
READ Burst Identified
(WE# = HIGH)
Undefined
Don’t Care
Note:
Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
12
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 6: Burst Mode WRITE (4-word burst, OE# HIGH)
CLK
Address
A[20:16]
ADV#
Address
Latency Code 2(3 clocks)
CE#
WE#
LB#/UB#
A/DQ[15:0]
WAIT
Address
Address
D0
D1
D2
D3
WRITE Burst Identified
(WE# = LOW)
WRITE Burst Identified
(WE# = LOW)
Don’t Care
Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen,
or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the address. It goes back to
the first address and continues to burst when continuous bursts meet the end of address.
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between
the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE
operations always use fixed latency). Variable latency allows the CellularRAM to be configured for minimum latency at high clock
frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency
time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency
also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory.
WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length. With wrap off, the CellularRAM device
will restore the previous row’s data and access the next row, WAIT will be de-asserted, and the burst can continue across the row
boundary(See Figeure 29 for a READ, Figure 34 for a WRITE). If the burst is to terminate at the row boundary, CE# must go HIGH
within 2 clocks of the last data(See Figure 28). CE# must go HIGH before any clock edge following the last word of a defined-length
burst WRITE(See Figure 31 and 32).
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE#
to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
13
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 7: Refresh Collision During Variable-Latency READ Operation
V
IH
CLK
A[20:16]
ADV#
V
IL
V
IH
Valid
Address
V
V
IL
IH
V
IL
V
IH
CE#
V
IL
V
IH
OE#
WE#
V
V
IL
IH
V
IL
V
IH
LB#/UB#
V
IL
V
V
OH
OH
Valid
Address
D3
A/DQ[15:0]
D0
D1
D2
V
V
V
OL
OL
High-Z
OH
WAIT
V
OL
Additional WAIT states inserted to allow refresh completion.
Undefined
Don’t Care
Note: Non-default BCR settings for refresh collision during variable-latency READ operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
14
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during the
entire sequence. The ADV# signal can be used to latch the target address. CE# can remain LOW when the device is transitioning
between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation
facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 36 on page 49 for the “Asynchronous
WRITE Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal(See Figure 8). The shared
WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
Figure 8: Wired or WAIT Configuration
External
Pull-Up
CellularRAM
Pull-Down
Resistor
WAIT
READY
WAIT
WAIT
Processor
Other
Device
Other
Device
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires addi-
tional time before data can be transferred. For burst READ operations, WAIT will remain active until valid data is output from the device.
For burst WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When
WAIT transitions to an inactive state, the data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data
corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ operations
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed(See Figure 7 ). When the refresh operation has completed, the burst READ operation will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new
row to be accessed.
WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during asynchronous WRITE
operations. WAIT should be ignored during all asynchronous operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal.
However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of the row. If WAIT is
not monitored, the controller must properly terminate all burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written
is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When
both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data.
Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
15
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
LOW-POWER OPERATION
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby
operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or
when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the
address or control inputs.
Temperature Compensated Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This CellularRAM device includes
an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device
continually monitors the temperature to select an appropriate self-refresh rate.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce
standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map(See Table 7). READ and WRITE operations to address ranges receiving refresh will not be affected. Data
stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are
available immediately upon writing to the RCR.
16
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the Cellular-
RAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded
with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides
information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input
is HIGH(see Figure 9 through 12 on pages 17 through 20) . When CRE is LOW, a READ or WRITE operation will access the memory
array. The configuration register values are written via addresses A[20:16] and A/DQ[15:0]. In an asynchronous WRITE, the values are
latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”.
The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b.
For READs, address inputs other than A[19:18] are “Don’t Care”, and register bits 15:0 are output on DQ[15:0]. Immediately after a
configuration register READ or WRITE operation is performed, reading the memory array is highly recommended.
Figure 9: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
A[20:16]
OPCODE
Address
Address
(except A[19:18])
t
t
AVS
AVH
Select control register
1
A[19:18]
CRE
t
AVS
t
AVH
ADV#
t
VP
t
CPH
Initiate Control register access
CE#
OE#
t
CW
t
WP
Write address bus value
to control register
WE#
LB#/UB#
A/DQ[15:0]
Valid
data
OPCODE
Address
Don’t Care
Note: A[19:18] = 00b to load RCR, and 10b to load BCR.
17
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[20:16]
OPCODE
Address
Address
(except A[19:18])
t
HD
t
SP
Latch control register address
2
A[19:18]
t
HD
t
SP
CRE
ADV#
CE#
t
SP
t
HD
t
CBPH
t
CSP
Note3
OE#
WE#
t
SP
t
HD
LB#/UB#
Valid
data
A/DQ[15:0]
OPCODE
Address
t
KHTL
High-Z
High-Z
WAIT
Don’t Care
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
collisions require a corresponding number of additional CE# LOW cycles.
18
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation
A[20:16]
Address
Address
(except A[19:18])
t
t
AVH
AVS
Select register
1
A[19:18]
t
t
AVH
AA
t
CRE
AVS
t
AA
ADV#
t
VP
t
AADV
t
CPH
Initiate register access
CE#
t
t
HZ
CPH
t
CO
OE#
WE#
t
t
OHZ
OE
t
BA
t
BHZ
t
OLZ
LB#/UB#
Valid
A/DQ[15:0]
Valid CR
Address
data
Undefined
Don’t Care
Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
19
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[20:16]
(except A[19:18])
Address
t
HD
t
SP
Latch control register address
2
A[19:18]
Address
t
HD
t
SP
CRE
t
SP
t
HD
ADV#
t
CBPH
t
ABA
t
CSP
CE#
OE#
WE#
Note3
t
HZ
t
OHZ
t
SP
t
t
HD
BOE
LB#/UB#
t
t
KOH
ACLK
t
OLZ
Valid
A/DQ[15:0]
Valid CR
Address
data
t
KHTL
High-Z
High-Z
WAIT
Undefined
Don’t Care
Note:
1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CE# LOW cycles.
20
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the
configuration registers can be modified and all registers can be read using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two
asynchronous WRITE operations (see Figure 13 ). The READ sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 14). The address used during all READ and WRITE operations is the highest address
of the CellularRAM device being accessed (1FFFFFh); the contents of this address are not changed by using this sequence.
The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be
accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is
0002h, the sequence will access the DIDR. This value must be valid at the falling edge of WE#. During the fourth operation, DQ[15:0]
transfer data in to or out of bits 15:0 of the registers.
The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the
configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software
mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required.
21
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 13: Load Configuration Register
WRITE
READ
READ
WRITE
CE#
OE#
WE#
LB#/UB#
ADV#
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
A[20:16]
0ns (min); Note 1
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
CR Value
in
A/DQ[15:0]
XXXX
XXXX
RCR : 0000h
BCR : 0001h
Don’t Care
Note:
If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
Figure 14: Read Configuration Register
WRITE
READ
READ
READ
CE#
OE#
WE#
LB#/UB#
ADV#
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
A[20:16]
0ns (min); Note 1
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
CR Value
out
A/DQ[15:0]
XXXX
XXXX
RCR : 0000h
BCR : 0001h
DIDR : 0002h
Don’t Care
Note:
If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
22
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
BUS CONFIGURATION REGISTER
The BCR defines how the CellularRAM device interacts with the system memory bus. Figure 15 describes the control bits in the BCR.
At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access
software sequence with A/DQ = 0001h on the third cycle.
Figure 15: Bus Configuration Register Definition
A
[20]
A
A
A/DQ A/DQ
A/DQ
[13:11]
A/DQ A/DQ
A/DQ
8
A/DQ
7
A/DQ A/DQ
A/DQ
3
A/DQ
[2:0]
[19:18] [17:16]
15
14
10
9
6
[5:4]
20
19-18
17-16
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Select
Operating Initial
Latency
Counter
WAIT
Polarity
WAIT
Configuration(WC)
Drive
Burst
Burst
Reserved
Reserved
Reserved
Reserved Reserved
Mode
Latency
Strength Wrap(BW) Length(BL)
All must be set to “0”
Must be set to “0”
Must be set to “0”
Must be set to “0” Must be set to “0”
BCR[14]
Initial Access Latency
Variable (default)
Fixed
BCR[3]
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
0
1
0
1
BCR[5] BCR[4]
Drive Strength
Full
BCR[13] BCR[12] BCR[11]
Latency Counter
Code 8
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/2 (default)
1/4
Code 1 - Reserved
Code 2
Reserved
Code 3 (default)
Code 4
Code 5
BCR[8]
WAIT Configuration
Asserted during delay
Code 6
0
1
Asserted one data cycle before delay (default)
Code 7 - Reserved
BCR[10]
WAIT Polarity
0
1
Active LOW
Active HIGH (default)
BCR[15]
Operating Mode
0
1
Synchronousburstaccessmode
BCR[2] BCR[1] BCR[0]
Burst Length (Note 1)
4 words
Asynchronous access mode (default)
0
0
0
1
1
0
1
0
1
0
1
1
8 words
BCR[19] BCR[18] Register Select
1
16 words
0
1
0
0
0
1
Select RCR
Select BCR
Select DIDR
0
32 words
1
Continuous burst (default)
Reserved
Others
Note:
1. Burst wrap and length apply to both READ and WRITE operations.
2. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionallity. BCR[15:0] will be read back as written.
23
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst
length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is output sequentially without regard to
address boundaries; the internal address wraps to 000000h if the device is read past the last address.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4, 8, 16, or 32 word READ or WRITE burst wraps within the burst length, or steps through
sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to address
boundaries; the internal address wrap to 000000h if the device is read past the last address.
Table 3: Sequence and Burst Length
4 Word
Starting
Address
8 Word
16 Word
Burst Length
32 Word
Burst Length
Continuous
Burst
BURST Wrap
Burst
Burst Length
Length
BCR[3] Wrap Decimal Linear
Linear
Linear
Linear
Linear
0
1
2
3
4
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
0-1-2 ... 29-30-31
1-2-3 ... 30-31-0
2-3-4 ... 31-0-1
3-4-5 ... 0-1-2
4-5-6 ... 1-2-3
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10-...
5
6
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
...
5-6-7 ... 2-3-4
6-7-8 ... 3-4-5
7-8-9 ... 4-5-6
...
5-6-7-8-9-10-11-...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13-...
...
0
Yes
7
...
14
15
...
30
31
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
14-15-16-...-11-12-13 14-15-16-17-18-19-20-...
15-16-17...-12-13-14
...
15-16-17-18-19-20-21-...
...
30-31-0-...-27-28-29
31-0-1-... -28-29-30
30-31-32-33-34-...
31-32-33-34-35-...
0
1
2
3
4
5
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
0-1-2-...-29-30-31
1-2-3-...-30-31-32
2-3-4-...-31-32-33
3-4-5-...-32-33-34
4-5-6-...-33-34-35
5-6-7-...-34-35-36
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10-...
5-6-7-8-9-10-11-...
5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20
6-7-8-9-10-11-12-
6
7
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21
13
6-7-8-...-35-36-37
7-8-9-...-36-37-38
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13-...
7-8-9-10-11-12-13- 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-
1
No
14
22
...
...
...
...
14
14-15-16-17-18-...-23-24-25-26-27-28-29
15-16-17-18-19-...-24-25-26-27-28-29-30
14-15-16-...43-44-45
14-15-16-17-18-19-20-...
15
...
15-16-17-...-44-45-46 15-16-17-18-19-20-21-...
... ...
30
31
30-31-32-...-59-60-61 30-31-32-33-34-35-36-...
31-32-33-...-60-61-62 31-32-33-34-35-36-37-...
24
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The
reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus.
The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength
should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured
at half-drive strength during testing. See Table 4 for additional information.
Table 4: Drive Strength
BCR[5]
BCR[4]
Drive Strength
Use Recommendation
Impedance Typ (Ω )
0
0
Full
25~30
CL = 30pF to 50pF
1/2
(default)
CL = 15pF to 30pF
104 MHz at light load
0
1
50
1
1
0
1
1/4
100
CL = 15pF or lower
Reserved
25
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to
valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the
de-asserted or asserted state, respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going
valid or invalid(See Figure 16).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT
signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 16: WAIT Configuration During Burst Operation
CLK
BCR[8] = 0
Data Valid in current cycle
WAIT
BCR[8] = 1
Data Valid in next cycle
WAIT
initial latency
D3
D0
D1
D2
A/DQ[15:0]
End of row
Don’t Care
Note: Non-default BCR setting: WAIT active LOW.
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data
value transferred. For allowable latency codes, see Table 5 and 6 on pages 26 and 27, respectively, and Figure 17 and 18 in page 27,
respctively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to
detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that
allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is
not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency
counter(See Table 6 on page 27 and Figure 18 on page 27).
Table 5: Variable Latency Configuration Codes
Latency
Configuration
Code
1
Max Input CLK Frequency (MHz)
Latency
BCR[13:11]
Normal
Refresh Collision
133
104
83
010
011
2 (3 clocks)
2
3
4
-
4
6
8
-
66(15ns)
66(15ns)
52(19.2ns)
3 (4 clocks)-default
4 (5 clocks)
104(9.62ns) 104(9.62ns)
83(12ns)
100
133(7.5ns)
-
-
-
-
-
Others
Reserved
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
26
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision)
V
IH
CLK
V
IL
V
IH
Valid
Address
A[21:16]
V
IL
V
IH
ADV#
V
IL
Code 2
V
IH
Valid
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
D0
D1
D0
D2
D1
D0
D3
D2
D1
D4
D5
D4
D3
D6
D5
D4
D7
D6
D5
Address
V
IL
Code 3 (default)
V
IH
Valid
Address
Code 4
Valid
Address
D3
D7
D6
V
IL
V
IH
D2
V
IL
Undefined
Don’t Care
Table 6: Fixed Latency Configuration Codes
Latency
Latency Count (N)
Normal
Max Input CLK Frequency (MHz)
BCR[13:11]
Configuration
Code
133
104
83
010
011
2 (3 clocks)
2
3
4
5
6
8
--
33(30ns)
52(19.2ns)
66(15ns)
75(13.3ns)
104(9.62ns)
133(7.5ns)
-
33(30ns)
52(19.2ns)
66(15ns)
75(13.3ns)
104(9.62ns)
-
33(30ns)
52(19.2ns)
66(15ns)
75(13.3ns)
83(12ns)
-
3 (4 clocks)-default
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
8 (9 clocks)
Reserved
100
101
110
000
Others
-
-
Figure 18: Latency Counter (Fixed Latency)
N-1
Cycles
Cycle N
V
IH
CLK
V
IL
t
AA
V
IH
Valid
Address
A[20:16]
V
IL
t
AADV
V
IH
ADV#
CE#
V
IL
t
CO
V
IH
V
IL
t
ACLK
V
OH
A/DQ[15:0]
(READ)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
V
OL
t
t
SP HD
V
OH
A/DQ[15:0]
(WRITE)
Valid
Address
Valid
Input
Valid
Input
Valid
Valid
Input
Valid
Input
Input
V
OL
Burst Identified
(ADV# = LOW)
Undefined
Don’t Care
27
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
REFRESH CONFIGURATION REGISTER
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh
parameters can dramatically reduce current consumption during standby mode. Figure 19 describes the control bits used in the RCR. At
power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software
sequence with A/DQ = 0000h on the third cycle.
Figure 19: Refresh Configuration Register Mapping
A[20]
A[19:18]
A[17:16]
A/DQ
[15:7]
A/DQ
6
A/DQ
5
A/DQ
4
A/DQ
3
A/DQ
2
A/DQ
1
A/DQ
0
20
19-18
17-16
15~7
6
5
4
3
2
1
0
Register
Select
Reserved
Reserved
Reserved
Ignored
Reserved
PAR
Setting is ignored
(Default 001b)
All must be set to “0”
Must be set to “0”
All must be set to “0”
RCR[19] RCR[18]
Register Select
Select RCR
RCR[2]
RCR[1]
RCR[0]
Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Select BCR
Select DIDR
Top 1/2 array
Top 1/4 array
Top 1/8 array
Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written.
28
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh)
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address
map(See Table 7 and Table 8).
Table 7: Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full Die
Address Space
000000h-1FFFFFh
000000h-0FFFFFh
000000h-07FFFFh
000000h-03FFFFh
0
Size
Density
32Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Meg x 16
1 Meg x 16
512 K x 16
256 K x 16
0 Meg x 16
1 Meg x 16
512 K x 16
256 K x 16
One-half die
One-quarter of die
One-eighth of die
None of die
4Mb
0Mb
One-half of die
One-quarter of die
One-eighth of die
100000h-1FFFFFh
180000h-1FFFFFh
1C0000h-1FFFFFh
16Mb
8Mb
4Mb
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8
describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the
register access software sequence with A/DQ = 0002h on the third cycle.
Table 8: Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
Device version
Bit
DIDR[10:8]
Device density
Bit
DIDR[7:5]
DIDR[4:0]
Field name
Row Length
CellularRAM generation
Vendor ID
Bit
Setting
Bit
Generation
Bit
Setting
Length
Version
Density
Vendor
EMLSI
Setting
Setting
Setting
Options
128 words
0b
2nd
0001b
32Mb
001b
CR 1.5
010b
01010b
29
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
ELECTRICAL CHARACTERISTICS
Table 9: Absolute Maximum Ratings
Parameter
Rating
-0.3V to VccQ + 0.3V
-0.2V to +2.45V
-0.2V to +2.45V
-55°C to +150°C
-30°C to +85°C
+260°C
Voltage to any pin except Vcc, VccQ relative to Vss
Voltage on Vcc supply relative to Vss
Voltage on VccQ supply relative to Vss
Storage temperature (plastic)
Operating temperature (case) Wireless
Soldering temperature and time: 10s (solder ball only)
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Table 10: Electrical Characteristics and Operating Conditions
Wireless Temperature (-30°C < TC < +85°C)
Description
Conditions
Symbol
Min
1.7
Max
1.95
1.95
Unit Notes
V
Supply voltage
V
V
CC
V
I/O supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Operating current
1.7
CCQ
V
V
- 0.4
V
+ 0.2
CCQ
V
V
1
2
3
3
IH
CCQ
V
-0.20
0.4
IL
OH
OL
LI
I
I
= -0.2mA
= +0.2mA
V
0.80 X V
V
OH
CCQ
V
I
0.20 X V
V
OL
CCQ
V
= 0 to V
CCQ
1
1
µA
µA
IN
OE# = V or chip disabled
IH
I
LO
Conditions
Symbol
Typ
Max
Unit Notes
Asynchronous random
READ/WRITE
I
I
1
70ns
25
mA
4
CC
133MHz
104MHz
83MHz
40
35
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Initial access,
burst READ/WRITE
2
4
CC
30
133MHz
104MHz
83MHz
35
V
= V
or 0V chip enabled, I
= 0
OUT
IN
CCQ
I
3R
Continuous burst READ
Continuous burst WRITE
30
4
4
CC
25
133MHz
104MHz
83MHz
40
I
3W
35
CC
30
Standard
Low Power
140
120
V
= V
or 0V, CE# = V
I
SB
Standby current
Note:
TBD
5, 6
IN
CCQ
CCQ
Low-Low Power
100
1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b (default setting of one-half drive strength).
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output
capacitance expected in the actual system.
5. I (max) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs must be driven to
SB
either VCCQ or VSS. I might be slightly higher for up to 500ms after power-up, or when entering standby mode.
SB
6. I (typ) is the average I at 25°C and VCC = VCCQ = 1.8V. This parameter is verified during characterization, and is not 100% tested.
SB
SB
30
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 11: Capacitance
Description
Conditions
Symbol
Min
Max
Unit Notes
C
Input Capacitance
2.0
6
pF
1
IN
Tc = = +25°C; f = 1 MHz;
C
Input/Output
Capacitance(A/DQ)
V
= 0V
IO
IN
3.0
6.5
pF
1
Note: 1. These parameters are verified in device characterization and are not 100% tested.
Figure 20: AC Input/Output Reference Waveform
VccQ
2
1
3
VccQ/2
Test Points
Output
Input
VccQ/2
VssQ
Note:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 21: AC Output Load Circuit
Test Points
50Ω
VccQ/2
DUT
30pF
Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
31
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
TIMING REQUIREMENTS
Table 12: Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol
Min
Max
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
Address access time
AA
t
ADV# access time
70
AADV
t
Address hold from ADV# HIGH
Address setup to ADV# HIGH
LB#/UB# access time
2
5
AVH
t
AVS
t
70
7
BA
t
LB#/UB# disable to DQ High-Z output
Chip select access time
1
1
BHZ
t
70
CO
t
CE# LOW to ADV# HIGH
Chip disable to DQ and WAIT High-Z output
Output enable to valid output
OE# LOW to WAIT valid
7
1
CVS
t
7
20
7.5
8
HZ
t
OE
t
OEW
t
Output disable to DQ High-Z output
Output enable to Low-Z output
ADV# pulse width
1
2
OHZ
t
3
5
OLZ
t
VP
Note:
1. The High-Z timings measure a 100mV transition from either V or V toward VccQ/2.
OH
OL
2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either V or V
OH
.
OL
32
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 13: Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
133MHz
104MHz
83MHZ
Parameter
Symbol
Unit Notes
Min
Max
Min
Max
Min
Max
t
Address access time (fixed latency)
ADV# access time (fixed latency)
Burst to READ access time (variable latency)
CLK to output delay
70
70
70
70
70
70
45
9
ns
ns
ns
ns
ns
ns
AA
t
AADV
t
35.5
5.5
35.9
7
ABA
t
ACLK
t
Address hold from ADV# HIGH(fixed latency)
Burst OE# LOW to output delay
2
5
2
5
2
6
AVH
t
20
20
20
BOE
CE# HIGH between subsequent burst or mixed
mode operations
t
ns
1
1
CBPH
t
Maximum CE# pulse width
CLK period
4
4
4
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CEM
t
7.5
9.62
12
CLK
t
Chip select access time (fixed latency)
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
70
70
70
CO
t
2.5
1.5
3
2
4
2
CSP
t
HD
t
7
8
1.6
7
8
1.8
9
2
HZ
t
1.2
5.5
KHKL
t
CLK to WAIT valid
2
2
3
2
2
4
KHTL
t
Output HOLD from CLK
2
3
KOH
t
CLK HIGH or LOW time
KP
t
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
7
8
8
2
3
OHZ
t
3
2
3
3
3
3
OLZ
t
SP
Note:
1. A refresh opportunity must be provided every t
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
CEM
HIGH, or b) CE# HIGH for longer than 15ns.
2. The High-Z timings measure a 100mV transition from either V or V toward VccQ/2.
OH
OL
3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either V or V
OH
.
OL
33
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 14: Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol
Min
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
Address and ADV# LOW setup time to WE# LOW
Address HOLD from ADV# going HIGH
Address setup to ADV# going HIGH
Address valid to end of WRITE
LB#/UB# select to end of WRITE
CE# HIGH between subsequent async operations
CE# LOW to ADV# HIGH
AS
t
2
AVH
t
5
AVS
t
70
70
5
AW
t
BW
t
CPH
t
7
CVS
t
Chip enable to end of WRITE
Data HOLD from WRITE time
Data WRITE setup time
70
0
CW
t
DH
t
20
DW
t
Chip disable to WAIT High-Z output
ADV# pulse width
7
1
HZ
t
5
VP
t
ADV# setup to end of WRITE
WRITE to DQ High-Z output
WRITE pulse width
70
VS
t
8
1
2
WHZ
t
45
0
4000
WP
t
WRITE recovery time
WR
Note:
1. The High-Z timings measure a 100mV transition from either V or V toward VccQ/2.
OH
OL
2. WE# Low time must be limited to t
(4µs).
CEM
34
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Table 15: Burst WRITE Cycle Timing Requirements
133MHz
104MHz
83MHZ
Parameter
Symbol
Unit Notes
Min
Max
Min
Max
Min
Max
Address and ADV# LOW setup time
to WE# LOW
tAS
0
2
5
0
2
5
0
ns
ns
ns
1
t
Address HOLD from ADV# HIGH(fixed latency)
2
AVH
CE# HIGH between subsequent burst or
mixed mode operations
tCBPH
6
2
2
tCEM
tCLK
tCSP
tHD
4
4
4
Maximum CE# pulse width
Clock period
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
2.5
1.5
9.62
3
12
4
CE# setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
CLK rise or fall time
2
2
tHZ
7
8
1.6
7
8
1.8
9
3
tKHKL
tKHTL
1.2
5.5
Clock to WAIT valid
t
Output HOLD from CLK
2
3
2
2
3
3
2
3
3
KOH
tKP
tSP
CLK HIGH or LOW time
Setup time to activate CLK edge
Note:
1. t required if t
> 20ns.
AS
CSP
2. A refresh opportunity must be provided every t
HIGH, or b) CE# HIGH for longer than 15ns.
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
CEM
3. The High-Z timings measure a 100mV transition from either V or V toward VccQ/2.
OH
OL
35
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
TIMING DIAGRAMS
Figure 22: Initialization Period
Vcc(MIN)
Vcc, VccQ = 1.7V
Device ready for
normal operation
t
PU
Table 16: Initialization Timing Parameters
Parameter
Symbol
Min
Max
Unit
Initialization period (required before normal operations)
t
150
µs
PU
Figure 23: Asynchronous READ
V
V
IH
IL
A[20:16]
Valid Address
t
AA
t
t
AVH
AVS
V
V
IH
IL
ADV#
t
AADV
t
t
VP
t
HZ
CVS
V
IH
IL
CE# V
t
CO
t
BHZ
OHZ
t
BA
V
IH
IL
LB#/UB#
V
t
t
OE
V
V
IH
IL
OE#
V
V
IH
IL
t
OLZ
WE#
t
t
AVH
AVS
V
V
V
V
IH
IL
OH
A/DQ[15:0]
Valid address
t
Valid Output
OL
AA
t
HZ
tOEW
WAIT V
High-Z
High-Z
OH
OL
V
Undefined
Don’t Care
36
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 24: Single-Access Burst READ Operation - Variable Latency
t
t
t
KP
CLK
KP
V
IH
IL
CLK V
t
KHKL
t
t
SP
HD
V
IH
IL
Valid Address
A[20:16]
V
t
HD
t
SP
V
V
IH
IL
t
ADV#
CE#
HD
t
CEM
t
HZ
t
t
CSP
ABA
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
t
OHZ
t
BOE
OE#
t
t
t
OLZ
SP
HD
WE#
t
HD
t
SP
LB#/UB#
A/DQ[15:0]
t
t
t
ACLK
t
KOH
HD
SP
V
V
V
V
OH
IH
IL
Valid
Address
Valid Output
High-Z
High-Z
High-Z
OL
t
KOH
V
V
OH
OL
High-Z
WAIT
t
KHTL
t
KHTL
READ Burst Identified
(WE# = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
37
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 25: 4-Word Burst READ Operation - Variable Latency
t
t
t
t
KP
KHKL
CLK
KP
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
CLK
A[20:16]
ADV#
CE#
t
t
HD
SP
Valid Address
t
HD
t
SP
t
t
ABA
t
t
CBPH
CSP
HD
t
CEM
t
HZ
t
BOE
OE#
t
OHZ
t
t
t
HD
OLZ
SP
WE#
t
HD
t
SP
IH
IL
LB#/UB#
t
t
t
t
KOH
ACLK
HD
SP
V
V
OH
OL
Note 3
High-Z
IH
IL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
address
A/DQ[15:0]
t
KOH
Note 2
High-Z
OH
OL
High-Z
WAIT
t
KHTL
t
KHTL
READ Burst Identified
(WE# = HIGH)
Undefined
Don’t Care
Notes :
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT Will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
38
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 26: Single-Access Burst READ Operation - Fixed Latency
t
t
KP
t
CLK
KP
V
V
V
V
IH
IL
CLK
t
t
KHKL
SP
IH
IL
A[20:16]
Valid Address
t
AVH
t
AA
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
AADV
HD
t
CEM
t
HZ
t
CSP
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
CE#
OE#
t
CO
t
OHZ
t
BOE
t
OLZ
t
t
SP
HD
WE#
t
t
SP
HD
IH
IL
UB#/LB#
t
t
AVH
t
t
ACLK
SP
KOH
Valid Output
KOH
V
V
V
IH
IL
OH
Valid Address
High-Z
High-Z
A/DQ[15:0]
V
OL
t
V
OH
OL
High-Z
WAIT
V
t
KHTL
t
KHTL
READ Burst Identified
(WE# = HIGH)
Undefined
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
39
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 27: 4-Word Burst READ Operation - Fixed Latency
t
t
t
t
KP
KHKL
CLK
KP
V
V
V
V
IH
CLK
IL
t
SP
IH
IL
A[20:16]
Valid Address
t
AVH
t
AA
t
HD
t
V
V
SP
IH
ADV#
IL
t
AADV
t
CEM
t
t
CBPH
HD
t
CSP
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
CE#
OE#
t
HZ
t
CO
t
BOE
t
OHZ
t
OLZ
t
t
HD
SP
WE#
t
HD
t
SP
IH
IL
UB#/LB#
t
t
KOH
ACLK
t
t
AVH
SP
V
V
V
OH
OL
Note 3
High-Z
IH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
address
A/DQ[15:0]
WAIT
V
V
IL
t
KOH
OH
Note 2
High-Z
High-Z
V
OL
tKHTL
tKHTL
READ Burst Identified
(WE# = HIGH)
Undefined
Don’t Care
Notes :
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
40
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 28: Burst READ Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL
t
CLK
VIH
VIL
VIH
VIL
VIH
A[20:16]
ADV#
UB#/LB# V
IL
t
t
CSP
HD
Note 2
VIH
VIL
VIH
CE#
OE# V
IL
VIH
VIL
WE#
End of row
A/DQ[15:0]V
OH
Valid
Output
Valid
Output
VOL
t
t
HZ
HZ
t
KHTL
VOH
VOL
WAIT
High-Z
t
KOH
Undefined
Don’t Care
Notes :
1. Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW; WAIT asserted during delay.
2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( befor the second CLK after WAIT asserts with BCR[8]=0, or
before the third CLK after WAIT asserts with BCR[8]=1 ).
41
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 29: Burst READ Row Boundary Crossing
V
V
V
IH
IL
CLK
A[20:16]
ADV#
t
CLK
IH
V
V
IL
IH
V
IL
V
V
IH
IL
UB#/LB#
CE#
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
OE#
WE#
End of row
Valid output
t
t
HD
SP
V
V
OH
OL
Valid output
A/DQ[15:0]
WAIT
Valid output
Valid out
t
t
KTHL
KTHL
V
OH
Note 2
V
OL
t
KOH
t
KOH
Don’t Care
Note:
1. Nondefault BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as
solid line)
2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
42
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 30: Asynchronous WRITE
V
V
IH
Valid Address
A[20:16]
ADV#
IL
t
t
AVS
AVH
t
VS
t
VP
V
V
IH
t
t
AS
t
AW
IL
AS
t
CW
V
V
V
V
V
V
V
V
t
IH
IL
IH
IL
IH
IL
IH
IL
CVS
CE#
UB#/LB#
OE#
t
BW
t
WP
t
WE#
A/DQ[15:0]
WAIT
AS
t
t
t
t
DH
AVS
AVH
DW
V
IH
Valid Address
Valid Input
V
IL
V
V
t
OH
OL
AW
High-Z
Don’t Care
43
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 31: Burst WRITE Operation - Variable Latency Mode
t
t
t
KP
t
KHKL
CLK
KP
V
V
V
V
V
V
IH
IL
CLK
A[20:16]
ADV#
t
t
HD
SP
IH
IL
IH
IL
Valid Address
3
3
t
t
AS
t
t
SP
HD
AS
t
SP
t
HD
V
IH
UB#/LB#
CE#
V
V
IL
t
t
HD
CBPH
t
CSP
t
CEM
IH
IL
Note4
V
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
t
SP
HD
3
t
t
t
t
HD
AS
HD
SP
V
IH
IL
A/DQ[15:0]
Valid Address
D1
D2
D3
D0
V
t
t
KHTL
HZ
t
t
SP
KHTL
V
V
OH
OL
WAIT
High-Z
High-Z
Note 2
t
KOH
WRITE Burst Identified
(WE# = Low)
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted
during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
t
t
3. AS required if CSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
44
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 32: Burst WRITE Operation - Fixed Latency Mode
t
t
t
KP
t
KHKL
CLK
KP
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
CLK
A[20:16]
ADV#
t
SP
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Valid Address
3
3
t
t
t
AS
AVH
t
t
SP
HD
AS
t
SP
t
HD
UB#/LB#
CE#
t
t
CBPH
HD
t
CSP
t
CEM
Note 4
OE#
t
t
HD
SP
V
V
V
V
IH
IL
IH
IL
WE#
A/DQ[15:0]
WAIT
t
t
HD
t
3
SP
AVH
t
AS
Valid Address
t
D1
D2
D3
D0
t
t
KHTL
t
HZ
SP
KHTL
V
V
OH
OL
High-Z
High-Z
Note2
t
KOH
Don’t Care
WRITE Burst Identified
(WE# = LOW)
Note:
1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2(3 clocks), WAIT active LOW,
WAIT asserted during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
t
t
3. AS required if CSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
45
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL
t
CLK
VIH
VIL
VIH
VIL
VIH
VIL
VIH
A[20:16]
ADV#
UB#/LB#
t
t
HD
CSP
Note 2
CE# V
IL
VIH
OE#
VIL
VIH
VIL
VIH
VIL
WE#
A/DQ[15:0]
WAIT
t
t
HD
SP
Valid
Intput
Valid
Intput
t
t
HZ
HZ
End of row
VOH
VOL
High-Z
t
t
KOH
KHTL
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay.
(shown as solid line)
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with
BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).
46
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 34: Burst WRITE Row Boundary Crossing
V
V
V
V
IH
IL
CLK
t
CLK
IH
IL
A[20:16]
V
V
IH
IL
ADV#
V
V
V
V
IH
IL
IH
IL
UB#/LB#
CE#
V
V
V
V
IH
IL
IH
IL
OE#
WE#
End of row
Valid input
KTHL
t
t
HD
SP
V
IH
IL
A/DQ[15:0] V
Valid input
Valid input
Valid output
Valid output
t
t
KTHL
V
V
OH
OL
WAIT
t
KOH
t
KOH
Note 2
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as
solid line)
2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
47
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 35: Burst WRITE Followed by Burst READ
t
CLK
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
CLK
t
t
t
t
SP HD
SP HD
Valid
Valid
A[20:16]
Address
Address
t
t
SP HD
t
t
SP HD
ADV#
t
HD
t
SP
UB#/LB#
CE#
t
t
t
HD CBPH
CSP
Note 2
t
t
OHZ
CSP
OE#
t
t
t
t
SP
HD
SP HD
VIH
VIL
VIH
VIL
WE#
A/DQ[15:0]
WAIT
t
t
t
t
t
KOH
SP HD
t
SP
BOE
t
t
HD
SP HD
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
D0
D1
D2
D3
Address
VOH
VOL
t
ACLK
High-Z
High-Z
Undefined
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW,
WAIT asserted during delay.
t
2. A refresh opportunity must be provided every CEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
48
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 36: Asynchronous WRITE Followed by Burst READ
t
CLK
VIH
CLK
VIL
t
t
HD
SP
VIH
Valid Address
Valid Address
A[20:16]
VIL
t
t
AVH
AVS
t
t
t
HD
SP
VIH
VIL
t
VP
ADV#
t
t
AS
HD
t
BW
SP
VIH
VIL
UB#/LB#
CE#
t
t
CSP
CBPH
t
VIH
VIL
VIH
VIL
CW
Note 2
t
OHZ
OE#
WE#
t
t
t
SP HD
WP
VIH
VIL
t
WC
t
BOE
t
t
t
SP
HD
AS
VOH
VOL
VIH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Data
Valid Address
Valid Address
t
A/DQ[15:0] V
IL
t
t
t
DH
AVS
DW
t
AVH
ACLK
VOH
VOL
t
KHTL
tKOH
WAIT
High-Z
Undefined
Don’t Care
Note:
1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. When the divice is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the
t
device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided every CEM. A refresh opportunity is satisfied by
either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
49
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 37: Burst READ Followed by Asynchronous WRITE
t
CLK
V
V
V
V
IH
IL
CLK
t
t
HD
SP
IH
IL
Valid Address
Valid Address
A[20:16]
t
t
AVH
AVS
t
VS
t
t
HD
t
SP
VP
V
V
IH
IL
ADV#
t
AS
t
AW
t
t
CBPH
HD
t
t
CSP
CW
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
CE#
OE#
t
HZ
Note 2
t
OHZ
t
BOE
t
t
t
t
t
t
WPH
AS
SP
HD
OLZ
WP
WE#
t
t
t
HD
BW
t
SP
IH
IL
UB#/LB#
t
AS
t
t
t
HD
t
t
KOH
t
SP
ACLK
t
DW
DH
AVS
AVH
VOH
VOL
VIH
VIL
IH
IL
Valid Address
Valid Address
Valid Output
Valid Input
A/DQ[15:0]
WAIT
t
KOH
V
V
OH
OL
High-Z
High-Z
t
KHTL
t
KHTL
Undefined
Don’t Care
READ Burst Identified
(WE# = HIGH)
Notes:
1. Nondefault BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW
when the device is transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity
t
must be provided every CEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH
for longer than 15ns.
50
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
Figure 38: Asynchronous WRITE Followed by Asynchronous READ
VIH
Valid Address
t
Valid Address
A[20:16]
VIL
t
t
t
AVS
AVH
AVH
AVS
t
AA
t
AS
t
t
AW
VS
t
AADV
VIH
VIL
tVP
tVP
t
ADV#
WR
t
AS
t
t
BHZ
CVS
t
BA
VIH
VIL
VIH
VIL
VIH
VIL
t
BW
UB#/LB#
CE#
t
t
HZ
t
CPH
CO
t
CVS
t
CW
Note 1
t
OHZ
t
OLZ
t
OE
OE#
t
WP
WE#V
IH
VIL
t
AS
t
AA
t
AW
VIH
VIL
VOH
VOL
Valid Address
t
Valid Address
A/DQ[15:0]
WAIT
Valid Input
t
V
alid Output
t
t
t
t
t
AVH
AVS
AVS
AVH
HZ
DS
DH
t
OEZ
VOH
VOL
High-Z
Undefined
Don’t Care
Note:
t
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( CPH) to schedule the appropriate refresh
t
interval. Otherwise, CPH is only required after CE#-controlled WRITEs.
51
Preliminary
EMC326SP16AK
2Mx16 CellularRAM AD-MUX
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
12. Power
11. Speed
10. PKG
4. Function
9. Option
5. Technology
8. Version
6. Operating Voltage
1. Memory Component
7. Organization
8. Version
Blank ----------------- Mother die
A ----------------------- 2’nd generation
B ----------------------- 3’rd generation
C ----------------------- 4’th generation
D ----------------------- 5’th generation
2. Device Type
6 ---------------------- Low Power SRAM
7 ---------------------- STRAM
C ---------------------- CellularRAM
9. Option
3. Density
Blank ---- No optional mode
4 ----------------------- 4M
8 ----------------------- 8M
16 --------------------- 16M
32 --------------------- 32M
64 --------------------- 64M
28 --------------------- 128M
H ----------- Demultiplexed with DPD
J ------------ Demultiplexed with DPD & RBC
K ------------ Multiplexed with RBC
L ------------ Multiplexed with DPD & RBC
10. Package
Blank ---------------------- Wafer
4. Function
S
T
U
P
Z
Y
V
---------------------- 32 sTSOP1
---------------------- 32 TSOP1
---------------------- 44 TSOP2
---------------------- 48 FPBGA
---------------------- 52 FPBGA
---------------------- 54 FPBGA
---------------------- 90 FPBGA
2 ----Multiplexed async.
3-----Demultiplexed async. with page mode
4-----Demultiplexed async. with direct DPD
5-----Multiplexed sync.
6-----Optional mux/demuxed sync.
5. Technology
S ----------------------- Single Transistor & Trench Cell
11. Speed (@async.)
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
6. Operating Voltage
V ----------------------- 3.3V
U ----------------------- 3.0V
S ----------------------- 2.5V
R ----------------------- 2.0V
P ----------------------- 1.8V
L ----------------------- 1.5V
7. Organization
12. Power
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power
(Pb-Free&Green)
L ---------------------- Low Power
52
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