EN29LV160BT-70BIP_技术文档

EN29LV160B

Purpose

Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on

ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the

compositions of the ICs. Eon is still keeping the promise of quality for all the products with the

same as that of Eon delivered before. Please be advised with the change and appreciate your

kindly cooperation and fully support Eon’s product family.

Eon products’ New Top Marking

cFeon Top Marking Example:

cFeon

Part Number: XXXX-XXX

Lot Number: XXXXX

Date Code: XXXXX

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as an Eon product. Any

changes that have been made are the result of normal data sheet improvement and are noted in

the document revision summary, where supported. Future routine revisions will occur when

appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To

order these products, during the transition please specify “Eon top marking” or “cFeon top marking”

on your purchasing orders.

For More Information

Please contact your local sales office for additional information about Eon memory solutions.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

1

Rev. I, Issue Date: 2011/10/26

EN29LV160B

16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory

Boot Sector Flash Memory, CMOS 3.0 Volt-only

FEATURES

• 3.0V, single power supply operation

- Minimizes system level power requirements

• JEDEC Standard program and erase

commands

• High performance

- Access times as fast as 70 ns

• JEDEC standard DATA# polling and toggle

bits feature

• Low power consumption (typical values at 5

MHz)

- 9 mA typical active read current

- 20 mA typical program/erase current

- Less than 1 μA standby current

• Single Sector and Chip Erase

• Sector Unprotect Mode

• Embedded Erase and Program Algorithms

• Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

• Flexible Sector Architecture:

- One 16-Kbyte, two 8-Kbyte, one 32-Kbyte,

and thirty-one 64-Kbyte sectors (byte mode)

- One 8-Kword, two 4-Kword, one 16-Kword

and thirty-one 32-Kword sectors (word mode)

• Triple-metal double-poly triple-well CMOS

Flash Technology

• Sector protection :

• Low Vcc write inhibit < 2.5V

- Hardware locking of sectors to prevent

program or erase operations within individual

sectors

• minimum 100K program/erase endurance

cycle

- Additionally, temporary Sector Group

Unprotect allows code changes in previously

locked sectors.

• Package Options

- 48-pin TSOP (Type 1)

- 48 ball 6mm x 8mm TFBGA

• High performance program/erase speed

- Byte/Word program time: 8µs typical

- Sector erase time: 100ms typical

- Chip erase time: 4s typical

• Industrial Temperature Range

GENERAL DESCRIPTION

The EN29LV160B is a 16-Megabit, electrically erasable, read/write non-volatile flash memory,

organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 8µs. The

EN29LV160B features 3.0V voltage read and write operation, with access times as fast as 70ns to

eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV160B has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)

controls, which eliminate bus contention issues. This device is designed to allow either single Sector or

full chip erase operation, where each Sector can be individually protected against program/erase

operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K

program/erase cycles on each Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

2

Rev. I, Issue Date: 2011/10/26

EN29LV160B

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

Vss

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Vcc

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

9

Standard

TSOP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

Vss

CE#

A0

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

3

Rev. I, Issue Date: 2011/10/26

EN29LV160B

TABLE 1. PIN DESCRIPTION

FIGURE 1. LOGIC DIAGRAM

EN29LV160B

Pin Name

A0-A19

DQ0-DQ14

DQ15 / A-1

CE#

Function

20 Addresses

DQ0 – DQ15

(A-1)

A0 – A19

15 Data Inputs/Outputs

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

Reset#

CE#

OE#

Chip Enable

OE#

Output Enable

Hardware Reset Pin

Ready/Busy Output

Write Enable

RY/BY#

WE#

Byte#

RESET#

RY/BY#

WE#

Supply Voltage

(2.7-3.6V)

Vcc

Vss

Ground

NC

Not Connected to anything

Byte/Word Mode

BYTE#

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

4

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 2. Top Boot Sector Address Tables (EN29LV160BT)

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Word Mode

Sector A19 A18 A17 A16 A15 A14 A13 A12

Byte mode (x8)

(x16)

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

000000–00FFFF

00000–07FFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FBFFF

FC000–FCFFF

FD000–FDFFF

FE000–FFFFF

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8/4

1

X

16/8

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

5

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 3. Bottom Boot Sector Address Tables (EN29LV160BB)

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Word Mode

Sector A19 A18 A17 A16 A15 A14 A13 A12

Byte mode (x8)

(x16)

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

16/8

8/4

000000–003FFF

00000–01FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

02000–02FFF

03000–03FFF

04000–07FFF

08000–0FFFF

10000–17FFF

18000–1FFFF

20000–27FFF

28000–2FFFF

30000–37FFF

38000–3FFFF

40000–47FFF

48000–4FFFF

50000–57FFF

SA2

0

1

8/4

SA3

1

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

58000–5FFFF

60000–67FFF

68000–6FFFF

70000–77FFF

78000–7FFFF

80000–87FFF

88000–8FFFF

90000–97FFF

98000–9FFFF

A0000–A7FFF

A8000–AFFFF

B0000–B7FFF

B8000–BFFFF

C0000–C7FFF

C8000–CFFFF

D0000–D7FFF

D8000–DFFFF

E0000–E7FFF

E8000–EFFFF

F0000–F7FFF

F8000–FFFFF

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

6

Rev. I, Issue Date: 2011/10/26

EN29LV160B

PRODUCT SELECTOR GUIDE

Product Number

EN29LV160B

Speed

-70

70

30

Max Access Time, ns (t_acc

Max CE# Access, ns (t_ce)

Max OE# Access, ns (t_oe)

)

BLOCK DIAGRAM

RY/BY#

Vcc

Vss

DQ0-DQ15 (A-1)

Block Protect Switches

Erase Voltage Generator

Input/Output Buffers

State

Control

WE#

Program Voltage

Generator

Command

Register

STB

Chip Enable

Output Enable

Logic

Data Latch

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

Vcc Detector

Timer

Cell Matrix

A0-A19

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

7

Rev. I, Issue Date: 2011/10/26

EN29LV160B

TABLE 3. OPERATING MODES

16M FLASH USER MODE TABLE

DQ8-DQ15

A0-

A19

Byte#

= V_IH

D_OUT

D_IN

Byte#

= V_IL

High-Z

Operation

CE#

OE# WE#

Reset#

DQ0-DQ7

Read

Write

L

H

L

H

A_IN

X

D_OUT

D_IN

H

X

H

X

V_cc± 0.3V

H

L

V_cc± 0.3V

CMOS Standby

TTL Standby

Output Disable

Hardware Reset

Temporary

X

H

X

High-Z

High-Z High-Z

H

L

X

V_ID

A_IN

D_IN

X

Sector Unprotect

Notes:

L=logic low= V_IL, H=Logic High= V_IH, V_ID=11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),

D_IN=Data In, D_OUT=Data Out, A_IN=Address In

TABLE 4. Autoselect Codes (Using High Voltage, V_ID)

16M FLASH MANUFACTURER/DEVICE ID TABLE

A19

to

A12

A11

to

A10

A5

A9²A8 A7 A6 to

DQ8

to

DQ15 DQ0

DQ7

to

Description

CE#

L

OE# WE#

A1 A0

A2

L

7FH

Manufacturer ID:

Eon

L

H

X

V_ID

X

L

X

L

X

H¹

1CH

C4H

Device

Word

ID

(top boot

block)

Device

ID

(bottom

boot

block)

L

H

22h

X

H

Byte

Word

L

H

22h

X

49H

X

V_ID

X

L

H

L

Byte

01h

(Protected)

00h

(Unprotected)

X

Sector Protection

Verification

L

H

SA

V_ID

H

Note:

1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration

code 7Fh

2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

8

Rev. I, Issue Date: 2011/10/26

EN29LV160B

USER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the

byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word

configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only

data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are

tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV160B has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).

It is placed in CMOS-compatible standby when the CE# pin is at V_CC± 0.5. RESET# and BYTE# pin

must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which

reduces the maximum V_CCcurrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin

is at V_IH. When in standby modes, the outputs are in a high-impedance state independent of the OE#

input.

Read Mode

The device is automatically set to reading array data after device power-up. No commands are required

to retrieve data. The device is also ready to read array data after completing an Embedded Program or

Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.

The system can read array data using the standard read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See “Erase Suspend/Erase Resume Commands” for more additional information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset Command” additional details.

Output Disable Mode

When the CE# or OE# pin is at a logic high level (V_IH), the output from the EN29LV160B is disabled.

The output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming

equipment to automatically match a device to be programmed with its corresponding programming

algorithm. However, the autoselect codes can also be accessed in-system through the command

register.

When using programming equipment, the autoselect mode requires V_ID(10.5 V to 11.5 V) on address

pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when

verifying sector protection, the sector address must appear on the appropriate highest order address

bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the

remaining address bits that are don’t-care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on DQ15–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via the

command register, as shown in the Command Definitions table. This method does not require V_ID. See

“Command Definitions” for details on using the autoselect mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

9

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Write Mode

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two

unlock write cycles, followed by the program set-up command. The program address and data are

written next, which in turn initiate the Embedded Program algorithm. The system is not required to

provide further controls or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the

address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and

addresses are no longer latched. The system can determine the status of the program operation by

using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be

programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”,

or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding

read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The

hardware sector unprotection feature re-enables both program and erase operations in previously

protected sectors.

There are two methods to enabling this hardware protection circuitry. The first one requires only that

the RESET# pin be at V and then standard microprocessor timings can be used to enable or disable

ID

this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.

When doing Sector Unprotect, all the other sectors should be protected first.

The second method is meant for programming equipment. This method requires V be applied to

ID

both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in

a separate document called EN29LV160B Supplement, which can be obtained by contacting a

representative of Eon Silicon Solution, Inc.

Temporary Sector Unprotect

Start

This feature allows temporary unprotection of previously protected

sector groups to change data while in-system. The Sector

Unprotect mode is activated by setting the RESET# pin to V_ID.

During this mode, formerly protected sectors can be programmed

or erased by simply selecting the sector addresses. Once is

removed from the RESET# pin, all the previously protected sectors

Reset#=V_ID(note 1)

Perform Erase or Program

Operations

are protected again.

diagrams for more details.

See accompanying figure and timing

Reset#=V_IH

Notes:

Temporary Sector

Unprotect Completed _{(note 2)}

1. All protected sectors unprotected.

2. Previously protected sectors protected

again.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

10

Rev. I, Issue Date: 2011/10/26

EN29LV160B

COMMON FLASH INTERFACE (CFI)

The common flash interface (CFI) specification outlines device and host systems software interrogation

handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device families. Flash vendors can standardize their

existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array

data.

The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper

address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the

reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The

device enters the CFI query mode and the system can read CFI data at the addresses given in Tables

5–8. The system must write the reset command to return the device to the autoselect mode.

Table 5. CFI Query Identification String

Adresses

(Word Mode) (Byte Mode)

Data

Description

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h Query Unique ASCII string “QRY”

0059h

0002h

0000h

0040h

Primary OEM Command Set

Address for Primary Extended Table

0000h

Alternate OEM Command set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists

0000h

Table 6. System Interface String

Addresses

(Word Mode) (Byte Mode)

Data

Description

Vcc Min (write/erase)

D7-D4: volt, D3 –D0: 100 millivolt

Vcc Max (write/erase)

D7-D4: volt, D3 –D0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

0036h

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h Vpp Min. voltage (00h = no Vpp pin present)

0000h Vpp Max. voltage (00h = no Vpp pin present)

0004h Typical timeout per single byte/word write 2^N ꢀs

Typical timeout for Min, size buffer write 2^N ꢀs (00h = not

supported)

20h

40h

0000h

21h

22h

23h

24h

25h

42h

44h

46h

48h

4Ah

000Ah Typical timeout per individual block erase 2^N ms

0000h Typical timeout for full chip erase 2^N ms (00h = not supported)

0005h Max. timeout for byte/word write 2^N times typical

0000h Max. timeout for buffer write 2^N times typical

0004h Max. timeout per individual block erase 2^N times typical

Max timeout for full chip erase 2^N times typical (00h = not

supported)

26h

4Ch

0000h

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

11

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 7. Device Geometry Definition

Addresses

(Word mode)

27h

Addresses

(Byte Mode)

4Eh

50h

Data

0015h

0002h

0000h

0004h

0000h

0040h

0000h

0001h

0000h

0020h

0000h

0080h

0000h

001Eh

0000h

0001h

Description

Device Size = 2^N byte

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

Flash Device Interface description (refer to CFI publication

100)

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

52h

54h

56h

58h

5Ah

5Ch

5Eh

60h

62h

64h

66h

68h

6Ah

6Ch

6Eh

70h

72h

74h

76h

78h

Number of Erase Block Regions within device

Erase Block Region 1 Information

(refer to the CFI specification of CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

38h

39h

3Ah

3Bh

3Ch

Table 8. Primary Vendor-specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

Query-unique ASCII string “PRI”

40h

41h

42h

43h

44h

80h

82h

84h

86h

0050h

0052h

0049h

0031h

0030h

Major version number, ASCII

Minor version number, ASCII

88h

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0001h

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

49h

92h

0004h

4Ah

4Bh

4Ch

94h

96h

98h

0000h

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

12

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Hardware Data protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes as seen in the Command Definitions table. Additionally, the

following hardware data protection measures prevent accidental erasure or programming, which might

otherwise be caused by false system level signals during Vcc power up and power down transitions, or

from system noise.

Low V_CCWrite Inhibit

When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during Vcc

power up and power down. The command register and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The system must

provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than

V_LKO

.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH, or WE# = V_IH. To initiate a write

cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all

logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even with

CE# = V_IL, WE#= V_ILand OE# = V_IH, the device will not accept commands on the rising edge of WE#.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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13

Rev. I, Issue Date: 2011/10/26

EN29LV160B

COMMAND DEFINITIONS

The operations of the EN29LV160B are selected by one or more commands written into the command

register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase,

Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at

specific addresses via the command register. The sequences for the specified operation are defined in

the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper

sequences will reset the device to Read Mode.

Table 9. EN29LV160B Command Definitions

Bus Cycles

1^st

2^nd

Write Cycle

Data

3^rd

Write Cycle

4^th

5^th

6^th

Write Cycle

Data Add Data

Command

Sequence

Write Cycle

Add

RA

xxx

Data Add

Add

Data

Add

Data

Add

Read

Reset

1

RD

F0

000

100

000

200

x01

x02

7F

1C

7F

1C

22C4

C4

Word

Byte

555

2AA

55

555

Manufacturer

ID

4

AA

90

AAA

Device ID

Top Boot

Word

Byte

555

AAA

2AA

55

555

AAA

4

AA

90

555

Device ID

Bottom Boot

Word

Byte

555

2AA

555

x01

x02

2249

49

55

AAA

555

AAA

2AA

(SA) XX00

X02

(SA) 00

Word

Byte

555

Sector Protect

Verify

XX01

4

AA

55

90

AAA

555

AAA

X04

01

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

xxx

55

AA

2AA

55

555

AAA

555

AAA

555

Program

4

6

AA

A0

80

PA

PD

555

2AA

555

AAA

555

2AA

555

2AA

555

10

Chip Erase

55

AA

55

AAA

2AA

555

Sector Erase

55

SA

30

AAA

Erase Suspend

Erase Resume

1

B0

30

Word

Byte

CFI Query

1

98

Address and Data values indicated in hex

RA = Read Address: address of the memory location to be read. This is a read cycle.

RD = Read Data: data read from location RA during Read operation. This is a read cycle.

PA = Program Address: address of the memory location to be programmed. X = Don’t-Care

PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A12 uniquely select any Sector.

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to

retrieve data. The device is also ready to read array data after completing an Embedded Program or

Embedded Erase algorithm.

Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array

data using the standard read timings, with the only difference in that if it reads at an address within

erase suspended sectors, the device outputs status data. After completing a programming operation in

the Erase Suspend mode, the system may once again read array data with the same exception.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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14

Rev. I, Issue Date: 2011/10/26

EN29LV160B

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or

while in the autoselect mode. See next section for details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t-

care for this command.

The reset command may be written between the sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however, the

device ignores reset commands until the operation is complete. The reset command may be written

between the sequence cycles in a program command sequence before programming begins. This

resets the device to reading array data (also applies to programming in Erase Suspend mode). Once

programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must be written to return to reading array data (also

applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to

reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected. The Command Definitions table shows the

address and data requirements. This is an alternative to the method that requires V_IDon address bit A9

and is intended for PROM programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number

of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word / Byte Programming Command

The device can be programmed by byte or by word, depending on the state of the Byte# Pin.

Programming the EN29LV160B is performed by using a four-bus-cycle operation (two unlock write

cycles followed by the Program Setup command and Program Data Write cycle). When the program

command is executed, no additional CPU controls or timings are necessary. An internal timer

terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,

whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.

Programming status can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit).

When the program operation is successfully completed, the device returns to read mode and the user

can read the data programmed to the device at that address. Note that data can not be programmed

from a “0” to a “1”. Only an erase operation can change a data from “0” to “1”. When programming time

limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read

mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

15

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by

the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not

require the system to preprogram prior to erase. The Embedded Erase algorithm automatically

preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or timings during these operations. The Command

Definitions table shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables

in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing

two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed

by the address of the sector to be erased, and the sector erase command. The Command Definitions

table shows the address and data requirements for the sector erase command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and

addresses are no longer latched. The system can determine the status of the erase operation by using

DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4

illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the

“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for

timing waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected for erasure. This command is valid only during

the sector erase operation. The Erase Suspend command is ignored if written during the chip erase

operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase

Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation

Status” for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for

more information. The Autoselect command is not supported during Erase Suspend Mode.

This Data Sheet may be revised by subsequent versions

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16

Rev. I, Issue Date: 2011/10/26

EN29LV160B

The system must write the Erase Resume command (address bits are don’t-care) to exit the erase

suspend mode and continue the sector erase operation. Further writes of the Resume command are

ignored. Another Erase Suspend command can be written after the device has resumed erasing.

WRITE OPERATION STATUS

DQ7

DATA# Polling

The EN29LV160B provides DATA# polling on DQ7 to indicate the status of the embedded operations.

The DATA# polling feature is active during Byte Programming, Sector Erase, Chip Erase, and Erase

Suspend. (See Table 10)

When the embedded Programming is in progress, an attempt to read the device will produce the

complement of the data written to DQ7. Upon the completion of the Byte Programming, an attempt to

read the device will produce the true data written to DQ7. For the Byte Programming, DATA# polling is

valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7

output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output

during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE#

or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or

CE# pulse for chip erase or sector erase.

DATA# Polling must be performed at any address within a sector that is being programmed or erased

and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used

is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the

output enable (OE#) is low. This means that the device is driving status information on DQ7 at one

instant of time and valid data at the next instant of time. Depending on when the system samples the

DQ7 output, it may read the status of valid data. Even if the device has completed the embedded

operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data

on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing

diagram is shown in Figure 8.

RY/BY#: Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in

progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together

in parallel with a pull-up resistor to Vcc.

In the output-low period, signifying Busy, the device is actively erasing or programming. This includes

programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is

ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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17

Rev. I, Issue Date: 2011/10/26

EN29LV160B

DQ6

Toggle Bit I

The EN29LV160B provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming

and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device at

any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the

embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read

on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising

edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid

after the rising edge of the sixth WE# pulse for sector erase or chip erase.

In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,

then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read

mode without changing data in all protected sectors.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown

in Figure 9.

DQ5 Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or

erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the

device has successfully completed its operation and has returned to read mode, the user must check

again to see if the DQ6 is toggling after detecting a “1” on DQ5.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,

the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a

“1.” Under both these conditions, the system must issue the reset command to return the device to

reading array data.

DQ3 Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be used to determine whether

or not an erase operation has begun. (The sector erase timer does not apply to the chip erase

command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not support

multiple sector erase command sequences so it is not very meaningful since it immediately shows as a

“1” after the first 30h command. Future devices may support this feature.

DQ2 Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2

toggles when the system reads at addresses within those sectors that have been selected for erasure.

(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to

compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.

See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical

form.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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18

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle

bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, a system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still toggling, the device did not complete the

operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5

has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive

read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose

to perform other system tasks. In this case, the system must start at the beginning of the algorithm

when it returns to determine the status of the operation (top of Flowchart 6).

Write Operation Status

Operation

DQ7

DQ6

DQ5

DQ3

DQ2

RY/BY#

Embedded Program

Algorithm

No

toggle

DQ7#

Toggle

0

N/A

1

0

1

Standar

d Mode

Embedded Erase Algorithm

0

1

Toggle

Reading within Erase

Suspended Sector

Reading within Non-Erase

Suspended Sector

No

Toggle

N/A

Toggle

Erase

Suspend

Mode

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend Program

DQ7#

Toggle

This Data Sheet may be revised by subsequent versions

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19

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 10. Status Register Bits

DQ

Name

Logic Level

Definition

Erase Complete or

erase Sector in Erase suspend

Erase On-Going

‘1’

‘0’

DATA#

POLLING

7

Program Complete or

data of non-erase Sector

during Erase Suspend

Program On-Going

DQ7

DQ7#

‘-1-0-1-0-1-0-1-’

DQ6

‘-1-1-1-1-1-1-1-‘

Erase or Program On-going

Read during Erase Suspend

Erase Complete

TOGGLE

BIT

6

5

3

‘1’

‘0’

‘1’

‘0’

Program or Erase Error

Program or Erase On-going

Erase operation start

TIME OUT BIT

ERASE TIME

OUT BIT

Erase timeout period on-going

Chip Erase, Erase or Erase

suspend on currently

addressed

Sector. (When DQ5=1, Erase

Error due to currently

addressed Sector. Program

during Erase Suspend on-

going at current address

‘-1-0-1-0-1-0-1-’

TOGGLE

BIT

2

Erase Suspend read on

non Erase Suspend Sector

DQ2

Notes:

DQ7 DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for

Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive

reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Time Out Bit: set to “1” if failure in programming or erase

DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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20

Rev. I, Issue Date: 2011/10/26

EN29LV160B

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data# Poll Device

Verify Data?

No

Yes

Last

Increment

Address

No

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

See the Command Definitions section for more information.

555H / AAH

2AAH / 55H

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

This Data Sheet may be revised by subsequent versions

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21

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

Data# Poll from

System or Toggle Bit

successfully

completed

Data =FFh?

No

Yes

Erase Done

Flowchart 4. Embedded Erase Command Sequence

See the Command Definitions section for more information.

Chip Erase

555H/AAH

Sector Erase

555H/AAH

2AAH/55H

555H/80H

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

Sector Address/30H

This Data Sheet may be revised by subsequent versions

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22

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Flowchart 5. DATA# Polling

Algorithm

Start

Read Data

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data (1)

Notes:

Yes

(1) This second read is necessary in case the

first read was done at the exact instant when

the status data was in transition.

DQ7 = Data?

No

Fail

Pass

Start

Flowchart 6. Toggle Bit Algorithm

Read Data twice

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data twice (2)

Notes:

No

(2) This second set of reads is necessary in case

the first set of reads was done at the exact

instant when the status data was in transition.

DQ6 = Toggle?

Yes

Fail

Pass

This Data Sheet may be revised by subsequent versions

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23

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Flowchart 7a. In-System Sector Protect Flowchart

START

PLSCNT = 1

RESET# = V_ID

Wait 1 μs

No

First Write

Cycle =

60h?

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

Sector Protect: Write 60h

to sector addr with

A6 = 0, A1 = 1, A0 = 0

Wait 150 μs

Verify Sector Protect:

Write 40h to sector

address with

A6 = 0, A1 = 1, A0 = 0

Increment

PLSCNT

Reset

PLSCNT = 1

Wait 0.4 μs

Read from sector

address with

A6 = 0, A1 = 1, A0 = 0

No

Data = 01h?

Yes

PLSCNT = 25?

Yes

Device failed

Yes

Protect another

sector?

No

Remove V_ID

from RESET#

Write reset

command

Sector Protect

Algorithm

Sector Protect

complete

This Data Sheet may be revised by subsequent versions

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24

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Flowchart 7b. In-System Sector Unprotect Flowchart

START

PLSCNT = 1

Protect all sectors:

The indicated portion

of the sector protect

RESET# = V_ID

algorithm must be

performed for all

Wait 1 μS

unprotected sectors

prior to issuing the

first sector unprotect

No

address (see

Diagram 7a.)

Temporary Sector

Unprotect Mode

First Write

Cycle = 60h?

Yes

No

All sectors

protected?

Yes

Set up first sector

address

Sector Unprotect: Write 60H to

sector address with A6 = 1,

A1 = 1, A0 = 0

Wait 15 ms

Verify Sector Unprotect:

Write 40h to sector address

with A6 = 1, A1 = 1, A0 =0

Increment

PLSCNT

Wait 0.4 μS

Read from sector address with

A6 = 1, A1 = 1, A0 = 0

No

PLSCCNT =

1000?

Set up next sector

Data = 00h?

address

Yes

Sector

Unprotect

Algorithm

No

Last sector

verified?

Device failed

Yes

Remove V_IDfrom

RESET#

Write reset

command

Sector Unprotect

complete

This Data Sheet may be revised by subsequent versions

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25

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 11. DC Characteristics

(T_a= - 40°C to 85°C; V_CC= 2.7-3.6V)

Symbol

Parameter

Test Conditions

Min

Max

Unit

Typ

Input Leakage Current

Output Leakage Current

±5

16

µA

I

0V≤ V ≤ Vcc

IN

LI

I

0V≤ V ≤ Vcc

OUT

LO

Active Read Current ( Byte mode)

Active Read Current ( Word mode)

9

mA

CE# = V ; OE# = V

IL

IH ;

I

CC1

f = 5MHZ

CE# = BYTE# =

RESET# = Vcc ± 0.3V

(Note 1)

Supply Current (Standby-

CMOS)

1

5.0

µA

I

CC2

CC3

Byte program, Sector or

Chip Erase in progress

20

30

mA

Supply Current (Program or Erase)

Input Low Voltage

-0.5

0.8

V

IL

0.7 x

Vcc

Vcc +

0.3

Input High Voltage

V

IH

Output Low Voltage

0.45

V

I

= 4.0 mA

OL

Vcc -

0.4V

Output High Voltage CMOS

V

OH

I

= -100μA

OH

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

10.5

11.5

100

V

ID

A9 = V_ID

µA

I

ID

Supply voltage (Erase and

Program lock-out)

V

LKO

2.3

2.5

V

Notes

1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they

draw power if not at full CMOS supply voltages.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

26

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Test Conditions

Test Specifications

Test Conditions

Output Load Capacitance, C_L

Input Rise and Fall times

Input Pulse Levels

-70

30

Unit

pF

ns

5

0.0-3.0

V

Input timing measurement

reference levels

Output timing measurement

reference levels

1.5

V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

27

Rev. I, Issue Date: 2011/10/26

EN29LV160B

AC CHARACTERISTICS

Hardware Reset (Reset#)

Speed

Unit

Paramete

r Std

Test

Setup

Description

-70

RESET# Pulse Width (During Embedded Algorithms)

RESET# Pulse Width (NOT During Embedded Algorithms)

Reset# High Time Before Read

t_RP1

t_RP2

t_RH

t_RB1

t_RB2

t_READY1

Min

10

500

50

0

us

ns

RY/BY# Recovery Time ( to CE#, OE# go low)

RY/BY# Recovery Time ( to WE# go low)

Reset# Pin Low (During Embedded Algorithms)

to Read or Write

Reset# Pin Low (NOT During Embedded Algorithms)

to Read or Write

50

Max

20

us

ns

t_READY2

500

Figure 1. AC Waveforms for RESET#

Reset# Timings

t_RB1

CE#, OE#

WE#

t_READY1

t_RB2

RY/BY#

RESET#

t_RP1

Reset Timing during Embedded Algorithms

CE#, OE#

t_RH

RY/BY#

RESET#

t_RP2

t_READY2

Reset Timing NOT during Embedded Algorithms

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

28

Rev. I, Issue Date: 2011/10/26

EN29LV160B

AC CHARACTERISTICS

Word / Byte Configuration (Byte#)

Speed

Std

Parameter

Test

Setup

Unit

-70

0

Description

t_BCS

Byte# to CE# switching setup time

CE# to Byte# switching hold time

RY/BY# to Byte# switching hold time

Min

ns

t_CBH

0

t_RBH

0

Figure 2. AC Waveforms for BYTE#

CE#

OE#

Byte#

t_CBH

t_BCS

Byte# timings for Read Operations

CE#

WE#

Byte#

t_RBH

t_BCS

RY/BY#

Byte #timings for Write Operations

Note: Switching BYTE# pin not allowed during embedded operations

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

29

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 12. AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Speed

Symbols

Test Setup

Description

Unit

JEDEC

Standard

-70

Min

70

ns

t_AVAV

t_RC

Read Cycle Time

CE# = V_IL

OE#= V_IL

Max

70

30

20

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ACC

t_CE

t_OE

t_DF

Address to Output Delay

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

Output Enable to Output High Z

OE#= V_IL

t_DF

Output Hold Time from

Addresses, CE# or OE#,

whichever occurs first

Min

0

ns

t_AXQX

t_OH

MIn

Min

0

ns

Read

Toggle and

DATA# Polling

Output Enable

Hold Time

t_OEH

10

Notes:

1. High Z is Not 100% tested.

2. For - 70 Vcc = 2.7V – 3.6V

Output Load : 30pF

Input Rise and Fall Times: 5ns

Input Rise Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level, Input and Output: 1.5 V

Figure 3. AC Waveforms for READ Operations

t_RC

Addresses

Addresses Stable

t_ACC

CE#

t_DF

t_OE

OE#

t_OEH

WE#

Outputs

RESET#

RY/BY#

t_CE

t_OH

HIGH Z

Output Valid

0V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. I, Issue Date: 2011/10/26

www.eonssi.com

30

EN29LV160B

Table 13. AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter

Speed

Symbols

Description

Unit

JEDEC

Standard

-70

Min

70

ns

t_AVAV

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_WC

Write Cycle Time (Note 1)

0

t_AS

t_AH

t_DS

t_DH

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

45

30

Min

MIn

Min

0

ns

Read

Output Enable

Hold Time

Toggle and

DATA# Polling

t_OEH

10

Read Recovery Time before Write (OE#

High to WE# Low)

Min

0

ns

t_GHWL

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_GHWL

t_CS

CE# SetupTime

CE# Hold Time

Min

Typ

Max

Typ

Max

Min

Max

Min

0

ns

µs

s

t_CH

35

20

8

t_WP

Write Pulse Width

t_WPH

Write Pulse Width High

Programming Operation

(Word AND Byte Mode)

t_WHWH1t_WHWH1

200

0.1

4

Erase Operation

(Note 2)

Sector

Chip

t_WHWH2t_WHWH2

s

50

70

0

µs

ns

t_VCS

t_BUSY

Vcc Setup Time

B

WE# High to RY/BY# Low

t_RB

Recovery Time from RY/BY#

1. Not 100% tested.

2. See Erase and Programming Performance for more information.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

31

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 14. AC CHARACTERISTICS

Write (Erase/Program) Operations

Alternate CE# Controlled Writes

Parameter

Speed

Symbols

Description

Unit

JEDEC

Standard

-70

Min

70

ns

t_AVAV

t_AVEL

t_ELAX

t_DVEH

t_EHDX

t_WC

Write Cycle Time (Note 1)

0

45

30

0

t_AS

t_AH

Address Setup Time

Address Hold Time

Data Setup Time

t_DS

t_DH

t_OES

Data Hold Time

0

Output Enable Setup Time

Min

0

ns

Read

Output Enable

Hold Time

t_OEH

Toggle and Data Polling

10

Read Recovery Time before Write

(OE# High to CE# Low)

Min

0

ns

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_GHEL

t_WS

Min

Typ

Max

Typ

0

ns

µs

s

WE# SetupTime

t_WH

WE# Hold Time

35

20

8

t_CP

Write Pulse Width

Write Pulse Width High

t_CPH

Programming Operation

t_WHWH1t_WHWH1

(Byte AND word mode) (Note 2)

200

0.1

4

Erase Operation

(Note 2)

Sector

Chip

t_WHWH2t_WHWH2

t_VCS

s

Min

50

0

µs

ns

Vcc Setup Time

Recovery Time from RY/BY#

t_RB

1. Not 100% tested.

2. See Erase and Programming Performance for more information.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

32

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 15. ERASE AND PROGRAMMING PERFORMANCE

Limits

Max

Parameter

Comments

Typ

Unit

Sector Erase Time

Chip Erase Time

0.1

2

sec

Excludes 00h programming prior

to erasure

4

8

35

sec

µs

Byte Programming Time

Word Programming Time

200

µs

Excludes system level overhead

Minimum 100K cycles

Byte

16.8

8.4

50.4

25.2

Chip Programming

sec

Time

Word

Erase/Program Endurance

100K

cycles

Notes: Maximum program and erase time assume the following conditions V = 2.7 V , 85°C

cc

Table 16. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

= 0

Package

TSOP

BGA

Typ

6

Max

7.5

1.2

12

Unit

C

IN

V

IN

Input Capacitance

pF

1.2

8.5

1.1

7.5

1.0

TSOP

BGA

C

OUT

V

OUT

= 0

Output Capacitance

pF

1.2

9

TSOP

BGA

C

IN2

V

IN

= 0

Control Pin Capacitance

1.3

Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.

Table 17. DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C

125°C

10

20

Years

Data Retention Time

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

33

Rev. I, Issue Date: 2011/10/26

EN29LV160B

AC CHARACTERISTICS

Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings

Erase Command Sequence (last 2 cycles)

Read Status Data (last two cycles)

t_AS

SA

t_AH

t_WC

Addresses

CE#

0x2AA

VA

0x555 for chip

erase

t_GHW

L

t_CH

OE#

WE#

t_WP

t_WPH

t_CS

t_WHWH2

Data

0x55

t_DS

0x30

Status

D_OUT

t_RB

10 for chip

erase

t_DH

t_BUSY

RY/BY#

V_CC

t_VCS

Notes:

1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, D_out=true data at read address.

2. V_ccshown only to illustrate t_vcsmeasurement references. It cannot occur as shown during a valid command

sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

34

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Figure 5. Program Operation Timings

Program Command Sequence (last 2 cycles)

t_AS

PA

t_AH

t_WC

Addresses

CE#

0x555

PA

t_GHWL

t_CH

OE#

WE#

t_WP

t_WPH

t_WHWH1

t_CS

Data

D_OUT

t_RB

OxA0

Status

PD

t_DS

t_DH

t_BUSY

RY/BY#

V_CC

t_VCS

Notes:

1. PA=Program Address, PD=Program Data, D_OUTis the true data at the program address.

2. V_CCshown in order to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid command

sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

35

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

t_RC

Addresses

CE#

VA

t_ACC

VA

t_CH

t_CE

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Comple

-ment

Valid Data

Complement

Status Data

True

DQ[7]

Status

Data

True

DQ[6:0]

t_BUSY

RY/BY#

Notes:

1. VA=Valid Address for reading Data# Polling status data

2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.

Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

t_RC

Addresses

CE#

VA

t_CH

t_ACC

t_CE

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Valid Data

Valid Status

(first read)

Valid Status

DQ6, DQ2

RY/BY#

t_BUSY

(second read)

(stops toggling)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

36

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Figure 8. Alternate CE# Controlled Write Operation Timings

PA for Program

SA for Sector Erase

0x555 for Program

0x2AA for Erase

0x555 for Chip Erase

Addresses

WE#

VA

t_WC

t_AS

t_AH

t_WH

t_GHEL

OE#

CE#

Data

t_CP

t_CPH

t_WHWH1/ t_WHWH2

t_WS

t_BUSY

t_DH

t_DS

Status

D_OUT

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

0xA0 for

Program

0x55 for Erase

RY/BY

t_RH

Reset#

Notes:

PA = address of the memory location to be programmed.

PD = data to be programmed at byte address.

VA = Valid Address for reading program or erase status

D_out= array data read at VA

Shown above are the last two cycles of the program or erase command sequence and the last status read cycle

Reset# shown to illustrate t_RHmeasurement references. It cannot occur as shown during a valid command

sequence.

Figure 9. DQ2 vs. DQ6

Enter

Embedded

Erase

Enter Erase

Suspend

Program

Erase

Suspend

Erase

Resume

WE#

Erase

Enter

Suspend

Read

Enter

Suspend

Program

Erase

Suspend

Read

Erase

Complete

Erase

DQ6

DQ2

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

37

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Table 19. Temporary Sector Unprotect

Speed Option

-70

Unit

Parameter

Description

Std

t_VIDR

t_RSP

V_IDRise and Fall Time

Min

500

4

ns

µs

RESET# Setup Time for Temporary

Sector Unprotect

Notes: t_RSPis Not 100% tested.

Figure 10. Temporary Sector Unprotect Timing Diagram

V_ID

RESET#

0 or 3 V

t_VIDR

CE#

WE#

t_RSP

RY/BY#

Figure 11. Sector Protect/Unprotect Timing Diagram

V_ID

Vcc

RESET#

0V

t_VIDR

SA,

A6,A1,A0

Valid

60h

Valid

Data

60h

40h

Status

Sector Protect/Unprotect

Verify

CE#

>0.4μS

WE#

>1μS

Sector Protect: 150 uS

Sector Unprotect: 15 mS

OE#

Notes:

Use standard microprocessor timings for this device for read and write cycles.

For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

38

Rev. I, Issue Date: 2011/10/26

EN29LV160B

FIGURE 12. 48L TSOP 12mm x 20mm package outline

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

39

Rev. I, Issue Date: 2011/10/26

EN29LV160B

FIGURE 13. 48L TFBGA 6mm x 8mm package outline

DIMENSION IN MM

NOR

SYMBOL

MIN.

- - -

MAX

1.30

0.35

0.95

8.10

6.10

- - -

A

A1

A2

D

- - -

0.29

0.91

8.00

6.00

5.60

4.00

0.80

0.40

0.23

0.84

7.90

5.90

- - -

E

D1

E1

e

- - -

b

0.35

0.45

Note : 1. Coplanarity: 0.1 mm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

40

Rev. I, Issue Date: 2011/10/26

EN29LV160B

ABSOLUTE MAXIMUM RATINGS

Parameter

Value

Unit

°C

Storage Temperature

-65 to +150

°C

Plastic Packages

-65 to +125

-55 to +125

Ambient Temperature

With Power Applied

Output Short Circuit Current¹

200

mA

V

A9, OE#, Reset# ²

-0.5 to +11.5

Voltage with

Respect to Ground

All other pins ³

Vcc

-0.5 to Vcc+0.5

-0.5 to + 4.0

V

Notes:

1.

2.

No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.

Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may

undershoot V_ssto –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input

voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.

3.

4.

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V_ssto –1.0V for periods of

up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is V_cc+ 0.5

V. During voltage transitions, outputs may overshoot to V_cc+ 1.5 V for periods up to 20ns. See figure below.

Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress

rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the

device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES¹

Parameter

Value

Unit

Ambient Operating Temperature

Industrial Devices

°C

-40 to 85

Operating Supply Voltage

Vcc

Full Voltage Range:

2.7 to 3.6V

V

3. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+1.5V

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot

Waveform

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

41

Rev. I, Issue Date: 2011/10/26

EN29LV160B

ORDERING INFORMATION

EN29LV160B

T

-

70

T

I

P

PACKAGING CONTENT

(Blank) = Conventional

P = RoHS compliant

TEMPERATURE RANGE

I = Industrial (-40°C to +85°C)

PACKAGE

T = 48-pin TSOP

B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA)

0.80mm pitch, 6mm x 8mm package

SPEED

70 = 70ns

BOOT CODE SECTOR ARCHITECTURE

T = Top boot Sector

B = Bottom boot Sector

BASE PART NUMBER

EN = Eon Silicon Solution Inc.

29LV = FLASH, 3V Read Program Erase

160 = 16 Megabit (2M x 8 / 1M x 16)

B = version identifier

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

42

Rev. I, Issue Date: 2011/10/26

EN29LV160B

Revisions List

Revision No Description

Date

A

B

C

Preliminary draft

2008/03/12

1. Remove 44-pin SOP package on page 1、2 、39 and 44.

2. Remove C grade option of temperature range on page 1 and page 44

3. Update 48 pin TSOP-I package outline on page 38

Modify Figure 5. AC Waveforms for READ Operations in page 29

1. Delete -90 Speed option in datasheet.

2008/06/17

2008/07/17

2. Add t_OEHon table12.

3. Delete t_OES, t_VIDRand add t_BUSYon Table13.

4. Delete t_VIDRand add t_RBon Table 14.

D

2008/08/01

E

F

Add Chip Erase Time Max value in Table 15 on page 32.

Add 48L TFBGA package A1, A2 dimension maximum value on page

39.

Add Eon products’ New top marking “cFeon“ information on page 1.

1. Update Erase and Program performance on page 2 and 32.

2. Modify Table 10 Status Register Bits DQ5 from ERROE BIT to TIME

OUT BIT on page 20.

2008/08/21

2008/08/29

2009/01/09

G

3. Modify I_OHfrom -100mA to -100μA on page 26

4. Modify Test Conditions illustration on page 27.

5. Update Hardware Reset (RESET#) table and Figure 1. AC

Waveforms for RESET# on page 28

6. Update Table 13. Write (Erase/Program) Operations on page 31.

7. Update Table 14. Write (Erase/Program) Operations on page 32

8. Update Figure 4. AC Waveforms for Chip/Sector Erase Operations

Timings on page 34

H

2009/4/20

9. Update Figure 8. Alternate CE# Controlled Write Operation Timings

on page 37

10. Modify Storage Temperature from "-65 to + 125" to "-65 to +150" on

page 41.

11. Modify P = Pb free to P = RoHS compliant on page 42.

12. Remove the Latch up Characteristics Table from version G.

1. Correct the typo of V_IH(max.) = Vcc + 0.3V on page 26.

2. Add BGA PACKAGE CAPACITANCE on page 33.

I

2011/10/26

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

43

Rev. I, Issue Date: 2011/10/26


型号：	EN29LV160BT-70BIP
厂家：	EON SILICON SOLUTION INC.
描述：	16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only 16兆位（ 2048K ×8位/ 1024K ×16位）闪存引导扇区快闪记忆体， CMOS 3.0伏只闪存
文件：	总43页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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