EN29LV320AB-90B_技术文档

EN29LV320A

32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory

Boot Sector Flash Memory, CMOS 3.0 Volt-only

FEATURES

• Single power supply operation

- Full voltage range: 2.7 to 3.6 volts read and

write operations

• Standard DATA# polling and toggle bits

feature

• Unlock Bypass Program command supported

• High performance

- Access times as fast as 70 ns

• Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

• Low power consumption (typical values at 5

MHz)

- 9 mA typical active read current

- 20 mA typical program/erase current

- Less than 1 μA current in standby or automatic

sleep mode.

• Support JEDEC Common Flash Interface

(CFI).

• Low Vcc write inhibit < 2.5V

• Minimum 100K program/erase endurance

cycles.

• Flexible Sector Architecture:

- Eight 8-Kbyte sectors, sixty-three 64k-byte

sectors.

- 8-Kbyte sectors for Top or Bottom boot.

- Sector/Sector Group protection:

Hardware locking of sectors to prevent

program or erase operations within individual

sectors

• RESET# hardware reset pin

- Hardware method to reset the device to read

mode.

• WP#/ACC input pin

- Write Protect (WP#) function allows

protection of outermost two boot sectors,

regardless of sector protect status

Additionally, temporary Sector Group

Unprotect allows code changes in previously

locked sectors.

- Acceleration (ACC) function provides

accelerated program times

• High performance program/erase speed

- Word program time: 8µs typical

- Sector erase time: 500ms typical

- Chip erase time: 70s typical

• Package Options

- 48-pin TSOP (Type 1)

- 48 ball 6mm x 8mm FBGA

• Commercial and Industrial Temperature

Range.

• JEDEC Standard compatible

GENERAL DESCRIPTION

The EN29LV320A is a 32-Megabit, electrically erasable, read/write non-volatile flash memory,

organized as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8µs. The

EN29LV320A features 3.0V voltage read and write operation, with access times as fast as 70ns to

eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV320A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)

controls, which eliminate bus contention issues. This device is designed to allow either single Sector

or full Chip erase operation, where each Sector can be individually protected against program/erase

operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K

program/erase cycles on each Sector.

.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

1

Rev. B, Issue Date: 2007/07/17

EN29LV320A

CONNECTION DIAGRAMS

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

DQ15/A-1

G5

H6

A13

A12

A14

A15

A16

BYTE#

F5

Vss

A5

B5

C5

D5

E5

H5

A9

A8

A10

A11

DQ7

DQ14

F4

DQ13

G4

DQ6

A4

WE#

A3

B4

RESET#

B3

C4

NC

C3

D4

A19

D3

E4

DQ5

E3

H4

DQ12

F3

Vcc

G3

DQ4

H3

RY/BY#

A2

WP# /ACC

B2

DQ3

H2

A18

C2

A20

DQ2

E2

DQ10

F2

DQ11

G2

D2

A7

A1

A17

B1

A6

C1

A5

D1

DQ0

E1

DQ8

F1

DQ9

G1

DQ1

H1

A3

A4

A2

A1

A0

CE#

OE#

Vss

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

2

Rev. B, Issue Date: 2007/07/17

EN29LV320A

TABLE 1. PIN DESCRIPTION

LOGIC DIAGRAM

Pin Name

A0-A20

DQ0-DQ14

DQ15 / A-1

CE#

Function

EN29 LV320

21 Address inputs

15 Data Inputs/Outputs

DQ0 – DQ15

(A-1)

A0 – A20

DQ15 (data input/output, in word mode),

A-1 (LSB address input, in byte mode)

WP#/ACC

RESET#

CE#

Chip Enable

OE#

Output Enable

OE#

RY/BY#

WE#

Write Enable

BYTE#

WP#/ACC

RESET#

BYTE#

RY/BY#

Vcc

Write Protect / Acceleration Pin

Hardware Reset Pin

Byte/Word mode selection

Ready/Busy Output

Supply Voltage

(2.7-3.6V)

Vss

Ground

NC

Not Connected to anything

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

3

Rev. B, Issue Date: 2007/07/17

EN29LV320A

ORDERING INFORMATION

EN29LV320A

T

─

70

T

C

P

PACKAGING CONTENT

(Blank) = Conventional

P = Pb Free

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE

T = 48-pin TSOP

B = 48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80mm pitch, 6mm x 8mm package

SPEED

70 = 70ns

90 = 90ns

BOOT CODE SECTOR ARCHITECTURE

T = Top boot Sector

B = Bottom boot Sector

BASE PART NUMBER

EN = EON Silicon Solution Inc.

29LV = FLASH, 3V Read, Program and Erase

320A = 32 Megabit (4M x 8 / 2M x 16)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

4

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Table 2A. Top Boot Sector Address Tables (EN29LV320AT)

Sector Size

(Kbytes / Kwords)

Address Range (h) Address Range (h)

Sector

A20 – A12

Byte mode (x8)

Word Mode (x16)

SA0

SA1

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

64/32

000000–00FFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

5

Rev. B, Issue Date: 2007/07/17

EN29LV320A

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

64/32

8/4

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3F1FFF

3F2000–3F3FFF

3F4000–3F5FFF

3F6000–3F7FFF

3F8000–3F9FFF

3FA000–3FBFFF

3FC000–3FDFFF

3FE000–3FFFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1F8FFF

1F9000–1F9FFF

1FA000–1FAFFF

1FB000–1FBFFF

1FC000–1FCFFF

1FD000–1FDFFF

1FE000–1FEFFF

1FF000–1FFFFF

8/4

Note: The address bus is A20:A-1 in byte mode where BYTE# = V_ILor A20:A0 in word mode where

BYTE# = V_IH

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

6

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Table 2B. Bottom Boot Sector Address Tables (EN29LV320AB)

Sector Size

(Kbytes / Kwords)

Address Range (h) Address Range (h)

Sector

A20 – A12

Byte mode (x8)

Word Mode (x16)

SA0

SA1

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

8/4

000000–001FFF

000000–000FFF

001000–001FFF

002000–002FFF

003000–003FFF

004000–004FFF

005000–005FFF

006000–006FFF

007000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

8/4

002000–003FFF

004000–005FFF

006000–007FFF

008000–009FFF

00A000–00BFFF

00C000–00DFFF

00E000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

7

Rev. B, Issue Date: 2007/07/17

EN29LV320A

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

64/32

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

Note: The address bus is A20:A-1 in byte mode where BYTE# = V_ILor A20:A0 in word mode where

BYTE# = V_IH

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

8

Rev. B, Issue Date: 2007/07/17

EN29LV320A

PRODUCT SELECTOR GUIDE

Product Number

EN29LV320A

Speed Option

-70

-90

70

30

90

35

Max Access Time, ns (t_acc

Max CE# Access, ns (t_ce)

Max OE# Access, ns (t_oe)

)

Notes:

1. Vcc=3.0 – 3.6 V for 70ns read operation

BLOCK DIAGRAM

RY/BY#

Vcc

Vss

DQ0-DQ15 (A-1)

Block Protect Switches

Erase Voltage Generator

Input/Output Buffers

State

Control

WE#

Program Voltage

Generator

Command

Register

STB

Chip Enable

Output Enable

Logic

Data Latch

CE#

OE#

Y-Decoder

Y-Gating

STB

Vcc Detector

Timer

X-Decoder

Cell Matrix

A0-A20

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

9

Rev. B, Issue Date: 2007/07/17

EN29LV320A

TABLE 3. OPERATING MODES

32M FLASH USER MODE TABLE

DQ8-DQ15

RESET

#

WP#/AC

C

A0-

A20

DQ0-

DQ7

BYTE#

= V_IH

D_OUT

D_IN

BYTE#

= V_IL

DQ8-

DQ14=

High-Z,

DQ15 =

A-1

Operation

CE#

OE#

WE#

Read

Write

L

H

L

H

L/H

(Note 1)

A_IN

D_OUT

D_IN

Accelerated

Program

L

H

L

H

V_HH

A_IN

D_IN

V_cc

0.3V

H

L

X

±

V_cc

0.3V

H

L

±

CMOS Standby

X

H

X

High-Z

TTL Standby

Output Disable

Hardware Reset

X

H

X

H

X

H

L/H

X

High-Z

SA,

Sector (Group)

Protect

A6=L,

A1=H,

A0=L

SA,

A6=H,

A1=H,

A0=L

L

H

L

V_ID

L/H

(Note 2)

X

Sector

Unprotect

L

H

X

L

V_ID

(Note 1)

Temporary

Sector

X

A_IN

(Note 2) (Note 2) High-Z

Unprotect

L=logic low= V_IL, H=Logic High= V_IH, V_ID=V_HH=11 ± 0.5V = 10.5-11.5V, X=Don’t Care (either L or H, but not floating ),

SA=Sector Addresses, D_IN=Data In, D_OUT=Data Out, A_IN=Address In

Notes:

1. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP# / ACC = V_IH, the outermost boot sector

protection depends on whether they were last protected or unprotected. If WP#/ACC = V_HH, all sectors will be

unprotected.

2. Please refer to “Sector/Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

10

Rev. B, Issue Date: 2007/07/17

EN29LV320A

TABLE 4. Autoselect Codes (Using High Voltage, V_ID)

32M FLASH MANUFACTURER/DEVICE ID TABLE

A20

WE# to

A11

to

A5

A9²A8 A7 A6 to

DQ8

A1 A0 to

Description

CE# OE#

DQ7 to DQ0

A12

A10

A2

DQ15

H¹

L

1Ch

7Fh

Manufacturer ID:

Eon

L

H

X

V_ID

X

L

X

L

X

Device ID

(top boot

sector)

Device ID

(bottom boot

sector)

Word

Byte

L

H

22h

X

F6h

F9h

X

V_ID

X

L

X

L

H

Word

Byte

22h

X

01h

X

Sector Protection

Verification

(Protected)

L

H

SA

X

V_ID

X

L

X

H

L

00h

(Unprotected)

L=logic low= V_IL, H=Logic High= V_IH, V_ID=11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector

Addresses

Note:

1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a

configuration code 7Fh.

2. A9 = V_IDis for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

11

Rev. B, Issue Date: 2007/07/17

EN29LV320A

USER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte

or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word configuration,

DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only

data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-

stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV320A has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).

It is placed in CMOS-compatible standby when the CE# pin is at V_CC± 0.5. RESET# and BYTE# pin must

also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the

maximum V_CCcurrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V_IH. When

in standby modes, the outputs are in a high-impedance state independent of the OE# input.

Automatic Sleep Mode

The EN29LV320A has a automatic sleep mode, which minimizes power consumption. The devices will

enter this mode automatically when the states of address bus remain stable for t^acc+ 30ns. ICC4 in the DC

Characteristics table shows the current specification. With standard access times, the device will output

new data when addresses change.

Read Mode

The device is automatically set to reading array data after device power-up or hardware reset. No

commands are required to retrieve data. The device is also ready to read array data after completing an

Embedded Program or Embedded Erase algorithm

After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase

Suspend mode. The system can read array data using the standard read timings, except that if it reads at

an address within erase-suspended sectors, the device outputs status data. After completing a

programming operation in the Sector Erase Suspend mode, the system may once again read array data

with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional

information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes

high or while in the autoselect mode. See the “Reset Command” for additional details.

Output Disable Mode

When the OE# pin is at a logic high level (V_IH), the output from the EN29LV320A is disabled. The output

pins are placed in a high impedance state.

Autoselect Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming

equipment to automatically match a device to be programmed with its corresponding programming

algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_ID(10.5 V to 11.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

12

Rev. B, Issue Date: 2007/07/17

EN29LV320A

sector protection, the sector address must appear on the appropriate highest order address bits. Refer to

the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining

address bits that are don’t-care. When all necessary bits have been set as required, the programming

equipment may then read the corresponding identifier code on DQ15–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via the

command register, as shown in the Command Definitions table. This method does not require V_ID. See

“Command Definitions” for details on using the autoselect mode.

Writing Command Sequences

To write a command or command sequence to program data to the device or erase data, the system has

to drive WE# and CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or

words. An erase operation can erase one sector or the whole chip.

The system can also read the autoselect codes by entering the autoselect mode, which need the

autoselect command sequence to be written. Please refer to the “Command Definitions” for all the

available commands.

RESET#: Hardware Reset

When RESET# is driven low for t_RP, all output pins are tristates. All commands written in the internal state

machine are reset to reading array data.

Please refer to timing diagram for RESET# pin in “AC Characteristics”.

Sector/Sector Group Protection & Chip Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector. The

hardware chip unprotection feature re-enables both program and erase operations in previously protected

sectors. A sector group implies three or four adjacent sectors that would be protected at the same time. Please

see the following tables which show the organization of sector groups.

There are two methods to enable this hardware protection circuitry. The first one requires only that the

RESET# pin be at V_IDand then standard microprocessor timings can be used to enable or disable this

feature. See Flowchart 7a and 7b for the algorithm and Figure. 12 for the timings.

When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect

write cycle.

The second method is for programming equipment. This method requires V_IDto be applied to both OE#

and A9 pins and non-standard microprocessor timings are used. This method is described in a separate

document named EN29LV320A Supplement, which can be obtained by contacting a representative of Eon

Silicon Solution, Inc.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

13

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Top Boot Sector/Sector Group Organization Table (EN29LV320AT) for (Un)Protection

Sector Group

SG 0

SG 1

SG 2

SG 3

SG 4

SG 5

SG 6

SG 7

SG 8

SG 9

SG10

SG11

SG12

SG13

SG14

Sectors

A20-A12

Sector Group Size

64 Kbytes x 4

SA 0-SA 3

SA 4-SA 7

SA 8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

0000XXXXX

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

111100XXX

111101XXX

111110XXX

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

SG15

SA60-SA62

64 Kbytes x 3

SG16

SG17

SG18

SG19

SG20

SG21

SG22

SG23

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

8 Kbytes

Bottom Boot Sector/Sector Group Organization Table (EN29LV320AB) for (Un)Protection

Sector Group

SG23

SG22

SG21

SG20

SG19

SG18

SG17

SG16

SG15

SG14

SG13

SG12

SG11

SG10

SG 9

Sectors

A20-A12

Sector Group Size

64 Kbytes x 4

SA70-SA67

SA66-SA63

SA62-SA59

SA58-SA55

SA54-SA51

SA50-SA47

SA46-SA43

SA42-SA39

SA38-SA35

SA34-SA31

SA30-SA27

SA26-SA23

SA22-SA19

SA18-SA15

SA14-SA11

1111XXXXX

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

1010XXXXX

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

000011XXX

000010XXX

000001XXX

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

SG 8

SA10-SA 8

64 Kbytes x 3

SG 7

SG 6

SG 5

SG 4

SG 3

SG 2

SG 1

SG 0

SA 7

SA 6

SA 5

SA 4

SA 3

SA 2

SA 1

SA 0

8 Kbytes

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

14

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Write Protect / Accelerated Program (WP# / ACC)

The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware method

of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing

throughput at the factory, using an external high voltage.

When WP#/ACC is Low, the device protects the outermost tw 8K-byte Boot Sector; no matter the sectors

are protected or unprotected using the method described in “Sector/Sector Group Protection & Chip

Unprotection”, Program and Erase operations in these sectors are ignored.

When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8K-byte

boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte Boot

Sector unless the sector is protected using Sector Protection.

When WP#/ACC is raised to V_HHthe memory automatically enters the Unlock Bypass mode(please refer

to “Command Definitions”), temporarily unprotects every protected sectors, and reduces the time required

for program operation. The system would use a two-cycle program command sequence as required by

the Unlock Bypass mode. When WP#/ACC returns to V_IHor V_IL, normal operation resumes. The

transitions from V_IHor V_ILto V_HHand from V_HHto V_IHor V_ILmust be slower than t_VHH, see Figure 11.

Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin must not

be at V_HHfor operations other than accelerated programming. It could cause the device to be damaged.

Never raise this pin to V_HHfrom any mode except Read mode, otherwise the memory may be left in an

indeterminate state.

A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the currents

required during Unlock Bypass Program.

Temporary Sector Unprotect

Start

This feature allows temporary unprotection of previously protected

sector groups to change data while in-system. The Temporary

Sector Unprotect mode is activated by setting the RESET# pin to

VBIDB. During this mode, formerly protected sectors can be

programmed or erased by simply selecting the sector addresses.

Once VBIDB is removed from the RESET# pin, all the previously

Reset#=V_{ID (note 1)}

Perform Erase or Program

Operations

protected sectors are protected again.

flowchart and figure 10 for more timing details.

See accompanying

RESET#=V_IH

Temporary Sector Unprotect

Completed _{(note 2)}

Notes:

1. All protected sectors are unprotected. (If

WP#/ACC=V_IL, outermost boot sectors will remain

protected.)

2. Previously protected sectors are protected again.

COMMON FLASH INTERFACE (CFI)

The common flash interface (CFI) specification outlines device and host systems software

interrogation handshake, which allows specific vendor-specified software algorithms to be used for

entire families of devices. Software support can then be device-independent, JEDEC ID-

independent, and forward- and backward-compatible for the specified flash device families. Flash

vendors can standardize their existing interfaces for long-term compatibility.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

15

Rev. B, Issue Date: 2007/07/17

EN29LV320A

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte mode), any time the device is ready to read

array data.

The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper

address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the

reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The

device enters the CFI query mode and the system can read CFI data at the addresses given in

Tables 5–8. The system must write the reset command to return the device to the autoselect mode.

Table 5. CFI Query Identification String

Addresses

Adresses

(Word Mode) (Byte Mode)

Data

Description

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h Query Unique ASCII string “QRY”

0059h

0002h

0000h

0040h

Primary OEM Command Set

Address for Primary Extended Table

0000h

Alternate OEM Command set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

0000h

Table 6. System Interface String

Addresses

(Word Mode) (Byte Mode)

Data

Description

0027h Vcc Min (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

0036h Vcc Max (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

0000h Vpp Min. voltage (00h = no Vpp pin present)

0000h Vpp Max. voltage (00h = no Vpp pin present)

1Bh

1Ch

36h

38h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

Typical timeout per single byte/word write 2^NμS

0004h

0000h

Typical timeout for Min, size buffer write 2^NμS (00h = not supported)

000Ah Typical timeout per individual block erase 2^Nms

0000h Typical timeout for full chip erase 2^Nms (00h = not supported)

0005h Max. timeout for byte/word write 2^Ntimes typical

0000h Max. timeout for buffer write 2^Ntimes typical

0004h Max. timeout per individual block erase 2^Ntimes typical

0000h Max timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 7. Device Geometry Definition

Addresses

(Word mode)

27h

Addresses

(Byte Mode)

4Eh

Data

0016h

0002h

0000h

Description

Device Size = 2^Nbytes

28h

29h

50h

52h

Flash Device Interface description (refer to CFI publication 100)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

16

Rev. B, Issue Date: 2007/07/17

EN29LV320A

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

54h

56h

58h

5Ah

5Ch

5Eh

60h

62h

64h

66h

68h

6Ah

6Ch

6Eh

70h

72h

74h

76h

78h

0000h

0002h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device

Erase Block Region 1 Information

(refer to the CFI specification of CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

Table 8. Primary Vendor-specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

Query-unique ASCII string “PRI”

40h

41h

42h

43h

44h

80h

82h

84h

86h

0050h

0052h

0049h

0031h

Major version number, ASCII

Minor version number, ASCII

88h

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Minimum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV

Maximum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0004h

0001h

49h

92h

0004h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

94h

96h

98h

9Ah

9Ch

9Eh

0000h

00A5h

00B5h

0002h/ Top/Bottom Boot Sector Identifier

0003h 02h = Bottom Boot, 03h = Top Boot

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

17

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Hardware Data protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes as seen in the Command Definitions table. Additionally, the

following hardware data protection measures prevent accidental erasure or programming, which

might otherwise be caused by false system level signals during Vcc power up and power down

transitions, or from system noise.

Low V_CCWrite Inhibit

When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during

Vcc power up and power down. The command register and all internal program/erase circuits are

disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The

system must provide the proper signals to the control pins to prevent unintentional writes when Vcc

is greater than V_LKO

.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH, or WE# = V_IH. To initiate a

write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#

are all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even

with CE# = V_IL, WE#= V_ILand OE# = V_IH, the device will not accept commands on the rising edge of

WE#.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

18

Rev. B, Issue Date: 2007/07/17

EN29LV320A

COMMAND DEFINITIONS

The operations of the device are selected by one or more commands written into the command

register. Commands are made up of data sequences written at specific addresses via the

command register. The sequences for the specified operation are defined in the Command

Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will

reset the device to Read Mode.

Table 9. EN29LV320A Command Definitions

Bus Cycles

3^rdCycle 4^thCycle

Command

Sequence

1^stCycle

2^ndCycle

5^thCycle

6^thCycle

Addr

Data

RD

F0

Addr

Data

Addr

Data

Addr Data

Addr

Data

Addr

Data

Read

Reset

1

RA

xxx

000

100

000

200

7F

Word

555

2AA

555

Manufacturer

ID

1C

7F

1C

4

AA

55

90

Byte

AAA

Word

Byte

555

2AA

555

2AA

555

x01

x02

x01

x02

22F6

Device ID

Top Boot

4

AA

55

90

AAA

555

AAA

555

F6

Word

Byte

22F9

F9

Device ID

Bottom Boot

AAA

555

AAA

2AA

(SA)

X02

(SA)

X04

00

01

00

01

Word

555

Sector Protect

Verify

4

AA

55

90

Byte

AAA

555

AAA

555

Word

2AA

Program

4

3

AA

A0

20

PA

PD

Byte

AAA

555

AAA

555

Word

2AA

Unlock Bypass

55

Byte

AAA

555

PA

AAA

Unlock Bypass Program

Unlock Bypass Reset

2

XXX A0

XXX 90

PD

XXX 00

Word

555

AA

2AA

55

555

2AA

555

Chip Erase

6

80

AA

55

10

30

Byte

Word

Byte

AAA

555

AAA

555

AAA

555

AAA

555

2AA

555

AAA

555

AA

2AA

55

Sector Erase

SA

AAA

555

Sector Erase Suspend

Sector Erase Resume

1

xxx

B0

30

xxx

55

Word

Byte

CFI Query

1

98

AA

Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles

RA = Read Address: address of the memory location to be read. This is a read cycle.

RD = Read Data: data read from location RA during Read operation. This is a read cycle.

PA = Program Address: address of the memory location to be programmed. X = Don’t-Care

PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

19

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to

retrieve data. The device is also ready to read array data after completing an Embedded Program

or Embedded Erase algorithm.

Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system

can read array data using the standard read timings from sectors other than the one which is being

erase-suspended. If the system reads at an address within erase-suspended sectors, the device

outputs status data. After completing a programming operation in the Sector Erase Suspend mode,

the system may once again read array data with the same exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high

during an active program or erase operation or while in the autoselect mode. See next section for

details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are

don’t-care for this command.

The reset command may be written between the cycle sequences in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however,

the device ignores reset commands until the operation is complete. The reset command may be

written between the sequence cycles in a program command sequence before programming begins.

This resets the device to reading array data (also applies to programming in Sector Erase Suspend

mode). Once programming begins, however, the device ignores reset commands until the operation

is complete.

The reset command may be written between the cycle sequences in an autoselect command

sequence. Once in the autoselect mode, the reset command must be written to return to reading

array data.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device

to reading array data (also applies in Sector Erase Suspend mode).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices

ID codes, and determine whether or not a sector (group) is protected. The Command Definitions

table shows the address and data requirements. This is an alternative to the method that requires

V_IDon address bit A9 and is intended for commercial programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at addresses shown in Table 9 any

number of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array

data.

Word / Byte Programming Command

The device can be programmed by byte or by word, depending on the state of the BYTE# Pin.

Programming the EN29LV320A is performed by using a four-bus-cycle operation (two unlock write

cycles followed by the Program Setup command and Program Data Write cycle). When the program

command is executed, no additional CPU controls or timings are necessary. An internal timer

terminates the program operation automatically. Address is latched on the falling edge of CE# or

WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

20

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Any commands written to the device during the program operation are ignored. Programming status

can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the

program operation is successfully completed, the device returns to read mode and the user can read

the data programmed to the device at that address. Note that data can not be programmed from a

“0” to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was successful. However, a succeeding read will show

that the data is still “0”. Only erase operations can convert a “0” to a “1”. When programming time

limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to

Read mode.

Programming is allowed in any sequence across sector boundaries.

Unlock Bypass

To speed up programming operation, the Unlock Bypass Command may be used. Once this feature

is activated, the shorter two-cycle Unlock Bypass Program command can be used instead of the

normal four-cycle Program Command to program the device. During the unlock bypass mode, only

the Unlock Bypass Program and Unlock Bypass Reset command can be accepted. This mode is

exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature

disabled

The device provides accelerated program operations through the WP#/ACC pin. When WP#/ACC is

asserted to V_HH, the device automatically enters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass Program command sequence.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing

two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then

followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The

device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any controls or timings during these

operations. The Command Definitions table shows the address and data requirements for the chip

erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and addresses are no longer latched.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by

writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are

then followed by the address of the sector to be erased, and the sector erase command. The

Command Definitions table shows the address and data requirements for the sector erase

command sequence.

Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All

other commands are ignored. If there are several sectors to be erased, Sector Erase Command

sequences must be issued for each sector. That is, only a sector address can be specified for

each Sector Erase command. Users must issue another Sector Erase command for the next

sector to be erased after the previous one is completed.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

21

Rev. B, Issue Date: 2007/07/17

EN29LV320A

When the Embedded Erase algorithm is completed, the device returns to reading array data and

addresses are no longer latched. The system can determine the status of the erase operation by

using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits.

Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations

tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing

diagram for timing waveforms.

Sector Erase Suspend / Resume Command

The Sector Erase Suspend command allows the system to interrupt a sector erase operation and

then read data from, or program data to, any sector not selected for erasure. This command is valid

only during the sector erase operation. The Sector Erase Suspend command is ignored if written

during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when

writing the Sector Erase Suspend command.

When the Sector Erase Suspend command is written during a sector erase operation, the device

requires a maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program

data to any sector not selected for erasure. Normal read and write timings and command definitions

apply. Please note that Autoselect command sequence can not be accepted during Sector

Erase Suspend.

Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is

erase-suspended. See “Write Operation Status” for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array

data within non-suspended sectors. The system can determine the status of the program operation

using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation

Status” for more information. The Autoselect command is not supported during Sector Erase

Suspend Mode.

The system must write the Sector Erase Resume command (address bits are don’t-care) to exit the

sector erase suspend mode and continue the sector erase operation. Further writes of the Resume

command are ignored. Another Sector Erase Suspend command can be written after the device has

resumed erasing.

WRITE OPERATION STATUS

DQ7: DATA# Polling

The EN29LV320A provides DATA# polling on DQ7 to indicate the status of the embedded

operations. The DATA# Polling feature is active during the Word/Byte Programming, Sector Erase,

Chip Erase, and Sector Erase Suspend. (See Table 10)

When the embedded programming is in progress, an attempt to read the device will produce the

complement of the data written to DQ7. Upon the completion of the programming operation, an

attempt to read the device will produce the true data written to DQ7. DATA# polling is valid after the

rising edge of the fourth WE# or CE# pulse in the four-cycle sequence for program.

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the

DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising

edge of the last WE# or CE# pulse in the six-cycle sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

22

Rev. B, Issue Date: 2007/07/17

EN29LV320A

DATA# Polling must be performed at any address within a sector that is being programmed or

erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the

address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when

the output enable (OE#) is low. This means that the device is driving status information on DQ7 at

one instant of time and valid data at the next instant of time. Depending on the time the system

samples the DQ7 output, it may read the status of valid data. Even if the device has completed the

embedded operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.

The valid data on DQ0-DQ7 should be read on the subsequent read attempts.

The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing

diagram is shown in Figure 6.

RY/BY#: Ready/Busy Status output

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is

in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in

the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied

together in parallel with a pull-up resistor to Vcc.

In the output-low period, signifying Busy, the device is actively erasing or programming. This

includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the

device is ready to read array data (including during the Erase Suspend mode), or is in the standby

mode.

DQ6: Toggle Bit I

The EN29LV320A provides a “Toggle Bit” on DQ6 to indicate the status of the embedded

programming and erase operations. (See Table 10)

During an embedded Program or Erase operation, successive attempts to read data from the device

at any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once

the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will

be read on the next successive attempts. During Programming, the Toggle Bit is valid after the rising

edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is

valid after the rising edge of the sixth WE# pulse for sector erase or chip erase.

In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,

then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read

mode without changing data in all protected sectors.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is

shown in Figure 7.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count

limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the

program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a

1 when the device has successfully completed its operation and has returned to read mode, the user

must check again to see if the DQ6 is toggling after detecting a “1” on DQ5.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is

previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under

this condition, the device halts the operation, and when the operation has exceeded the timing limits,

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

23

Rev. B, Issue Date: 2007/07/17

EN29LV320A

DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to

return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be checked to determine

whether or not an erase operation has begun. (The sector erase timer does not apply to the chip

erase command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not

support multiple sector erase (continuous sector erase) command sequences so it is not very

meaningful since it immediately shows as a “1” after the first 30h command. Future devices may

support this feature.

DQ2: Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively

erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-

suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command

sequence. DQ2 toggles when the system reads at addresses within those sectors that have been

selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2

cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by

comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and

mode information. Refer to the following table to compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.

See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical

form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is

toggling. Typically, a system would note and store the value of the toggle bit after the first read. After

the second read, the system would compare the new value of the toggle bit with the first. If the

toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read cycle.

However, after the initial two read cycles, the system determines that the toggle bit is still toggling.

And the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is,

the system should then determine again whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has

successfully completed the program or erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system must write the reset command to return to

reading array data.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

24

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Write Operation Status

Operation

DQ7

DQ6

DQ5 DQ3

DQ2

RY/BY#

Embedded Program

No

toggle

DQ7# Toggle

0

N/A

1

0

1

Standard

Mode

Algorithm

Embedded Erase Algorithm

0

1

Toggle

Reading within Erase

Suspended Sector

Reading within Non-Erase

Suspended Sector

No

Toggle

N/A

Toggle

Erase

Suspend

Mode

Data

Data Data

Data

N/A

1

0

Erase-Suspend Program

DQ7# Toggle

0

N/A

Table 10. Status Register Bits

DQ

Name

Logic Level

Definition

Erase Complete or erased sector in Sector Erase

Suspend

‘1’

‘0’

Erase On-Going

DATA#

POLLING

7

Program Complete or data of non-erased sector

during Sector Erase Suspend

DQ7

DQ7#

‘-1-0-1-0-1-0-1-’

DQ6

Program On-Going

Erase or Program On-going

Read during Sector Erase Suspend

Erase Complete

6

TOGGLE BIT

ERROR BIT

‘-1-1-1-1-1-1-1-‘

‘1’

‘0’

‘1’

‘0’

Program or Erase Error

Program or Erase On-going

Erase operation start

5

3

SECTOR

ERASE TIME

BIT

Erase timeout period on-going

Chip Erase, Sector Erase or Read within Erase-

Suspended sector. (When DQ5=1, Erase Error due

to currently addressed Sector or Program on

Erase-Suspended sector

‘-1-0-1-0-1-0-1-’

DQ2

2

TOGGLE BIT

Read on addresses of non Erase-Suspend sectors

Notes:

DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5

for Program or Erase Success.

DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.

Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5: Error Bit: set to “1” if failure in programming or erase

DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

25

Rev. B, Issue Date: 2007/07/17

EN29LV320A

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data# Poll Device

Verify Data?

Last

Increment

Address

No

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

(See the Command Definitions section for more information.)

555H / AAH

2AAH / 55H

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

26

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

Data Poll from

System or Toggle Bit

successfully

completed

Data =FFh?

No

Yes

Erase Done

Flowchart 4. Embedded Erase Command Sequence

(See the Command Definitions section for more information.)

Chip Erase

Sector Erase

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

555H/10H

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

27

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Flowchart 5. DATA# Polling

Algorithm

Start

Read Data

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data (1)

Notes:

Yes

(1) This second read is necessary in case the

first read was done at the exact instant when

the status data was in transition.

DQ7 = Data?

No

Fail

Pass

Start

Flowchart 6. Toggle Bit Algorithm

Read Data twice

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data twice (2)

Notes:

(2) This second set of reads is necessary in

case the first set of reads was done at the

exact instant when the status data was in

transition.

No

DQ6 = Toggle?

Yes

Fail

Pass

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

28

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Flowchart 7a. In-System Sector (Group) Protect Flowchart

START

PLSCNT = 1

RESET# = V_ID

Wait 1 μs

No

First Write

Cycle =

60h?

Temporary Chip

Unprotect Mode

Yes

Set up sector

(group) address

To Protect: Write 60h to

sector addr with

A6 = 0, A1 = 1, A0 = 0

Wait 150 μs

To Verify: Write 40h to

sector(group) address

with

A6 = 0, A1 = 1, A0 = 0

Increment

PLSCNT

Reset

PLSCNT = 1

Wait 0.4 μs

Read from sector

address with

A6 = 0, A1 = 1, A0

No

Data = 01h?

Yes

PLSCNT = 25?

Yes

Device failed

Yes

Protect another

sector?

No

Remove V_ID

from RESET#

Write reset

command

Sector Protect Algorithm

Sector Protect

complete

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

29

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Flowchart 7b. In-System Chip Unprotect Flowchart

START

PLSCNT = 1

Protect all sectors

(groups): The

indicated portion of

RESET# = V_ID

the sector protect

algorithm must be

Wait 1 μS

performed for all

unprotected sectors

prior to issuing the

No

first sector unprotect

Temporary Chip

Unprotect Mode

First Write

Cycle = 60h?

address (see

Diagram 7a.)

Yes

No

All sectors

protected?

Yes

Set up first sector

address

Chip Unprotect: Write 60H to sector

address with A6 = 1,

A1 = 1, A0 = 0

Wait 15 ms

Verify Chip Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1, A0 =0

Increment

PLSCNT

Wait 0.4 μS

Read from sector address with

A6 = 1, A1 = 1, A0 = 0

No

PLSCCNT =

1000?

Set up next sector

(group) address

Data = 00h?

Yes

No

Last sector

verified?

Device failed

Yes

Remove V_IDfrom

RESET#

Write reset

command

Chip Unprotect

complete

Chip Unprotect Algorithm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

30

Rev. B, Issue Date: 2007/07/17

EN29LV320A

ABSOLUTE MAXIMUM RATINGS

Parameter

Value

Unit

Storage Temperature

-65 to +125

°C

Plastic Packages

-65 to +125

-55 to +125

°C

Ambient Temperature

With Power Applied

Output Short Circuit Current¹

200

MA

V

A9, OE#, RESET#

-0.5 to +11.5

and WP#/ACC²

Voltage with

Respect to Ground

All other pins ³

-0.5 to Vcc+0.5

-0.5 to + 4.0

V

Vcc

Notes:

1.

2.

No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.

Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#,

RESET# and WP#/ACC pins may undershoot V_ssto –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns.

See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods

up to 20ns.

3.

4.

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V_ssto –1.0V for

periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O

pins is V_cc+ 0.5 V. During voltage transitions, outputs may overshoot to V_cc+ 1.5 V for periods up to 20ns. See figure

below.

Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress

rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the

device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES¹

Parameter

Value

Unit

Ambient Operating Temperature

Commercial Devices

0 to 70

-40 to 85

°C

Industrial Devices

Operating Supply Voltage

Vcc

Full Voltage Range: 2.7 to

3.6V

V

1.

Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+1.5V

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot

Waveform

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

31

Rev. B, Issue Date: 2007/07/17

EN29LV320A

DC Characteristics

Table 11. DC Characteristics

(T_a= 0°C to 70°C or - 40°C to 85°C; V_CC= 2.7-3.6V)

Symbol

Parameter

Test Conditions

0V≤ V ≤ Vcc

Min

Typ

Max

±5

Unit

µA

Input Leakage Current

I

LI

IN

Output Leakage Current

±5

µA

I

0V≤ V

≤ Vcc

OUT

LO

Active Read Current ( Byte mode )

Active Read Current ( Word mode )

9

16

mA

CE# = V ; OE# = V

IL

IH ;

I

CC1

f = 5MHZ

16

CE# = V , OE# = V

IL IH

,

20

1

30

5.0

mA

µA

CC2

CC3

Supply Current (Program or Erase)

Supply Current (Standby - CMOS)

WE# = V

IL

CE# = BYTE# =

RESET# = Vcc ± 0.3V

(Note 1)

RESET# = Vss ± 0.3V

1

µA

uA

I

CC4

CC5

Reset Current

V

= Vcc ± 0.3V

= Vss ± 0.3V

IH

5.0

0.8

Automatic Sleep Mode

Input Low Voltage

Input High Voltage

V

IL

-0.5

V

IL

0.7 x

Vcc

Vcc ±

0.3

V

IH

#WP/ACC Voltage (Write Protect /

Program Acceleration)

Voltage for Autoselect or

10.5

11.5

V

HH

11.5

0.45

V

ID

Temporary Sector Unprotect

Output Low Voltage

V

I

= 4.0 mA

= -2.0 mA

OL

0.85 x

Vcc

Vcc -

0.4V

Output High Voltage TTL

I

OH

V

OH

Output High Voltage CMOS

V

I

= -100 μA,

Supply voltage (Erase and

Program lock-out)

V

LKO

2.3

2.5

Notes:

1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that

they draw power if not at full CMOS supply voltages.

2. Maximum I_CCspecifications are tested with Vcc = Vcc max.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

32

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Test Conditions

3.3 V

2.7 kΩ

Device under Test

C_L

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Test Specifications

Test Conditions

Output Load

-70

-90

Unit

1 TTL Gate

100

Output Load Capacitance, C_L

Input Rise and Fall times

Input Pulse Levels

30

5

pF

ns

V

5

0.0-3.0

Input timing measurement

reference levels

Output timing measurement

reference levels

1.5

V

Notes:

1. Vcc=3.0 – 3.6 V for 70ns read operation

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

33

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Hardware Reset (RESET#)

Speed options

-70 -90

Unit

Parameter

Test

Setup

Description

Std

Reset# Pin Low to Read or Write

Embedded Algorithms

Reset# Pin Low to Read or Write

Non Embedded Algorithms

t_READY

Max

20

μs

t_READY

500

nS

t_RP

t_RH

t_RPD

Reset# Pulse Width

Reset# High Time Before Read

Reset# to Standby Mode

Min

500

50

20

nS

μs

Figure 1. AC Waveforms for RESET#

Reset# Timings

RY/BY#

0 V

CE#

OE#

t_RH

RESET#

t_RP

t_READY

Reset Timings NOT During Automatic Algorithms

RY/BY#

t_READY

CE#

OE#

RESET#

t_RP

t_RH

Reset Timings During Automatic Algorithms

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

34

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Word / Byte Configuration (BYTE#)

Speed

Unit

Std

Parameter

Description

-70

0

-90

0

t_BCS

BYTE# to CE# switching setup time

CE# to BYTE# switching hold time

RY/BY# to BYTE# switching hold time

Min

ns

t_CBH

0

t_RBH

Figure 2. AC Waveforms for BYTE#

CE#

OE#

Byte#

t_CBH

t_BCS

Byte# timings for Read Operations

CE#

WE#

Byte#

t_RBH

t_BCS

RY/BY#

Byte #timings for Write Operations

Note: Switching BYTE# pin not allowed during embedded operations

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

35

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Table 12. Read-only Operations Characteristics

Parameter

Speed Options

Symbols

Test

Description

Setup

JEDEC

Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

t_RC

Read Cycle Time

CE# = V_IL

OE# = V_IL

Max

70

30

20

90

35

20

ns

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ACC

t_CE

t_OE

t_DF

Address to Output Delay

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

Output Enable to Output High Z

OE# = V_IL

t_DF

Output Hold Time from

Addresses, CE# or OE#,

whichever occurs first

Min

0

ns

t_AXQX

t_OH

Read

Min

0

ns

Output Enable

Hold Time

t_OEH

Toggle and

Data# Polling

10

Notes:

For - 70

Vcc = 3.0V – 3.6V

Output Load: 1 TTL gate and 30pF

Input Rise and Fall Times: 5ns

Input Pulse Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level, Input and Output: 1.5 V

- 90

Vcc = 2.7V – 3.6V

Output Load: 1 TTL gate and 100 pF

Input Rise and Fall Times: 5 ns

Input Pulse Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level, Input and Output: 1.5 V

Figure 3. AC Waveforms for READ Operations

t_RC

Addresses Stable

Addresses

t_ACC

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

36

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Table 13. Write (Erase/Program) Operations

Parameter

Symbols

Speed Options

Description

JEDEC

Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

t_WC

Write Cycle Time

0

45

30

0

45

0

ns

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_AS

t_AH

Address Setup Time

Address Hold Time

Data Setup Time

t_DS

t_DH

t_OES

Data Hold Time

Min

MIn

Min

0

ns

Output Enable Setup Time

Output

Read

Enable

Hold Time

Toggle and

DATA# Polling

t_OEH

10

Read Recovery Time before

Write (OE# High to WE# Low)

Min

0

ns

t_GHWL

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_GHWL

t_CS

CE# Setup Time

CE# Hold Time

Min

0

ns

t_CH

45

20

45

20

t_WP

Write Pulse Width

t_WPH

Write Pulse Width High

Byte

Typ

8

Programming

Operation

µs

t_WHW1t_WHWH1

Word

Accelerated Programming

Operation

(Word AND Byte Mode)

Typ

7

µs

s

t_WHW1t_WHWH1

0.5

t_WHW2t_WHWH2

Sector Erase Operation

Typ

Min

70

50

70

50

s

t_WHW3t_WHWH3

t_VCS

Chip Erase Operation

Vcc Setup Time

µs

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

37

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Table 14. Write (Erase/Program) Operations

Alternate CE# Controlled Writes

Parameter

Symbols

Speed Options

Description

JEDEC

Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

t_WC

Write Cycle Time

0

45

30

0

45

0

ns

t_AVEL

t_ELAX

t_DVEH

t_EHDX

t_AS

t_AH

Address Setup Time

Address Hold Time

Data Setup Time

t_DS

t_DH

t_OES

t_GHEL

t_WS

Data Hold Time

0

Output Enable Setup Time

Read Recovery Time before

Write (OE# High to CE# Low)

Min

Typ

0

ns

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

WE# Setup Time

WE# Hold Time

0

t_WH

35

20

8

45

20

8

t_CP

CE# Pulse Width

CE# Pulse Width High

t_CPH

Byte

Programming

Operation

µs

s

t_WHW1t_WHWH1

t_WHW2t_WHWH2

8

Word

Accelerated Programming

Operation

(Word AND Byte Mode)

Typ

7

0.5

Sector Erase Operation

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

38

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings

Erase Command Sequence (last 2 cycles)

Read Status Data (last two cycles)

t_WC

t_AS

t_AH

Addresses

CE#

0x2AA

SA

VA

0x555 for chip

erase

t_GHWL

OE#

WE#

t_CH

t_WP

t_CS

t_WPH

t_WHWH2or t_WHWH3

Status

Data

0x55

0x30

D_OUT

t_DS

t_BUSY

t_DH

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, D_out=true data at read address.

2. V_ccshown only to illustrate t_vcsmeasurement references. It cannot occur as shown during a valid command

sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

39

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Figure 5. Program Operation Timings

Program Command Sequence (last 2 cycles)

t_WC

t_AS

t_AH

Addresses

CE#

0x555

PA

t_GHWL

OE#

WE#

t_WP

t_CH

t_WPH

t_CS

t_WHWH1

Data

OxA0

PD

Status

D_OUT

t_DS

t_RB

t_BUSY

t_DH

RY/BY#

V_CC

t_VCS

Notes:

1. PA=Program Address, PD=Program Data, D_OUTis the true data at the program address.

2. V_CCshown in order to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid

command sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

40

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

t_RC

VA

t_ACC

t_CE

VA

Addresses

CE#

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Comple-

ment

True

Complement

Status Data

Valid Data

DQ[7]

Status

Data

True

DQ[6:0]

t_BUS

RY/BY#

Notes:

1. VA=Valid Address for reading Data# Polling status data

2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.

Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm

Operations

t_RC

Addresses

CE#

VA

t_ACC

t_CE

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Valid Status

(second

Valid Data

Valid Status

(first read)

Valid Status

DQ6, DQ2

RY/BY#

(stops toggling)

t_BUSY

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

41

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Figure 8. Alternate CE# Controlled Write Operation Timings

PA for Program

SA for Sector Erase

0x555 for Chip Erase

0x555 for Program

0x2AA for Erase

Addresses

VA

t_WC

t_AS

t_AH

WE#

OE#

CE#

Data

t_WH

t_GHEL

t_CP

t_CPH

t_CWHWH1/ t_CWHWH2/ t_CWHWH3

t_WS

t_BUSY

t_DS

t_DH

Status

D_OUT

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

0xA0 for

Program

RY/BY#

Reset#

t_RH

Notes:

PA = address of the memory location to be programmed.

PD = data to be programmed at byte address.

VA = Valid Address for reading program or erase status

D_out= array data read at VA

Shown above are the last two cycles of the program or erase command sequence and the last status read cycle

RESETt# shown to illustrate t_RHmeasurement references. It cannot occur as shown during a valid command

sequence.

Figure 9. DQ2 vs. DQ6

Enter

Embedded

Erase

Enter Erase

Suspend

Program

Erase

Suspend

Erase

Resume

WE#

Erase

Enter

Suspend

Read

Enter

Suspend

Program

Erase

Suspend

Read

Erase

Complete

Erase

DQ6

DQ2

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

42

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Temporary Sector Unprotect

Speed Option

-70 -90

Unit

Parameter

Description

Std

t_VIDR

t_VIHH

V_IDRise and Fall Time

V_HHRise and Fall Time

Min

500

Ns

RESET# Setup Time for Temporary

Sector Unprotect

t_RSP

Min

4

µs

Figure 10. Temporary Sector Unprotect Timing Diagram

V_ID

RESET#

0 or 3 V

t_VIDR

CE#

WE#

t_RSP

RY/BY#

AC CHARACTERISTICS

Write Protect / Accelerated Program

Figure 11. Accelerated Program Timing Diagram

V_HH

WP#/ACC

0 or 3 V

t_VHH

CE#

WE#

t_RSP

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

43

Rev. B, Issue Date: 2007/07/17

EN29LV320A

AC CHARACTERISTICS

Sector (Group) Protect and Chip Unprotect

Figure 12. Sector (Group) Protect and Chip Unprotect Timing Diagram

V_ID

Vcc

RESET#

0V

t_VIDR

SA,

A6,A1,A0

Valid

60h

Valid

Data

60h

40h

Status

Sector Protect/Unprotect

Verify

CE#

>0.4μS

WE#

>1μS

Protect: 150 uS

Unprotect: 15 mS

OE#

Notes:

Use standard microprocessor timings for this device for read and write cycles.

For Sector (Group) Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

44

Rev. B, Issue Date: 2007/07/17

EN29LV320A

ERASE AND PROGRAM PERFORMANCE

Limits

Max

Parameter

Sector Erase Time

Comments

Typ

Unit

0.5

10

Sec

Excludes 00h programming prior to

erasure

Chip Erase Time

70

8

Sec

µS

Byte Programming Time

Accelerated Byte/Word Program Time

Word Programming Time

300

200

300

7

Excludes system level overhead

Minimum 100K cycles

8

Byte

Chip Programming Time

Word

35

17

100

50

Sec

Erase/Program Endurance

100K

Cycles

Note: Typical Conditions are room temperature, 3V and checkboard pattern programmed.

LATCH UP CHARACTERISTICS

Parameter Description

Min

Max

Input voltage with respect to V_sson all pins except I/O pins

(including A9, Reset and OE#)

-1.0 V

12.0 V

Input voltage with respect to V_sson all I/O Pins

Vcc Current

-1.0 V

Vcc + 1.0 V

100 mA

-100 mA

Note: These are latch up characteristics and the device should never be put under these conditions. Refer to

Absolute Maximum ratings for the actual operating limits.

48-PIN TSOP PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

IN

V

IN

Input Capacitance

6

7.5

pF

C

V

= 0

OUT

Output Capacitance

8.5

7.5

12

9

pF

C

V

= 0

IN2

IN

Control Pin Capacitance

Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C

10

Years

Minimum Pattern Data Retention Time

125°C

20

Years

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

45

Rev. B, Issue Date: 2007/07/17

EN29LV320A

FIGURE 13. TSOP 12mm x 20mm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

46

Rev. B, Issue Date: 2007/07/17

EN29LV320A

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

47

Rev. B, Issue Date: 2007/07/17

EN29LV320A

FIGURE 14. 48TFBGA package outline

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

48

Rev. B, Issue Date: 2007/07/17

EN29LV320A

Revisions List

Revision No

Description

Date

A

Initial Release

2006/11/06

To correct the Table 11. DC Characteristics, I

Current) Unit from mA to µA in page 32

(Reset

CC4

B

2007/07/17

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

49

Rev. B, Issue Date: 2007/07/17


型号：	EN29LV320AB-90B
厂家：	EON SILICON SOLUTION INC.
描述：	32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only 32兆位（ 4096K ×8位/ 2048K ×16位）闪存引导扇区快闪记忆体， CMOS 3.0伏只闪存
文件：	总49页 (文件大小：411K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EN29LV320AB-90B [EON]

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