EN29LV320BB-70TIP [EON]
32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only; 32兆位( 4096K ×8位/ 2048K ×16位)闪存引导扇区快闪记忆体, CMOS 3.0伏只![EN29LV320BB-70TIP](http://pdffile.icpdf.com/pdf1/p00190/img/icpdf/EN29LV_1072426_icpdf.jpg)
型号: | EN29LV320BB-70TIP |
厂家: | ![]() |
描述: | 32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only |
文件: | 总49页 (文件大小:405K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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EN29LV320B
EN29LV320B
32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• JEDEC Standard compatible
• Single power supply operation
- Full voltage range: 2.7 to 3.6 volts read and
write operations
• Standard DATA# polling and toggle bits
feature
• High performance
- Access times as fast as 70 ns
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• Low power consumption (typical values at 5
MHz)
• Support JEDEC Common Flash Interface
- 9 mA typical active read current
- 20 mA typical program/erase current
- Less than 1 μA current in standby or automatic
sleep mode
(CFI).
• Low Vcc write inhibit < 2.5V
• Minimum 100K program/erase endurance
cycles
• Flexible Sector Architecture:
- Eight 8-Kbyte sectors, sixty-three 64k-byte
sectors
- 8-Kbyte sectors for Top or Bottom boot
- Sector Group protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Unprotect
allows code changes in previously locked
sectors
• RESET# hardware reset pin
- Hardware method to reset the device to read
mode
• WP#/ACC input pin
- Write Protect (WP#) function allows
protection of outermost two boot sectors,
regardless of sector protect status
- Acceleration (ACC) function provides
accelerated program times
• Package Options
- 48-pin TSOP (Type 1)
- 48 ball 6mm x 8mm TFBGA
• High performance program/erase speed
- Word program time: 8µs typical
- Sector erase time: 100ms typical
- Chip erase time: 8s typical
• Industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV320B is a 32-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8µs.
The EN29LV320B features 3.0V voltage read and write operation, with access times as fast as 70ns
to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV320B has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full Chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
.
This Data Sheet may be revised by subsequent versions
1
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2011/08/18
EN29LV320B
CONNECTION DIAGRAMS
48-Ball TFBGA
Top View, Balls Facing Down
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2011/08/18
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
2
EN29LV320B
TABLE 1. PIN DESCRIPTION
LOGIC DIAGRAM
Pin Name
A0-A20
DQ0-DQ14
DQ15 / A-1
CE#
Function
EN29LV320B
21 Address inputs
15 Data Inputs/Outputs
21
16 or 8
A0 – A20
DQ0 – DQ15
(A-1)
DQ15 (data input/output, in word mode),
A-1 (LSB address input, in byte mode)
CE#
Chip Enable
OE#
WE#
OE#
Output Enable
WP#/ACC
RESET#
BYTE#
WE#
Write Enable
RY/BY#
WP#/ACC
RESET#
BYTE#
RY/BY#
Vcc
Write Protect / Acceleration Pin
Hardware Reset Pin
Byte/Word mode selection
Ready/Busy Output
Supply Voltage
(2.7-3.6V)
Vss
Ground
NC
Not Connected to anything
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
3
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 2A. Top Boot Sector Address Tables (EN29LV320BT)
Sector Size
(Kbytes / Kwords)
Address Range (h) Address Range (h)
Sector
A20 – A12
Byte mode (x8)
Word Mode (x16)
SA0
SA1
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
4
Rev. D, Issue Date: 2011/08/18
EN29LV320B
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3F1FFF
3F2000–3F3FFF
3F4000–3F5FFF
3F6000–3F7FFF
3F8000–3F9FFF
3FA000–3FBFFF
3FC000–3FDFFF
3FE000–3FFFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1F8FFF
1F9000–1F9FFF
1FA000–1FAFFF
1FB000–1FBFFF
1FC000–1FCFFF
1FD000–1FDFFF
1FE000–1FEFFF
1FF000–1FFFFF
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address bus is A20:A-1 in byte mode where BYTE# = VIL or A20:A0 in word mode where
BYTE# = VIH
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
5
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 2B. Bottom Boot Sector Address Tables (EN29LV320BB)
Sector Size
(Kbytes / Kwords)
Address Range (h) Address Range (h)
Sector
A20 – A12
Byte mode (x8)
Word Mode (x16)
SA0
SA1
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
8/4
000000–001FFF
000000–000FFF
001000–001FFF
002000–002FFF
003000–003FFF
004000–004FFF
005000–005FFF
006000–006FFF
007000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
8/4
002000–003FFF
004000–005FFF
006000–007FFF
008000–009FFF
00A000–00BFFF
00C000–00DFFF
00E000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
6
Rev. D, Issue Date: 2011/08/18
EN29LV320B
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VIL or A20:A0 in word mode where
BYTE# = VIH
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
7
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 3. PRODUCT SELECTOR GUIDE
Product Number
EN29LV320B
Speed
-70
70
70
30
Max Access Time, ns (tacc
Max CE# Access, ns (tce)
Max OE# Access, ns (toe)
)
BLOCK DIAGRAM
RY/BY#
DQ0-DQ15 (A-1)
Vcc
Vss
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE#
Program Voltage
Generator
Command
Register
STB
Chip Enable
Output Enable
Logic
Data Latch
CE#
OE#
Y-Decoder
Y-Gating
STB
Vcc Detector
Timer
X-Decoder
Cell Matrix
A0-A20
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
8
Rev. D, Issue Date: 2011/08/18
EN29LV320B
TABLE 4. OPERATING MODES
32M FLASH USER MODE TABLE
DQ8-DQ15
A0-
A20
DQ0-
DQ7
RESET#
WP#/ACC
Operation
Read
CE#
OE# WE#
BYTE#
= VIH
DOUT
DIN
BYTE#
= VIL
DQ8-
DQ14=
High-Z,
DQ15 =
A-1
L
L
L
H
H
L
H
H
L/H
(Note 1)
AIN
AIN
DOUT
DIN
Write
Accelerated
Program
L
H
L
H
VHH
AIN
DIN
DIN
Vcc
±0.3V
L
CMOS Standby
X
X
H
X
High-Z
High-Z
High-Z
Vcc±0.3V
Output Disable
Hardware Reset
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA,
Sector Group
Protect
A6=L,
A1=H,
A0=L
SA,
A6=H,
A1=H,
A0=L
L
H
L
VID
L/H
(Note 2)
(Note 2)
X
X
X
X
Chip Unprotect
L
H
X
L
VID
VID
(Note 1)
(Note 1)
Temporary
Sector
X
X
AIN
(Note 2) (Note 2) High-Z
Unprotect
L=logic low= VIL, H=Logic High= VIH, VID =VHH =11 ± 0.5V = 10.5-11.5V, X=Don’t Care (either L or H, but not
floating ), SA=Sector Addresses, DIN=Data In, DOUT=Data Out, AIN=Address In
Notes:
1. If WP#/ACC = VIL , the two outermost boot sectors remain protected. If WP# / ACC = VIH, the outermost boot
sector protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors will
be unprotected.
2. Please refer to “Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
9
Rev. D, Issue Date: 2011/08/18
EN29LV320B
TABLE 5. Autoselect Codes (Using High Voltage, VID)
32M FLASH MANUFACTURER/DEVICE ID TABLE
A20 A11
to to
A12 A10
A5
DQ8
to
DQ15
Description
CE#
L
OE#
L
WE#
H
A92 A8 A7 A6 to A1 A0
A2
DQ7 to DQ0
H1
1Ch
7Fh
Manufacturer ID:
Eon
X
X
VID
X
L
X
L
L
X
L
Device ID
(top boot
sector)
Device ID
(bottom boot
sector)
Word
Byte
L
L
L
L
L
L
L
L
H
H
H
H
22h
X
F6h
F6h
F9h
F9h
X
X
X
X
VID
VID
X
X
X
L
L
X
X
L
L
H
H
Word
Byte
22h
X
X
X
01h
(Protected)
00h
(Unprotected)
X
X
Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
H
L
L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector
Addresses
Note:
1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a
configuration code 7Fh.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect
Mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
10
Rev. D, Issue Date: 2011/08/18
EN29LV320B
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV320B has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).
It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin
must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which
reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin
is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE#
input.
Automatic Sleep Mode
The EN29LV320B has an automatic sleep mode, which minimizes power consumption. The devices
will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in
the DC Characteristics table shows the current specification. With standard access times, the device
will output new data when addresses change.
Read Mode
The device is automatically set to reading array data after device power-up or hardware reset. No
commands are required to retrieve data. The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts a Sector Erase Suspend command, the device enters the Sector Erase
Suspend mode. The system can read array data using the standard read timings, except that if it reads
at an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Sector Erase Suspend mode, the system may once again read array
data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional
information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high or while in the autoselect mode. See the “Reset Command” for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VIH), the output from the EN29LV320B is disabled. The
output pins are placed in a high impedance state.
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
11
Rev. D, Issue Date: 2011/08/18
EN29LV320B
When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on address
pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the
remaining address bits that are don’t-care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ15–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
Writing Command Sequences
To write a command or command sequence to program data to the device or erase data, the system
has to drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes
or words. An erase operation can erase one sector or the whole chip.
The system can also read the autoselect codes by entering the autoselect mode, which need the
autoselect command sequence to be written. Please refer to the “Command Definitions” for all the
available commands.
RESET#: Hardware Reset
When RESET# is driven low for tRP, all output pins are tristates. All commands written in the internal
state machine are reset to reading array data.
Please refer to timing diagram for RESET# pin in “AC Characteristics”.
Sector Group Protection & Chip Unprotection
The hardware sector group protection feature disables both program and erase operations in any
sector. The hardware chip unprotection feature re-enables both program and erase operations in
previously protected sectors. A sector group implies three or four adjacent sectors that would be
protected at the same time. Please see the following tables which show the organization of sector
groups.
There are two methods to enable this hardware protection circuitry. The first one requires only that the
RESET# pin be at V and then standard microprocessor timings can be used to enable or disable this
ID
feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect
write cycle.
The second method is for programming equipment. This method requires V to be applied to both
ID
OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a
separate document named EN29LV320B Supplement, which can be obtained by contacting a
representative of Eon Silicon Solution, Inc.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
12
Rev. D, Issue Date: 2011/08/18
EN29LV320B
TABLE 6. Top Boot Sector/Sector Group Organization Table (EN29LV320BT) for
(Un)Protection
Sector Group
SG 0
SG 1
SG 2
SG 3
SG 4
SG 5
SG 6
SG 7
SG 8
SG 9
SG10
SG11
SG12
SG13
SG14
Sectors
A20-A12
Sector Group Size
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SA 0-SA 3
SA 4-SA 7
SA 8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
0000XXXXX
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
SG15
SA60-SA62
64 Kbytes x 3
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
TABLE 7. Bottom Boot Sector/Sector Group Organization Table (EN29LV320BB)
for (Un)Protection
Sector Group
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12
SG11
SG10
SG 9
Sectors
A20-A12
Sector Group Size
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SA70-SA67
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
1111XXXXX
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
000011XXX
000010XXX
000001XXX
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
SG 8
SA10-SA 8
64 Kbytes x 3
SG 7
SG 6
SG 5
SG 4
SG 3
SG 2
SG 1
SG 0
SA 7
SA 6
SA 5
SA 4
SA 3
SA 2
SA 1
SA 0
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
13
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Write Protect / Accelerated Program (WP# / ACC)
The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware meth-
od of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing
throughput at the factory, using an external high voltage.
When WP#/ACC is Low, the device protects the outermost two 8K-byte Boot Sector; no matter the
sectors are protected or unprotected using the method described in “Sector/Sector Group Protection &
Chip Unprotection”, Program and Erase operations in these sectors are ignored.
When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8K-
byte boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte
Boot Sector unless the sector is protected using Sector Protection.
When WP#/ACC is raised to VHH the memory automatically enters the Accelerated Program mode, this
mode permit the system to skip the normal command unlock sequences and program byte/word
locations directly to reduces the time required for program operation. When WP#/ACC returns to VIH or
VIL, normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be
slower than tVHH, see Figure 11.
Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin
must not be at VHH for operations other than accelerated programming. It could cause the device to be
damaged.
Never raise this pin to VHH from any mode except Read mode. Otherwise the memory may be left in an
indeterminate state.
A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to
decouple the current surges from the power supply. The PCB track widths must be sufficient to carry
the currents required during Accelerated Program mode.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Temporary
Sector Unprotect mode is activated by setting the RESET# pin to
VBIDB. During this mode, formerly protected sectors can be
programmed or erased by simply selecting the sector addresses.
Once VBIDB is removed from the RESET# pin, all the previously
Reset#=VID (note 1)
Perform Erase or Program
Operations
protected sectors are protected again.
flowchart and figure 10 for more timing details.
See accompanying
RESET#=VIH
Temporary Sector Unprotect
Completed (note 2)
Notes:
1. All protected sectors are unprotected. (If
WP#/ACC=VIL, outermost boot sectors will remain
protected.)
2. Previously protected sectors are protected again.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
14
Rev. D, Issue Date: 2011/08/18
EN29LV320B
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software
interrogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-
independent, and forward- and backward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read
array data.
The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper
address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in
Tables 5–8. The system must write the reset command to return the device to the autoselect mode.
Table 8. CFI Query Identification String
Addresses
Adresses
(Word Mode) (Byte Mode)
Data
Description
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h Query Unique ASCII string “QRY”
0059h
0002h
0000h
0040h
0000h
0000h
0000h
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command set (00h = none exists)
0000h Address for Alternate OEM Extended Table (00h = none
0000h exists)
Table 9. System Interface String
Addresses
Addresses
(Word Mode) (Byte Mode)
Data
Description
0027h Vcc Min (write/erase)
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
0036h Vcc Max (write/erase)
1Bh
1Ch
36h
38h
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
0000h Vpp Min. voltage (00h = no Vpp pin present)
0000h Vpp Max. voltage (00h = no Vpp pin present)
1Dh
1Eh
1Fh
3Ah
3Ch
3Eh
Typical timeout per single byte/word write 2N μS
0004h
0000h
Typical timeout for Min, size buffer write 2N μS (00h = not
20h
40h
supported)
21h
22h
23h
24h
25h
42h
44h
46h
48h
4Ah
000Ah Typical timeout per individual block erase 2N ms
0000h Typical timeout for full chip erase 2N ms (00h = not supported)
0005h Max. timeout for byte/word write 2N times typical
0000h Max. timeout for buffer write 2N times typical
0004h Max. timeout per individual block erase 2N times typical
0000h Max timeout for full chip erase 2N times typical (00h = not
supported)
26h
4Ch
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
15
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 10. Device Geometry Definition
Addresses
(Word mode)
27h
Addresses
(Byte Mode)
4Eh
50h
Data
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Description
Device Size = 2N bytes
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
Flash Device Interface description (refer to CFI publication
100)
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
38h
39h
3Ah
3Bh
3Ch
Table 11. Primary Vendor-specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
Query-unique ASCII string “PRI”
40h
41h
42h
43h
44h
80h
82h
84h
86h
0050h
0052h
0049h
0031h
0031h
Major version number, ASCII
Minor version number, ASCII
88h
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Minimum ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV
Maximum ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0004h
0001h
49h
92h
0004h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
94h
96h
98h
9Ah
9Ch
9Eh
0000h
0000h
0000h
00A5h
00B5h
0002h/ Top/Bottom Boot Sector Identifier
0003h
02h = Bottom Boot, 03h = Top Boot
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
16
www.eonssi.com
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = VIL, WE#= VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
17
Rev. D, Issue Date: 2011/08/18
EN29LV320B
COMMAND DEFINITIONS
The operations of the device are selected by one or more commands written into the command
register. Commands are made up of data sequences written at specific addresses via the command
register. The sequences for the specified operation are defined in the Command Definitions table
(Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to
Read Mode.
Table 12. EN29LV320B Command Definitions
Bus Cycles
3rd Cycle 4th Cycle
Command
Sequence
1st Cycle
2nd Cycle
5th Cycle
6th Cycle
Addr
Data
RD
F0
Addr
Data
Addr
Data
Addr Data
Addr
Data
Addr
Data
Read
Reset
1
1
RA
xxx
000
100
000
200
7F
Word
555
2AA
555
555
Manufacturer
ID
1C
7F
1C
4
AA
55
90
Byte
AAA
AAA
Word
Byte
555
2AA
555
2AA
555
555
x01
x02
x01
x02
22F6
Device ID
Top Boot
4
4
AA
AA
55
55
90
90
AAA
555
AAA
555
F6
Word
Byte
22F9
F9
Device ID
Bottom Boot
AAA
AAA
(SA)
X02
(SA)
X04
00
01
00
01
Word
555
2AA
555
Sector Protect
Verify
4
4
AA
AA
55
55
90
A0
Byte
AAA
555
555
AAA
555
Word
2AA
Program
PA
PD
Byte
AAA
555
555
AAA
555
Word
2AA
555
2AA
555
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Byte
Word
Byte
AAA
555
AAA
555
2AA
555
AAA
555
AAA
AAA
555
AAA
555
2AA
555
AAA
Sector Erase
SA
Sector Erase Suspend
Sector Erase Resume
1
1
xxx
B0
30
xxx
55
Word
Byte
CFI Query
1
98
AA
Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
18
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can
read array data using the standard read timings from sectors other than the one which is being erase-
suspended. If the system reads at an address within erase-suspended sectors, the device outputs
status data. After completing a programming operation in the Sector Erase Suspend mode, the system
may once again read array data with the same exception.
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high
during an active program or erase operation or while in the autoselect mode. See next section for
details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t-
care for this command.
The reset command may be written between the cycle sequences in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is complete. The reset command may be written
between the sequence cycles in a program command sequence before programming begins. This
resets the device to reading array data (also applies to programming in Sector Erase Suspend mode).
Once programming begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the cycle sequences in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies in Sector Erase Suspend mode).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices ID
codes, and determine whether or not a sector (group) is protected. The Command Definitions table
shows the address and data requirements. This is an alternative to the method that requires VID on
address bit A9 and is intended for commercial programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number
of times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array
data.
Word / Byte Programming Command
The device can be programmed by byte or by word, depending on the state of the BYTE# Pin.
Programming the EN29LV320B is performed by using a four-bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,
whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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19
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Any commands written to the device during the program operation are ignored. Programming status
can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program
operation is successfully completed, the device returns to read mode and the user can read the data
programmed to the device at that address. Note that data can not be programmed from a “0” to a “1”.
Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to
indicate the operation was successful. However, a succeeding read will show that the data is still “0”.
Only erase operations can convert a “0” to a “1”. When programming time limit is exceeded, DQ5 will
produce a logical “1” and a Reset command can return the device to Read mode.
Programming is allowed in any sequence across sector boundaries.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The Command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All
other commands are ignored. If there are several sectors to be erased, Sector Erase Command
sequences must be issued for each sector. That is, only a sector address can be specified for each
Sector Erase command. Users must issue another Sector Erase command for the next sector to be
erased after the previous one is completed.
When the Embedded Erase algorithm is completed, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by using
DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4
illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for
timing waveforms.
Sector Erase Suspend / Resume Command
The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. This command is valid only
during the sector erase operation. The Sector Erase Suspend command is ignored if written during the
chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the
Sector Erase Suspend command.
When the Sector Erase Suspend command is written during a sector erase operation, the device
requires a maximum of 20 µs to suspend the erase operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
20
Rev. D, Issue Date: 2011/08/18
EN29LV320B
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. Normal read and write timings and command definitions apply.
Please note that Autoselect command sequence can not be accepted during Sector Erase
Suspend.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-
suspended. See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for
more information. The Autoselect command is not supported during Sector Erase Suspend Mode.
The system must write the Sector Erase Resume command (address bits are don’t-care) to exit the
sector erase suspend mode and continue the sector erase operation. Further writes of the Resume
command are ignored. Another Sector Erase Suspend command can be written after the device has
resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN29LV320B provides DATA# polling on DQ7 to indicate the status of the embedded operations.
The DATA# Polling feature is active during the Word/Byte Programming, Sector Erase, Chip Erase, and
Sector Erase Suspend. (See Table 10)
When the embedded programming is in progress, an attempt to read the device will produce the
complement of the data written to DQ7. Upon the completion of the programming operation, an attempt
to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge
of the fourth WE# or CE# pulse in the four-cycle sequence for program.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7
output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output
during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of
the last WE# or CE# pulse in the six-cycle sequence.
DATA# Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used
is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (OE#) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on the time the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on
DQ0-DQ7 should be read on the subsequent read attempts.
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to Vcc.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
21
Rev. D, Issue Date: 2011/08/18
EN29LV320B
In the output-low period, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV320B provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming
and erase operations. (See Table 10)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read
on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of
the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after
the rising edge of the sixth WE# pulse for sector erase or chip erase.
In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown
in Figure 7.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or
erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the
device has successfully completed its operation and has returned to read mode, the user must check
again to see if the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a
“1.” Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support
multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since
it immediately shows as a “1” after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2
toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
22
Rev. D, Issue Date: 2011/08/18
EN29LV320B
for erasure. Thus, both status bits are required for sector and mode information. Refer to the following
table to compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle
bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not complete
the operation successfully, and the system must write the reset command to return to reading array
data.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
23
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 13. Write Operation Status
Operation
DQ7
DQ6
DQ5 DQ3
DQ2
RY/BY#
Embedded Program
No
toggle
DQ7# Toggle
0
0
0
N/A
1
0
0
1
Standard
Mode
Algorithm
Embedded Erase Algorithm
0
1
Toggle
Toggle
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
No
Toggle
N/A
Toggle
Erase
Suspend
Mode
Data
Data
Data Data
Data
N/A
1
0
Erase-Suspend Program
DQ7# Toggle
0
N/A
Table 14. Status Register Bits
DQ
Name
Logic Level
Definition
Erase Complete or erased sector in Sector Erase
Suspend
‘1’
‘0’
Erase On-Going
DATA#
POLLING
7
Program Complete or data of non-erased sector
during Sector Erase Suspend
DQ7
DQ7#
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Sector Erase Suspend
Erase Complete
6
TOGGLE BIT
‘-1-1-1-1-1-1-1-‘
‘1’
Program or Erase Error
5
3
TIME OUT BIT
‘0’
‘1’
‘0’
Program or Erase On-going
Erase operation start
ERASE TIME
OUT BIT
Erase timeout period on-going
Chip Erase, Sector Erase or Read within Erase-
Suspended sector. (When DQ5=1, Erase Error due
to currently addressed Sector or Program on
Erase-Suspended sector
‘-1-0-1-0-1-0-1-’
DQ2
2
TOGGLE BIT
Read on addresses of non Erase-Suspend sectors
Notes:
DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for
Program or Erase Success.
DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive
reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5: Time Out Bit: set to “1” if failure in programming or erase
DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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24
Rev. D, Issue Date: 2011/08/18
EN29LV320B
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data# Poll Device
No
Verify Data?
Yes
Last
Increment
Address
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
(See the Command Definitions section for more information.)
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2011/08/18
© 2004 Eon Silicon Solution, Inc.,
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25
EN29LV320B
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
Flowchart 4. Embedded Erase Command Sequence
(See the Command Definitions section for more information.)
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
Sector Address/30H
555H/10H
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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26
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Flowchart 5. DATA# Polling
Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
Yes
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
(2) This second set of reads is necessary in
case the first set of reads was done at the
exact instant when the status data was in
transition.
No
DQ6 = Toggle?
Yes
Fail
Pass
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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27
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Flowchart 7a. In-System Sector Group Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
No
First Write
Cycle =
60h?
Temporary Sector
Unprotect Mode
Yes
Set up sector
group address
To Protect: Write 60h to
sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 μs
To Verify: Write 40h to
sector group address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 μs
Read from sector
address with
A6 = 0, A1 = 1, A0 = 0
No
No
Data = 01h?
Yes
PLSCNT = 25?
Yes
Device failed
Yes
Protect another
sector?
No
Remove VID
from RESET#
Write reset
command
Sector Group Protect
Algorithm
Sector Protect
complete
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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28
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Flowchart 7b. In-System Chip Unprotect Flowchart
START
PLSCNT = 1
Protect all sector
groups: The
indicated portion of
RESET# = VID
the sector protect
algorithm must be
Wait 1 μs
performed for all
unprotected sectors
prior to issuing the
No
first sector unprotect
Temporary Sector
Unprotect Mode
First Write
address (see
Cycle = 60h?
Diagram 7a.)
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Chip Unprotect: Write 60H to sector
address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Verify Chip Unprotect: Write
40h to sector address with
A6 = 1, A1 = 1, A0 =0
Increment
PLSCNT
Wait 0.4 μs
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
No
PLSCCNT =
1000?
Set up next sector
group address
Data = 00h?
Yes
Yes
No
Last sector
verified?
Device failed
Yes
Remove VID from
RESET#
Write reset
command
Chip Unprotect
complete
Chip Unprotect Algorithm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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29
Rev. D, Issue Date: 2011/08/18
EN29LV320B
DC Characteristics
Table 15. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
0V≤ V ≤ Vcc
Min
Typ
Max
±5
Unit
µA
Input Leakage Current
I
LI
IN
Output Leakage Current
±5
µA
I
0V≤ V ≤ Vcc
OUT
LO
Active Read Current ( Byte mode )
Active Read Current ( Word mode )
9
9
16
mA
mA
CE# = V ; OE# = V
IL
IH ;
I
I
I
CC1
f = 5MHz
16
CE# = V , OE# = V
IL
,
IH
20
1
30
5.0
5.0
mA
µA
CC2
CC3
Supply Current (Program or Erase)
Supply Current (Standby - CMOS)
WE# = V
IL
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
RESET# = Vss ± 0.3V
1
1
µA
µA
I
I
CC4
CC5
Reset Current
V
= Vcc ± 0.3V
= Vss ± 0.3V
IH
5.0
0.8
Automatic Sleep Mode
Input Low Voltage
Input High Voltage
V
IL
-0.5
V
V
V
IL
0.7 x
Vcc
Vcc +
0.3
V
IH
#WP/ACC Voltage (Write Protect /
Program Acceleration)
Voltage for Autoselect or
10.5
10.5
11.5
V
V
HH
11.5
0.45
V
V
V
ID
Temporary Sector Unprotect
Output Low Voltage
V
I
= 4.0 mA
OL
OL
Vcc -
0.4V
Output High Voltage CMOS
V
V
V
I
= -100 μA
OH
OH
Supply voltage (Erase and
Program lock-out)
V
LKO
2.3
2.5
Notes:
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that
they draw power if not at full CMOS supply voltages.
2. Maximum ICC specifications are tested with Vcc = Vcc max.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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30
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Test Conditions
Test Specifications
Test Conditions
Output Load Capacitance, CL
Input Rise and Fall times
Input Pulse Levels
-70
30
Unit
pF
ns
5
0.0-3.0
V
Input timing measurement
reference levels
Output timing measurement
reference levels
1.5
1.5
V
V
This Data Sheet may be revised by subsequent versions
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31
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 16. Hardware Reset (RESET#)
Speed
Unit
Paramete
Description
r Std
Test
Setup
-70
RESET# Pulse Width (During Embedded Algorithms)
tRP1
tRP2
tRH
tRB1
tRB2
tREADY1
Min
Min
Min
Min
Min
10
500
50
0
us
ns
ns
ns
ns
RESET# Pulse Width (NOT During Embedded Algorithms)
Reset# High Time Before Read
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms)
to Read or Write
Reset# Pin Low (NOT During Embedded Algorithms)
to Read or Write
50
Max
Max
20
us
ns
tREADY2
500
Figure 1. AC Waveforms for RESET#
Reset# Timings
tRB1
CE#, OE#
WE#
tREADY1
tRB2
RY/BY#
RESET#
tRP1
Reset Timing during Embedded Algorithms
CE#, OE#
tRH
RY/BY#
RESET#
tRP2
tREADY2
Reset Timing NOT during Embedded Algorithms
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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32
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 17. Word / Byte Configuration (BYTE#)
Speed
Test
Setup
Std
Parameter
Unit
-70
0
Description
tBCS
tCBH
tRBH
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
Min
Min
Min
ns
ns
ns
0
0
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte#
tCBH
tBCS
Byte# timings for Read Operations
CE#
WE#
Byte#
tRBH
tBCS
RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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33
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 18. Read-only Operations Characteristics
Parameter
Speed
Unit
Symbols
Test Setup
Description
JEDEC Standard
-70
Min
70
70
70
30
20
20
ns
ns
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tRC
tACC
tCE
tOE
tDF
Read Cycle Time
CE# = VIL
OE#= VIL
Max
Max
Max
Max
Max
Address to Output Delay
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
Output Enable to Output High Z
OE#= VIL
tDF
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
ns
tAXQX
tOH
MIn
Min
0
ns
ns
Read
Toggle and
DATA# Polling
Output Enable
Hold Time
tOEH
10
Notes:
1. High Z is Not 100% tested.
2. For - 70 Vcc = 2.7V – 3.6V
Output Load: 30pF
Input Pulse Levels: 0.0 V to 3.0 V
Input Rise and Fall Times: 5ns
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 3. AC Waveforms for READ Operations
tRC
Addresses
Addresses Stable
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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34
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 19. Write (Erase/Program) Operations
Parameter
Speed
-70
Symbols
Description
Unit
JEDEC
Standard
Min
Min
Min
Min
Min
70
0
ns
ns
ns
ns
ns
tAVAV
tWC
Write Cycle Time
tAVWL
tWLAX
tDVWH
tWHDX
tAS
tAH
Address Setup Time
Address Hold Time
Data Setup Time
45
30
0
tDS
tDH
tOES
Data Hold Time
Min
MIn
Min
0
0
ns
ns
ns
Output Enable Setup Time
Output
Read
Enable
Hold Time
Toggle and
DATA# Polling
tOEH
10
Read Recovery Time before
Write (OE# High to WE# Low)
Min
0
ns
tGHWL
tELWL
tWHEH
tWLWH
tWHDL
tGHWL
tCS
CE# Setup Time
CE# Hold Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
tCH
45
20
tWP
Write Pulse Width
tWPH
Write Pulse Width High
Byte
Typ
Typ
8
8
Programming
Operation
µs
µs
tWHW1 tWHWH1
Word
Accelerated Programming
Operation
(Word AND Byte Mode)
Typ
7
tWHW1 tWHWH1
Typ
Typ
Min
Max
Min
0.1
8
s
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time
tWHW2 tWHWH2
s
50
70
0
µs
ns
ns
tVCS
tBUSY
tRB
B
WE# High to RY/BY# Low
Recovery Time from RY/BY#
Notes: tWC is Not 100% tested.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
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35
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 20. Write (Erase/Program) Operations
Alternate CE# Controlled Writes
Parameter
Speed Options
Symbols
Description
Unit
JEDEC
Standard
tWC
-70
Min
Min
Min
Min
Min
Min
70
ns
ns
ns
ns
ns
ns
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
Write Cycle Time
0
45
30
0
tAS
Address Setup Time
Address Hold Time
Data Setup Time
tAH
tDS
tDH
Data Hold Time
0
tOES
Output Enable Setup Time
Output
Read
Min
Min
0
ns
ns
tOEH
Enable
Toggle and
Hold Time
10
Data Polling
Read Recovery Time before
Write (OE# High to CE# Low)
Min
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
ns
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tGHEL
tWS
WE# Setup Time
WE# Hold Time
0
tWH
35
20
8
tCP
CE# Pulse Width
CE# Pulse Width High
tCPH
Byte
Programming
µs
µs
tWHW1 tWHWH1
Operation
8
Word
Accelerated Programming
Operation
(Word AND Byte Mode)
Typ
7
tWHW1 tWHWH1
Typ
Min
Min
0.1
50
0
s
tWHW2 tWHWH2
Sector Erase Operation
Vcc Setup Time
µs
ns
tVCS
tRB
Recovery Time from RY/BY#
Notes: tWC is Not 100% tested.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
36
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Figure 4. AC Waveforms for WE# Control Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
Read Status Data (last two cycles)
tAS
SA
tAH
tWC
Addresses
CE#
0x2AA
VA
VA
0x555 for chip
erase
tGHW
L
tCH
OE#
WE#
tWP
tWPH
tCS
tWHWH2
Data
0x55
tDS
0x30
Status
DOUT
tRB
10 for chip
erase
tDH
tBUSY
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
37
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Figure 5. Program Operation Timings
Program Command Sequence (last 2 cycles)
Program Command Sequence (last 2 cycles)
tAS
PA
tAH
tWC
Addresses
CE#
0x555
PA
PA
tGHWL
tCH
OE#
WE#
tWP
tWPH
tWHWH1
tCS
Data
DOUT
tRB
OxA0
Status
PD
tDS
tDH
tBUSY
RY/BY#
VCC
tVCS
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
38
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
Addresses
CE#
VA
VA
tACC
VA
tCH
tCE
tOE
OE#
WE#
tOEH
tDF
tOH
Comple
-ment
Valid Data
Valid Data
Complement
Status Data
True
DQ[7]
Status
Data
True
DQ[6:0]
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC
Addresses
CE#
VA
VA
VA
VA
tCH
tACC
tCE
tOE
OE#
WE#
tOEH
tDF
tOH
Valid Data
Valid Status
(first read)
Valid Status
Valid Status
DQ6, DQ2
RY/BY#
tBUSY
(second read)
(stops toggling)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
39
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Figure 8. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Program
0x2AA for Erase
0x555 for Chip Erase
Addresses
WE#
VA
tWC
tAS
tAH
tWH
tGHEL
OE#
CE#
Data
tCP
tCPH
tWHWH1 / tWHWH2
tWS
tBUSY
tDH
tDS
Status
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
0xA0 for
Program
0x55 for Erase
RY/BY
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
RESETt# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 9. DQ2 vs. DQ6
Enter
Embedded
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Resume
WE#
Erase
Enter
Suspend
Read
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
40
Rev. D, Issue Date: 2011/08/18
EN29LV320B
AC CHARACTERISTICS
Table 21. Temporary Sector Unprotect
Speed Option
Parameter
Description
Std
Unit
-70
500
500
tVIDR
tVIHH
VID Rise and Fall Time
VHH Rise and Fall Time
Min
Min
ns
ns
RESET# Setup Time for Temporary
Sector Unprotect(Note)
tRSP
Min
4
µs
Notes: Not 100% tested.
Figure 10. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
AC CHARACTERISTICS
Write Protect / Accelerated Program
Figure 11. Accelerated Program Timing Diagram
VHH
WP#/ACC
0 or 3 V
0 or 3 V
tVHH
tVHH
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
41
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Figure 12. Sector Group Protect and Chip Unprotect Timing Diagram
VID
Vcc
RESET#
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Valid
60h
Valid
Valid
Data
60h
40h
Status
Sector Protect/Unprotect
Verify
CE#
>0.4μS
WE#
>1μS
Protect: 150 uS
Unprotect: 15 mS
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Group Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
42
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Table 22. ERASE AND PROGRAM PERFORMANCE
Limits
Max
Parameter
Comments
Typ
Unit
Sector Erase Time
0.1
2
sec
Excludes 00h programming prior to
erasure
Chip Erase Time
8
8
7
8
70
sec
µs
Byte Programming Time
Accelerated Byte/Word Program Time
Word Programming Time
200
200
200
µs
Excludes system level overhead
Minimum 100K cycles
µs
Byte
Chip Programming Time
Word
33.6
16.8
100.8
50.4
sec
Erase/Program Endurance
100K
Cycles
Notes:
1. Typical program and erase times assume the following conditions: room temperature, 3V and checkboard
pattern programmed.
2. Maximum program and erase times assume the following conditions: worst case Vcc, 90°C and 100,000 cycles.
Table 23. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Package
TSOP
BGA
Typ
6
Max
7.5
1.2
12
Unit
C
IN
V
IN
Input Capacitance
pF
1.2
8.5
1.1
7.5
1.0
TSOP
BGA
C
OUT
V
= 0
OUT
Output Capacitance
pF
pF
1.2
9
TSOP
BGA
C
IN2
V
= 0
IN
Control Pin Capacitance
1.3
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.
Table 24. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
20
Years
Data Retention Time
125°C
Years
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
43
Rev. D, Issue Date: 2011/08/18
EN29LV320B
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
°C
Storage Temperature
-65 to +150
°C
°C
Plastic Packages
-65 to +125
-55 to +125
Ambient Temperature
With Power Applied
Output Short Circuit Current1
200
mA
V
A9, OE#, RESET#
-0.5 to +11.5
and WP#/ACC2
Voltage with
Respect to Ground
All other pins 3
-0.5 to Vcc+0.5
-0.5 to + 4.0
V
V
Vcc
Notes:
1.
2.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#, RESET#
and WP#/ACC pins may undershoot Vss
below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5
V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B
B
to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure
3.
4.
B
B
B
B
B
B
RECOMMENDED OPERATING RANGES1
P
P
Parameter
Value
Unit
Ambient Operating Temperature
Industrial Devices
°C
-40 to 85
Operating Supply Voltage
Vcc
Full Voltage Range:
2.7 to 3.6V
V
1.
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
44
Rev. D, Issue Date: 2011/08/18
EN29LV320B
FIGURE 13. 48L TSOP 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
45
Rev. D, Issue Date: 2011/08/18
EN29LV320B
FIGURE 14. 48L TFBGA 6mm x 8mm package outline
DIMENSION IN MM
SYMBOL
MIN.
- - -
NOR
- - -
MAX
A
A1
A2
D
1.30
- - -
0.23
0.84
7.90
5.90
- - -
0.29
0.91
8.00
6.00
5.60
4.00
0.80
0.40
- - -
8.10
6.10
- - -
E
D1
E1
e
- - -
- - -
- - -
- - -
b
0.35
0.45
Note : 1. Coplanarity: 0.1 mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
46
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code: XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
47
Rev. D, Issue Date: 2011/08/18
EN29LV320B
ORDERING INFORMATION
EN29LV320B
T
─ 70
T
I
P
PACKAGING CONTENT
(Blank) = Conventional
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA)
0.80mm pitch, 6mm x 8mm package
SPEED
70 = 70ns
BOOT CODE SECTOR ARCHITECTURE
T = Top boot Sector
B = Bottom boot Sector
BASE PART NUMBER
EN = EON Silicon Solution Inc.
29LV = FLASH, 3V Read, Program and Erase
320 = 32 Megabit (4M x 8 / 2M x 16)
B = version identifier
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
48
Rev. D, Issue Date: 2011/08/18
EN29LV320B
Revisions List
Revision No Description
Date
A
B
C
D
Initial Release
2009/01/14
2009/06/05
2009/10/28
2011/08/18
Correct typo tBUSY MinÆMax on page 35
Correct Figure 4 WE# typo tWP Æ tWPH on page 37
Add BGA PACKAGE CAPACITANCE on page 43
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
49
Rev. D, Issue Date: 2011/08/18
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