EN29LV512-45RJIP [EON]
512 Kbit (64K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory; 512千位（ 64K ×8位）的统一部门， CMOS 3.0伏只快闪记忆体
| 型号： | EN29LV512-45RJIP |
| 厂家： | 
EON SILICON SOLUTION INC. |
| 描述： | 512 Kbit (64K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory |
| 文件： | 总35页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EN29LV512
EN29LV512
512 Kbit (64K x 8-bit ) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory
FEATURES
• Single power supply operation
• High performance program/erase speed
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations for high performance
3.3 volt microprocessors.
- Byte program time: 8µs typical
- Sector erase time: 500ms typical
• JEDEC Standard program and erase
commands
• JEDEC standard
polling and toggle bits
DATA
• High performance
feature
- Full voltage range: access times as fast as 55
ns
• Single Sector and Chip Erase
- Regulated voltage range: access times as fast
as 45ns
• Embedded Erase and Program Algorithms
• Low power consumption (typical values at 5
MHz)
• Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
• triple-metal double-poly triple-well CMOS Flash
Technology
• Low Vcc write inhibit < 2.5V
• Flexible Sector Architecture:
- Four 16 Kbyte sectors
• >100K program/erase endurance cycle
- Supports full chip erase
• Package options
-
- Individual sector erase supported
- Sector protection and unprotection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
- 8mm x 20mm 32-pin TSOP (Type 1)
- 8mm x 14mm 32-pin TSOP (Type 1)
- 32-pin PLCC
• Commercial and industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV512 is a 512-Kbit, electrically erasable, read/write non-volatile flash memory, organized
as 65,536 bytes. Any byte can be programmed typically in 8µs. The EN29LV512 features 3.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT
states in high-performance microprocessor systems.
The EN29LV512 has separate Output Enable (
), Chip Enable (
), and Write Enable (WE)
CE
OE
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
1
or modifications due to changes in technical specifications.
EN29LV512
CONNECTION DIAGRAMS
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
A0-A15
DQ0-DQ7
WE#
Function
Addresses
EN29LV512
8 Data Inputs/Outputs
Write Enable
Chip Enable
DQ0 – DQ7
A0 - A15
CE#
OE#
Output Enable
Supply Voltage
Ground
Vcc
CE#
OE#
Vss
WE#
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
2
or modifications due to changes in technical specifications.
EN29LV512
TABLE 2. UNIFORM BLOCK SECTOR ARCHITECTURE
SIZE (Kbytes)
A15
1
A14
1
Sector
ADDRESSES
0C000h – 0FFFFh
08000h – 0BFFFh
04000h - 07FFFh
00000h - 03FFFh
3
2
1
0
16
16
16
16
1
0
0
1
0
0
PRODUCT SELECTOR GUIDE
Product Number
EN29LV512
Regulated Voltage Range: Vcc=3.0-3.6 V
Full Voltage Range: Vcc=2.7 – 3.6 V
-45R
Speed Option
-55
-70
-90
Max Access Time, ns (tacc
Max CE# Access, ns (tce)
Max OE# Access, ns (toe)
)
45
45
25
55
70
90
55
30
70
30
90
35
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
3
or modifications due to changes in technical specifications.
EN29LV512
BLOCK DIAGRAM
DQ0-DQ7
Vcc
Vss
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE#
Program Voltage
Generator
Command
Register
STB
Chip Enable
Output Enable
Logic
Data Latch
CE#
OE#
Y-Decoder
Y-Gating
STB
Vcc Detector
A0-A15
Timer
X-Decoder
Cell Matrix
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
4
or modifications due to changes in technical specifications.
EN29LV512
TABLE 3. OPERATING MODES
512K FLASH USER MODE TABLE
Operation
CE#
OE#
WE#
A0-A15
DQ0-DQ7
Read
L
L
H
X
X
H
H
AIN
DOUT
Write
L
L
AIN
DIN
CMOS Standby
TTL Standby
Output Disable
Vcc ± 0.3V
X
X
H
X
High-Z
High-Z
High-Z
H
L
X
X
Sector address,
A6=L, A1=H, A0=L
Sector address,
A6=H, A1=H, A0=L
Sector Protect2
Sector
L
L
H
H
L
L
DIN , DOUT
DIN , DOUT
Unprotect2
Notes:
1. L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),
DIN=Data In, DOUT=Data Out, AIN=Address In
2. Sector protection/unprotection can be implemented by programming equipment.
TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)
512K FLASH MANUFACTURER/DEVICE ID TABLE
A15 A13
to to
A14 A10
A5
to
Description
CE# OE# WE#
A92 A8 A7 A6
A1 A0
DQ7 to DQ0
1Ch
A2
Manufacturer
ID: Eon
L
L
L
L
H
H
X
X
VID
VID
H1
X
X
X
L
L
X
L
L
L
Device ID
X
X
X
H
6Fh
01h
Sector
(Protected)
Protection
Verification
L
L
H
SA
X
VID
X
X
L
X
H
L
00h
(Unprotected)
Note:
1. A8=H is recommended for manufacture ID check. If a manufacture ID is read with A8=L, the chip will output a configuration
code 7Fh.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
5
or modifications due to changes in technical specifications.
EN29LV512
USER MODE DEFINITIONS
Standby Mode
The EN29LV512 has a CMOS-compatible standby mode, which reduces the current to < 1µA
(typical). It is placed in CMOS-compatible standby when the pin is at VCC ± 0.3. The device also
CE
has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is
placed in TTL-compatible standby when the
pin is at VIH. When in standby modes, the outputs
CE
are in a high-impedance state independent of the
input.
OE
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the
or
pin is at a logic high level (VIH), the output from the EN29LV512 is disabled.
OE
CE
The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (11 V) on address pin A9.
Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the
remaining address bits that are don’t-care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
VID. See “Command Definitions” for details on using the autoselect mode.
Write Mode
Write operations, including programming data and erasing sectors of memory, require the host
system to write a command or command sequence to the device. Write cycles are initiated by
placing the byte or word address on the device’s address inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE# and WE# pins Low and the OE# pin High for a
valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#,
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
6
or modifications due to changes in technical specifications.
EN29LV512
whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. The system is not required to provide further controls or timings. The device automatically
provides internally generated program / erase pulses and verifies the programmed /erased cells’
margin. The host system can detect completion of a program or erase operation by reading the
DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits.
The ‘Command Definitions’ section of this document provides details on the specific device
commands implemented in the EN29LV512.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.
Sector protection/unprotection is intended only for programming equipment. This method requires
VID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This
method is described in a separate document called EN29LV512 Supplement, which can be obtained
by contacting a representative of Eon Silicon Solution, Inc.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. ICC4 in the DC Characteristics table represents the automatic sleep more
current specification.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
7
or modifications due to changes in technical specifications.
EN29LV512
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during
Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when Vcc
is greater than VLKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on
Logical Inhibit
,
or
do not initiate a write cycle.
W E
OE CE
Write cycles are inhibited by holding any one of
= VIL,
OE
= VIH, or
is a logical one. If
= VIH. To initiate a
W E
OE
CE
write cycle,
and
must be a logical zero while
,
, and
W E
are
OE
CE
CE
W E
all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with
W E
= V ,
= VIL and
= VIH, the device will not accept commands on the rising edge of
OE
CE
.
WE
IL
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05
8
or modifications due to changes in technical specifications.
EN29LV512
COMMAND DEFINITIONS
The operations of the EN29LV512 are selected by one or more commands written into the
command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,
Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data
sequences written at specific addresses via the command register. The sequences for the
specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses,
incorrect data values or improper sequences will reset the device to Read Mode.
Table 5. EN29LV512 Command Definitions
Bus Cycles
1st
2nd
3rd
4th
5th
6th
Command
Sequence
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Add
Data Add
Data
Add
Data
Add
Data
Add
Data Add
Data
Read
Reset
1
1
RA
Xxx
RD
F0
Manufacturer ID
4
555
555
AA
AA
2AA 55
2AA 55
555
555
90
90
100
1C
Device ID
4
X01 6F
(SA) 00/
X02 01
Sector Protect Verify
4
555
AA
2AA 55
555
90
Program
4
3
555
555
AA
AA
2AA 55
2AA 55
555
555
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program
Unlock Bypass Reset
2
2
XXX A0
XXX 90
PA
PD
XXX 00
Chip Erase
6
555
AA
2AA 55
555
555
80
80
555
555
AA
AA
2AA 55
2AA 55
555
SA
10
30
Sector Erase
6
555
AA
2AA 55
Erase Suspend
Erase Resume
1
1
xxx
xxx
B0
30
Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A16-A14 uniquely select any Sector.
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array
data using the standard read timings, with the only difference in that if it reads at an address within erase
suspended sectors, the device outputs status data. After completing a programming operation in the
Erase Suspend mode, the system may once again read array data with the same exception.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
9
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2004/01/05
EN29LV512
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See next section for details on Reset.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows the
address and data requirements. This is an alternative to the method that requires VID on address bit A9
and is intended for PROM programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of
times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Programming Command
Programming the EN29LV512 is performed by using a four bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of
or
CE
, whichever is last; data is latched on the rising edge of
or
, whichever is first.
W E
CE
W E
Programming status may be checked by sampling data on DQ7 (
polling) or on DQ6 (toggle
bit). ). When the program operation is successfully completed, the device returns to read mode and
the user can read the data programmed to the device at that address. Note that data can not be
programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When
programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can
return the device to Read mode.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature
is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the
normal four cycle Program Command to program the device. This mode is exited after issuing the
Unlock Bypass Reset Command. The device powers up with this feature disabled.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in
“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing
waveforms.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
10
Rev. B, Issue Date: 2004/01/05
EN29LV512
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information. The Autoselect command is not supported during Erase Suspend Mode.
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7: Polling
The EN29LV512 provides
Polling on DQ7 to indicate to the host system the status of the
DATA
embedded operations. The
Polling feature is active during the embedded Programming,
DATA
Sector Erase, Chip Erase, Erase Suspend. (See Table 6)
When the embedded Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the embedded Programming,
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
11
Rev. B, Issue Date: 2004/01/05
EN29LV512
an attempt to read the device will produce the true data last written to DQ7. For the embedded
Programming,
polling is valid after the rising edge of the fourth
or
WE
pulse in the four-
CE
DATA
cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
polling is valid after the rising edge of the sixth
DATA
pulse in the six-cycle sequence. For Sector Erase, polling is valid after the last
DATA
or
W E
CE
rising edge of the sector erase
or
pulse.
CE
W E
Polling must be performed at any address within a sector that is being programmed or
DATA
erased and not a protected sector. Otherwise,
polling may give an inaccurate result if the
DATA
address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable (
) is low. This means that the device is driving status information on DQ7 at
OE
one instant of time and valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
Polling (DQ7) is shown on Flowchart 5. The
Polling (DQ7) timing
DATA
DATA
diagram is shown in Figure 8.
DQ6: Toggle Bit I
The EN29LV512 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling
or
) will result in DQ6 toggling between “zero” and “one”. Once
CE
OE
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth
pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is
WE
valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after
the last rising edge of the Sector Erase pulse.
W E
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read
mode without changing data in all protected blocks.
Toggling either
or
will cause DQ6 to toggle.
OE
CE
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the
program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a
1 when the device has successfully completed its operation and has returned to read mode, the user
must check again to see if the DQ6 is toggling after detecting a “1” on DQ5.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
12
Rev. B, Issue Date: 2004/01/05
EN29LV512
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is
previously programmed to “0.”
Under
Only an erase operation can change a “0” back to a “1.”
this condition, the device halts the operation, and when the operation has exceeded the timing limits,
DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to
return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be used to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip
erase command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not
support multiple sector erase command sequences so it is not very meaningful since it immediately
shows as a “1” after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence. DQ2 toggles when the system reads at addresses within those sectors that have been
selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Flowchart 6).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
13
Rev. B, Issue Date: 2004/01/05
EN29LV512
Write Operation Status
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
Embedded Program
No
DQ7#
Toggle
Toggle
0
0
0
N/A
1
Standard
Mode
Algorithm
toggle
Embedded Erase Algorithm
0
1
Toggle
Reading within Erase
No
N/A
Toggle
Suspended Sector
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend Program
DQ7#
Toggle
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
14
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 6. Status Register Bits
DQ
Name
Logic Level
Definition
Erase Complete or
erase Sector in Erase suspend
Erase On-Going
‘1’
‘0’
Program Complete or
data of non-erase Sector
during Erase Suspend
DATA
7
POLLING
DQ7
DQ7
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Erase Suspend
TOGGLE
BIT
6
Erase Complete
‘-1-1-1-1-1-1-1-‘
‘1’
‘0’
‘1’
‘0’
Program or Erase Error
Program or Erase On-going
Erase operation start
5
3
ERROR BIT
ERASE
TIME BIT
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
Sector. (When DQ5=1, Erase
Error due to currently
TOGGLE
BIT
2
‘-1-0-1-0-1-0-1-’
DQ2
addressed Sector. Program
during Erase Suspend on-
going at current address
Erase Suspend read on
non Erase Suspend Sector
Notes:
DQ7
Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5
DATA
for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
15
Rev. B, Issue Date: 2004/01/05
EN29LV512
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data Poll Device
Verify Data?
Last
Increment
Address
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
555H/AAH
2AAH/55H
555H/A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
16
Rev. B, Issue Date: 2004/01/05
EN29LV512
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
17
Rev. B, Issue Date: 2004/01/05
EN29LV512
Flowchart 4. Embedded Erase Command Sequence
Chip Erase
555H/AAH
Sector Erase
555H/AAH
2AAH/55H
555H/80H
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/AAH
2AAH/55H
Sector Address/30H
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
18
Rev. B, Issue Date: 2004/01/05
EN29LV512
Flowchart 5. Polling
Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
Yes
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
No
(2) This second set of reads is necessary in case
the first set of reads was done at the exact
instant when the status data was in transition.
DQ6 = Toggle?
Yes
Fail
Pass
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
19
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 7. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
0V≤ V ≤ Vcc
Min
Max
Unit
Typ
Input Leakage Current
Output Leakage Current
Supply Current (read) TTL
(read) CMOS
±1
±1
µA
µA
I
LI
IN
I
0V≤ V
≤ Vcc
OUT
LO
8
7
14
mA
mA
mA
µA
CE# = V ; OE# = V
IL
;
IH
I
I
CC1
f = 5MHz
12
Supply Current (Standby - TTL)
Supply Current (Standby - CMOS)
0.4
1
1.0
5.0
CE# = V
IH
,
CC2
CE# = Vcc ± 0.3V
Byte program, Sector or
Chip Erase in progress
15
1
30
mA
µA
I
I
CC3
CC4
Supply Current (Program or Erase)
V
V
= Vcc ± 0.3 V
= Vss ± 0.3 V
IH
5.0
0.8
Automatic Sleep Mode
Input Low Voltage
IL
-0.5
V
V
V
V
V
IL
0.7 x
Vcc ±
Input High Voltage
V
IH
Vcc
0.3
Output Low Voltage
Output High Voltage TTL
0.45
V
I
= 4.0 mA
= -2.0 mA
OL
OL
0.85 x
Vcc
I
OH
OH
V
OH
Vcc -
Output High Voltage CMOS
V
I
= -100 µA,
0.4V
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
10.5
2.3
11.5
100
V
V
ID
A9 = VID
µA
I
ID
Supply voltage (Erase and
V
LKO
2.5
V
Program lock-out)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
20
Rev. B, Issue Date: 2004/01/05
EN29LV512
Test Conditions
3.3 V
2.7 kΩ
Device Under Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Test Specifications
Test Conditions
Output Load
-45R
-55
1 TTL Gate
-70
-90
Unit
Output Load Capacitance, CL
Input Rise and Fall times
Input Pulse Levels
30
5
0.0-3.0
30
5
0.0-3.0
100
5
0.0-3.0
100
5
0.0-3.0
pF
ns
V
Input timing measurement
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
V
V
reference levels
Output timing measurement
reference levels
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
21
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Test
Description
Setup
JEDEC
Standard
-45R
-55
-70
-90
Unit
Min
45
55
70
90
ns
Read Cycle Time
tAVAV
tRC
Max
45
55
70
90
ns
Address to Output Delay
tAVQV
tACC
= V
= V
CE
OE
IL
IL
Max
Max
Max
Max
Min
45
25
10
10
0
55
30
15
15
0
70
30
20
20
0
90
35
20
20
0
ns
ns
ns
ns
ns
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tDF
tDF
tOH
OE= VIL
Output Enable to Output High Z
Output Hold Time from
Addresses,
or ,
CE OE
whichever occurs first
Notes:
For -45R,-55
Vcc = 3.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
For -70, -90
Vcc = 3.0V ± 5%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 5. AC Waveforms for READ Operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
22
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed Options
Description
JEDEC
Standard
-45R
-55
-70
-90
Unit
Min
Min
Min
Min
Min
45
55
70
90
ns
tAVAV
tWC
Write Cycle Time
0
35
20
0
0
45
25
0
0
45
30
0
0
45
45
0
ns
ns
ns
ns
tAVWL
tWLAX
tDVWH
tWHDX
tAS
tAH
Address Setup Time
Address Hold Time
Data Setup Time
tDS
Data Hold Time
tDH
tOES
Min
MIn
Min
0
0
0
0
0
0
0
0
ns
ns
ns
Output Enable Setup Time
Read
Output Enable
Toggle and
tOEH
Hold Time
10
10
10
10
Polling
DATA
Read Recovery Time before
Min
0
0
0
0
ns
tGHWL
tGHWL
Write (
High to
Low)
W E
OE
CE
Min
Min
Min
Min
0
0
0
0
0
0
0
0
ns
ns
ns
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
tWP
tWPH
SetupTime
Hold Time
CE
25
20
30
20
35
20
45
20
Write Pulse Width
Write Pulse Width High
Typ
8
8
8
8
µs
Programming Operation
tWHWH1 tWHWH1
Max
Typ
Min
300
0.5
50
300
0.5
50
300
0.5
50
300
0.5
50
µs
s
tWHWH2 tWHWH2
Sector Erase Operation
Vcc Setup Time
µs
tVCS
Min
500
500
500
500
ns
tVIDR
Rise Time to V
ID
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
23
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter
Symbols
Speed Options
Description
Write Cycle Time
JEDEC
Standard
-45R
45
-55
-70
-90
90
Unit
ns
Min
Min
Min
Min
Min
Min
55
70
tAVAV
tWC
0
35
20
0
0
45
25
0
0
45
30
0
0
45
45
0
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAVEL
tELAX
tDVEH
tEHDX
tAS
tAH
tDS
tDH
tOES
Data Hold Time
0
0
0
0
Output Enable Setup Time
Min
Min
0
0
0
0
ns
ns
Output Enable Read
tOEH
Hold Time
Toggle and
Data Polling
10
10
10
10
Read Recovery Time before
Min
0
0
0
0
ns
tGHEL
tGHEL
Write (
High to
Low)
CE
OE
Min
Min
0
0
0
0
0
0
0
0
ns
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
SetupTime
Hold Time
W E
W E
Min
Min
Typ
Max
Typ
Min
Min
25
20
30
20
35
20
45
20
ns
ns
µs
µs
s
Write Pulse Width
Write Pulse Width High
tCPH
8
8
8
8
tWHWH1 tWHWH1
Programming Operation
300
0.5
50
300
0.5
50
300
0.5
50
300
0.5
50
tWHWH2 tWHWH2
Sector Erase Operation
Vcc Setup Time
µs
ns
tVCS
tVIDR
500
500
500
500
Rise Time to V
ID
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
24
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Limits
Max
Parameter
Comments
Typ
Unit
Sector Erase Time
Chip Erase Time
0.5
10
sec
Excludes 00H programming prior
to erasure
2
40
sec
Byte Programming Time
8
300
µs
Excludes system level overhead
Minimum 100K cycles
Chip Programming Time
Erase/Program Endurance
0.5
1.5
sec
100K
cycles
Table 12. LATCH UP CHARACTERISTICS
Parameter Description
Min
Max
Input voltage with respect to Vss on all pins except I/O pins
-1.0 V
12.0 V
(including A9 and
)
OE
Input voltage with respect to Vss on all I/O Pins
Vcc Current
-1.0 V
Vcc + 1.0 V
100 mA
-100 mA
Note : These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute
Maximum ratings for the actual operating limits.
Table 13. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
Minimum Pattern Data Retention Time
125°C
20
Years
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
25
Rev. B, Issue Date: 2004/01/05
EN29LV512
Table 14. TSOP PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
C
IN
V
IN
Input Capacitance
6
7.5
pF
C
V
= 0
OUT
OUT
Output Capacitance
8.5
7.5
12
9
pF
pF
C
V
= 0
IN2
IN
Control Pin Capacitance
Table 15. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
C
IN
V
IN
Input Capacitance
4
6
pF
pF
pF
C
OUT
V
= 0
OUT
Output Capacitance
8
8
12
12
C
IN2
V
= 0
IN
Control Pin Capacitance
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
26
Rev. B, Issue Date: 2004/01/05
EN29LV512
AC CHARACTERISTICS
Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings
Figure 7. Program Operation Timings
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
27
Rev. B, Issue Date: 2004/01/05
EN29LV512
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
28
Rev. B, Issue Date: 2004/01/05
EN29LV512
Figure 10. Alternate CE# Controlled Write Operation Timings
Figure 11. DQ2 vs. DQ6
Enter
Enter Erase
Erase
Erase
Embedded
Erase
Suspend
Program
Suspend
Resume
WE#
Erase
Enter
Suspend
Read
Enter
Erase
Erase
Erase
Suspend
Program
Suspend
Read
Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
29
Rev. B, Issue Date: 2004/01/05
EN29LV512
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +125
°C
Plastic Packages
-65 to +125
°C
Ambient Temperature
With Power Applied
-55 to +125
°C
Output Short Circuit Current1
200
mA
V
A9 and OE# 2
-0.5 to +11.5
Voltage with
All other pins 3
Vcc
-0.5 to Vcc+0.5
-0.5 to +4.0
V
V
Respect to Ground
Notes:
1.
2.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Minimum DC input voltage on A9 and OE# pins is –0.5V. During voltage transitions, A9 and OE# pins may undershoot Vss
to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on
A9 and OE# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
3.
4.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for
periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O
pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure
below.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter
Value
Unit
Ambient Operating Temperature
Commercial Devices
0 to 70
°C
Industrial Devices
-40 to 85
Regulated Voltage
Range: 3.0-3.6
Operating Supply Voltage
Vcc
V
Standard Voltage Range:
2.7 to 3.6
1.
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
30
Rev. B, Issue Date: 2004/01/05
EN29LV512
PHYSICAL DIMENSIONS
PL 032 — 32-Pin Plastic Leaded Chip Carrier
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
31
Rev. B, Issue Date: 2004/01/05
EN29LV512
PHYSICAL DIMENSIONS (continued)
32L TSOP-1 8mm x 20mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
32
Rev. B, Issue Date: 2004/01/05
EN29LV512
PHYSICAL DIMENSIONS (continued)
32L TSOP-1 8mm x 14mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
33
Rev. B, Issue Date: 2004/01/05
EN29LV512
ORDERING INFORMATION
EN29LV512
70
T
C
P
PACKAGING CONTENT
(Blank) = Conventional
P = Pb Free
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
J = 32-pin Plastic PLCC
T = 32-pin 8mm x 20mm TSOP-1
S = 32-pin 8mm x 14mm TSOP-1
SPEED
45R = 45ns Regulated range 3.0V~3.6V
55 = 55ns
70 = 70ns
90 = 90ns
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29LV = FLASH, 3V Read Program Erase
512 = 512Kbit (64K x 8) uniform sector
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
34
Rev. B, Issue Date: 2004/01/05
EN29LV512
Revisions List
Revision No
Description
Date
A
B
Initial draft
12/10/2003
1. correct the typing error of address input at Page 9 Table 5
Command Definitions
01/05/2004
change “AAA” to “555” at cycle 1,3,4,6
change “555” to “2AA” at cycle 2,5
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
35
Rev. B, Issue Date: 2004/01/05
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