EN29P640B-70TIP_技术文档

EN29LV640T/B

Purpose

Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on

ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the

compositions of the ICs. Eon is still keeping the promise of quality for all the products with the

same as that of Eon delivered before. Please be advised with the change and appreciate your

kindly cooperation and fully support Eon’s product family.

Eon products’ New Top Marking

cFeon Top Marking Example:

cFeon

Part Number: XXXX-XXX

Lot Number: XXXXX

Date Code: XXXXX

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as an Eon product. Any

changes that have been made are the result of normal data sheet improvement and are noted in

the document revision summary, where supported. Future routine revisions will occur when

appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To

order these products, during the transition please specify “Eon top marking” or “cFeon top marking”

on your purchasing orders.

For More Information

Please contact your local sales office for additional information about Eon memory solutions.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

1

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

64 Megabit (8M x 8-bit / 4M x 16-bit) Flash Memory

Boot Sector Flash Memory, CMOS 3.0 Volt-only

FEATURES

• Single power supply operation

- Full voltage range: 2.7 to 3.6 volts read and

write operations

• Standard DATA# polling and toggle bits

feature

• Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

• High performance

- Access times as fast as 70 ns

• Low power consumption (typical values at 5

MHz)

• Support JEDEC Common Flash Interface

(CFI).

- 9 mA typical active read current

- 20 mA typical program/erase current

- Less than 1 μA current in standby or automatic

sleep mode.

• Low Vcc write inhibit < 2.5V

• Minimum 100K program/erase endurance

cycles.

• Flexible Sector Architecture:

• RESET# hardware reset pin

- Hardware method to reset the device to read

mode.

- Eight 8-Kbyte sectors, One hundred and

twenty-seven 32K-Word / 64K-byte sectors.

- 8-Kbyte sectors for Top or Bottom boot.

- Sector/Sector Group protection:

Hardware locking of sectors to prevent

program or erase operations within individual

sectors

Additionally, temporary Sector Group

Unprotect allows code changes in previously

locked sectors.

• WP#/ACC input pin

- Write Protect (WP#) function allows

protection of outermost two boot sectors,

regardless of sector protect status

- Acceleration (ACC) function provides

accelerated program times

• Package Options

- 48-pin TSOP (Type 1)

- 48 ball 6mm x 8mm TFBGA

- 64 ball 11mm x 13mm TFBGA

• High performance program/erase speed

- Word program time: 8µs typical

- Sector erase time: 100ms typical

- Chip erase time: 16s typical

• Industrial Temperature Range.

• JEDEC Standard compatible

GENERAL DESCRIPTION

The EN29LV640T/B is a 64-Megabit, electrically erasable, read/write non-volatile flash memory,

organized as 8,388,608 bytes or 4,194,304 words. Any word can be programmed typically in 8µs. The

EN29LV640T/B features 3.0V voltage read and write operation, with access times as fast as 70ns to

eliminate the need for WAIT states in high-performance microprocessor systems.

The EN29LV640T/B has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)

controls, which eliminate bus contention issues. This device is designed to allow either single Sector or

full Chip erase operation, where each Sector can be individually protected against program/erase

operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K

program/erase cycles on each Sector.

.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

2

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

A19

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

Vss

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Vcc

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

9

Standard

TSOP

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

Vss

CE#

A0

48-Ball TFBGA

Top View, Balls Facing Down

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

3

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

64-Ball TFBGA

Top View, Balls Facing Down

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. G, Issue Date: 2009/03/30

www.eonssi.com

4

EN29LV640T/B

TABLE 1. PIN DESCRIPTION

LOGIC DIAGRAM

Pin Name

A0-A21

DQ0-DQ14

DQ15 / A-1

CE#

Function

22 Address inputs

15 Data Inputs/Outputs

DQ15 (data input/output, in word mode),

A-1 (LSB address input, in byte mode)

Chip Enable

OE#

Output Enable

WE#

Write Enable

WP#/ACC

RESET#

BYTE#

RY/BY#

Vcc

Write Protect / Acceleration Pin

Hardware Reset Pin

Byte/Word mode selection

Ready/Busy Output

Supply Voltage

(2.7-3.6V)

Vss

Ground

NC

Not Connected to anything

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

5

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

ORDERING INFORMATION

EN29LV640

T ― 70

T

I

P

PACKAGING CONTENT

(Blank) = Conventional

P = RoHS compliant

TEMPERATURE RANGE

I = Industrial (-40°C to +85°C)

PACKAGE

T = 48-pin TSOP

B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA)

0.80mm pitch, 6mm x 8mm package

E = 64-Ball Thin Fine Pitch Ball Grid Array (TFBGA)

1.0mm pitch, 11mm x 13mm package

SPEED

70 = 70ns

90 = 90ns

BOOT CODE SECTOR ARCHITECTURE

T = Top boot Sector

B = Bottom boot Sector

BASE PART NUMBER

EN = EON Silicon Solution Inc.

29LV = FLASH, 3V Read, Program and Erase

640 = 64 Megabit (8M x 8 / 4M x 16)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

6

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

U

Table 2A. Top Boot Sector Address Tables (EN29LV640T)

Sector Size

(Kbytes / Kwords)

Address Range (h) Address Range (h)

Sector

A21 – A12

Byte mode (x8)

Word Mode (x16)

SA0

SA1

0000000xxx

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001110xxx

0001111xxx

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011100xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0100011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

64/32

000000–00FFFF

000000–007FFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

7

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0110100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

64/32

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

400000–40FFFF

410000–41FFFF

420000–42FFFF

430000–43FFFF

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

8

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA83

SA84

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

64/32

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

9

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

1111110xxx

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

64/32

8/4

7E0000–7EFFFF

7F0000–7F1FFF

7F2000–7F3FFF

7F4000–7F5FFF

7F6000–7F7FFF

7F8000–7F9FFF

7FA000–7FBFFF

7FC000–7FDFFF

7FE000–7FFFFF

3F0000–3F7FFF

3F8000–3F8FFF

3F9000–3F9FFF

3FA000–3FAFFF

3FB000–3FBFFF

3FC000–3FCFFF

3FD000–3FDFFF

3FE000–3FEFFF

3FF000–3FFFFF

Note: The address bus is A21:A-1 in byte mode where BYTE# = V_IL

B

or A21:A0 in word mode where

BYTE# = V_IH

B

U

Table 2B. Bottom Boot Sector Address Tables (EN29LV640B)

Sector Size

(Kbytes / Kwords)

Address Range (h) Address Range (h)

Sector

A21 – A12

Byte mode (x8)

Word Mode (x16)

SA0

SA1

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001110xxx

0001111xxx

8/4

000000–001FFF

000000–000FFF

002000–003FFF

004000–005FFF

006000–007FFF

008000–009FFF

00A000–00BFFF

00C000–00DFFF

00E000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

001000–001FFF

002000–002FFF

003000–003FFF

004000–004FFF

005000–005FFF

006000–006FFF

007000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

10

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011100xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0100011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0110100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

64/32

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

11

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

64/32

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

400000–40FFFF

410000–41FFFF

420000–42FFFF

430000–43FFFF

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

12

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

1111110xxx

1111111xxx

64/32

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

7E0000–7EFFFF

7F0000–7FFFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

Note: The address bus is A21:A-1 in byte mode where BYTE# = V_IL

B

or A21:A0 in word mode where

BYTE# = V_IH

B

PRODUCT SELECTOR GUIDE

Product Number

EN29LV640T/B

Speed Option

-70

-90

70

30

90

35

Max Access Time, ns (t_acc

Max CE# Access, ns (t_ce

Max OE# Access, ns (t_oe

B

)

B

)

B

)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

13

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

BLOCK DIAGRAM

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

14

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

TABLE 3. OPERATING MODES

64M FLASH USER MODE TABLE

DQ8-DQ15

DQ0-

RESET

#

WP#/AC

C

A0-

A21

Operation

Read

CE#

OE# WE#

BYTE#

= V_IL

DQ7

= V_IH

D_OUT

D_IN

B

L

H

L

H

L/H

(Note 1)

A_IN

B

D_OUT

B

DQ8-

DQ14=

High-Z,

DQ15 =

A-1

Write

A_IN

B

D_IN

B

Accelerated

Program

L

H

L

H

V_HH

B

A_IN

B

D_IN

B

D_IN

B

V_CC

0.3V

L

B

±

V_CC±

0.3V

H

B

CMOS Standby

X

H

X

High-Z

Output Disable

Hardware Reset

H

X

H

X

L/H

X

High-Z

X

L

SA,

Sector (Group)

Protect

A6=L,

A1=H,

A0=L

SA,

A6=H,

A1=H,

A0=L

L

H

L

V_ID

B

L/H

(Note 2)

X

Sector

Unprotect

L

H

X

L

V_ID

B

(Note 1)

Temporary

Sector

X

V_ID

B

A_IN

B

(Note 2) (Note 2) High-Z

Unprotect

L=logic low= V_IL

SA=Sector Addresses, D_IN

B

, H=Logic High= V_IH

B

, V_ID

B

=V_HH

B

=11 ± 0.5V = 10.5-11.5V, X=Don’t Care (either L or H, but not floating ),

=Address In

B

=Data In, D_OUT

B

=Data Out, A_IN

B

Notes:

1. If WP#/ACC = V_IL

sector protection depends on whether they were last protected or unprotected. If WP#/ACC = V_HH

be unprotected.

B

, the two outermost boot sectors remain protected. If WP# / ACC = V_IH

B

, the outermost boot

B

, all sectors will

2. Please refer to “Sector/Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

15

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

TABLE 4. Autoselect Codes (Using High Voltage, V_ID

B

)

64M FLASH MANUFACTURER/DEVICE ID TABLE

A21

WE# to

A11

to

A5

A8 A7 A6 to

DQ8

A1 A0 to

DQ7

to

A9²

P

Description

CE# OE#

A12

A10

A2

DQ15 DQ0

H¹

P

1Ch

P

Manufacturer ID:

Eon

L

H

X

V_ID

B

X

L

X

L

X

L

7Fh

Device ID

(top boot

sector)

Device ID

(bottom boot

sector)

Word

Byte

Word

Byte

L

H

22h

X

C9h

CBh

X

V_ID

B

X

L

X

L

H

22h

X

V_ID

B

X

01h

(Protected)

00h

(Unprotected)

X

Sector Protection

Verification

L

H

SA

X

V_ID

B

X

L

X

H

L

L=logic low= V_IL, H=Logic High= V_IH, V_ID=11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector

Addresses

Note:

1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a

configuration code 7Fh.

2. A9 = V_IDis for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect

Mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

16

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

USER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the

byte or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word

configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only

data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are

tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV640T/B has a CMOS-compatible standby mode, which reduces the

(typical). It is placed in CMOS-compatible standby when the CE# pin is at V_CC± 0.5. RESET# and

BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode,

which reduces the maximum V_CCcurrent to < 1mA. It is placed in TTL-compatible standby when the

_IH. When in standby modes, the outputs are in a high-impedance state independent of

B

current to < 1µA

B

CE# pin is at V

the OE# input.

B

Automatic Sleep Mode

The EN29LV640T/B has an automatic sleep mode, which minimizes power consumption. The devices

will enter this mode automatically when the states of address bus remain stable for t^acc+ 30ns. I_CC4in

the DC Characteristics table shows the current specification. With standard access times, the device

will output new data when addresses change.

Read Mode

The device is automatically set to reading array data after device power-up or hardware reset. No

commands are required to retrieve data. The device is also ready to read array data after completing an

Embedded Program or Embedded Erase algorithm

After the device accepts a Sector Erase Suspend command, the device enters the Sector Erase

Suspend mode. The system can read array data using the standard read timings, except that if it reads

at an address within erase-suspended sectors, the device outputs status data. After completing a

programming operation in the Sector Erase Suspend mode, the system may once again read array

data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional

information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes

high or while in the autoselect mode. See the “Reset Command” for additional details.

Output Disable Mode

When the OE# pin is at a logic high level (V_IH), the output from the EN29LV640T/B is disabled. The

B

output pins are placed in a high impedance state.

Autoselect Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming

equipment to automatically match a device to be programmed with its corresponding programming

algorithm. However, the autoselect codes can also be accessed in-system through the command

register.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

17

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

When using programming equipment, the autoselect mode requires V_ID

B

(10.5 V to 11.5 V) on address

pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when

verifying sector protection, the sector address must appear on the appropriate highest order address

bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the

remaining address bits that are don’t-care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on DQ15–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via the

command register, as shown in the Command Definitions table. This method does not require V

“Command Definitions” for details on using the autoselect mode.

B

_ID. See

Writing Command Sequences

To write a command or command sequence to program data to the device or erase data, the system

has to drive WE# and CE# to V_IL, and OE# to V_IH

B

.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes

or words. An erase operation can erase one sector or the whole chip.

The system can also read the autoselect codes by entering the autoselect mode, which need the

autoselect command sequence to be written. Please refer to the “Command Definitions” for all the

available commands.

RESET#: Hardware Reset

When RESET# is driven low for t_RP, all output pins are tristates. All commands written in the internal

B

state machine are reset to reading array data.

Please refer to timing diagram for RESET# pin in “AC Characteristics”.

Sector/Sector Group Protection & Chip Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector.

The hardware chip unprotection feature re-enables both program and erase operations in previously

protected sectors. A sector group implies three or four adjacent sectors that would be protected at the same

time. Please see the following tables which show the organization of sector groups.

There are two methods to enable this hardware protection circuitry. The first one requires only that the

RESET# pin be at V_IDand then standard microprocessor timings can be used to enable or disable this

feature. See Flowchart 7a and 7b for the algorithm and Figure. 12 for the timings.

When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect

write cycle.

The second method is for programming equipment. This method requires V_IDto be applied to both OE#

and A9 pins and non-standard microprocessor timings are used. This method is described in a

separate document named EN29LV640T/B Supplement, which can be obtained by contacting a

representative of Eon Silicon Solution, Inc.

U

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

18

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Top Boot Sector/Sector Group Organization Table (EN29LV640T) for (Un)Protection

Sector Group

SG 0

SG 1

SG 2

SG 3

SG 4

SG 5

SG 6

SG 7

SG 8

SG 9

SG10

SG11

SG12

SG13

SG14

SG15

SG16

SG17

SG18

SG19

SG20

SG21

SG22

SG23

SG24

SG25

SG26

SG27

SG28

SG29

SG30

Sectors

SA 0-SA

SA 4-SA

A21-A12

00000XXXXX

00001XXXXX

Sector Group Size

64 Kbytes x 4

3

7

SA 8-SA 11 00010XXXXX

SA 12-SA 15 00011XXXXX

SA 16-SA 19 00100XXXXX

SA 20-SA 23 00101XXXXX

SA 24-SA 27 00110XXXXX

SA 28-SA 31 00111XXXXX

SA 32-SA 35 01000XXXXX

SA 36-SA 39 01001XXXXX

SA 40-SA 43 01010XXXXX

SA 44-SA 47 01011XXXXX

SA 48-SA 51 01100XXXXX

SA 52-SA 55 01101XXXXX

SA 56-SA 59 01110XXXXX

SA 60-SA 63 01111XXXXX

SA 64-SA 67 10000XXXXX

SA 68-SA 71 10001XXXXX

SA 72-SA 75 10010XXXXX

SA 76-SA 79 10011XXXXX

SA 80-SA 83 10100XXXXX

SA 84-SA 87 10101XXXXX

SA 88-SA 91 10110XXXXX

SA 92-SA 95 10111XXXXX

SA 96-SA 99 11000XXXXX

SA100-SA103 11001XXXXX

SA104-SA107 11010XXXXX

SA108-SA111 11011XXXXX

SA112-SA115 11100XXXXX

SA116-SA119 11101XXXXX

SA120-SA123 11110XXXXX

1111100XXX

SG31

SA124-SA126 1111101XXX

1111110XXX

64 Kbytes x 3

SG32

SG33

SG34

SG35

SG36

SG37

SG38

SG39

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

8 Kbytes

Bottom Boot Sector/Sector Group Organization Table (EN29LV640B) for (Un)Protection

Sector Group

SG39

SG38

SG37

SG36

SG35

SG34

SG33

SG32

SG31

SG30

SG29

SG28

Sectors

A21-A12

Sector Group Size

64 Kbytes x 4

SA134-SA131 11111XXXXX

SA130-SA127 11110XXXXX

SA126-SA123 11101XXXXX

SA122-SA119 11100XXXXX

SA118-SA115 11011XXXXX

SA114-SA111 11010XXXXX

SA110-SA107 11001XXXXX

SA106-SA103 11000XXXXX

SA102-SA 99 10111XXXXX

SA 98-SA 95 10110XXXXX

SA 94-SA 91 10101XXXXX

SA 90-SA 87 10100XXXXX

SA 86-SA 83 10011XXXXX

SG27

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

19

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

SG26

SG25

SG24

SG23

SG22

SG21

SG20

SG19

SG18

SG17

SG16

SG15

SG14

SG13

SG12

SG11

SG10

SG 9

SA 82-SA 79 10010XXXXX

SA 78-SA 75 10001XXXXX

SA 74-SA 71 10000XXXXX

SA 70-SA 67 01111XXXXX

SA 66-SA 63 01110XXXXX

SA 62-SA 59 01101XXXXX

SA 58-SA 55 01100XXXXX

SA 54-SA 51 01011XXXXX

SA 50-SA 47 01010XXXXX

SA 46-SA 43 01001XXXXX

SA 42-SA 39 01000XXXXX

SA 38-SA 35 00111XXXXX

SA 34-SA 31 00110XXXXX

SA 30-SA 27 00101XXXXX

SA 26-SA 23 00100XXXXX

SA 22-SA 19 00011XXXXX

SA 18-SA 15 00010XXXXX

SA 14-SA 11 00001XXXXX

0000011XXX

64 Kbytes x 4

64 Kbytes x 3

64 Kbytes x 4

SG 8

SA 10-SA

8

0000010XXX

0000001XXX

0000000111

0000000110

0000000101

0000000100

0000000011

0000000010

0000000001

0000000000

64 Kbytes x 3

SG 7

SG 6

SG 5

SG 4

SG 3

SG 2

SG 1

SG 0

SA

7

6

5

4

3

2

1

0

8 Kbytes

Write Protect / Accelerated Program (WP# / ACC)

The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware meth-

od of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing

throughput at the factory, using an external high voltage.

When WP#/ACC is Low, the device protects the outermost two 8K-byte Boot Sector; no matter the

sectors are protected or unprotected using the method described in “Sector/Sector Group Protection &

Chip Unprotection”, Program and Erase operations in these sectors are ignored.

When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8K-

byte boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte

Boot Sector unless the sector is protected using Sector Protection.

When WP#/ACC is raised to V_HHthe memory automatically enters the Accelerated Program mode, this

mode permit the system to skip the normal command unlock sequences and program byte/word

locations directly to reduces the time required for program operation. When WP#/ACC returns to V_IHor

V_ILnormal operation resumes. The transitions from V_IHor V_ILto V_HHand from V_HHto V_IHor V_ILmust be

slower than tB_VHHB, see Figure 11.

Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin

must not be at V_HHfor operations other than accelerated programming. It could cause the device to be

damaged.

Never raise this pin to V_HHfrom any mode except Read mode. Otherwise the memory may be left in an

indeterminate state.

A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to

decouple the current surges from the power supply. The PCB track widths must be sufficient to carry

the currents required during Accelerated Program mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

20

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Temporary Sector Unprotect

Start

This feature allows temporary unprotection of previously protected

sector groups to change data while in-system. The Temporary

Sector Unprotect mode is activated by setting the RESET# pin to

VBIDB. During this mode, formerly protected sectors can be

programmed or erased by simply selecting the sector addresses.

Once VBIDB is removed from the RESET# pin, all the previously

Reset#=V_{ID (note 1)}

Perform Erase or Program

Operations

protected sectors are protected again.

flowchart and figure 10 for more timing details.

See accompanying

RESET#=V_IH

Temporary Sector Unprotect

Completed _{(note 2)}

Notes:

1. All protected sectors are unprotected. (If

WP#/ACC=V_IL, outermost boot sectors will remain

protected.)

2. Previously protected sectors are protected again.

COMMON FLASH INTERFACE (CFI)

The common flash interface (CFI) specification outlines device and host systems software interrogation

handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array

data.

The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper

address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset

command.

The system can also write the CFI query command when the device is in the autoselect mode. The

device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–

8. The system must write the reset command to return the device to the autoselect mode.

Table 5. CFI Query Identification String

Addresses

Adresses

(Word Mode) (Byte Mode)

Data

Description

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h Query Unique ASCII string “QRY”

0059h

0002h

Primary OEM Command Set

0000h

0040h

Address for Primary Extended Table

0000h

Alternate OEM Command set (00h = none exists)

0000h

Address for Alternate OEM Extended Table (00h = none exists)

0000h

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

21

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Table 6. System Interface String

Addresses

(Word Mode) (Byte Mode)

Data

Description

Vcc Min (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

Vcc Max (write/erase)

DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

0036h

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h Vpp Min. voltage (00h = no Vpp pin present)

0000h Vpp Max. voltage (00h = no Vpp pin present)

0004h Typical timeout per single byte/word write 2^N

P

ꢀS

P

Typical timeout for Min, size buffer write 2^N

supported)

000Ah Typical timeout per individual block erase 2^N

P

ꢀS (00h = not

P

20h

40h

0000h

P

21h

22h

23h

24h

25h

42h

44h

46h

48h

4Ah

P

ms

0000h Typical timeout for full chip erase 2^N

P

ms (00h = not supported)

P

0005h Max. timeout for byte/word write 2^N

times typical

P

0000h Max. timeout for buffer write 2^N

P

times typical

P

0004h Max. timeout per individual block erase 2^N

P

times typical

P

Max timeout for full chip erase 2^N

supported)

P

times typical (00h = not

P

26h

4Ch

0000h

Table 7. Device Geometry Definition

Addresses

(Word mode)

27h

Addresses

(Byte Mode)

4Eh

Data

Description

Device Size = 2^N

bytes

P

0017h

0002h

0000h

0002h

0007h

0000h

0020h

0000h

007Eh

0000h

0001h

0000h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

50h

52h

54h

56h

58h

5Ah

5Ch

5Eh

60h

62h

64h

66h

68h

6Ah

6Ch

6Eh

Flash Device Interface description (refer to CFI publication 100)

Max. number of byte in multi-byte write = 2^N

P

(00h = not supported)

Number of Erase Block Regions within device

Erase Block Region 1 Information

(refer to the CFI specification of CFI publication 100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

38h

39h

3Ah

3Bh

70h

72h

74h

76h

3Ch

78h

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

22

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Table 8. Primary Vendor-specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

80h

Data

Description

Query-unique ASCII string “PRI”

40h

41h

42h

43h

44h

0050h

0052h

0049h

0031h

82h

84h

86h

88h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Minimum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV

Maximum ACC (Acceleration) Supply Voltage

00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0004h

0001h

49h

92h

0004h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

94h

96h

98h

9Ah

9Ch

9Eh

0000h

00A5h

00C5h

0002h/ Top/Bottom Boot Sector Identifier

0003h 02h = Bottom Boot, 03h = Top Boot

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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23

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Hardware Data protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes as seen in the Command Definitions table. Additionally, the

following hardware data protection measures prevent accidental erasure or programming, which might

otherwise be caused by false system level signals during Vcc power up and power down transitions, or

from system noise.

Low V_CCWrite Inhibit

B

When Vcc is less than V_LKO

power up and power down. The command register and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The system must

provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than

V_LKO

B

, the device does not accept any write cycles. This protects data during Vcc

B

.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL

B

, CE# = V_IH

B

, or WE# = V_IH. To initiate a write

B

cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all

logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even with

CE# = V

B

_IL, WE#= V_IL

B

and OE# = V_IH, the device will not accept commands on the rising edge of WE#.

B

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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24

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

COMMAND DEFINITIONS

The operations of the device are selected by one or more commands written into the command

register. Commands are made up of data sequences written at specific addresses via the command

register. The sequences for the specified operation are defined in the Command Definitions table

(Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to

Read Mode.

Table 9. EN29LV640T/B Command Definitions

Bus Cycles

Command

Sequence

1^st

Addr Data Addr Data

P

Cycle

2^nd

P

Cycle

3^rd

Addr

P

Cycle

Data

4^th

Addr Data

P

Cycle

5^th

P

Cycle

6^th

Cycle

P

Addr Data Addr Data

Read

Reset

1

RA

xxx

RD

F0

000

100

000

200

7F

Word

555

2AA

555

1C

7F

1C

Manufacturer ID

4

AA

55

90

Byte

AAA

Word

Byte

555

2AA

555

2AA

555

x01

x02

x01

x02

22C9

Device ID

Top Boot

4

AA

55

90

AAA

555

AAA

555

C9

Word

Byte

22CB

CB

Device ID

Bottom Boot

AAA

(SA)

X02

(SA)

X04

00

01

00

01

Word

555

2AA

555

Sector Protect

Verify

4

AA

55

90

A0

Byte

AAA

555

AAA

555

Word

2AA

Program

PA

PD

Byte

AAA

555

AAA

555

Word

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

555

AAA

555

2AA

555

AAA

555

AAA

555

AAA

555

2AA

555

AAA

Sector Erase

SA

Sector Erase Suspend

Sector Erase Resume

1

xxx

B0

30

xxx

55

Word

Byte

CFI Query

1

98

AA

Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles

RA = Read Address: address of the memory location to be read. This is a read cycle.

RD = Read Data: data read from location RA during Read operation. This is a read cycle.

PA = Program Address: address of the memory location to be programmed. X = Don’t-Care

PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.

Notes:

1. The data is 00H for an unprotected sector/sector block and 01H for a protected sector/sector block.

2. The data is 88H for factory locked and 08H for not factory locked.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

25

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to

retrieve data. The device is also ready to read array data after completing an Embedded Program or

Embedded Erase algorithm.

Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can

read array data using the standard read timings from sectors other than the one which is being erase-

suspended. If the system reads at an address within erase-suspended sectors, the device outputs

status data. After completing a programming operation in the Sector Erase Suspend mode, the system

may once again read array data with the same exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high

during an active program or erase operation or while in the autoselect mode. See next section for

details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t-

care for this command.

The reset command may be written between the cycle sequences in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however, the

device ignores reset commands until the operation is complete. The reset command may be written

between the sequence cycles in a program command sequence before programming begins. This

resets the device to reading array data (also applies to programming in Sector Erase Suspend mode).

Once programming begins, however, the device ignores reset commands until the operation is

complete.

The reset command may be written between the cycle sequences in an autoselect command sequence.

Once in the autoselect mode, the reset command must be written to return to reading array data.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to

reading array data (also applies in Sector Erase Suspend mode).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices ID

codes, and determine whether or not a sector (group) is protected. The Command Definitions table

shows the address and data requirements. This is an alternative to the method that requires V_ID

B

on

address bit A9 and is intended for commercial programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number

of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array

data.

Word / Byte Programming Command

The device can be programmed by byte or by word, depending on the state of the BYTE# Pin.

Programming the EN29LV640T/B is performed by using a four-bus-cycle operation (two unlock write

cycles followed by the Program Setup command and Program Data Write cycle). When the program

command is executed, no additional CPU controls or timings are necessary. An internal timer

terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,

whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.

Any commands written to the device during the program operation are ignored. Programming status

can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program

This Data Sheet may be revised by subsequent versions

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26

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

operation is successfully completed, the device returns to read mode and the user can read the data

programmed to the device at that address. Note that data can not be programmed from a “0” to a “1”.

Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to

indicate the operation was successful. However, a succeeding read will show that the data is still “0”.

Only erase operations can convert a “0” to a “1”. When programming time limit is exceeded, DQ5 will

produce a logical “1” and a Reset command can return the device to Read mode.

Programming is allowed in any sequence across sector boundaries.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by

the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not

require the system to preprogram prior to erase. The Embedded Erase algorithm automatically

preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or timings during these operations. The Command

Definitions table shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and addresses are no longer latched.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing

two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed

by the address of the sector to be erased, and the sector erase command. The Command Definitions

table shows the address and data requirements for the sector erase command sequence.

Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All

other commands are ignored. If there are several sectors to be erased, Sector Erase Command

sequences must be issued for each sector. That is, only a sector address can be specified for each

Sector Erase command. Users must issue another Sector Erase command for the next sector to be

erased after the previous one is completed.

When the Embedded Erase algorithm is completed, the device returns to reading array data and

addresses are no longer latched. The system can determine the status of the erase operation by using

DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4

illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the

“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for

timing waveforms.

Sector Erase Suspend / Resume Command

The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then

read data from, or program data to, any sector not selected for erasure. This command is valid only

during the sector erase operation. The Sector Erase Suspend command is ignored if written during the

chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the

Sector Erase Suspend command.

When the Sector Erase Suspend command is written during a sector erase operation, the device

requires a maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. Normal read and write timings and command definitions apply.

Please note that Autoselect command sequence can not be accepted during Sector Erase

This Data Sheet may be revised by subsequent versions

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27

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Suspend.

Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-

suspended. See “Write Operation Status” for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for

more information. The Autoselect command is not supported during Sector Erase Suspend Mode.

The system must write the Sector Erase Resume command (address bits are don’t-care) to exit the

sector erase suspend mode and continue the sector erase operation. Further writes of the Resume

command are ignored. Another Sector Erase Suspend command can be written after the device has

resumed erasing.

WRITE OPERATION STATUS

DQ7: DATA# Polling

The EN29LV640T/B provides DATA# polling on DQ7 to indicate the status of the embedded operations.

The DATA# Polling feature is active during the Word/Byte Programming, Sector Erase, Chip Erase, and

Sector Erase Suspend. (See Table 10)

When the embedded programming is in progress, an attempt to read the device will produce the

complement of the data written to DQ7. Upon the completion of the programming operation, an attempt

to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge

of the fourth WE# or CE# pulse in the four-cycle sequence for program.

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7

output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output

during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of

the last WE# or CE# pulse in the six-cycle sequence.

DATA# Polling must be performed at any address within a sector that is being programmed or erased

and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used

is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the

output enable (OE#) is low. This means that the device is driving status information on DQ7 at one

instant of time and valid data at the next instant of time. Depending on the time the system samples the

DQ7 output, it may read the status of valid data. Even if the device has completed the embedded

operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on

DQ0-DQ7 should be read on the subsequent read attempts.

The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing

diagram is shown in Figure 6.

RY/BY#: Ready/Busy Status output

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in

progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together

in parallel with a pull-up resistor to Vcc.

In the output-low period, signifying Busy, the device is actively erasing or programming. This includes

programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is

ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

DQ6: Toggle Bit I

The EN29LV640T/B provides a “Toggle Bit” on DQ6 to indicate the status of the embedded

programming and erase operations. (See Table 10)

During an embedded Program or Erase operation, successive attempts to read data from the device at

any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the

embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read

on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of

the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after

the rising edge of the sixth WE# pulse for sector erase or chip erase.

In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,

then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read

mode without changing data in all protected sectors.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown

in Figure 7.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or

erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the

device has successfully completed its operation and has returned to read mode, the user must check

again to see if the DQ6 is toggling after detecting a “1” on DQ5.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,

the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a

“1.” Under both these conditions, the system must issue the reset command to return the device to

reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be checked to determine

whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase

command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support

multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since

it immediately shows as a “1” after the first 30h command. Future devices may support this feature.

DQ2: Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2

toggles when the system reads at addresses within those sectors that have been selected for erasure.

(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

for erasure. Thus, both status bits are required for sector and mode information. Refer to the following

table to compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.

See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical

form.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle

bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, a system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And

the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the

system should then determine again whether the toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has

successfully completed the program or erase operation. If it is still toggling, the device did not complete

the operation successfully, and the system must write the reset command to return to reading array

data.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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30

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Write Operation Status

Operation

DQ7

DQ6

DQ5 DQ3

DQ2

RY/BY#

Embedded Program

No

toggle

DQ7# Toggle

0

N/A

1

0

1

Standard

Mode

Algorithm

Embedded Erase Algorithm

0

1

Toggle

Reading within Erase

Suspended Sector

Reading within Non-Erase

Suspended Sector

No

Toggle

N/A

Toggle

Erase

Suspend

Mode

Data

Data Data

Data

N/A

1

0

Erase-Suspend Program

DQ7# Toggle

0

N/A

Table 10. Status Register Bits

DQ

Name

Logic Level

Definition

Erase Complete or erased sector in Sector Erase

Suspend

‘1’

‘0’

Erase On-Going

DATA#

POLLING

7

Program Complete or data of non-erased sector

during Sector Erase Suspend

DQ7

DQ7#

Program On-Going

‘-1-0-1-0-1-0-1-’

DQ6

Erase or Program On-going

Read during Sector Erase Suspend

Erase Complete

6

TOGGLE BIT

‘-1-1-1-1-1-1-1-‘

‘1’

‘0’

‘1’

‘0’

Program or Erase Error

Program or Erase On-going

Erase operation start

5

3

TIME OUT BIT

ERASE TIME

OUT BIT

Erase timeout period on-going

Chip Erase, Sector Erase or Read within Erase-

Suspended sector. (When DQ5=1, Erase Error due

to currently addressed Sector or Program on Erase-

Suspended sector

‘-1-0-1-0-1-0-1-’

DQ2

2

TOGGLE BIT

Read on addresses of non Erase-Suspend sectors

Notes:

DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for

Program or Erase Success.

DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive

reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5: Tim Out Bit: set to “1” if failure in programming or erase

DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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EN29LV640T/B

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data# Poll Device

Verify Data?

Last

Increment

Address

No

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

(See the Command Definitions section for more information.)

555H / AAH

2AAH / 55H

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

This Data Sheet may be revised by subsequent versions

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EN29LV640T/B

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

Data Poll from

System or Toggle Bit

successfully

completed

Data =FFh?

No

Yes

Erase Done

Flowchart 4. Embedded Erase Command Sequence

(See the Command Definitions section for more information.)

Chip Erase

Sector Erase

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

555H/10H

This Data Sheet may be revised by subsequent versions

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EN29LV640T/B

Flowchart 5. DATA# Polling

Algorithm

Start

Read Data

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data (1)

Notes:

Yes

(1) This second read is necessary in case the

first read was done at the exact instant when

the status data was in transition.

DQ7 = Data?

No

Fail

Pass

Start

Flowchart 6. Toggle Bit Algorithm

Read Data twice

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data twice (2)

Notes:

(2) This second set of reads is necessary in

case the first set of reads was done at the

exact instant when the status data was in

transition.

No

DQ6 = Toggle?

Yes

Fail

Pass

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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EN29LV640T/B

Flowchart 7a. In-System Sector (Group) Protect Flowchart

START

PLSCNT = 1

RESET# = V_ID

Wait 1 μs

No

First Write

Cycle =

60h?

Temporary Chip

Unprotect Mode

Yes

Set up sector

(group) address

To Protect: Write 60h to

sector addr with

A6 = 0, A1 = 1, A0 = 0

Wait 150 μs

To Verify: Write 40h to

sector(group) address with

A6 = 0, A1 = 1, A0 = 0

Increment

PLSCNT

Reset

PLSCNT = 1

Wait 0.4 μs

Read from sector address

with

A6 = 0, A1 = 1, A0 = 0

No

Data = 01h?

Yes

PLSCNT = 25?

Yes

Device failed

Yes

Protect another

sector?

No

Remove V_ID

from RESET#

Write reset

command

Sector Protect Algorithm

Sector Protect

complete

This Data Sheet may be revised by subsequent versions

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Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Flowchart 7b. In-System Chip Unprotect Flowchart

START

PLSCNT = 1

Protect all sectors

(groups): The

indicated portion of

RESET# = V_ID

the sector protect

algorithm must be

Wait 1 μS

performed for all

unprotected sectors

prior to issuing the

No

first sector unprotect

Temporary Chip

Unprotect Mode

First Write

address (see

Cycle = 60h?

Diagram 7a.)

Yes

No

All sectors

protected?

Yes

Set up first sector

address

Chip Unprotect: Write 60H to sector

address with A6 = 1,

A1 = 1, A0 = 0

Wait 15 ms

Verify Chip Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1, A0 =0

Increment

PLSCNT

Wait 0.4 μS

Read from sector address with

A6 = 1, A1 = 1, A0 = 0

No

PLSCCNT =

1000?

Set up next sector

(group) address

Data = 00h?

Yes

No

Last sector

verified?

Device failed

Yes

Remove V_IDfrom

RESET#

Write reset

command

Chip Unprotect

complete

Chip Unprotect Algorithm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

36

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

ABSOLUTE MAXIMUM RATINGS

Parameter

Value

Unit

℃

Storage Temperature

-65 to +150

℃

Plastic Packages

-65 to +125

-55 to +125

Ambient Temperature

With Power Applied

Output Short Circuit Current¹

P

200

mA

V

P

A9, OE#, RESET#

and WP#/ACC

P

-0.5 to +11.5

2

P

Voltage with

Respect to Ground

3

P

All other pins

Vcc

P

-0.5 to Vcc+0.5

-0.5 to + 4.0

V

Notes:

1.

2.

No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.

Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#, RESET#

and WP#/ACC pins may undershoot V_ss

below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V_ssto –1.0V for periods of

up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is V_cc+ 0.5

V. During voltage transitions, outputs may overshoot to V_cc+ 1.5 V for periods up to 20ns. See figure below.

Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress

rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the

device to the maximum rating values for extended periods of time may adversely affect the device reliability.

B

to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure

3.

4.

B

RECOMMENDED OPERATING RANGES¹

P

Parameter

Value

Unit

Ambient Operating Temperature

Industrial Devices

℃

-40 to 85

Operating Supply Voltage

Vcc

Full Voltage Range:

2.7 to 3.6V

V

1.

Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+1.5V

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot

Waveform

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

37

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

DC Characteristics

Table 11. DC Characteristics

(T_a= - 40°C to 85°C; V_CC= 2.7-3.6V)

Symbol

Parameter

Input Leakage Current

Test Conditions

0V≤ V ≤ Vcc

Min

Typ

Max

±5

Unit

µA

I

B

LI

IN

Output Leakage Current

Supply Current (read) CMOS Byte

(read) CMOS Word

±5

µA

I

B

0V≤ V

B

≤ Vcc

LO

OUT

9

16

mA

CE# = V

B

; OE# = V

B

IL

f = 5MHZ

IH ;

I

B

CC1

CC2

CC3

B

16

CE# = V , OE# =

B

IL

20

1

30

5.0

mA

µA

B

Supply Current (Program or Erase)

Supply Current (Standby - CMOS)

V

B

, WE# = V

B

IH

IL

CE# = BYTE# =

RESET# = Vcc ± 0.3V

(Note 1)

B

RESET# = Vss ± 0.3V

1

mA

uA

I

B

CC4

Reset Current

V

B

= Vcc ± 0.3V

= Vss ± 0.3V

IH

5.0

0.8

I

B

CC5

Automatic Sleep Mode

Input Low Voltage

Input High Voltage

V

B

IL

-0.5

V

B

IL

0.7 x

Vcc

Vcc ±

0.3

V

B

IH

#WP/ACC Voltage (Write Protect /

Program Acceleration)

Voltage for Autoselect or

10.5

11.5

V

B

HH

11.5

0.45

V

B

ID

Temporary Sector Unprotect

Output Low Voltage

V

B

I

B

= 4.0 mA

OL

Vcc -

0.4V

Output High Voltage CMOS

V

B

I

= -100 μA,

OH

Supply voltage (Erase and

Program lock-out)

V

B

2.3

2.5

V

LKO

Notes:

1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that

they draw power if not at full CMOS supply voltages.

2. Maximum I

B

specifications are tested with Vcc = Vcc max.

CC

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

38

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Test Conditions

Device Under Test

C_L

Test Specifications

Test Conditions

-70

30

-90

100

Unit

pF

ns

Output Load Capacitance, C_L

B

Input Rise and Fall times

Input Pulse Levels

5

0.0-3.0

V

Input timing measurement

reference levels

Output timing measurement

reference levels

1.5

V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

39

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Std

Speed

Unit

Test

Setup

Description

-70

-90

RESET# Pulse Width (During Embedded Algorithms)

RESET# Pulse Width (NOT During Embedded Algorithms)

Reset# High Time Before Read

t_RP1

t_RP2

t_RH

t_RB1

t_RB2

t_READY1

Min

10

500

50

0

us

ns

RY/BY# Recovery Time ( to CE#, OE# go low)

RY/BY# Recovery Time ( to WE# go low)

Reset# Pin Low (During Embedded Algorithms)

to Read or Write

Reset# Pin Low (NOT During Embedded Algorithms)

to Read or Write

50

Max

20

us

ns

t_READY2

500

Figure 1. AC Waveforms for RESET#

Reset# Timings

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

40

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Word / Byte Configuration (BYTE#)

Speed

Unit

Std

Parameter

Description

-70

0

-90

t_BCS

t_CBH

t_RBH

B

BYTE# to CE# switching setup time

CE# to BYTE# switching hold time

RY/BY# to BYTE# switching hold time

Min

0

ns

B

0

B

0

Figure 2. AC Waveforms for BYTE#

CE#

OE#

Byte#

t_CBH

t_BCS

Byte# timings for Read Operations

CE#

WE#

Byte#

t_RBH

t_BCS

RY/BY#

Byte #timings for Write Operations

Note: Switching BYTE# pin not allowed during embedded operations

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

41

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Table 12. Read-only Operations Characteristics

Parameter

Speed Options

Symbols

Test

Description

Setup

JEDEC

Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

t_RC

Read Cycle Time

CE# = V_IL

OE# = V_IL

Max

70

30

20

90

35

20

ns

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ACC

t_CE

t_OE

t_DF

Address to Output Delay

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

Output Enable to Output High Z

OE# = V_IL

t_DF

Output Hold Time from

Addresses, CE# or OE#,

whichever occurs first

Min

0

ns

t_AXQX

t_OH

Read

Min

0

ns

Output Enable

Hold Time

t_OEH

Toggle and

Data# Polling

10

Notes:

1. High Z is Not 100% tested.

2. For - 70

Vcc = 2.7V – 3.6V

Input Rise and Fall Times: 5ns

Timing Measurement Reference Level, Input and Output: 1.5 V

Vcc = 2.7V – 3.6V Output Load: 100 pF

Output Load: 30pF

Input Pulse Levels: 0.0 V to 3.0 V

-90:

Input Rise and Fall Times: 5 ns Input Pulse Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level, Input and Output: 1.5 V

Figure 3. AC Waveforms for READ Operations

t_RC

Addresses

Addresses Stable

t_ACC

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

42

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Table 13. Write (Erase/Program) Operations

Parameter

Speed Options

Symbols

Description

JEDEC

Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

B

t_WC

B

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

0

ns

t_AVWL

B

t_AS

B

45

30

45

40

t_WLAX

B

t_AH

B

t_DVWH

B

t_DS

B

Min

0

ns

t_WHDX

B

t_DH

t_OES

t_GHWL

t_CS

t_CH

t_WP

t_WPH

B

Data Hold Time

B

Output Enable Setup Time

Read Recovery Time before Write (OE# High

to WE# Low)

t_GHWL

B

CE# Setup Time

CE# Hold Time

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

B

45

20

45

25

B

Write Pulse Width

B

Write Pulse Width High

Byte

Typ

8

Programming Operation

(Note 2)

µs

t_WHW1

B

t_WHWH1

B

Word

Accelerated Programming Operation

(Word AND Byte Mode) (Note 2)

Typ

7

t_WHW1

B

t_WHWH1

B

Typ

Min

Max

0.1

16

250

50

0

0.1

16

250

50

0

s

Erase Operation

(Note 2)

Sector

Chip

t_WHW2

B

t_WHWH2

B

s

ns

µs

ns

t_VHH

t_VCS

t_RB

t_BUSY

V_HHRise and Fall Time

Vcc Setup Time

B

Recovery Time from RY/BY#

WE# High to RY/BY# Low

70

90

B

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

43

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Table 14. Write (Erase/Program) Operations

Alternate CE# Controlled Writes

Parameter

Speed Options

Symbols

Description

JEDEC Standard

-70

-90

Unit

Min

70

90

ns

t_AVAV

B

t_WC

B

Write Cycle Time (Note 1)

0

45

30

0

45

40

0

ns

t_AVEL

B

t_AS

B

Address Setup Time

Address Hold Time

Data Setup Time

t_ELAX

B

t_AH

B

t_DVEH

B

t_DS

B

t_EHDX

B

t_DH

t_OES

t_GHEL

t_WS

t_WH

t_CP

t_CPH

B

Data Hold Time

0

B

Output Enable Setup Time

Read Recovery Time before Write (OE# High

to CE# Low)

Min

Typ

0

ns

t_GHEL

B

t_WLEL

t_EHWH

t_ELEH

t_EHEL

B

WE# Setup Time

WE# Hold Time

0

B

35

20

8

45

20

8

B

CE# Pulse Width

CE# Pulse Width High

B

Programming Operation

(Note 2)

Byte

µs

t_WHW1

B

t_WHWH1

B

8

Word

Accelerated Programming Operation

(Word AND Byte Mode) (Note 2)

Typ

7

t_WHW1

B

t_WHWH1

B

Typ

Min

0.1

16

0

0.1

16

0

s

Erase Operation

(Note 2)

Sector

Chip

t_WHW2

B

t_WHWH2

B

ns

t_RB

Recovery Time from RY/BY#

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

44

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings

Erase Command Sequence (last 2 cycles)

Read Status Data (last two cycles)

t_AS

SA

t_AH

t_WC

Addresses

CE#

0x2AA

VA

0x555 for chip

erase

t_GHW

L

t_CH

OE#

WE#

t_WP

t_WPH

t_CS

t_WHWH2

Data

0x55

t_DS

0x30

Status

D_OUT

t_RB

10 for chip

erase

t_DH

t_BUSY

RY/BY#

V_CC

t_VCS

Notes:

1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, D_out

2. V_ccshown only to illustrate t_vcsmeasurement references. It cannot occur as shown during a valid command

sequence.

B

=true data at read address.

B

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

45

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Figure 5. Program Operation Timings

Program Command Sequence (last 2 cycles)

t_AS

PA

t_AH

t_WC

Addresses

CE#

0x555

PA

t_GHWL

t_CH

OE#

WE#

t_WP

t_WPH

t_WHWH1

t_CS

Data

D_OUT

t_RB

OxA0

Status

PD

t_DS

t_DH

t_BUSY

RY/BY#

V_CC

t_VCS

Notes:

1. PA=Program Address, PD=Program Data, D_OUT

2. V_CCshown in order to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid

command sequence.

B

is the true data at the program address.

B

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

46

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

t_RC

Addresses

CE#

VA

t_ACC

VA

t_CH

t_CE

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Comple

-ment

Valid Data

Complement

Status Data

True

DQ[7]

Status

Data

True

DQ[6:0]

t_BUSY

RY/BY#

Notes:

1. VA=Valid Address for reading Data# Polling status data

2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.

Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

t_RC

Addresses

CE#

VA

t_CH

t_ACC

t_CE

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Valid Data

Valid Status

(first read)

Valid Status

DQ6, DQ2

RY/BY#

t_BUSY

(second read)

(stops toggling)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

47

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Figure 8. Alternate CE# Controlled Write Operation Timings

PA for Program

SA for Sector Erase

0x555 for Program

0x2AA for Erase

0x555 for Chip Erase

Addresses

WE#

VA

t_WC

t_AS

t_AH

t_WH

t_GHEL

OE#

CE#

Data

t_CP

t_CPH

t_WHWH1/ t_WHWH2

t_WS

t_BUSY

t_DH

t_DS

Status

D_OUT

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

0xA0 for

Program

0x55 for Erase

RY/BY

t_RH

Reset#

Notes:

PA = address of the memory location to be programmed.

PD = data to be programmed at byte address.

VA = Valid Address for reading program or erase status

D_out

B

= array data read at VA

Shown above are the last two cycles of the program or erase command sequence and the last status read cycle

RESETt# shown to illustrate t_RH

B

measurement references. It cannot occur as shown during a valid command

sequence.

Figure 9. DQ2 vs. DQ6

Enter

Embedded

Erase

Enter Erase

Suspend

Program

Erase

Suspend

Erase

Resume

WE#

Erase

Enter

Suspend

Read

Enter

Suspend

Program

Erase

Suspend

Read

Erase

Complete

Erase

DQ6

DQ2

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

48

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Temporary Sector Unprotect

Speed Option

-70 -90

Unit

Parameter

Description

Std

t_VIDR

t_VIHH

B

V_ID

B

Rise and Fall Time

Min

500

ns

B

V_HH

B

RESET# Setup Time for Temporary

Sector Unprotect

t_RSP

B

Min

4

µs

Notes: t_RSPis Not 100% tested.

Figure 10. Temporary Sector Unprotect Timing Diagram

V_ID

RESET#

0 or 3 V

t_VIDR

CE#

WE#

t_RSP

RY/BY#

AC CHARACTERISTICS

Write Protect / Accelerated Program

Figure 11. Accelerated Program Timing Diagram

V_HH

WP#/ACC

0 or 3 V

t_VHH

CE#

WE#

t_RSP

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

49

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

AC CHARACTERISTICS

Sector (Group) Protect and Chip Unprotect

Figure 12. Sector (Group) Protect and Chip Unprotect Timing Diagram

V_ID

Vcc

RESET#

0V

t_VIDR

SA,

A6,A1,A0

Valid

60h

Valid

Data

60h

40h

Status

Sector Protect/Unprotect

Verify

CE#

>0.4μS

WE#

>1μS

Protect: 150 uS

Unprotect: 15 mS

OE#

Notes:

Use standard microprocessor timings for this device for read and write cycles.

For Sector (Group) Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

50

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

ERASE AND PROGRAM PERFORMANCE

Limits

Max

Parameter

Sector Erase Time

Comments

Typ

Unit

0.1

2

sec

Excludes 00h programming prior to

erasure

Chip Erase Time

16

8

140

200

sec

µs

Byte Programming Time

Word Programming Time

Accelerated Byte/Word Program Time

8

200

µs

Excludes system level overhead

Minimum 100K cycles

7

120

µs

Byte

Chip Programming Time

Word

67.2

201.6

100.8

sec

33.6

sec

Erase/Program Endurance

100K

Cycles

Note: Typical Conditions are room temperature, 3V and checkboard pattern programmed.

48-PIN TSOP PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

B

V

IN

Input Capacitance

6

7.5

pF

C

B

V

= 0

OUT

Output Capacitance

8.5

7.5

12

9

pF

C

B

V

= 0

IN2

IN

Control Pin Capacitance

Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C

10

Years

Pattern Data Retention Time

125°C

20

Years

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

51

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

FIGURE 13. 48L TSOP 12mm x 20mm package outline

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

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52

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

FIGURE 14. 48L TFBGA 6mm x 8mm package outline

DIMENSION IN MM

SYMBOL

MIN.

- - -

NOR

- - -

MAX

A

A1

A2

D

1.30

- - -

0.23

0.84

7.90

5.90

- - -

0.29

0.91

8.00

6.00

5.60

4.00

0.80

0.40

- - -

8.10

6.10

- - -

E

D1

E1

e

- - -

b

0.35

0.45

Note : 1. Coplanarity: 0.1 mm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

53

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

FIGURE 15. 64L TFBGA 11mm x 13mm package outline

DIMENSION IN MM

SYMBOL

MIN.

- - -

NOR

- - -

MAX

A

A1

A2

D

1.40

0.60

- - -

0.70

0.40

0.60

- - -

11.00

13.00

7.00

1.00

0.60

E

- - -

D1

E1

e

- - -

b

0.50

Note : 1. Coplanarity: 0.1 mm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

54

Rev. G, Issue Date: 2009/03/30

EN29LV640T/B

Revisions List

Revision No Description

Date

A

Initial Release

2007/3/13

1. Move the feature of SECURED SILICON SECTOR.

2. Change the notes for 70 ns products from Vcc = 2.7V – 3.6V to Vcc =

3.0V – 3.6V at Table 12. Read-only Operations Characteristics on

page 40.

1. Add the t_BUSYdescription in Table 13. Write (Erase/Program)

Operations on page 41.

2. Correct the Figure 5. Program Operation Timings on page 44.

3. Update 48 pin TSOP-I package outline on page 50.

4. Correct the 48 Ball package thickness from 1.2 mm to 1.3 mm on

page 51.

B

2007/05/16

2008/06/17

C

5. Remove C grade option of temperature range on page 1 and page 4.

1. Add the 64 Ball TFBGA package and connection diagrams information

on page 1, 3, 5 and 53.

D

E

2. Delete t_OESin page 41.

3. Modify AC Waveforms for READ Operations on page 41.

4. Add t_RBon page 42, 43.

2008/08/27

2009/01/09

1. Add Eon products’ New top marking “cFeon“ information on page 1.

2. Modify Table 8 addresses 4Eh data from 00B5h to 00C5h on page 23.

1. Update Erase and Program performance on page 2 and 51.

2. Modify P = Pb free to P = RoHS compliant on page 6.

3. Remove Unlock Bypass, Unlock Bypass Program, and Unlock

Bypass Reset commands from Table 9 on page 25.

4. Remove description of Unlock Bypass from version E.

5. Modify Table 10 Status Register Bits DQ5 from ERROE BIT to TIME

OUT BIT on page 31.

6. Modify Storage Temperature from "-65 to + 125" to "-65 to +150" on

page 37

7. Modify I_OHfrom -100mA to -100μA on page 38

8. Modify Test Conditions illustration on page 39.

9. Update Hardware Reset (RESET#) table and Figure 1. AC

Waveforms for RESET# on page 40

F

2009/03/13

10. Update Table 13. Write (Erase/Program) Operations on page 43.

11. Update Table 14. Write (Erase/Program) Operations on page 44

12. Update Figure 4. AC Waveforms for Chip/Sector Erase Operations

Timings on page 45

13. Update Figure 8. Alternate CE# Controlled Write Operation Timings

on page 48

14. Remove the Latch up Characteristics Table from version E.

G

2009/03/30

1. Correct typo in Table 13, “ t_BUSY“ from Min. to Max on page 43.

B

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. G, Issue Date: 2009/03/30

www.eonssi.com

55


型号：	EN29P640B-70TIP
厂家：	EON SILICON SOLUTION INC.
描述：	64 Megabit (8M x 8-bit / 4M x 16-bit) Flash Memory 64兆位（ 8M ×8位/ 4M ×16位）闪存闪存
文件：	总55页 (文件大小：570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EN29P640B-70TIP [EON]

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