EN39LV010-70NIP_技术文档

EN39LV010

1 Megabit (128K x 8-bit ) 4 Kbyte Uniform Sector,

CMOS 3.0 Volt-only Flash Memory

FEATURES

• Single power supply operation

• High performance program/erase speed

- Byte program time: 8µs typical

- Sector erase time: 90ms typical

- Full voltage range: 2.7-3.6 volt read and write

operations for battery-powered applications.

- Regulated voltage range: 3.0-3.6 volt read

and write operations for high performance

3.3 volt microprocessors.

• JEDEC Standard program and erase

commands

• JEDEC standard

feature

polling and toggle bits

DATA

• High performance

- Full voltage range: access times as fast as 70

ns

• Single Sector and Chip Erase

- Regulated voltage range: access times as fast

as 45ns

• Embedded Erase and Program Algorithms

• Erase Suspend / Resume modes:

Read or program another Sector during

Erase Suspend Mode

• Low power consumption (typical values at 5

MHz)

- 7 mA typical active read current

- 15 mA typical program/erase current

- 1 µA typical standby current (standard access

time to active mode)

• triple-metal double-poly triple-well CMOS Flash

Technology

• Low Vcc write inhibit < 2.5V

• Flexible Sector Architecture:

- Thirty-two 4 Kbyte sectors

• Minimum 100K program/erase endurance

cycles

• Sector protection:

• Package options

Hardware locking of sectors to prevent

program or erase operations within individual

sectors

- 4mm x 6mm 34-ball WFBGA

- 8mm x 14mm 32-pin TSOP (Type 1)

- 32-pin PLCC

• Industrial Temperature Range

GENERAL DESCRIPTION

The EN39LV010 is a 1-Megabit, electrically erasable, read/write non-volatile flash memory, organized

as 131,072 bytes. Any byte can be programmed typically in 8µs.The EN39LV010 features 3.0V

voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT

states in high-performance microprocessor systems.

The EN39LV010 has separate Output Enable (

), Chip Enable (

), and Write Enable (WE)

CE

OE

controls, which eliminate bus contention issues. This device is designed to allow either single Sector

or full chip erase operation, where each Sector can be individually protected against program/erase

operations or temporarily unprotected to erase or program. The device can sustain a minimum of

100K program/erase cycles on each Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

1

Rev. B, Issue Date: 2009/03/16

EN39LV010

CONNECTION DIAGRAMS

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

2

Rev. B, Issue Date: 2009/03/16

EN39LV010

TABLE 1. PIN DESCRIPTION

FIGURE 1. LOGIC DIAGRAM

EN39LV010

Pin Name

A0-A16

DQ0-DQ7

WE#

Function

Addresses

DQ0 – DQ7

A0 - A16

8 Data Inputs/Outputs

Write Enable

Chip Enable

CE#

OE#

Output Enable

Supply Voltage

Ground

Vcc

WE#

Vss

TABLE 2. UNIFORM SECTOR ARCHITECTURE

Sector

Address range

SIZE (Kbytes)

01F000h

01E000h

01D000h

01C000h

01B000h

01A000h

019000h

018000h

017000h

016000h

015000h

014000h

013000h

012000h

011000h

010000h

00F000h

00E000h

00D000h

00C000h

00B000h

00A000h

009000h

008000h

007000h

006000h

005000h

004000h

003000h

002000h

001000h

000000h

01FFFFh

01EFFFh

01DFFFh

01CFFFh

01BFFFh

01AFFFh

019FFFh

018FFFh

017FFFh

016FFFh

015FFFh

014FFFh

013FFFh

012FFFh

011FFFh

010FFFh

00FFFFh

00EFFFh

00DFFFh

00CFFFh

00BFFFh

00AFFFh

009FFFh

008FFFh

007FFFh

006FFFh

005FFFh

004FFFh

003FFFh

002FFFh

001FFFh

000FFFh

4

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

3

Rev. B, Issue Date: 2009/03/16

EN39LV010

PRODUCT SELECTOR GUIDE

Product Number

EN39LV010

Regulated Voltage Range: Vcc=3.0-3.6 V

Full Voltage Range: Vcc=2.7 – 3.6 V

-45R

Speed Option

-70

Max Access Time, ns (t_acc

Max CE# Access, ns (t_ce)

Max OE# Access, ns (t_oe)

)

45

25

70

30

BLOCK DIAGRAM

DQ0-DQ7

Vcc

Vss

Block Protect Switches

Erase Voltage Generator

Input/Output Buffers

State

Control

WE#

Program Voltage

Generator

Command

Register

STB

Chip Enable

Output Enable

Data Latch

CE#

OE#

Logic

Y-Decoder

Y-Gating

STB

Vcc Detector

A0-A16

Timer

X-Decoder

Cell Matrix

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

4

Rev. B, Issue Date: 2009/03/16

EN39LV010

TABLE 3. OPERATING MODES

1M FLASH USER MODE TABLE

Operation

CE#

OE#

WE#

A0-A16

DQ0-DQ7

Read

Write

CMOS Standby

Output Disable

L

H

X

H

L

X

H

A_IN

X

D_OUT

D_IN

High-Z

L

V_cc± 0.3V

L

X

Sector address,

A6=L, A1=H, A0=L

Sector address,

A6=H, A1=H, A0=L

Sector Protect²

Sector

L

H

L

D_IN, D_OUT

Unprotect²

Notes:

1. L=logic low= V_IL, H=Logic High= V_IH, V_ID=11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),

D_IN=Data In, D_OUT=Data Out, A_IN=Address In

2. Sector protection/unprotection can be implemented by programming equipment.

TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)

1M FLASH MANUFACTURER/DEVICE ID TABLE

A16 A13

to to

A14 A10

A5

to

A2

Description

CE# OE# WE#

A9²A8 A7 A6

H¹

A1 A0

DQ7 to DQ0

1Ch

7Fh

Manufacturer

ID: Eon

L

H

X

V_ID

X

L

X

L

Device ID

V_ID

X

L

H

D5h

01h

Sector

Protection

Verification

(Protected)

L

H

SA

X

V_ID

X

L

X

H

L

00h

(Unprotected)

Note:

1. A8=H is recommended for manufacture ID check. If a manufacture ID is read with A8=L, the chip will output a

configuration code 7Fh.

2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

5

Rev. B, Issue Date: 2009/03/16

EN39LV010

USER MODE DEFINITIONS

Standby Mode

The EN39LV010 has a CMOS-compatible standby mode, which reduces the current to < 1µA

(typical). It is placed in CMOS-compatible standby when the

pin is at V_CC± 0.3. When in standby

CE

modes, the outputs are in a high-impedance state independent of the

input.

OE

Read Mode

The device is automatically set to reading array data after device power-up. No commands are required to

retrieve data. The device is also ready to read array data after completing an Embedded Program or

Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The

system can read array data using the standard read timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status data. After completing a programming operation in

the Erase Suspend mode, the system may once again read array data with the same exception. See

“Erase Suspend/Erase Resume Commands” for more additional information.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset Command” additional details.

Output Disable Mode

When the

or

pin is at a logic high level (V_IH), the output from the EN39LV010 is disabled.

OE

CE

The output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection

verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for

programming equipment to automatically match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can also be accessed in-system through the

command register.

When using programming equipment, the autoselect mode requires V_ID(11 V) on address pin A9.

Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when

verifying sector protection, the sector address must appear on the appropriate highest order address

bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the

remaining address bits that are don’t-care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via

the command register, as shown in the Command Definitions table. This method does not require V_ID.

See “Command Definitions” for details on using the autoselect mode.

Write Mode

Write operations, including programming data and erasing sectors of memory, require the host

system to write a command or command sequence to the device. Write cycles are initiated by

placing the byte or word address on the device’s address inputs while the data to be written is input

on DQ[7:0]. The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid

write operation to take place. All addresses are latched on the falling edge of WE# and CE#,

whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens

first. The system is not required to provide further controls or timings. The device automatically

provides internally generated program / erase pulses and verifies the programmed /erased cells’

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

6

Rev. B, Issue Date: 2009/03/16

EN39LV010

margin. The host system can detect completion of a program or erase operation by reading the DQ[7]

(Data# Polling) and DQ[6] (Toggle) status bits.

The ‘Command Definitions’ section of this document provides details on the specific device

commands implemented in the EN39LV010.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The

hardware sector unprotection feature re-enables both program and erase operations in previously

protected sectors.

Sector protection/unprotection is intended only for programming equipment. This method requires

V

be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This

ID

method is described in a separate document called EN39LV010 Supplement, which can be obtained

by contacting a representative of Eon Silicon Solution, Inc.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically

enables this mode when addresses remain stable for t_acc+ 30ns. The automatic sleep mode is

independent of the CE#, WE# and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output is latched and always available

to the system. ICC₄in the DC Characteristics table represents the automatic sleep more current

specification.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

7

Rev. B, Issue Date: 2009/03/16

EN39LV010

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes as seen in the Command Definitions table. Additionally, the

following hardware data protection measures prevent accidental erasure or programming, which

might otherwise be caused by false system level signals during Vcc power up and power down

transitions, or from system noise.

Low V_CCWrite Inhibit

When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during

Vcc power up and power down. The command register and all internal program/erase circuits are

disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The

system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is

greater than V_LKO

.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on

Logical Inhibit

,

or

do not initiate a write cycle.

W E

OE CE

Write cycles are inhibited by holding any one of

= VIL,

= VIH, or

= VIH. To initiate a

W E

OE

CE

write cycle,

and

must be a logical zero while

is a logical one. If

,

, and

W E

are

OE

CE

OE

CE

W E

all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even

with

W E

= V ,

= V_ILand

= V_IH, the device will not accept commands on the rising edge of

OE

CE

.

WE

IL

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

8

Rev. B, Issue Date: 2009/03/16

EN39LV010

COMMAND DEFINITIONS

The operations of the EN39LV010 are selected by one or more commands written into the

command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,

Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data

sequences written at specific addresses via the command register. The sequences for the

specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses,

incorrect data values or improper sequences will reset the device to Read Mode.

Table 5. EN39LV010 Command Definitions

Bus Cycles

1^st

Cycle

2^nd

Cycle

3^rd

Cycle

4^th

Cycle

5^th

Cycle

6^th

Cycle

Command

Sequence

Add

Data Add

Data

Add

Data Add

Data

Read

Reset

1

RA

Xxx

RD

F0

000

100

7F

1C

Manufacturer ID

Device ID

4

555

AA

2AA 55

555

90

4

AA

X01 D5

(SA) 00/

X02 01

Sector Protect Verify

4

555

AA

2AA 55

555

90

Program

4

6

555

AA

2AA 55

555

A0

80

PA

PD

AA

Chip Erase

555

2AA 55

555

SA

10

30

Sector Erase

Erase Suspend

Erase Resume

1

xxx

B0

30

Address and Data values indicated in hex

RA = Read Address: address of the memory location to be read. This is a read cycle.

RD = Read Data: data read from location RA during Read operation. This is a read cycle.

PA = Program Address: address of the memory location to be programmed. X = Don’t-Care

PD = Program Data: data to be programmed at location PA

SA = Sector Address: address of the Sector to be erased or verified. Address bits A16-A12 uniquely select any Sector.

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to

retrieve data. The device is also ready to read array data after completing an Embedded Program or

Embedded Erase algorithm.

Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data

using the standard read timings, with the only difference in that if it reads at an address within erase

suspended sectors, the device outputs status data. After completing a programming operation in the

Erase Suspend mode, the system may once again read array data with the same exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or

while in the autoselect mode. See next section for details on Reset.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

9

Rev. B, Issue Date: 2009/03/16

EN39LV010

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected. The Command Definitions table shows the

address and data requirements. This is an alternative to the method that requires V_IDon address bit A9

and is intended for PROM programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of

times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Programming Command

Programming the EN39LV010 is performed by using a four bus-cycle operation (two unlock write

cycles followed by the Program Setup command and Program Data Write cycle). When the program

command is executed, no additional CPU controls or timings are necessary. An internal timer

terminates the program operation automatically. Address is latched on the falling edge of

or

,

W E

CE

whichever is last; data is latched on the rising edge of

or

, whichever is first.

W E

CE

Programming status may be checked by sampling data on DQ7 (

polling) or on DQ6 (toggle

DATA

bit). ). When the program operation is successfully completed, the device returns to read mode and

the user can read the data programmed to the device at that address. Note that data can not be

programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When

programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return

the device to Read mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations. The Command Definitions table shows the

address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by

the address of the sector to be erased, and the sector erase command. The Command Definitions table

shows the address and data requirements for the sector erase command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

10

Rev. B, Issue Date: 2009/03/16

EN39LV010

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or

DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the

algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing

waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for erasure. This command is valid only during the

sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation

or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”

for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more

information. The Autoselect command is not supported during Erase Suspend Mode.

The system must write the Erase Resume command (address bits are don’t-care) to exit the erase

suspend mode and continue the sector erase operation. Further writes of the Resume command are

ignored. Another Erase Suspend command can be written after the device has resumed erasing.

WRITE OPERATION STATUS

DQ7: DATA Polling

The EN39LV010 provides

Polling on DQ7 to indicate to the host system the status of the

DATA

embedded operations. The

Polling feature is active during the embedded Programming,

DATA

Sector Erase, Chip Erase, Erase Suspend. (See Table 6)

When the embedded Programming is in progress, an attempt to read the device will produce the

complement of the data last written to DQ7. Upon the completion of the embedded Programming, an

attempt to read the device will produce the true data last written to DQ7. For the embedded

Programming,

DATA

cycle sequence.

polling is valid after the rising edge of the fourth

or

WE

pulse in the four-

CE

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the

DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read. For Chip Erase, the

polling is valid after the rising edge of the sixth

DATA

pulse in the six-cycle sequence. For Sector Erase, polling is valid after the last

DATA

or

W E

CE

rising edge of the sector erase

or

pulse.

C E

W E

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

11

Rev. B, Issue Date: 2009/03/16

EN39LV010

Polling must be performed at any address within a sector that is being programmed or erased

DATA

and not a protected sector. Otherwise,

polling may give an inaccurate result if the address

DATA

used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the

output enable ( ) is low. This means that the device is driving status information on DQ7 at one

OE

instant of time and valid data at the next instant of time. Depending on when the system samples the

DQ7 output, it may read the status of valid data. Even if the device has completed the embedded

operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid

data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for

Polling (DQ7) is shown on Flowchart 5. The

Polling (DQ7) timing

DATA

diagram is shown in Figure 8.

DQ6: Toggle Bit I

The EN39LV010 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the

embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device

at any address (by toggling

or

) will result in DQ6 toggling between “zero” and “one”. Once

CE

OE

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be

read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth

pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid

WE

after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the

last rising edge of the Sector Erase pulse.

W E

In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then

stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read

mode without changing data in all protected blocks.

Toggling either

or

will cause DQ6 to toggle.

OE

CE

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is

shown in Figure 9

.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or

erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the

device has successfully completed its operation and has returned to read mode, the user must check

again to see if the DQ6 is toggling after detecting a “1” on DQ5.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is

previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under

this condition, the device halts the operation, and when the operation has exceeded the timing limits,

DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to

return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be used to determine

whether or not an erase operation has begun. (The sector erase timer does not apply to the chip

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

12

Rev. B, Issue Date: 2009/03/16

EN39LV010

erase command.) When sector erase starts, DQ3 switches from “0” to “1.” This device does not

support multiple sector erase command sequences so it is not very meaningful since it immediately

shows as a “1” after the first 30h command. Future devices may support this feature.

DQ2: Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively

erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-

suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command

sequence. DQ2 toggles when the system reads at addresses within those sectors that have been

selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2

cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison,

indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits are required for sector and mode information.

Refer to Table 5 to compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.

See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical

form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, a system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read

cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, the system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Flowchart 6).

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

13

Rev. B, Issue Date: 2009/03/16

EN39LV010

Write Operation Status

Operation

DQ7

DQ6

DQ5

DQ3

DQ2

Embedded Program

No

toggle

DQ7#

Toggle

0

N/A

1

Standard

Mode

Algorithm

Embedded Erase Algorithm

0

1

Toggle

Reading within Erase

Suspended Sector

Reading within Non-Erase

Suspended Sector

No

Toggle

N/A

Toggle

Erase

Suspend

Mode

Data

0

Data

N/A

Data

N/A

Erase-Suspend Program

DQ7#

Toggle

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

14

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 6. Status Register Bits

DQ

Name

Logic Level

Definition

Erase Complete or

erase Sector in Erase

suspend

‘1’

‘0’

Erase On-Going

DATA

POLLING

7

Program Complete or

data of non-erase Sector

during Erase Suspend

DQ7

‘-1-0-1-0-1-0-1-’

DQ6

Program On-Going

Erase or Program On-going

Read during Erase Suspend

TOGGLE

BIT

6

Erase Complete

‘-1-1-1-1-1-1-1-‘

‘1’

‘0’

‘1’

‘0’

Program or Erase Error

Program or Erase On-going

Erase operation start

5

3

TIME OUT BIT

ERASE

TIME BIT

Erase timeout period on-going

Chip Erase, Sector Erase or

Read within Erase-Suspended

sector. (When DQ5=1, Erase

‘-1-0-1-0-1-0-1-’

DQ2

Error

due

to

currently

TOGGLE

BIT

2

addressed Sector or Program

on Erase-Suspended sector)

Read on addresses of non

Erase-Suspend sectors

Notes:

DQ7

Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5

DATA

for Program or Erase Success.

DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.

Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5: Time Out Bit: set to “1” if failure in programming or erase

DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

15

Rev. B, Issue Date: 2009/03/16

EN39LV010

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data Poll Device

Verify Data?

Last

Increment

Address

No

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

555H/AAH

2AAH/55H

555H/A0H

PROGRAM ADDRESS / PROGRAM DATA

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

16

Rev. B, Issue Date: 2009/03/16

EN39LV010

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

Data Poll from

System or Toggle Bit

successfully

completed

Data =FFh?

No

Yes

Erase Done

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

17

Rev. B, Issue Date: 2009/03/16

EN39LV010

Flowchart 4. Embedded Erase Command Sequence

Chip Erase

555H/AAH

Sector Erase

555H/AAH

2AAH/55H

555H/80H

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

Sector Address/30H

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

18

Rev. B, Issue Date: 2009/03/16

EN39LV010

Flowchart 5. DATA Polling

Algorithm

Start

Read Data

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data (1)

Notes:

Yes

(1) This second read is necessary in case the

first read was done at the exact instant when

the status data was in transition.

DQ7 = Data?

No

Fail

Pass

Start

Flowchart 6. Toggle Bit Algorithm

Read Data twice

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data twice (2)

Notes:

No

(2) This second set of reads is necessary in case

the first set of reads was done at the exact

instant when the status data was in transition.

DQ6 = Toggle?

Yes

Fail

Pass

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

19

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 7. DC Characteristics

(T_a= - 40°C to 85°C; V_CC= 2.7-3.6V)

Symbol

Parameter

Test Conditions

Min

Max

Unit

Typ

Input Leakage Current

Output Leakage Current

±1

µA

I

0V≤ V ≤ Vcc

IN

LI

I

0V≤ V

≤ Vcc

OUT

LO

CE# = V ; OE# = V

IL

;

IH

Supply Current (read)CMOS

Supply Current (Standby - CMOS)

Supply Current (Program or Erase)

7

12

mA

I

CC1

f = 5MHz

CE# = Vcc ± 0.3V

1

15

1

5.0

30

µA

mA

µA

I

CC2

CC3

CC4

Byte program, Sector or

Chip Erase in progress

V

= Vcc ± 0.3 V

= Vss ± 0.3 V

IH

5.0

0.8

Automatic Sleep Mode

Input Low Voltage

Input High Voltage

Output Low Voltage

V

IL

-0.5

V

IL

0.7 x

Vcc

Vcc ±

0.3

V

IH

0.45

V

I

= 4.0 mA

OL

Vcc -

0.4V

Output High Voltage CMOS

V

I

= -100 µA,

OH

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

10.5

11.5

100

V

ID

A9 = V_ID

µA

I

ID

Supply voltage (Erase and

Program lock-out)

V

LKO

2.3

2.5

V

Notes:

1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that

they draw power if not at full CMOS supply voltages.

2. Maximum

I

specifications are tested with Vcc

=

Vcc max.

CC

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

20

Rev. B, Issue Date: 2009/03/16

EN39LV010

Test Conditions

Test Specifications

Test Conditions

Output Load Capacitance, C_L

Input Rise and Fall times

Input Pulse Levels

-45R

30

-70

100

Unit

pF

ns

5

0.0-3.0

V

Input timing measurement

reference levels

Output timing measurement

reference levels

1.5

V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

21

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 8. AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbols

Speed Options

Test

Description

Setup

JEDEC

Standard

-45R

-70

Unit

Min

45

70

ns

Read Cycle Time

t_AVAV

t_RC

Max

45

70

ns

Address to Output Delay

t_AVQV

t_ACC

= V_IL

CE

OE

= V

IL

Max

Min

45

25

10

0

70

30

20

0

ns

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_AXQX

t_CE

t_OE

t_DF

t_OH

= V

OE

IL

Output Enable to Output High Z

Output Hold Time from

Addresses,

whichever occurs first

or ,

CE OE

Notes:

For -45R,

Vcc = 3.0V ~3.6V

Output Load : 30pF

Input Rise and Fall Times: 5ns

Input Rise Levels: 0.0 V to Vcc

Timing Measurement Reference Level, Input and Output: 1.5 V

For -70,

Vcc = 2.7V~3.6V

Output Load: 100 pF

Input Rise and Fall Times: 5 ns

Input Pulse Levels: 0.0 V to Vcc

Timing Measurement Reference Level, Input and Output: 1.5 V

Figure 5. AC Waveforms for READ Operations

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

22

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 9. AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter

Symbols

Speed Options

Description

JEDEC

Standard

-45R

-70

Unit

Min

45

70

ns

t_AVAV

t_WC

Write Cycle Time

0

35

20

0

45

30

0

ns

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_AS

t_AH

Address Setup Time

Address Hold Time

Data Setup Time

t_DS

t_DH

t_OES

Data Hold Time

Min

MIn

Min

0

ns

Output Enable Setup Time

Read

Output Enable

Toggle and

t_OEH

Hold Time

10

Polling

DATA

Read Recovery Time before

Min

0

ns

t_GHWL

Write (

High to

Low)

W E

OE

CE

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

t_WP

t_WPH

SetupTime

Hold Time

CE

25

20

35

20

Write Pulse Width

Write Pulse Width High

Typ

8

µs

Programming Operation

t_WHWH1t_WHWH1

Max

Typ

Max

Min

20

0.09

0.5

50

20

0.09

0.5

50

µs

s

t_WHWH2t_WHWH2

Sector Erase Operation

Vcc Setup Time

s

µs

t_VCS

Min

500

ns

t_VIDR

Rise Time to V

ID

Notes: t_WCis Not 100% tested.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

23

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 10. AC CHARACTERISTICS

Write (Erase/Program) Operations

^AlternateCE ^{Controlled Writes}

Parameter

Symbols

Speed Options

Description

Write Cycle Time

JEDEC

t_AVAV

t_AVEL

Standard

-45R

-70

Unit

Min

45

70

ns

t_WC

0

35

20

0

45

30

0

ns

t_AS

Address Setup Time

Address Hold Time

Data Setup Time

t_ELAX

t_DVEH

t_EHDX

t_AH

t_DS

t_DH

Data Hold Time

0

t_OES

Output Enable Setup Time

Min

0

ns

Read

Output Enable

Toggle and

Hold Time

t_OEH

10

Data Polling

Read Recovery Time before

Min

0

ns

t_GHEL

Write (

High to

Low)

CE

OE

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

SetupTime

Hold Time

W E

Min

Typ

Max

Typ

Max

Min

0

25

20

8

0

35

20

8

ns

µs

s

Write Pulse Width

t_CPH

Write Pulse Width High

Programming Operation

t_WHWH1t_WHWH1

t_WHWH2t_WHWH2

20

0.09

0.5

50

20

0.09

0.5

50

Sector Erase Operation

Vcc Setup Time

s

µs

t_VCS

Min

500

ns

t_VIDR

Rise Time to V

ID

Notes: t_WCis Not 100% tested.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

24

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Limits

Max

Parameter

Comments

Typ

Unit

Sector Erase Time

Chip Erase Time

0.09

0.5

sec

Excludes 00H programming prior

to erasure

3

8

15

20

sec

µs

Byte Programming Time

Chip Programming Time

Excludes system level overhead

Minimum 100K cycles

0.8

2

sec

Erase/Program Endurance

100K

cycles

Notes:

1. Typical program and erase times assume the following conditions: room temperature, 3V and checkboard

pattern programmed.

2. Maximum program and erase times assume the following conditions: worst case Vcc, 90 C and 100,000

cycles.

Table 12. DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C

10

Years

Data Retention Time

125°C

20

Years

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

25

Rev. B, Issue Date: 2009/03/16

EN39LV010

Table 13. TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

V

IN

Input Capacitance

6

7.5

pF

C

V

= 0

OUT

V = 0

IN

Output Capacitance

8.5

7.5

12

9

pF

C

IN2

Control Pin Capacitance

Table 14. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

V

IN

Input Capacitance

4

6

pF

C

V

= 0

OUT

Output Capacitance

8

12

C

IN2

V

= 0

IN

Control Pin Capacitance

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

26

Rev. B, Issue Date: 2009/03/16

EN39LV010

AC CHARACTERISTICS

Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings

Figure 7. Program Operation Timings

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

27

Rev. B, Issue Date: 2009/03/16

EN39LV010

Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm

Operations

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

28

Rev. B, Issue Date: 2009/03/16

EN39LV010

Figure 10. Alternate CE# Controlled Write Operation Timings

Figure 11. DQ2 vs. DQ6

Enter

Embedded

Erase

Enter Erase

Suspend

Program

Erase

Suspend

Erase

Resume

WE#

Erase

Enter

Suspend

Read

Enter

Suspend

Program

Erase

Suspend

Read

Erase

Complete

Erase

DQ6

DQ2

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

29

Rev. B, Issue Date: 2009/03/16

EN39LV010

ABSOLUTE MAXIMUM RATINGS

Parameter

Value

Unit

Storage Temperature

-65 to +150

°C

Plastic Packages

-65 to +125

-55 to +125

°C

Ambient Temperature

With Power Applied

Output Short Circuit Current¹

200

mA

V

A9 and OE# ²

-0.5 to +11.5

-0.5 to Vcc+0.5

Voltage with

Respect to Ground

All other pins ³

Vcc

V

-0.5 to +4.0

V

Notes:

1.

2.

No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.

Minimum DC input voltage on A9 and OE# pins is –0.5V. During voltage transitions, A9 and OE# pins may undershoot V_ss

to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9

and OE# is 11.5V which may overshoot to 12.5V for periods up to 20ns.

3.

4.

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V_ssto –1.0V for periods

of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is V_cc

+

0.5 V. During voltage transitions, outputs may overshoot to V_cc+ 1.5 V for periods up to 20ns. See figure below.

Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress

rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the

device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES¹

Parameter

Value

Unit

Ambient Operating Temperature

Industrial Devices

-40 to 85

°C

Regulated Voltage

Range: 3.0-3.6

Operating Supply Voltage

Vcc

V

Standard Voltage Range:

2.7 to 3.6

1.

Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+1.5V

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot

Waveform

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

30

Rev. B, Issue Date: 2009/03/16

EN39LV010

PHYSICAL DIMENSIONS

34-Ball Very-Very-Thin-Profile Fine Pitch Ball Grid Array (WFBGA)

Note : Controlling dimensions are in millimeters (mm).

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

31

Rev. B, Issue Date: 2009/03/16

EN39LV010

PL 032

32-Pin Plastic Leaded Chip Carrier

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

32

Rev. B, Issue Date: 2009/03/16

EN39LV010

PHYSICAL DIMENSIONS (continued)

32L TSOP-1 8mm x 14mm

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

33

Rev. B, Issue Date: 2009/03/16

EN39LV010

Purpose

Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking

on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and

the compositions of the ICs. Eon is still keeping the promise of quality for all the products with

the same as that of Eon delivered before. Please be advised with the change and appreciate

your kindly cooperation and fully support Eon’s product family.

Eon products’ New Top Marking

cFeon Top Marking Example:

cFeon

Part Number: XXXX-XXX

Lot Number: XXXXX

Date Code: XXXXX

For More Information

Please contact your local sales office for additional information about Eon memory solutions.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

34

Rev. B, Issue Date: 2009/03/16

EN39LV010

ORDERING INFORMATION

EN39LV010

70

S

I

P

PACKAGING CONTENT

(Blank) = Conventional

P = RoHS compliant

TEMPERATURE RANGE

I = Industrial (-40°C to +85°C)

PACKAGE

N = 34-Ball Very-Very-Thin-Profile Fine Pitch

Ball Grid Array (WFBGA)

0.50mm pitch, 4mm x 6mm package

J = 32-pin Plastic PLCC

S = 32-pin 8mm x 14mm TSOP-1

SPEED

45R = 45ns Regulated range 3.0V~3.6V

70 = 70ns

BASE PART NUMBER

EN = Eon Silicon Solution Inc.

39 = 4K byte uniform sector

LV =FLASH, 3V Read, Program and Erase

010 = 1 Megabit (128K x 8)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

35

Rev. B, Issue Date: 2009/03/16

EN39LV010

Revisions List

Revision No

Description

Date

A

B

Initial release

Modify program and erase time value in Table 11

Sector Erase time Max. 2‰0.5sec.

2009/1/23

2009/3/16

Chip Erase time Typ. 0.25‰3sec. Max. 2.5‰15sec.

Byte Programming time Max. 200‰20us.

Chip Programming time Typ. 1‰0.8sec. Max. 1.6‰2sec.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

36

Rev. B, Issue Date: 2009/03/16


型号：	EN39LV010-70NIP
厂家：	EON SILICON SOLUTION INC.
描述：	1 Megabit (128K x 8-bit ) 4 Kbyte Uniform Sector, CMOS 3.0 Volt-only Flash Memory 1兆位（ 128K ×8位）， 4 KB的统一部门， CMOS 3.0伏只快闪记忆体
文件：	总36页 (文件大小：1376K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EN39LV010-70NIP [EON]

相关型号：

EN39LV010-70SI

EN39LV010-70SIP

EN39LV010_11

EN39SL160AH

EN39SL160AH-70BAP

EN39SL160AH-70BIP

EN39SL160AH-70NAP

EN39SL160AH-70NIP

EN39SL160AH-90BAP

EN39SL160AH-90BIP

EN39SL160AH-90NAP

EN39SL160AH-90NIP