ED14U647-254SATEL [EOREX]
ED382R517-2G4SA-H9R is eorex Registered DDR3 SDRAM DIMMs;![ED14U647-254SATEL](http://pdffile.icpdf.com/pdf2/p00354/img/icpdf/ED14U646-25A_2173332_icpdf.jpg)
型号: | ED14U647-254SATEL |
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描述: | ED382R517-2G4SA-H9R is eorex Registered DDR3 SDRAM DIMMs 动态存储器 双倍数据速率 |
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eorex
ED382R517-2G4SA-H9R
Description
ED382R517-2G4SA-H9R is eorex Registered DDR3 SDRAM DIMMs (Registered Double Data Rate
Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules
that use DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory
when installed in systems such as servers and workstations.
Features
• Power Supply: VDD=1.5V (1.425V to 1.575V)
• VDDQ = 1.5V (1.425V to 1.575V)
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the DDR3L SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-12800, PC3-10600, PC3-8500
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
* This product is in compliance with the RoHS directive.
1
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ED382R517-2G4SA-H9R
Ordering Information
Part No
Density Organization Component Composition # of ranks FDHS
ED382R517-2G4SA-H9R
8G
1Gb x 72
2
O
512Mx4*36
E D 3 82 R 51 7 - 2G 4 S A – H9 R
Package Code
EOREX Memory
L: Leaded
P: Lead free
Product Type
D: Dimm
R: Lead free & Halogen free
Product Mode
Module Speed ( tCL-tRCD-tRP )
1: DDRI DRAM Module
2: DDRII DRAM Module
3: DDRIII DRAM Module
TE: DDR3-2133 14-14-14
RD: DDR3-1866 13-13-13
PB: DDR3-1600 11-11-11
H9: DDR3-1333 9-9-9
G7: DDR3-1066 7-7-7
S6: DDR3-800 6-6-6
DIMM Density
1: 1 Giga Byte
2: 2 Giga Byte
4: 4 Giga Byte
8: 8 Giga Byte
A:16Giga Byte
Die Version
A: 1st
B: 2nd
C: 3rd
B: 4th
Module Type
U: 240 pin Unbuffered DIMM
R: 240 pin Registered DIMM
V: 240 pin VLP Registered DIMM
S: 204 pin Unbuffered SO-DIMM
L: 240 pin LRDIMM
A: 204 pin ECC SO-DIMM
B: 204 pin SO-DIMM (Single Side)
E: 240 pin VLP ECC UDIMM
M: 244 pin ULP Mini UDIMM
Power consumption
S: 1.5V
M: 1.35V
N: 1.25V
Bit organization
4: X4
8: X8
A: X16
B: X32
Memory Depth
64: 64Mb
12: 128Mb
25: 256Mb
51: 512Mb
1G: 1Gb
2G: 2Gb
4G: 4Gb
8G: 8Gb
16:16Gb
Die Density
64: 64Mb
1G: 1Gb
2G: 2Gb
4G: 4Gb
8G: 8Gb
16:16Gb
12: 128Mb
25: 256Mb
51: 512Mb
Data Width
6: X64
7: X72
2
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ED382R517-2G4SA-H9R
Key Parameters
CAS
Latency
(tCK)
tCK
(ns)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
MT/s
Grade
CL-tRCD-tRP
13.5
13.5
49.5
(49.125)*
DDR3-1333
DDR3-1600
-17
-16
1.5
9
36
35
9-9-9
(13.125)* (13.125)*
13.75 13.75
(13.125)* (13.125)*
48.75
(48.125)*
1.25
11
11-11-11
*Eorex DRAM devices support optional downbinning to CL11, CL9, and CL7. SPD setting is programmed to
match.
Speed Grade
Frequency [MHz]
Grade
Remark
CL6
CL7
CL8
CL9
CL10
CL11
-18
-17
-16
800
800
800
1066
1066
1066
1066
1066
1066
1333
1333
1333
1333
1600
Address Table
2GB(1Rx8)
4GB(2Rx8)
4GB(1Rx4)
8GB(4Rx8)
8GB(2Rx4) 16GB(4Rx4)
Refresh
Method
8K/64ms
A0-A13
A0-A9
8K/64ms
A0-A13
A0-A9
8K/64ms
A0-A13
8K/64ms
A0-A13
A0-A9
8K/64ms
A0-A13
8K/64ms
A0-A13
Row Address
Column
Address
A0-A9,A11
A0-A9,A11
A0-A9,A11
Bank Address
Page Size
BA0-BA2
1KB
BA0-BA2
1KB
BA0-BA2
1KB
BA0-BA2
1KB
BA0-BA2
1KB
BA0-BA2
1KB
3
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ED382R517-2G4SA-H9R
Pin Descriptions
Num
ber
Num
ber
Pin Name
Description
Pin Name
Description
CK0
CK0
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
1
ODT[1:0]
DQ[63:0]
CB[7:0]
On Die Termination Inputs
Data Input/Output
2
64
8
1
CK1
1
Data check bits Input/Output
Data strobes
CK1
1
DQS[8:0]
DQS[8:0]
9
CKE[1:0]
2
Data strobes, negative line
9
DM[8:0]/
DQS[17:9],
TDQS[17:9]
Data Masks / Data strobes,
Termination data strobes
RAS
Row Address Strobe
1
1
9
9
Data strobes, negative line,
Termination data strobes
DQS[17:9],
TDQS[17:9]
CAS
WE
Column Address Strobe
Reserved for optional hardware
temperature sensing
Write Enable
Chip Selects
Address Inputs
1
4
EVENT
TEST
1
1
1
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
S[3:0]
A[9:0],A11,
A[15:13]
14
RESET
Register and SDRAM control pin
VDD
VSS
A10/AP
A12/BC
BA[2:0]
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
1
1
3
Power Supply
22
59
1
Ground
VREFDQ
Reference Voltage for DQ
Serial Presence Detect (SPD)
Clock Input
VREFCA
SCL
1
Reference Voltage for CA
1
VTT
SDA
SPD Data Input/Output
SPD Address Inputs
1
3
Termination Voltage
SPD Power
4
1
VDDSPD
SA[2:0]
Parity bit for the Address and
Control bus
Par_In
1
1
Parity error found on the
Address and Control bus
Err_Out
4
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ED382R517-2G4SA-H9R
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
Posit
Line
i
ve
Positive line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver.
CK0
IN
Negat
Line
i
ve Negative line of the differential pair of system clock inputs that drives the input to the
CK0
CK1
CK1
IN
IN
IN
on-DIMM Clock Driver.
Positive
Line
Terminated but not used on RDIMMs.
Terminated but not used on RDIMMs.
Negat ve
i
Line
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
Active
High
CKE[1:0]
IN
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Other combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
Active
Low
S[3:0]
IN
IN
Active
High
ODT[1:0]
On-Die Termination control signals
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
RAS, CAS, WE
VREFDQ
IN
Supply
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
VREFCA
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
BA[2:0]
IN
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a Precharge command to deter-
mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
A[15:13,
12/BC,11,
10/AP,[9:0]
—
—
DQ[63:0],
CB[7:0]
I/O
IN
Data and Check Bit Input/Output pins
Active
High
DM[8:0]
Masks write data when high, issued concurrently with input data.
VDD
,
VSS
Supply
Supply
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
VTT
5
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ED382R517-2G4SA-H9R
Symbol
Type
Polarity
Function
Positive
Edge
DQS[17:0]
I/O
Positive line of the differential data strobe for input and output data.
Negative
Edge
DQS[17:0]
I/O
Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS
function via mode register A11=0 in MR1
TDQS[17:9]
TDQS[17:9]
OUT
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
SA[2:0]
SDA
IN
I/O
IN
—
—
—
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SCL
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
OUT
(open
drain)
EVENT
VDDSPD
Active Low
No pull-up resister is provided on DIMM.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Supply
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
RESET
Par_In
IN
IN
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
OUT
(open
drain)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to VDD on the system planar to act as a pull up.
Err_Out
TEST
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
6
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ED382R517-2G4SA-H9R
Pin Assignments
Front Side
(left 1–60)
Back Side
(right 121–180)
Front Side
(left 61–120)
Back Side
(right 181–240)
Pin #
Pin #
Pin #
Pin #
1
2
3
4
V
REFDQ
121
122
123
124
V
SS
61
62
63
64
A2
181
182
183
184
A1
V
SS
DQ4
DQ5
V
DD
V
DD
DD
DQ0
DQ1
NC, CK1
NC, CK1
V
V
SS
CK0
CK0
DM0,DQS9,
TDQS9
5
6
V
SS
125
126
65
66
V
V
DD
DD
185
186
NC,DQS9,
TDQS9
DQS0
DQS0
VDD
7
8
127
128
129
130
131
132
133
V
SS
67
68
69
70
71
72
73
V
REFCA
187
188
189
190
191
192
193
EVENT, NC
A0
V
SS
DQ6
DQ7
Par_In, NC
9
DQ2
DQ3
V
DD
VDD
10
11
12
13
V
SS
A10 / AP
BA0
BA1
V
SS
DQ12
DQ13
VDD
DQ8
DQ9
V
DD
RAS
S0
V
SS
WE
DM1,DQS10,
TDQS10
14
15
V
SS
134
135
74
75
CAS
194
195
VDD
NC,DQS1,
TDQS10
DQS1
DQS1
V
DD
ODT0
A13
16
17
18
19
20
21
22
136
137
138
139
140
141
142
V
SS
76
77
78
79
80
81
82
S1, NC
196
197
198
199
200
201
202
V
SS
DQ14
DQ15
ODT1, NC
VDD
DQ10
DQ11
V
DD
S3, NC
V
SS
S2, NC
VSS
V
SS
DQ20
DQ21
V
SS
DQ36
DQ37
DQ16
DQ17
DQ32
DQ33
V
SS
VSS
DM2,DQS11,
TDQS11
DM4,DQS13,
TDQS13
23
24
V
SS
143
144
83
84
V
SS
203
204
NC,DQS1,
TDQS11
NC,DQS13,
TDQS13
DQS2
DQS2
DQS4
DQS4
25
26
27
28
29
30
31
145
146
147
148
149
150
151
V
SS
85
86
87
88
89
90
91
205
206
207
208
209
210
211
VSS
V
SS
DQ22
DQ23
V
SS
DQ38
DQ39
DQ18
DQ19
DQ34
DQ35
V
SS
VSS
V
SS
DQ28
DQ29
V
SS
DQ44
DQ45
DQ24
DQ25
DQ40
DQ41
V
SS
VSS
7
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ED382R517-2G4SA-H9R
NC = No Connect; RFU = Reserved Future Use
Front Side
(left 1–60)
Back Side
Front Side
Back Side
Pin #
32
Pin #
152
Pin #
92
Pin #
212
(right 121–180)
(left 61–120)
(right 181–240)
DM3,DQS12,
TDQS12
DM5,DQS14,
TDQS14
V
SS
VSS
NC,DQS1,
TDQS12
NC,DQS14,
TDQS14
33
DQS3
DQS3
153
93
DQS5
DQS5
213
34
35
36
37
38
39
40
154
155
156
157
158
159
160
V
SS
94
95
214
215
216
217
218
219
220
VSS
V
SS
DQ30
DQ31
V
SS
DQ46
DQ47
DQ26
DQ27
96
DQ42
DQ43
V
SS
97
VSS
V
SS
CB4, NC
CB5, NC
98
V
SS
DQ52
DQ53
CB0, NC
CB1, NC
99
DQ48
DQ49
V
SS
100
VSS
NC,DM8,DQS17,
TDQS17
DM6,DQS15,
TDQS15
41
42
V
SS
161
162
101
102
V
SS
221
222
NC,DQS1,
TDQS17
NC,DQS15,
TDQS15
DQS8
DQS8
DQS6
DQS6
43
44
45
46
47
48
163
164
165
166
167
168
V
SS
103
104
105
106
107
108
109
223
224
225
226
227
228
229
VSS
V
SS
CB6, NC
CB7, NC
V
SS
DQ54
DQ55
CB2, NC
CB3, NC
DQ50
DQ51
V
SS
VSS
V
SS
NC(TEST)
RESET
V
SS
DQ60
DQ61
VTT, NC
KEY
DQ56
DQ57
KEY
CKE1, NC
VSS
DM7,DQS16,
TDQS16
49
50
VTT, NC
CKE0
169
170
110
111
V
SS
230
231
NC,DQS16,
TDQS16
VDD
DQS7
DQS7
51
52
53
54
55
56
57
58
59
60
VDD
171
172
173
174
175
176
177
178
179
180
A15
A14
112
113
114
115
116
117
118
119
120
232
233
234
235
236
237
238
239
240
VSS
BA2
V
SS
DQ62
DQ63
Err_Out, NC
VDD
DQ58
DQ59
VDD
A12 / BC
A9
VSS
A11
A7
V
SS
V
DDSPD
SA1
VDD
SA0
SCL
SA2
VDD
A8
A6
SDA
A5
A4
V
SS
VDD
V
TT
V
TT
VDD
A3
NC = No Connect; RFU = Reserved Future Use
8
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ED382R517-2G4SA-H9R
Registering Clock Driver Specifications
Capacitance Values
Symbol
CI
Parameter
Conditions
Min Typ Max Unit
Input capacitance, Data inputs
1.5
1.5
-
-
2.5
2.5
pF
pF
Input capacitance, CK, CK, FBIN, FBIN
(up to DDR3-1600)
Input capacitance, RESET, MIRROR,
QCSEN
CIR
VI = VDD or GND; VDD = 1.5v
-
-
3
pF
Input & Output Timing Requirements
DDR3-800
1066/1333
DDR3-1600
Min Max
Symbol Parameter
Conditions
Unit
Min
Max
Input clock fre- Application fre-
fclock
fTEST
tSU
300
70
670
300
70
810
300
-
Mhz
Mhz
ps
quency
quency
Input clock fre-
Test frequency
300
quency
Input valid before
Setup time
100
175
-
-
50
CK/CK
Input to remain
valid after CK/CK
tH
Hold time
125
-
ps
Propagation
delay, single-bit CK/CK to output
switching
tPDM
tDIS
tEN
0.65
1.0
0.65
1.0
ns
ps
ps
Output disable
Yn/Yn to output
time (1/2-Clock
float
0.5 + tQSK1(min)
-
-
0.5 + tQSK1(min)
0.5 - tQSK1(max)
-
-
prelaunch)
Output enable
Output driving to
time (1/2-Clock
Yn/Yn
0.5 -
tQSK1(max)
prelaunch)
9
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ED382R517-2G4SA-H9R
On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal
sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
EVENT
SCL
SDA
SA0
SA1
SA2
EVENT
SCL
SPD with
Integrated
TS
SA0
SA1
SA2
SDA
Temperature-to-Digital Conversion Performance
Parameter
Condition
Min
Typ
± 0.5
Max
Unit
Active Range,
75°C < TA < 95°C
-
± 1.0
°C
Monitor Range,
40°C < TA < 125°C
Temperature Sensor Accuracy (Grade B)
-
-
± 1.0
± 2.0
± 3.0
°C
-20°C < TA < 125°C
± 2.0
°C
°C
Resolution
0.25
10
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ED382R517-2G4SA-H9R
8GB, 1Gx72 Module(2Rank of x4) - page1
DQS17
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS8
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS17
VSS
CB[7:4]
DQS8
VSS
CB[3:0]
D17
D12
D11
D10
D0
D35
D30
D29
D28
D18
DQ [3:0]
D8
D3
D2
D1
D9
D26
D21
D20
D19
D27
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS3
DQS3
VSS
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS12
DQS12
VSS
DQ[31:28]
DQ[27:24]
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS2
DQS2
VSS
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS11
DQS11
VSS
DQ[23:20]
DQ[19:16]
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS1
DQS1
VSS
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS10
DQS10
VSS
DQ[15:12]
DQ[11:8]
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS0
DQS0
VSS
DQS9
DQS9
VSS
DQ[3:0]
DQ[7:4]
Vtt
Vtt
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eorex
ED382R517-2G4SA-H9R
8GB, 1Gx72 Module(2Rank of x4) - page2
DQS14
DQS
DQS
DQS13
DQS
DQS
DQS14
VSS
DQS
DM
DQS
DM
DQS13
VSS
DQS
DM
DQS
DM
DQ[47:44]
DQ [3:0]
D14
DQ [3:0]
D32
D22
D34
D25
DQ[39:36]
DQ [3:0]
D13
DQ [3:0]
D31
D23
D33
D24
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQS
DQS
DM
DQ [3:0]
DQS4
DQS4
VSS
DQS5
DQS5
VSS
DQ[35:32]
DQ [3:0]
D4
DQ[43:40]
DQ [3:0]
D5
DQS16
DQS16
VSS
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS15
DQS15
VSS
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQ[63:60]
D16
DQ[55:52]
D15
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
DQS7
DQS7
VSS
DQS6
DQS6
VSS
DQ[59:56]
DQ[51:48]
D7
D6
Vtt
Vtt
VDDSPD
SPD
VDDSPD
SA0
VDDSPD
EVENT
SCL
SA0
SA1
SA2
VSS
V
DD
D0–D35
D0–D35
EVENT SPD with SA1
V
TT
Integrated
SCL
SA2
VSS
D0–D35
D0–D35
VREFCA
VREFDQ
TS
SDA
SDA
V
SS
D0–D35
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Eorex sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
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eorex
ED382R517-2G4SA-H9R
8GB, 1Gx72 Module(2Rank of x4) - page3
S0
S1
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
1:2
RS1A → CS: SDRAMs D[21:18], D[30:26], D35
RS1B → CS1: SDRAMs D[25:22], D[34:31]
R
E
G
I
S
T
E
R
/
BA[N:0]
A[N:0]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RAS
CAS
RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B → CKE1: SDRAMs D[25:22], D[34:31]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
WE
CKE0
CKE1
P
L
L
ODT0
ODT1
CK0
RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1A → ODT1: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
CK0
CK1
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
120
Ω
±5%
CK1
PAR_IN
Err_Out
RST: SDRAMs D[35:0]
RESET
RST
* S[3:2], CK1 and CK1 are NC
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ED382R517-2G4SA-H9R
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Rating
Units
Notes
VDD
- 0.4 V ~ 1.80 V
V
1,3
VDDQ
- 0.4 V ~ 1.80 V
- 0.4 V ~ 1.80 V
-55 to +100
V
V
1,3
1
VIN, VOUT Voltage on any pin relative to Vss
oC
1, 2
TSTG
Storage Temperature
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
oC
Notes
0 to 85
1,2
TOPER
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR3 SDRAMs support Auto
Self-Refresh and in Extended Temperature Range and please refer to component datasheet and/or the DIMM
SPD for tREFI requirements in the Extended Temperature Range
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ED382R517-2G4SA-H9R
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol
Parameter
Units Notes
Min.
Typ.
Max.
VDD
1.425
1.500
1.575
V
V
1,2
1,2
Supply Voltage
Supply Voltage for Output
VDDQ
1.425
1.500
1.575
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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ED382R517-2G4SA-H9R
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and ADDress
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
Notes
Min
Max
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VIL.CA(AC175)
VIH.CA(AC150)
VIL.CA(AC150)
VIH.CA(AC135)
VIL.CA(AC135)
VIH.CA(AC125)
VIL.CA(AC125)
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC Input logic high
AC input logic low
AC input logic high
AC input logic low
AC Input logic high
AC input logic low
Vref + 0.100
VDD
V
V
V
V
V
V
V
V
V
V
1, 5
VSS
Vref - 0.100
1, 6
Vref + 0.175
Note2
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
Note2
Vref - 0.175
Vref + 0.150
Note2
Note2
Vref - 0.150
-
-
-
-
-
-
-
-
Reference Voltage for
ADD, CMD inputs
VRefCA(DC
)
0.49 * VDD
0.51 * VDD
V
3, 4, 9
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 43.
3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for
RefCA(DC)
Ref
Ref
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and
VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is
used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced,
and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135), and
VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is
used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and
VIL.CA(AC125) value is used when Vref - 0.125V is referenced.
9. Vref is measured relative to VDD at the same point, time and same device.
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ED382R517-2G4SA-H9R
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Single Ended AC and DC Input Levels for DQ and DM
DDR3-800/1066
DDR3-1333/1600
Symbol
Parameter
Unit Notes
Min
VIH.DQ(DC100) DC input logic high Vref + 0.100
VIL.DQ(DC100) DC input logic low VSS
VIH.DQ(AC175) AC input logic high Vref + 0.175
VIL.DQ(AC175) AC input logic low Note2
VIH.DQ(AC150) AC Input logic high Vref + 0.150
Max
Min
Max
VDD
Vref - 0.100
Note2
Vref + 0.100
VDD
V
V
V
V
V
V
1, 5
VSS
Vref - 0.100
1, 6
-
-
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
Vref - 0.175
Note2
-
-
Vref + 0.150
Note2
VIL.DQ(AC150) AC input logic low
VIH.CA(AC135) AC input logic high
VIL.CA(AC135) AC input logic low
Reference Voltage
Note2
Vref - 0.150
-
Note2
Vref - 0.150
-
-
-
-
-
-
mV 1, 2, 7
mV 1, 2, 8
-
VRefDQ(DC
)
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3, 4, 9
for DQ, DM inputs
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 43.
3. The ac peak noise on V may not allow V to deviate from V by more than +/-1% VDD (for
RefDQ(DC)
Ref
Ref
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);
VIH.DQ(AC175) value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref
+ 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);
VIL.DQ(AC175) value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -
0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. Vref is measured relative to VDD at the same point, time and same device.
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ED382R517-2G4SA-H9R
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages
and V
are illustrated in
RefDQ
VRefCA
figure below. It shows a valid reference voltage V (t) as a function of time. (V stands for V and
RefCA
Ref
Ref
V
likewise).
RefDQ
V
(DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to
Ref
Ref
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 38. Further-
more V
(t) may temporarily deviate from V
by no more than +/- 1% VDD.
Ref
Ref (DC)
voltage
VDD
V
(t)
Ref
V
ac-noise
Ref
V
Ref(DC)max
V
Ref(DC)
VDD/2
V
Ref(DC)min
VSS
time
Illustration of V
tolerance and V
ac-noise limits
Ref(DC)
Ref
The voltage levels for setup and hold time measurements V
, V
, V
, and V
are depen-
IL(DC)
IH(AC) IH(DC) IL(AC)
dent on V
.
Ref
“V ” shall be understood as V
, as defined in figure above.
Ref
Ref(DC)
This clarifies that dc-variations of V affect the absolute voltage a signal has to reach to achieve a valid
Ref
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for V
deviations from the optimum position within the data-eye of the input
Ref(DC)
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with V ac-noise. Timing and voltage effects due to ac-noise on V up to the speci-
Ref
Ref
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
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ED382R517-2G4SA-H9R
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
t
DVAC
V
IL.DIFF.AC.MIN
V
IL.DIFF.MIN
0
half cycle
V
IL.DIFF.MAX
V
IL.DIFF.AC.MAX
t
DVAC
time
Definition of differential ac-swing and “time above ac-level” t
DVAC
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ED382R517-2G4SA-H9R
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3-800, 1066, 1333, 1600
Symbol
Parameter
Unit Notes
Min
Max
VIHdiff
VILdiff
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
+ 0.200
Note 3
Note 3
- 0.200
V
V
V
V
1
1
2
2
VIHdiff (ac)
VILdiff (ac)
2 x (VIH (ac) - Vref)
Note 3
Note 3
2 x (VIL (ac) - Vref)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 43.
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
tDVAC [ps]
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 350mV
@ |VIH/Ldiff (ac)| = 300mV
Slew Rate [V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
>
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
-
-
-
-
-
-
<
1.0
0
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ED382R517-2G4SA-H9R
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-
ended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
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ED382R517-2G4SA-H9R
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-800, 1066, 1333, 1600
Symbol
Parameter
Unit Notes
Min
Max
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
V
V
V
V
1,2
1,2
1,2
1,2
VSEH
VSEL
Note 3
(VDD / 2) = 0.175
(VDD / 2) = 0.175
Note 3
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 43.
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ED382R517-2G4SA-H9R
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3-800, 1066, 1333, 1600
Symbol
Parameter
Unit Notes
Min
Max
-150
-175
150
175
mV
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
VIX
VIX
mV
1
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
mV
Notes:
1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are
IX
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential
slew rate of CK - CK is larger than 3 V/ns.
2. Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 36
for VSEL and VSEH standard values.
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ED382R517-2G4SA-H9R
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-
ended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Differential Input Slew Rate Definition
Measured
Description
Defined by
Max
Min
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Delta
TRdiff
vIHdiffmin
0
vILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
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ED382R517-2G4SA-H9R
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
DDR3-800, 1066,
Symbol
Parameter
Unit
Notes
1333 and 1600
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
0.8 x VDDQ
V
V
V
V
V
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
Notes:
1. The swing of ±0.1 x V
is based on approximately 50% of the static single ended output high or low
DDQ
swing with a driver impedance of 40Ω and an effective test load of 25Ω to V = V
/ 2.
DDQ
TT
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
DDR3-800, 1066,
Symbol
Parameter
Unit
Notes
1333 and 1600
+ 0.2 x VDDQ
V
V
1
1
VOHdiff (AC)
VOLdiff (AC)
Notes:
1. The swing of ±0.2 x V
AC differential output high measurement level (for output SR)
- 0.2 x VDDQ
AC differential output low measurement level (for output SR)
is based on approximately 50% of the static differential output high or low
DDQ
swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to V = V
/2 at each of the
TT
DDQ
differential outputs.
25
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ED382R517-2G4SA-H9R
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between V
and V
for single ended signals are shown in table and figure below.
OH(AC)
OL(AC)
Single-ended Output slew Rate Definition
Measured
Description
Defined by
From
VOL(AC)
VOH(AC)
To
[VOH(AC)-VOL(AC)] / DeltaTRse
[VOH(AC)-VOL(AC)] / DeltaTFse
VOH(AC)
VOL(AC)
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
vOH(AC)
V
∏
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Parameter
Symbol Min
SRQse 2.5
Max
Min
Max
Min
Max
Min
Max
Single-ended Output Slew Rate
5
2.5
5
2.5
5
2.5
5
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular
maximum limite of 5 V/ns applies.
26
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ED382R517-2G4SA-H9R
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
VOLdiff (AC)
VOHdiff (AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta
TRdiff
vOHdiff(AC)
O
vOLdiff(AC)
Delta
TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Parameter
Symbol Min
SRQdiff
Max
Min
Max
Min
Max
Min
Max
Differential Output Slew Rate
5
12
5
12
5
12
5
12
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
27
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ED382R517-2G4SA-H9R
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
25 Ohm
CK, CK
DQ
DQS
DQS
VTT = VDDQ/2
DUT
Reference Load for AC Timing and Output Slew Rate
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ED382R517-2G4SA-H9R
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
DDR3- DDR3- DDR3- DDR3-
Parameter
Units
800
1066
1333
1600
Maximum peak amplitude allowed for overshoot area. (See figure below)
0.4
0.4
0.4
0.5
0.5
0.4
0.4
0.4
0.4
0.4
0.4
V
V
Maximum peak amplitude allowed for undershoot area. (See figure below) 0.4
Maximum overshoot area above VDD (See figure below)
Maximum undershoot area below VSS (See figure below)
0.67
0.67
0.33
0.33
V-ns
V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDD
VSS
Volts
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Address and Control Overshoot and Undershoot Definition
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ED382R517-2G4SA-H9R
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/UndershootSpecification for Clock, Data, Strobe and Mask
DDR3- DDR3- DDR3- DDR3-
Parameter
Units
800
1066
1333
1600
Maximum peak amplitude allowed for overshoot area (See figure below)
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
Maximum peak amplitude allowed for undershoot area (See figure below) 0.4
Maximum overshoot area above VDD (See figure below)
Maximum undershoot area below VSS (See figure below)
0.25
0.25
0.19
0.19
0.15
0.15
0.13
0.13
V-ns
V-ns
(CK, CK, DQ, DQS, DQS, DM)
See figure below for each parameter definition
Maxim um Am plitude
Overshoot Area
VDDQ
VSSQ
Volts
(V)
Undershoot Area
Maxim um Am plitude
Tim e (ns)
Clock, Data Strobe and Mask Overshoot and Undershoot Definition
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
30
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ED382R517-2G4SA-H9R
Refresh parameters by device density
Refresh parameters by device density
Parameter
RTT_Nom Setting
512Mb
1Gb
2Gb
4Gb
8Gb
Units Notes
REF command ACT or
REF command time
tRFC
90
110
160
260
350
ns
us
0 °C ≤ T
≤ 85 °C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
Average periodic
refresh interval
CASE
tREFI
85 °C < T
≤ 95 °C
us
1
CASE
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3-800E
6-6-6
Unit
Notes
CL - nRCD - nRP
Parameter
Symbol
min
max
tAA
15
20
—
—
—
ns
ns
ns
ns
ns
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tRCD
15
15
tRP
tRC
52.5
ACT to ACT or REF command period
ACT to PRE command period
tRAS
37.5
2.5
9 * tREFI
3.3
tCK(AVG)
ns
nCK
nCK
CL = 6
CWL = 5
1,2,3
6
5
Supported CL Settings
Supported CWL Settings
31
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ED382R517-2G4SA-H9R
DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3-1066F
7-7-7
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ns
ns
ns
ns
ACT to internal read or
write delay time
tRCD
13.125
13.125
50.625
—
—
—
tRP
PRE command period
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
37.5
2.5
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 6
ns
ns
1,2,3,6
1,2,3,4
4
CWL = 6
Reserved
Reserved
CWL = 5
CL = 7
ns
CWL = 6
1.875
1.875
< 2.5
< 2.5
ns
1,2,3,4
4
CWL = 5
CL = 8
Reserved
ns
CWL = 6
ns
1,2,3
nCK
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8
5, 6
32
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ED382R517-2G4SA-H9R
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3-1333H
9-9-9
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.5
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,10
13.5
(13.125)5,10
ACT to internal read or
write delay time
—
—
—
13.5
(13.125)5,10
PRE command period
49.5
(49.125)5,10
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
36
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
2.5
ns
ns
ns
ns
1,2,3,7
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,7
4
4
1.875
1.875
< 2.5
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,7
(Optional)5,10
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 5
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
4
Reserved
CWL = 6
1,2,3,7
1,2,3,4
4
CWL = 7
Reserved
Reserved
CWL = 5, 6
CWL = 7
CL = 9
1.5
1.5
<1.875
<1.875
1,2,3,4
4
CWL = 5, 6
Reserved
CL = 10
ns
ns
1,2,3
5
tCK(AVG)
CWL = 7
(Optional)
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8, 9, 10
nCK
5, 6, 7
33
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ED382R517-2G4SA-H9R
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3-1600K
11-11-11
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.75
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,10
13.75
(13.125)5,10
ACT to internal read or
write delay time
—
—
—
13.75
(13.125)5,10
PRE command period
48.75
(48.125)5,10
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
35
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
2.5
ns
ns
ns
ns
1,2,3,8
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,8
CL = 6
4
4
1.875
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,8
(Optional)5,10
Reserved
CL = 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
Reserved
4
4
Reserved
1.875
1.5
< 2.5
1,2,3,8
1,2,3,4,8
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
<1.875
tCK(AVG)
CWL = 7
ns
1,2,3,4,8
(Optional)5,10
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
CWL = 5, 6
CWL = 7
ns
ns
1,2,3,4
4
Reserved
1.5
<1.875
<1.5
ns
1,2,3,8
1,2,3,4
4
CL = 10
CL = 11
CWL = 8
Reserved
Reserved
ns
CWL = 5, 6,7
CWL = 8
ns
1.25
ns
1,2,3
nCK
nCK
Supported CL Settings
Supported CWL Settings
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
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ED382R517-2G4SA-H9R
Speed Bin Table Notes
Absolute Specification (T
; V
= V = 1.5V +/- 0.075 V);
DDQ DD
OPER
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to Eorex DIMM data sheet and/or the DIMM SPD information if and how this set-
ting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
35
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ED382R517-2G4SA-H9R
Environmental Parameters
Symbol
Parameter
Operating temperature
Rating
Units
Notes
TOPR
See Note
3
HOPR
TSTG
HSTG
PBAR
Operating humidity (relative)
10 to 90
-50 to +100
5 to 95
%
1
1
oC
%
Storage temperature
Storage humidity (without condensation)
Barometric Pressure (operating & storage)
1
105 to 69
K Pascal
1, 2
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only,
and device functional operation at or above the conditions indicated is not implied. Expousure to absolute
maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
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ED382R517-2G4SA-H9R
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
•
”0” and “LOW” is defined as VIN <= V
ILAC(max).
”1” and “HIGH” is defined as VIN >= V
IHAC(max).
•
•
•
•
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0 (Output Buffer enabled in MR1);
B
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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ED382R517-2G4SA-H9R
IDD
IDDQ (optional)
VDD
RESET
CK/CK
VDDQ
DDR3
SDRAM
RTT = 25 Ohm
CKE
CS
DQS, DQS
DQ, DM,
VDDQ/2
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
38
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ED382R517-2G4SA-H9R
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1066
DDR3-1333
DDR3-1600
Symbol
Unit
7-7-7
1.875
7
9-9-9
1.5
9
11-11-11
tCK
1.25
11
11
39
28
11
24
32
5
ns
CL
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
7
9
nRCD
nRC
nRAS
nRP
27
20
7
33
24
9
1KB page size
2KB page size
1KB page size
2KB page size
20
27
4
20
30
4
nFAW
nRRD
6
5
6
n
n
n
n
n
RFC -512Mb
48
59
86
139
187
60
74
107
174
234
72
88
128
208
280
RFC-1 Gb
RFC- 2 Gb
RFC- 4 Gb
RFC- 8 Gb
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
IDD0
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
IDD1
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
39
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ED382R517-2G4SA-H9R
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2N
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2NT
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
IDD2P0
IDD2P1
IDD2Q
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD3N
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
IDD3P
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
40
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ED382R517-2G4SA-H9R
Symbol
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
IDD4R
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
IDD4W
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
IDD5B
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
T
CASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
IDD6
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
IDD6ET
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
41
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ED382R517-2G4SA-H9R
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
IDD7
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature
range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
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ED382R517-2G4SA-H9R
Table 3 - IDD0 Measurement-Loop Patterna)
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
-
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
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ED382R517-2G4SA-H9R
Table 4 - IDD1 Measurement-Loop Patterna)
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD 00
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRCD
...
0
1
0
1
0
0
0
0
0
0
0
0
00000000
-
nRAS
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD 00
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRCD
...
0
1
0
1
0
0
0
0
F
0
00110011
-
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
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ED382R517-2G4SA-H9R
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
0
1
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
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ED382R517-2G4SA-H9R
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
Datab)
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
-
2,3
D,D
RD
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
0
WR
D
D,D
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
2,3
4
5
6,7
-
-
00110011
-
-
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
46
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ED382R517-2G4SA-H9R
Table 9 - IDD5B Measurement-Loop Patterna)
Datab)
0
1
REF
D, D
D, D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
0
1.2
00
00
3,4
5...8
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC-1
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
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ED382R517-2G4SA-H9R
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
1
0
1
2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
repeat above D Command until nRRD - 1
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
D
1
0
0
0
0
3
00
0
0
F
0
0
-
-
4
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
0
F
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
2*nFAW+nRRD+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
11
2&nFAW+nRRD+2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
12 2*nFAW+2*nRRD
13 2*nFAW+3*nRRD
D
1
0
0
0
0
3
00
0
0
0
0
-
14 2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
15 3*nFAW
16 3*nFAW+nRRD
17 3*nFAW+2*nRRD
18 3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
-
19 3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
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ED382R517-2G4SA-H9R
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
8GB, 1G x 72 R-DIMM: ED382R517-2G4SA-H9R
Symbol
IDD0
DDR3 1066
2024
2204
1664
1916
660
DDR3 1333
2204
2384
1844
2024
660
DDR3 1600
2474
2654
1844
2204
660
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
768
768
768
1664
1844
768
1844
2024
768
1844
2204
768
2654
2654
3914
660
3014
3014
4094
660
3374
3464
4544
660
IDD6ET
IDD7
768
768
768
3914
4634
4904
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ED382R517-2G4SA-H9R
1Gx72 - Module Dimentions
Module Demensions:
50
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ED382R517-2G4SA-H9R
1Gx72 - Heat Spreader
51
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