EM6164K800VBA-70IF_技术文档

64Kx16 LP SRAM EM6164K600V Series

GENERAL DESCRIPTION

The EM6164K600V is a 1,048,576-bit low power CMOS static random access memory organized as

65,536 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology.

Its standby current is stable within the range of operating temperature.

The EM6164K600V is well designed for low power application, and particularly well suited for battery

back-up nonvolatile memory application.

The EM6164K600V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are

fully TTL compatible

FEATURES

z

Fast access time: 45/55/70ns

Low power consumption:

Operating current:

z

Tri-state output

Data byte control :

LB# (DQ0 ~ DQ7)

23/20/18mA (TYP.)

Standby current: -L/-LL version

10/1µA (TYP.)

UB# (DQ8 ~ DQ15)

Data retention voltage: 1.5V (MIN.)

Package:

z

Single 2.7V ~ 3.6V power supply

All inputs and outputs TTL compatible

Fully static operation

44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

FUNCTIONAL BLOCK DIAGRAM

Vcc

Vss

64Kx16

MEMORY

ARRAY

A0-A15

DECODER

DQ0-DQ7

Lower Byte

DQ8-DQ15

Upper Byte

I/O DATA

CURCUIT

COLUMN I/O

CE#

WE#

OE#

LB#

CONTROL

CIRCUIT

UB#

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A15

Address Inputs

DQ0 – DQ15 Data Inputs/Outputs

CE#

WE#

OE#

LB#

UB#

Vcc

Chip Enable Input

Write Enable Input

Output Enable Input

Lower Byte Control

Upper Byte Control

Power Supply

Vss

Ground

1

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

PIN CONFIGURATION

TSOP-II

A4

A3

A2

A1

A0

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

2

A6

3

A7

4

OE#

UB#

LB#

DQ15

DQ14

DQ13

DQ12

Vss

5

CE#

6

DQ0

DQ1

DQ2

DQ3

Vcc

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

Vss

Vcc

DQ4

DQ5

DQ6

DQ7

WE#

A15

A14

A13

A12

NC

DQ11

DQ10

DQ9

DQ8

NC

A8

A9

A10

A11

NC

TFBGA

A

B

C

D

E

F

LB#

DQ8

DQ9

Vss

Vcc

DQ14

DQ15

NC

OE#

UB#

DQ10

DQ11

DQ12

DQ13

NC

A0

A3

A5

NC

A14

A12

A9

3

A1

A4

A6

A2

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

5

NC

DQ0

DQ2

Vcc

Vss

DQ6

DQ7

NC

A7

NC

A15

A13

A10

4

G

H

A8

2

1

6

2

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

ABSOLUTE MAXIMUN RATINGS*

PARAMETER

SYMBOL

RATING

-0.5 to 4.6

0 to 70(C grade)

-20 to 80(E grade)

-40 to 85(I grade)

-65 to 150

1

UNIT

Terminal Voltage with Respect to Vss

VTERM

V

Operating Temperature

TA

°C

Storage Temperature

TSTG

PD

°C

W

Power Dissipation

DC Output Current

IOUT

50

mA

°C

Soldering Temperature (under 10 sec)

TSOLDER

260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device

reliability.

TRUTH TABLE

MODE

CE#

OE#

WE# LB# UB#

I/O OPERATION

DQ0-DQ7 DQ8-DQ15

SUPPLY CURRENT

ISB,ISB1

Standby

H

X

L

X

H

L

X

H

L

X

H

L

X

L

H

L

X

H

X

L

H

L

H

L

High-Z

DOUT

High-Z

DOUT

Output

Disable

Read

ICC,ICC1

I^CC,ICC1

High-Z

D^OUT

DOUT

Write

DIN

High-Z

D^IN

High-Z

DIN

I^CC,ICC1

L

H

L

Note: H = VIH, L = VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL TEST CONDITION

MIN.

TYP. ^*5MAX.

UNIT

Supply Voltage

Vcc

2.7

3.0

3.6

V

Input High Voltage

VIH*1

2.0

-

Vcc+

0.3

V

Input Low Voltage

VIL*2

-0.2

-1

-

0.6

V

Input Leakage

Current

ILI

Vcc ≧ VIN ≧ Vss

+1

µA

Output Leakage

Current

Output High

Voltage

Output Low

Voltage

Average Operating

Power supply

Current

ILO

VCC ≧ VOUT ≧ VSS,

Output Disabled

IOH = -1mA

-1

2.2

-

2.7

-

1

µA

V

VOH

VOL

ICC

-

IOL = 2mA

0.4

V

Cycle time = Min.

CE# = VIL , II/O = 0mA

-45

-55

-70

-

23

20

18

4

40

35

30

5

mA

I^CC1

Cycle time = 1µs

CE#≦0.2V and II/O = 0mA

other pins at 0.2V or VCC-0.2V

Standby Power

ISB

CE# = VIH

-

0.3

0.5

mA

3

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

ISB1

CE# V ≧ VCC - 0.2V

Supply Current

-L

-LL

-

20

1

80

10

µA

Notes:

1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.

2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. 10µA for special request

5. Typical values are included for reference only and are not guaranteed or tested.

Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C

CAPACITANCE (TA = 25°C , f = 1.0MHz)

PARAMETER

Input Capacitance

Input/Output Capacitance

SYMBOL

MIN.

-

MAX.

6

UNIT

pF

CIN

CI/O

8

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0.2V to VCC - 0.2V

Input Rise and Fall Times

Input and Output Timing Reference Levels

Output Load

3ns

1.5V

CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

READ CYCLE

PARAMETER

SYM.

-45

-55

70

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

Address Access Time

Chip Enable Access Time

tRC

tAA

45

-

10

5

-

10

-

55

-

10

5

-

10

-

70

-

10

5

-

10

-

ns

45

25

-

55

30

-

70

35

-

tACE

tOE

tCLZ*

tOLZ*

tCHZ*

Output Enable Access Time

Chip Enable to Output in Low-Z

Output Enable to Output in Low-Z

Chip Disable to Output in High-Z

Output Disable to Output in High-Z tOHZ*

Output Hold from Address Change tOH

LB#, UB# Access Time

LB#, UB# to High-Z Output

LB#, UB# to Low-Z Output

-

15

-

45

20

-

20

-

55

25

-

25

-

70

30

-

tBA

tBHZ*

tBLZ*

10

WRITE CYCLE

PARAMETER

SYM.

-45

-55

70

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

tWC

tAW

tCW

tAS

tWP

twr

tDW

tDH

tOW*

tWHZ*

tBW

45

40

0

35

0

20

0

5

-

55

50

0

45

0

25

0

5

-

70

60

0

55

0

30

0

5

-

ns

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Data Hold from End of Write Time

Output Active from End of Write

Write to Output in High-Z

LB#, UB# Valid to End of Write

-

35

15

-

45

20

-

60

25

-

*These parameters are guaranteed by device characterization, but not production tested.

4

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

tAA

tOH

Dout

Previous Data Valid

Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

tACE

OE#

tOH

tOHZ

tOE

tCHZ

tOLZ

tCLZ

Dout

Valid Data

High-Z

tBLZ

tBHZ

tBA

LB#, UB#

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low.

3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.

4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.

5

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

CE#

tAW

tCW

tBW

LB#, UB#

tAS

tWP

tWR

tOW

WE#

tWHZ

High-Z

Dout

(4)

tDW

tDH

High-Z

Din

Valid Data

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tWC

Address

tAW

CE#

tAS

tWR

tCW

tBW

LB#, UB#

WE#

tWP

tWHZ

High-Z

Dout

tDW

tDH

High-Z

Din

Valid Data

6

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

WRITE CYCLE 3 (LB#, UB# Controlled) (1,2,5,6)

tWC

Address

CE#

tAW

tWR

tAS

tCW

tBW

LB#, UB#

WE#

Dout

tWP

tWHZ

High-Z

tDW

tDH

High-Z

Din

Valid Data

Notes :

1. WE#, CE# must be high during all address transitions.

2. A write occurs during the overlap of a low CE#, low WE#.

3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and

data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high

impedance state.

6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

7

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

DATA RETENTION CHARACTERISTICS

PARAMETER

VCC for Data

SYMBOL

VDR

TEST CONDITION

CE# V ≧ VCC - 0.2V

MIN.

1.5

TYP. MAX. UNIT

-

3.6

V

Retention

Data Retention

Current

IDR

VCC = 1.5V

CE# V ≧ VCC - 0.2V

-L

-

1

0.5

50

5

10

µA

-LL

-LLE

-LLI

Chip Disable to Data

Retention Time

Recovery Time

tCDR

tR

See Data Retention

Waveforms (below)

0

-

ns

tRC*

tRC* = Read Cycle Time

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

VDR ≧ 1.5V

Vcc(min.)

tR

Vcc

tCDR

CE# ≧ Vcc-0.2V

VIH

CE#

Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)

VDR ≧ 1.5V

Vcc(min.)

tR

Vcc

tCDR

LB#, UB# ≧ Vcc-0.2V

VIH

LB#, UB#

8

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

PACKAGE OUTLINE DIMENSION

44-pin 400mil TSOP-II Package Outline Dimension

SYMBOLS

DIMENSIONS IN MILLMETERS

DIMENSIONS IN INCHS

MIN.

1.00

0.05

0.95

0.30

0.12

18.313

11.76

10.058

-

NOM.

-

MAX.

1.20

0.15

1.05

0.45

0.21

18.517

11.838

10.282

-

MIN.

0.039

0.002

0.037

0.012

0.0047

0.721

0.460

0.398

-

NOM.

-

MAX.

0.047

0.006

0.041

0.018

0.083

0.728

0.470

0.404

-

A

A1

A2

b

c

D

E

E1

e

L

ZD

y

-

0.039

0.014

-

0.725

0.466

0.400

0.0315

0.020

0.0317

0.35

-

18.415

11.836

10.160

0.800

0.50

0.805

0.40

-

0.00

0°

0.60

-

0.076

10°

0.0157

-

0.000

0°

0.0236

-

0.003

10°

Θ

9

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

48-ball 6mm × 8mm TFBGA Package Outline Dimension

10

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

Product ID Information

EM

61

64K

6

0

V

T

A – 45

IF*

Version

SRAM

Family

Option

Speed:

45ns

61: Standard

Configuration: Option

55ns

70ns

8: x8

16: x16

Voltage:

V: 3V

W: 2.7V

~5.5V

T: 5V

Address Density

TEMP:

Blank: Normal

I: Industrial

EOREX

Manufactured

Memory

Package:

S: sTSOP

P: PDIP

F: SOP

B: TFBGA

T: TSOP

Pb-Free PKG:

Blank: Normal

F: Pb-free

* Product ID example

11

DCC-SR-041002-A

64Kx16 LP SRAM EM6164K600V Series

Printed in Canada

The information in this document is subject to change without notice.

EOREX makes no commitment to update or keep current the information contained in this document. No part of this document

may be copied or reproduced in any form or by any means without the prior written consent of EOREX.

EOREX subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high

quality products suitable for usual commercial applications.

EOREX CORPORATION

http://www.eorex.com

sales@eorex.com

2F., No. 301-3, Guang-Ming 6th Rd., Chu-Pei City, Hsinchu County, Taiwan 302, ROC

TEL: +886-3-5585138

FAX: +886-3-5585139

12

DCC-SR-041002-A


型号：	EM6164K800VBA-70IF
厂家：	EOREX CORPORATION
描述：	64Kx16 LP SRAM 64Kx16 LP SRAM 静态存储器
文件：	总12页 (文件大小：239K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM6164K800VBA-70IF [EOREX]

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