EPC110-CSP10 [EPC]
Fully integrated configurable light barrier driver & receiver; 完全集成的可配置的光障的驱动程序和接收器
| 型号： | EPC110-CSP10 |
| 厂家： | 
ESPROS PHOTONICS CORP |
| 描述： | Fully integrated configurable light barrier driver & receiver |
| 文件： | 总27页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
epc110
Fully integrated configurable light barrier driver & receiver
General Description
Features
The epc110 is a general purpose, fully integrated self-contained Fully integrated light barrier chip
CMOS circuit to be used in light-barrier applications.
Needs just a photo diode and a LED with a LED driver
Customer configurable version
for i.e. high sensitivity or high speed applications
Integrated clock generator
CSP10 package with very small footprint
or standard QFN16 package available
The chip contains a controller which drives an LED, typically an IR-
LED. The LED is used in a pulsed mode to increase the signal-to-
noise ratio even when there is very strong sunlight biasing the photo
diode.
It contains also a high sensitive photo diode amplifier and a signal
conditioning circuitry to cancel unwanted environmental light including
strong sunlight and pulsed light sources. The receiver is built around a
synchronous demodulator circuitry. Two output signals with different
threshold levels are implemented in order to trigger the light barrier
output or to indicate light reserve.
Applications
Light barriers ranging from millimeters to tens of meters
Smoke detectors
Liquid detectors
The chip also includes a power supply circuitry to establish all
internally required voltages from one source only.
It can be used either as a standalone device, forming the whole core
of an industrial light barrier. It can also be used together with a micro-
controller (µC) for more advance applications.
Functional Block Diagram
for 10-Pin Chip Scale Package (for 16-pin QFN Package)
VDD33 VDD PROG
SCK
1 (9)
VDD
V
LED
LED
SCK
Interface
8 (14)
VDD33
9 (12)
LED
Parameter
Memory
Processor
VDD18
10 (10)
PD
SPI
Signal
Controller
Processor
3 (6)
f
D1
2 (7)
4 (4)
7 (15)
6 (1)
5 (2)
EN
SI
OUTN OUTH
SO
CS
GND
Figure 1: Block Diagram
Configuration
Fix-parameter mode
epc110
Dynamic mode
standalone
controlled
µC --> “SPI” --> epc110
µC --> “SPI / EN” --> epc110
Ambient adaptive reading
Internal controlled light barrier read rate
External controlled light barrier read rate
Application
“EN” --> epc110
Static parameters
Table 1: Configurations versus applications
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
1
Datasheet epc110 - V2.1
www.espros.ch
epc110
Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating Conditions
Voltage at any pin except pin VDD
-0.3V to VN +0.3 V
Min.
Max.
Units
Power Supply Voltage at pin VDD
Programming Voltage at pin VDD
-0.3V to +5.5V
-0.3V to +8.0V
Operating supply voltage at VDD
Programming voltage at VDD
3.0
7.0
3.6
8.0
V
V
Power Supply Voltage at pin VDD33
Output current at any pin except pin LED
Power Consumption with maximum load
Lead Temperature solder, 4 sec. (TL)
-0.3V to +5.5V
-6mA to +6mA
125 mW
Operating supply voltage at VDD33
Operating Temperature (TO)
3.0
3.6
V
C
-40°
+85°
+260°C
Humidity (non-condensing)
+5
+95
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions
indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specific -
ations and test conditions, see Electrical Characteristics.
Note 2: This device is a highly sensitive CMOS ac current amplifier with an ESD rating of JEDEC HBM class 0 (<250V). Handling and
assembly of this device should only be done at ESD protected workstations.
Electrical Characteristics
3.0V < VN < 3.6V, -40°C < TA < +85°C, unless otherwise specified
General Data
Symbol Parameter
Conditions/Comments
Values
Typ.
Units
Min.
3
Max.
3.6
3
VN
VPUP
VPP
Operating power supply voltage
at VDD33 (and VDD)
Power-up Threshold Voltage
Voltage at VDD33 when the device starts up
2.4
V
Ripple on supply voltage,
peak to peak
Input pulse IPD NST
36nA
48nA
72nA
108nA
70
150
350
600
2
mV
mV
mV
mV
mA
mA
V
IN
IProg
VOH
VOL
VHOH
VLEDH
ILED
VIH
Current consumption operating
in operation mode, IPD = 0 mA, no load
Current consumption programming in program mode, VDD @ 8.0V, IPD = 0 mA, no load
4
Output high voltage
Output low voltage
Output high voltage OUTH
Output high voltage LED
Source current maximum
Input high voltage
except OUTH and LED
VN - 0.5V
@ 4mA source, including OUTH and LED
see Figure 8
0.5
V
@ 0.1mA sink current
VN - 0.5V
0.7
V
mA
V
at Pin LED, VLED @ 0... VN - 1.0V
1.3
VN
0.7*VN
GND
VIL
Input low voltage
0.3*VN
10
V
ILEAKD
RPU
fclk
Input leakage current
Pull-up resistor
µA
kΩ
MHz
internal at digital input
30
200
Reference clock
of internal oscillator - for information only
32
All internal timings are referenced to this clock
dfclk
Temperature drift
of the oscillator - for information only
640
ppm/K
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
2
Datasheet epc110 - V2.1
www.espros.ch
epc110
SPI Interface Data (for more details refer to “SPI Interface“)
Symbol Parameter Conditions/Comments
Values
Typ.
Units
Min.
Max.
fSCK
tH
SCK Clock frequency
10
MHz
ns
High period of SCK
50
50
tL
Low period of SCK
ns
trfSCK
t1
Serial clock rise / fall time of SCK
Edge time CS --> SCK
Set-up time of SI
20
ns
50
15
15
ns
tSU
thold
tD
ns
Hold time of SI
ns
Output data of SO valid after SCK
Output data rise / fall time of SO
20
20
ns
trf
ns
Other Data (refer to “Functional Description“)
Symbol Parameter Conditions/Comments
Para-
meter
Values
Typ.
Units
Min.
Max.
IPDN
IPDH
Ipulse
Photo Current Sensitivity OUTN
Pulse height to trigger internal threshold
OUTN. Refer to Functional Description
SENSN
SENSH
Programmable between
24...108
nA
nA
µA
Photo Current Sensitivity OUTH
Maximum Input Pulse Current
Pulse height to trigger internal threshold
OUTH. Refer to Functional Description
Programmable between
60...144
If the input current pulse is above this level,
the recovery time tREC becomes trelax . (refer to
100
parameter trelax
)
IN_Imin
IN_Imax
IPDDC
Input related noise
@ IPDDC =0
15
20
nA RMS
nA RMS
mA
Input related noise
@ IPDDC =IPDDCMax
DC Photo Diode Current
generated by ambient light with no effect to
the sensitivity
0.0
2
CPD
tPulse
tCycle
Photodiode Capacitance
LED Pulse Length
LED Cycle Time
Refer to section Application Information,
Photodiode Capacitance
50
pF
µs
µs
TPULSE Programmable between
1…8
for fork light barrier, standalone mode
TPER
Programmable between
5…100'000
for fork light barrier, controlled mode
controlled by EN input
50
trelax
tR
Recovery time
Response Time
after a strong current pulse (Ipulse = 100µA)
Minimum time from light beam detection to
status change of the output OUTN or OUTH. tCycle / nV
tR_MAX = ( nV + 1 ) * tCycle
µs
refer to
Programmable between
10µs...3.3s
tF
Release Time (fall time)
Valid pulse counts
Minimum time from beam interruption to
status change of the output OUTN or OUTH. tCycle / nM
tF_MAX = ( nM + 1 ) * tCycle
refer to
Programmable between
10µs...54.6min
nV
nM
Number of weighted valid (non-missing)
pulses to trigger the output.
Refer to Functional Description
INC
(Programmable between
1…32 pulses)
Missing pulse counts
Number of weighted missing pulses to
release the output.
DEC
(Programmable between
1…32'767 pulses)
Refer to Functional Description
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
3
Datasheet epc110 - V2.1
www.espros.ch
epc110
Other Parameters
(typical values, Tamb = 25°C, VDD = 3.3V)
120
110
100
90
80
70
60
50
40
0
1
2
3
4
5
6
Pulse width [us]
Figure 2: Input Sensitivity vs. LED pulse width
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
4
Datasheet epc110 - V2.1
www.espros.ch
epc110
Connection Diagrams
2 1
1 1
0 1
9
9
8
7
6
VDD33
EN
SI
LED
SCK
OUTN
SO
NC_GND
GND
NC_GND
LED/SCK
EN/SI
Top View
OUTH
10 VDD18
5
Top View
PD
NC_GND
NC_GND
VDD
1
GND
2
PD
3
CS
4
1
2
4
3
10-Pin Chip Scale Package (CSP)
16-Pin QFN Package
10-Pin
CSP
16-Pin Pin Name Type
QFN
Description
1
9
VDD
Power Supply
Positive power supply.
Operation mode: to be connect to VDD33.
During command PROG: to be connected to programming voltage.
2
3
4
7
6
4
GND
PD
Power Supply
Analog Input
Digital Input
Negative power supply pin.
Photo diode input.
CS
Terminated with internal pull up resistor
Light barrier:
Mode selection:
CS = 1: Operation Mode (LED, EN, OUTN active)
Chip select,
SPI interface:
CS = 0: Command/Program Mode (SCK, SI, SO active)
5
6
2
1
OUTH
Digital Output
Light reserve detected - see Figure 8.
Load depending Refer to section Light Reserve Output OUTH
Open drain output
OUTN
SO
Digital Output
Open drain output
Light barrier:
Light pulses detected, amplified and filtered signal
see Functional Description
SPI interface:
Serial data output
7
8
15
14
EN
SI
Digital Input
Terminated with internal pull up resistor
Light barrier:
Fork light barrier controlled mode:
LED pulse stimulation
No function.
Fork light barrier standalone mode:
Serial data input
SPI interface:
LED
SCK
Digital Output
Digital Input
Light barrier:
SPI interface:
Output to LED driver
Serial input/output clock.
For start/stop condition of SPI communication (while CS = 1):
Set SCK =1 and SCK line in tristate mode (high ohmic)
12
10
VDD33 Power Supply
VDD18 Decoupling
Positive power supply.
10
Pin for external filter/decoupling of the internal 1.8V supply: 4.7nF ceramic type
Not for supply of external circuits
n/a
3, 5, 8,
11, 13,
16
NC_GND
Not connected. Connect this pins to GND (Guarding).
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
5
Datasheet epc110 - V2.1
www.espros.ch
epc110
Functional Description
Light barrier applications
To cover different aspects of applications the epc110 device can operate in various modes:
1. Standalone mode
The LED flashes in a predefined/programmed cycle time.
2. Controlled mode together with a micro-controller
The LED pulse starts on the positive edge of the input EN. The light is detected while the enable signal EN is high.
3. Fix-parameter mode
This is the use of a pre-programmed parameter setting all the time. Usually the programming takes place during configuration and
test period of the board.
4. Ambient adaptive reading by dynamic parameters
In this mode the micro-controller is doing the parameter setting during the operation mode. For the communication the SPI interface
is used. For more technical details refer to chapter “SPI Interface“.
Application is for enhanced functionality and requirements as additional filtering of environmental ac light, adjustments of the
sensitivity on the fly, controlling the LED current by micro-processor, etc. Example of a sensitivity control: The photo diode current is
compared to two threshold levels. The result from the higher comparison ( OUTH) may be used to regulate the LED current as well
the photodiode receiving parameters appropriate to the environmental conditions.
Light barrier application without an additional controller
RStab
VDD
VDD
epc110
VDD33
RLED
OUTN
OUTH
OUTN
OUTH
PD
LED
C1
C2
GND
D2
D1
GND
Figure 3: Principle of standalone light barrier application
Figure 3 shows the epc110 in a light barrier application with minimal part count. The LED flashes with a predefined rate. If the current of the
light reflected (e. g. from a diffuse reflecting object or a retro reflector) to the photo diode at pin PD exceeds the threshold val ue IPDN, the output
OUTN goes to the low state for a time which is longer than the time to the next LED pulse. Thus, the signal at the pin OUTN is constantly low
when the photo diode generates a photo current which exceeds the threshold level. The stored flashing parameters of the LED can be
programmed using the SPI interface described in this manual.
The photo diode current is compared to two threshold levels. The result OUTH from the higher comparison level may be used to detect the
light reserve.
Light barrier application using a micro-controller
If additional functionality is required in a specific application, a micro-controller can be used. Such additional requirements can be power
saving modes, additional filtering of environmental ac light, counting purposes, etc. In this configuration, the LED emits one light pulse on the
positive edge at the pin EN. The photo diode bias and amplifier chain is enabled while the enable signal EN is high so a light pulse can be
detected.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
6
Datasheet epc110 - V2.1
www.espros.ch
epc110
R
Stab
VDD
VDD
epc100
RLED
VDD33
VDD
OUTN
IN1
IN2
OUTH
LED
EN
C1
µC
EN
PD
OUT
GND
GND
OUT
GND
Figure 4: Principle of controlled light barrier application using a micro-controller
The photo diode current is compared to two threshold levels. The result OUTH from the higher comparison level may be used to detect the
light reserve.
Evaluation of a single light pulse
The photodiode is operated against ground and is reverse biased at a constant voltage of 1.2V. The input impedance of pin PD is kept low
(<1 kOhm @ 100kHz) in order to minimize the influence of the parasitic capacitance of the photodiode. To ensure proper operation under high
ambient-light conditions, the photo diode DC current can be up to 2 mA.
The resulting current from the light pulses are converted to a voltage, filtered, amplified and compared to two different threshold levels. The
lower threshold SENSN (input related 60nA typical) is used for the detection of the signal, the higher threshold SENSH (input related to
96nA typical) is used to provide an output when a certain signal reserve is achieved.
To detect the received light pulse properly, the given threshold must be at least five times higher than the rms value of the noise floor
generated by the circuitry without AC light stimulation.
The comparator results are digitally filtered and output at pin OUT and OUTH.
The parameter TPER defines the scan period in the standalone light barrier application but has also an impact to the settling time of the
receiver in the controlled mode application. It this case it has to be set corresponding to the scan period. Refer to the description of the TPER
command.
For each single light pulse, received and detected by the photodiode, the threshold levels for output OUTN and for output OUTH can be set by
programming (parameter SENSN resp. SENSH). They are processed according to the following principle to propagate the output signals
OUTN and OUTH resp. OUTNINT and OUTHINT. As far the received light pulse signal exceeds the corresponding threshold level, the pulse will
be recognized as a valid pulse and the detection circuit sets the appropriate output signal OUTN INT or OUTHINT
.
IPD
Light pulse detection
IPD
Light reserve detection
Threshold levels:
Light reserve OUTH
Signal output OUTN
t
t
t
t
t
t
OUTNINT
OUTHINT
Figure 5: Pulse evaluation
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
7
Datasheet epc110 - V2.1
www.espros.ch
epc110
Pulse Modulated Operation (e.g. OUTNint to OUTN)
The epc110 chip operates the LED and the receiver path on a pulse modulated concept. Thus, the LED is operated with short pulses whereas
the receiver channel does synchronous demodulation of the received light pulses by reading the current pulses of the photo diode. This
concept allows a very high sensitivity, high speed operation, and a high suppression of input ambient or foreign light (DC currents) generated
by sunlight or other DC light sources like light bulbs. The pulse length is set by the parameter TPULSE.
In the standalone mode the whole system is clocked by the scan period defined by the programmed parameter TPER. In the controlled mode
the timing is propagated from the external signal EN (positive edge, synchronized on the internal clock).
In order to eliminate interference caused by modulated light, e.g. a flashing light or by other light barriers, the input signal from the photodiode
is amplified, filtered, and processed by an integrated signal processor. If the photo diode signal meets the required frequency, pattern and
amplitude, the output(s) are triggered. The following timing diagram shows the basic concept.
t
t
Cycle
Pulse
on
off
Emitter LED
yes
no
Beam interrupted
Photo diode current I
OUTN or OUTH
PD
n
n
2
1
2
1
V
M
INT
INT
[V]
OUTN or OUTH
t
t
F
R
Release time
Response time
missing pulses
valid (non-missing) pulses
Figure 6: Pulse modulation concept
It is in fact a digital filter which counts missing and non-missing pulses to change the ou tput state of OUTN or OUTH.
Working principle of the digital filter e.g. for the signal OUTNint to OUTN Filter:
The aim of this programmable filter is to suppress single pulses, so they cannot trigger the output and generate a false signals.
This filter is based on a counter, which is counting up (increment) the valid pulses and counting down (decrement) the missing pulses in a
weighted manner. Separate weighting factors can be selected for valid pulses (parameter INC) and missing pulses (parameter DEC). If the
counter reaches the upper limit (maximum count, response time), the signal OUTN is set to LOW. Similar in the opposite direction, if the
counter reaches zero, the lower limit (minimum count, release time), the signal OUTN is put to HIGH. With the parameters INC and DEC the
filter has the advantage of individual selectable gradients of the slopes. Counter will never exceed maximum nor minimum limit. In between it
acts as an integrator of both parameters.
IF Pulse then
–
IF Pulse = valid then
Counter = Counter + (INC * 1024 for INC > 0 and 32 * 1024 for INC = 0)
IF counter > 215 (maximum limit) then Counter = maximum limit
IF counter = maximum limit then OUTN = 0
–
IF Pulse = missing then
Counter = Counter - (2DEC
)
IF counter < 0 (minimum limit) then Counter = minimum limit
IF counter = minimum limit then OUTN = 1
ELSE wait for Pulse
Lets assume that the photo diode does not receive light pulses for a long time: This means the light beam is interrupted. Then OUTN is at high
level. If the light beam is not anymore interrupted, the photodiode receives light pulses which are strong enough to trigger the OUTNINT
threshold and the internal pulse evaluation unit (designated in Figure 5 with 'Pulse evaluation') starts to count the receiving pulses. If the
number of received pulses reach the set level nV, the output OUTN turns to low level. Thus, single pulses cannot trigger the output and
generate a false signal.
The same procedure is used when a beam changes from not interrupted to interrupted. The internal pulse evaluation unit counts the missing
pulses. If the number of missing pulses reaches the set level n M, OUTN is turned to high level.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
8
Datasheet epc110 - V2.1
www.espros.ch
epc110
The same principle applies to the counter and signal of OUTH.
The parameter INC defines the delay nV in number of clock cycles from the start of a pulse chain to the negative edge of OUTN.
The parameter DEC defines the delay nM from the end of a pulse chain to the positive edge of OUTN.
Application
example
No. of
Pulses nM
No. of
missing Pulses nV
Long range
High speed
8
3
8
2
Table 2: Example: Settings based of filter coefficients INC and DEC
Light Pulse Detection Output OUTN
The epc110 contains two digital outputs to indicate that a valid signal of light pulses are received by the photo diode. The first output OUTN is
triggered, when the lower threshold is reached by the input signal (see Figure 5). This output is used usually to drive the output of the light
barrier. This is a fully CMOS compatible digital output.
Light Reserve Output OUTH
However, if the incoming signal is just at the trigger threshold of OUTN, an unstable situation can occur. Thus, a second output OUTH is
integrated with a higher trigger threshold to indicate that a certain 'light reserve' is reached (see Figure 5). This output is usually used to drive
a visible LED to indicate to the operator a stable detection function of the light barrier. To have not too short pulses OUTH, this signal is
stimulated by signal OUTH Filter and synchronized reseted by OUTN.
Emitter LED
OUTN Filter
OUTH Filter
OUTN
OUTH
Figure 7: synchronization OUTH with OUTN
The trigger threshold of OUTH is set usually approx. 50% above the trigger threshold of OUTN.
This output is not CMOS compatible. Its voltage is depending of the load according to Figure 8.
OUTH low max.
OUTH high max.: 3.6V / - 40ºC
OUTH high typ.
OUTH high min.: 3.0V / + 85ºC
Voltage OUTH [V]
Figure 8: Output voltage versus output current of output OUTH
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
9
Datasheet epc110 - V2.1
www.espros.ch
epc110
To have still digital compatible signals a level conversion is necessary. Below you find some examples for such circuits for converting OUTH
levels to full CMOS compatible digital output.
+3.3V
R4
10k
VDD
R2
OUTH
12k
epc110
R1
3k6
VDD33
VDD18
PD
T1
BC846 B
LED
OUTN
OUTH
GND
R3
4k7
GND
Figure 9: Non-inverting, low power level shifter (additional current approx. 0.6mA)
+3.3V
+3.3V
R4
R5
22k
33k
VDD
R3
33k
VDD
R2
12k
OUTH
epc110
R1
1k5
epc110
R1
3k6
VDD33
VDD18
PD
VDD33
VDD18
PD
T1
BC846 B
T2
BC846 B
OUTH
LED
LED
OUTN
OUTH
OUTN
OUTH
T1
BC846 B
R2
10k
GND
R3
4k7
GND
GND
GND
Figure 10: Simple inverting level shifter
(additional current approx. 1.6mA or 2.6mA)
Figure 11: Inverting, low power level shifter
(additional current approx. 0.8 ... 1.0mA)
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
10
Datasheet epc110 - V2.1
www.espros.ch
epc110
Parameters
The parameters are defining the functionality of the epc110. The big variety of possible settings allows to cover a wide range of applications.
The devices contains a memory to store the application parameters. They are stored into 16bit registers. The registers are organized into
2 blocks: a volatile and a non-volatile one.
Parameter Memory Organization (epc110)
The following classes of data are stored for each device:
•
•
Application parameters
Unique chip ID and chip adjustments (factory set)
This data can be permanently stored in a read-only memory (ROM)1 and is mirrored in a volatile memory (RAM). At power up, the data
(except the chip ID) is copied from the ROM to the RAM. During operation, the data from the RAM is used. Both memories are organized in
16 registers at 16 bits each. The data can be accessed on a 16-bit register base.
If a register has been burned (=stored into the ROM) the first bit is set: FUSEBIT = 1. If VMOD = 1 is selected, the register cannot be modified
any more nor in RAM nor in ROM area. For VMOD = 0 the RAM area is still accessible.
So far the chip can be operated in two different modes:
•
Fix-parameter mode VMOD = 1: e.g. as standalone or pre-configured device
Operated with not modifiable data from RAM, which are stored permanently in ROM.
•
Dynamic mode VMOD = 0: e.g. for adaptive systems, dynamic systems
Operated with modifiable data from RAM. The SPI interface allows to modify these data in the RAM area at any time on the fly.
At power up these data are loaded from the permanent stored data in the ROM. If the run-time configuration differs from the data set
stored in the ROM, it has to be restored after each power-up again by the external micro-processor over the SPI interface.
The following table shows the memory organization:
Non-Volatile Memory Address Range Volatile Memory Address Range Description
(Register no.)
(Register no.)
0 - 3
4 - 6
7
16 - 19
20 - 22
23
Application parameters
Trim values, factory set
Device Address (not applicable)
Chip ID, factory set
8 - 15
-
-
24 - 31
For factory test purpose. Read only.
Table 3: Memory map overview
As shown in the table above, registers 0 – 3 are used for configuring the chip in the application. Before the devices can be used in a final light-
barrier system, the required application parameters of the chip in the system have to be stored into the device memory.
The following table shows the allocation of the available parameters in the memory of the epc110:
Bit #
15
VMODE
0
14
13
MODE
0
12
0
11
1
10
0
9
0
1
8
7
6
0
5
0
4
3
2
1
0
ROM RAM
0
0
0
0
0
1
TPULSE
POL FUSEBIT
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TPER
0
DEC
INC
SENSH
0
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
Application
parameters
1
0
SENSN
2
don't use
don't use
don't use
don't use
don't use
Lot no. LSB
Lot no. MSB
Chip ID
Factory use only
Revision no.
no function
no function
no function
3
4
5
Trimming
6
7
Device Address
8
9
10
11
12
13
14
15
Chip ID
Figure 12: Detailed memory map epc110
1 The non-volatile memory is a one-time-programmable memory (OTP). Once the memory is programmed, the programmed values cannot be
overwritten anymore.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
11
Datasheet epc110 - V2.1
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epc110
Parameter settings can be done by writing complete 16 bit registers only.
Bits marked up in white fields shall be modified or programmed only. Gray marked bits with a given value in the memory map above must be
set to this. Never change the memory content of gray marked cells without numeric indication. Writing to this cells is not allowed.
The RAM can be written only, if the corresponding ROM memory hasn’t been written before (FUSEBIT = 0) or if the volatile mode is active
(VMODE = 0). The first bit of each 16-bit ROM register serves as write inhibit bit (FUSEBIT). To write to the ROM, the micro-controller has to
write the data to the RAM first (with FUSEBIT = 0). From there, the micro-controller can first double check the data integrity. When a memory
section is verified, the content can be transferred from the RAM memory to the ROM using the command PROG (refer to chapter Command
PROG). While processing this instruction the FUSEBIT will be set to “1” by epc110.
The device is fully operational as well without programming the ROM, but data will be lost at power down. Operating the chip in this mode is
helpful during the development of the product or if your application needs an adaptive mode. However, in the final application for a standalone
or self-reboot operation, the parameters must be stored into the ROM memory.
Parameter Description (epc110)
Parameter
Name
Register No.
ROM RAM
Bit No. Function
FUSEBIT
0
16
0
During write operation to this RAM register, put this bit = 0.
This bit will be set automatically, when corresponding ROM register is programmed.
0
0
1
Values
The corresponding ROM register is not programmed
The corresponding ROM register is programmed
POL
0
0
16
16
1
Polarity of the LED pulse. Setting is depending on the LED driver circuitry.
1
Values
Default
Recommended Setting
0
active low
X
1
active high
X
TPULSE
4...2
Pulse length tPulse of the light pulse
4
0
0
0
0
1
1
1
1
3
0
0
1
1
0
0
1
1
2
0
1
0
1
0
1
0
1
Values
1μs
Default
Recommended Setting
X
2μs
X (typical setting)
3μs
4μs
5μs
6μs
7μs
8μs
n/a
2
0
18
16
11...5
no function, must be set as listed below
11 10
9
8
7
6
5
1
0
0
0
0
0
0
MODE
14...12 Definition of operation mode.
14 13 12 Value
1
0
1
Fork light barrier, standalone mode:
LED pulse and light detection reading generated internally.
0
1
1
Fork light barrier, controlled mode:
Externally stimulated LED pulse by positive edge of signal on pin EN.
Externally controlled light detection by signal on pin EN=1.
x
x
x
All other settings forbidden. Function of the device not defined and guaranteed.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
12
Datasheet epc110 - V2.1
www.espros.ch
epc110
VMODE
0
16
15
Disables WRITE access to volatile RAM
11 Values Default Recommended Setting
0 On WRITE access to RAM possible.
X
1.
2.
Fix-parameter mode / Debug mode:
This setting allows to overwrite the RAM contents, which is useful during debugging.
Once the system is fully developed, this parameter should be set to “1”.
Dynamic mode:
This setting could also be useful for dynamic system application, if the system
parameters should be changed “on the fly” after power-up. It is recommended to
program the parameters and burn it into the ROM first. All deviating run-time
parameters have then to be downloaded on the fly after power-up every time.
1
Off
WRITE access to RAM denied.
Set to “1” in the final product to avoid accidentally overwriting of the contents of the RAM registers.
Parameter
Name
Register No.
ROM RAM
Bit No. Function
FUSEBIT
1
17
0
During write operation to this RAM register, put this bit = 0.
This bit will be set automatically, when corresponding ROM register is programmed.
0
0
1
Values
The corresponding ROM register is not programmed
The corresponding ROM register is programmed
n/a
1
1
17
17
2...1
no function, must be set to “0”
2
1
0
0
INC
6...3
Weight of valid pulse counts. Refer to Pulse Modulated Operation (e.g. OUTNint to OUTN):
Minimum number of valid (non-missing) pulses nV of light detection for counting the response time tR.
6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
INC
0
min. nV
Setting
1
32
16
11
8
X (Default setting)
1
2
3
4
X (typical setting)
5
7
6
6
7
5
8
4
9
4
10
11
12
13
14
15
4
3
3
3
3
3
n/a
1
17
8...7
no function, must be set to “0”
8
7
0
0
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Characteristics subject to change without notice
13
Datasheet epc110 - V2.1
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epc110
DEC
1
17
12...9 Weight of missing pulse counts. Refer to Pulse Modulated Operation (e.g. OUTNint to OUTN):
Minimum number of missing pulses nM of light detection for counting the release time (fall time) tF.
12 11 10
9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DEC Min. nM
Setting
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
32768
X (Default setting)
16384
8192
4096
2048
1024
512
256
128
64
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
16
8
X (typical setting)
4
2
1
TPER
1
17
15...13 For fork light barrier, standalone mode: LED cycle time tCycle
.
For fork light barrier, controlled mode: Select next lower value then external EN cycle time.
15 14 13
Values Default
Recommended Setting
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5μs
10μs
X
30μs
100μs
300μs
1ms
X (typical setting)
10ms
100ms
Parameter
Name
Register No.
ROM RAM
Bit No. Function
FUSEBIT
2
18
0
During write operation to this RAM register, put this bit = 0.
This bit will be set automatically, when corresponding ROM register is programmed.
0
0
1
Values
The corresponding ROM register is not programmed
The corresponding ROM register is programmed
SENSN
2
18
3...1
Lower threshold setting of the photo current sensitivity IPDN to trigger output OUTN.
3
0
0
0
0
1
1
1
1
2
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Values Default Recommended Comments
24nA
36nA
48nA
60nA
72nA
84nA
96nA
108nA
X
A lower value increases the sensitivity. A too sensitive setting leads to
false readings because of shot noise of the receiver photo diode and the
internal amplifier (typ. input noise level is 7nA RMS without photo diode).
Also induced EMI can lead to false readings if the sensitivity is set too
low. The EMI sensitivity is heavily depending on the system architecture
and the electromechanical design. The better the shielding of the chip
and the photo diode and the better the PCB layout, the better the EMI
immunity.
X
The tolerance of the threshold is approx. ±25%.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
14
Datasheet epc110 - V2.1
www.espros.ch
epc110
SENSH
2
18
6...4
Upper threshold setting of the photo current sensitivity IPDH. to trigger output OUTH.
6
5
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
Values Default Recommended Recommended Setting
0
0
0
0
1
1
1
1
60nA
72nA
X
Common use is to set this value 50% above the value used at SENSN,
i.e., if SENSN is put to 48nA, set SENSH to 72nA.
84nA
The tolerance of the threshold is approx. ±25%.
96nA
X
108nA
120nA
132nA
144nA
n/a
2
18
15...7
no function, must be set as listed below
15 14 13 12 11 10
9
8
7
0
0
0
0
1
0
1
0
1
Sample Parameter Setting
In the section “Applications“ you will find programming examples for “Long range light barrier application (refer also to datasheet epc111)“ and
for “High speed detection rate design (refer also to datasheet epc112) “.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
15
Datasheet epc110 - V2.1
www.espros.ch
epc110
SPI Interface
The serial peripheral interface (SPI) allows the micro-controller to communicate with the epc110 device. It allows the access to the internal
memory of the chip for parameter setting and programming for configuration or in a dynamic mode to change parameters on the fly.
Hardware interface
This functionality is given by double-used pins: LED/SCK, EN/SI, OUTN/SO.
The signal CS does the selection, if the operation mode or the command/program mode is active:
1. CS = 1: operation mode
2. CS = 0: command/program mode
→ LED, EN, OUTN are active.
→ SCK, SI, OUTN are active.
As long as CS = 0 the pin LED/SCK is set to high-ohmic and defined as input pin.
IMPORTANT NOTICE:
Due to fact of the advantage of the flexibility in use of this devic e the responsibility of any possible hardware, LED load or LED driver conflicts
have to be handled by the user and are depending of the final application schematic. Main items to take care of are:
•
•
•
Double-use as input as well output of LED/ SCK signals/line. For non-standalone application a well done decoupling of the signals is
needed.
Parameter setting and programming of the device in final application environment e.g. if LED and LED drivers are not designed for
continuous mode application, risk of overloading.
During SPI access of the device in final application environment e.g. if LED and LED drivers are not designed for continuous mode
application, risk of overloading.
Possible solutions are discussed at the example of the principal schematic “ Figure 13: Hardware interface micro-controller – epce110“.
VDD PROG
VLED
R5
R2
T2
VDD
R6
R8
D1
epc110
INV1
AND1
T3
VDD33
VDD18
CS
LED/SCK
EN/SI
+
T1
C1
D4
8V2
PD
OUTN/SO
OUTH
S1
R1
D2
D3
GND
V_IN
V_OUT
VDD µC
Regulator 3.3V
ADJ
VDD
µController
R7
OUT PROG
R3 T4
CS
SCK
SO
BUF1
SI
OUT ESCK
IN
R4
GND
GND
Figure 13: Hardware interface micro-controller – epce110
1. Mode selection: Operation mode - Parameter/Program mode
As long the device is not connected to an LED driver, the access to the SPI interface is allowed while CS = 0. This can simply be
done by the switch S1 before power up the circuit. In this case the output LED/ SCK will not be driven as an output.
2. Run-time access of SPI interface
To have no conflicts together with a micro-processor on the bus line LED/SCK (Output/input) during run-time operation in this
example, the decoupling and interfacing of the LED/ SCK line is done by the tristate buffer BUF1, the additional input IN and
additional output enable SCK (OUT ESCK). While the LED is in operation, driven by the epc110, OUT ESCK = 0 will tristate the
buffer and the SCK line from the micro-processor. With the input IN the micro-processor can read the status of the LED/ SCK line
after the buffer for finding the correct transition time.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
16
Datasheet epc110 - V2.1
www.espros.ch
epc110
Signal conditions and sequences:
Operation mode:
Mode transition to SPI:
Parameter/program mode:
CS = 1, SCK =1, BUF1 = tristate (OUT ESCK = 0), LED/SCK toggling by epc110.
If LED/SCK = 1: SCK =1, BUF1 = transparent (OUT ESCK = 1), CS = 0.
CS = 0, BUF1 = transparent (OUT ESCK = 1), SCK and LED/SCK toggling by micro-processor.
Mode transition to operation: If LED/SCK =1: BUF1 = tristate (OUT ESCK = 0), CS = 1.
3. Overload-protection of LED and LED driver
Are the LED and LED driver not designed for continuous mode operation, there is a risk of overloading the LED or the LED driver in
case of no decoupling of the LED driver input from the SPI interface as well from the command instructions. The signals on the line
LED/SCK are depending of the status of the SCK signal itself and from the commands polarity of LED pulse POL, pulse length
TPULSE, Mode selection MODE and the status of the line EN.
In the example circuitry this decoupling is done by the signal OUT ESCK, the inverter INV1 and the and-circuit AND1. In case of
switching the buffer BUF1 transparent (OUT ESCK =1) the LED driver signal is set to low.
4. Supply of the programming voltage (VPROG 7.5V) at pin VDD (refer also to chapter “ Programming Procedure“)
To write the data from the volatile RAM section to the non-volatile ROM section a programming voltage has to be connected to the
VDD pin of the epc110 following the timing diagram of Figure 17: Direct programming procedure.
This is done by an overwriting voltage source to the VDD pin in the proposed design. The main supply for he micro-processor and
the epc110, pin VDD33 is done by the 3.3V voltage regulator, the diode D3 and the resistors R3 and R4. Pin VDD of the epc110 is
fed by diode D2. This allows to overwrite the 3.3V operating supply by the higher 7.5V programming voltage. The programming
voltage is produced by the voltage regulator T3, D4 and R6. Switch on/off of the programming voltage will be done by the R7,T4,R5
and T2 and the signal OUT PROG.
Timing Specifications of telegrams
While CS = 0 and serial clock SCK is toggling in bi-directional function data are
–
–
on input SI read in (Command) with the positive edge and
on output SO read out (Result) with the negative edge of the serial clock.
Means whilst data are sent to the epc110 chip by the micro-controller, in parallel the result of the last (or more generally: of a previous)
command is sent back from the epc110 to the micro-controller according to the SPI protocol. The timing diagram is shown in Figure 14).
t
1
CS
t
t
1/f
t
H
rfSCK
L
SCK
SCK
SI
t
t
Hold
SU
t
t
rf
D
SO
CS
SCK
SI
Device selection
Serial input/output clock – positive edge: data read in; negative edge: data read out
Serial data input
Serial data output
SO
Figure 14: SPI bus timing
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
17
Datasheet epc110 - V2.1
www.espros.ch
epc110
Symbol Parameter
Comments / Conditions
Values
Typ.
Units
Min.
Max.
t1
Edge time CS to SCK
Falling edge CS to falling edge SCK
50
ns
MHz
ns
f SCK
tH / tL
Clock frequency of SCK
10
HIGH and LOW period of SCK
50
15
tSU / tHold Set-up and hold time of SI
tD Output data of SO valid
Data stable before and after positive edge of SCK
Data valid after negative edge of SCK
ns
20
20
ns
trf / trf SCK Rise / fall time SO / SCK
ns
Input Data Format and Command List
The communication is based on telegrams (Direct commands or results), which are sent and received over the SPI interface.
The input data format (telegram) is given in Figure 15. The first bit in the data stream from the microprocessor to the epc110 chip (SI pin) will
be B = 0 always.
CS
SCK
B
T1
T0
SI
C0
C1
C2
R0
R1
R2
R3
R4
D0
D1
Dn
Data
Register Address or Cmd Extension
Command
Figure 15: Communication to the epc110 device: Direct Command
Command set:
Name
Cmd Code
Start
B
Cmd Code
Command
C0...C2
Cmd Code
Extension
R0...R4
Cmd Code
Data
D0...D16
Cmd Code
Termination
T0, T1
Function
Result Data
No. of data bits
on SPI interface
Command / Result
NOP
0
000
---
---
---
No operation,
No
≧ 4
or read out data
READ
0
0
010
011
Register address
Register address
---
00
00
Read register Rn
Yes
No
11 / 22
27 / --
WRITE
Data
Write data to RAM
(Register 16...18)
PROG
0
0
110
111
Register address
11001
---
---
---
---
Copy data to ROM
Reset the device
No
No
9 / --
9 / --
RESET
Table 4: Command list
Remarks:
•
•
•
•
The telegram data is transmitted with the LSB first.
A telegram starts with the CS change from high to low (Synchronization) and ends with the change from low to high.
Single telegrams either commands as well results have to be separated by a CS = 1 in between.
Additional SCK clock cycles have no effect.
This allows to extend the above given minimal telegram lengths to a standardized telegram lengths (Byte, word or double-word).
•
The minimum telegram length is given in Table 3, section Number of data bits.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
18
Datasheet epc110 - V2.1
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epc110
Detailed Command & Result Descriptions
Command NOP: No operation
The command NOP can be used to fetch data without sending a new command – see next section Readout of Returned Results.
Readout of Returned Results
The results/data at output pin SO depend on the previous transmitted command to input pin SI.
Two ways to readout this data are possible:
1. Either it can be fetched in parallel of transmitting a next command
2.
or by sending NOP commands just by toggling SCK while CS is low.
Remarks:
•
•
•
The data is represented with the LSB first.
Data is valid on positive edge of clock SCK while CS is low.
If more clock toggles SCK are issued than data can be fetched, zeros are transmitted.
Command READ: Read register Rn
With the command READ the registers of the RAM and ROM memory can be read register by register.
The command extension “Register address” defines the requested register for reading it out.
After command transmission the expected result data can be readout on the SO pin.
Result readout frame (telegram):
CS
SCK
SO
N
R0
R1
R2
R3
R4
D0
Dn
Figure 16: Timing Result Data
Result data format:
Data Bits
Function
N
Not used, have to be ignored
5 bit register address
R0...R4
D0...D15
16 bit returned data of the corresponding register (one complete register)
Table 5: Result of a READ command
Command WRITE: Write to RAM register 16 - 18
Data can be written into the volatile RAM register 16 – 18 by using the command WRITE. The command extension “Register address” selects
the register. It is followed by the data to be written.
In VMOD = 1 it is possible to write to registers only, if the corresponding register in the ROM has not been written yet. It is not possible to write
directly to a ROM register. If the data has to be stored into the ROM register, a subsequent command PROG has to be used.
In VMOD = 0 the RAM registers can be written at anytime.
Command PROG
The command PROG transfers the data from the RAM register to the corresponding ROM register. See chapter Parameter Programming for a
detailed description.
Command RESET
The command RESET resets the device and initiates a startup.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
19
Datasheet epc110 - V2.1
www.espros.ch
epc110
Parameter Programming
General Description
A description of the hardware interface for programming is given in chapter “ Hardware interface“.
The device is initially not parametrized. In order to operate the light barrier, the micro-controller (or programmer) needs to do the correct
parameter settings for the selected functionality. This step is usually done in the factory of the light barrier manufacturer. After this the micro-
controller can operate the light barrier or it can work in a standalone mode.
To do so, a specific parametrization of the devices must be executed first. The following procedure is an example thereof.
No.
Step
Description
1
Set parameters
Parameters like POL, TPULSE, MODE, VMODE, INC, DEC, TPER, SENSN, SENSH are stored into the RAM
of the device using the command WRITE. Write them register by register.
2
3
4
Check
parameters
The parameters should be checked by reading them back from each device using the READ command.
Program
parameters
If all parameters are stored correctly, store the parameters into the non-volatile memory by using the command
PROG. Please refer to chapter Programming Procedure.
Final test
To check the programming of the parameters, turn off the power supply and readout all parameters again.
Programming Procedure
Programming the device is a transfer of the data from the RAM to the corresponding ROM register. Each 16-bit register must be transferred
individually. Thus, register 16 is transferred to register 0, register 17 to register 1, register 18 to register 2. All other registers must not be used.
Figure 12 shows the timing of the programming sequence for one register:
50μs
400μs
7.5V
3.3V
VDD
CS
SCK
SI
1
1
0
R0 R1 R2
R4
R3
B
PROG
Register
Figure 17: Direct programming procedure
“PROG” is the PROG command sequence (110). “Register” means the address of the target register (ROM), e.g. 0, 1, 2.
During programming the voltage at pin VDD has to be increased to VPROG (7.5V) and has to be kept stable buffered during the whole
programming cycle. For an example of a hardware design to generate this supply refer to chapter “Hardware interface“ in the SPI interface
section.
The timing parameters given in Figure 17 have to be obeyed.
Remarks:
•
It is possible to program more than one register during a VDD high cycle. Between two PROG commands a delay of 400μs is
needed.
•
•
Each register can be programmed once only (ROM).
After programming a register, bit no. 0 of this register becomes automatically a one to indicate that the register is programmed
(FUSEBIT).
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
20
Datasheet epc110 - V2.1
www.espros.ch
epc110
Applications
Long range light barrier application (refer also to datasheet epc111)
Figure 18 shows the epc110 as an example in a long range light barrier application with minimal part count. The LED flashes according to the
description of the previous chapter. Light of the LED is passing either direct, reflecting from a reflecting object or a retro reflector to the photo
diode PD. If the received light fulfills the criteria according to the description in the previous chapter, the output signals OUTN and OUTH are
set.
LED Driver:
The output LED of the epc110 to drive the LED driver circuit is a current source capable to drive typically 1mA. For a high performance long
range light barrier (>8m), an LED peak current of up to 1.5A is needed. To generate such a high LED current, an external driver circuit is
necessary. The circuitry in Figure 18 is a simple implementation of such a driver circuit. The darlington circuit with T2 and T3 and R2 and R3
does the job. In order to avoid interference on the supply voltage, the supply is isolated (filtered) with R1 and C1. The high peak LED pulse
current is delivered by the capacitor C1, which itself is charged by R1. Make sure, that there is no coupling of the high LED current to the
ground of the epc110 or to the cathode of the photo diode. This driver circuit operates with a VDD LED in a range of 10 to 30 VDC.
+3.3V
VDD = +24V
LED
C2 1μF
R1
100R
C3 100nF
R4
R8
10k
10k
R6
IR LED
12k
TSML1000
VDD
C4 100nF
epc110
R5
3k6
T1
VDD33
VDD18
PD
C5 4.7nF
BC846
T2
BC846
LED
T3
BCP56
OUTN
OUTH
C1
47μF
Low ESR
GND
PD
epc300
R2
1k
R7
4k7
R3
1R2
GND
OUTN
OUTH
Marked conductors must be short and low ohmic
C2
The epc111 device with its very sensitive input PD needs a well decoupled power supply
Figure 18: Long range light barrier application with minimal part count
Notice:
The schematic is for illustrating the basic circuit idea only. For the real built up the designer has to take all other additional influence factors in
consideration too e.g. design rules, power rating, heat dissipation, ...
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ROM RAM
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
1
1
0
1
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Application
parameters
2
don't use
don't use
don't use
don't use
don't use
Lot no. LSB
Lot no. MSB
Chip ID
Factory use only
Revision no.
no function
no function
no function
3
4
5
Trimming
6
7
Device Address
8
9
10
11
12
13
14
15
Chip ID
Figure 19: Corresponding memory map epc110 “Long range”
Parameter settings can be done by writing complete 16 bit registers only.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
21
Datasheet epc110 - V2.1
www.espros.ch
epc110
High speed detection rate design (refer also to datasheet epc112)
Figure 20 shows the epc 110 as an example in a high speed detection rate light barrier application with minimal part count. This design is
optimized for a fast reading of light beam interruptions. Where as the working principle is similar to the above example. This driver circuit
operates with a VDDLED in a range of 6 to 20 VDC.
VDD = +12V
+3.3V
LED
C2 1μF
C3 100nF
R1
47R
R3
R7
10k
10k
R5
12k
VDD
C4 100nF
C5 4.7nF
IR LED
TSML1000
epc110
R4
3k6
T2
BC846B
VDD33
VDD18
PD
T1
BC846B
LED
OUTN
OUTH
C1
10μF
Low ESR
GND
PD
epc300
R6
4k7
R2
13R
GND
OUTN
OUTH
Marked conductors must be short and low ohmic
C2
The epc112 device with its very sensitive input PD needs a well decoupled power supply
Figure 20: High speed detection rate light barrier application with minimal part count
Notice:
The schematic is for illustrating the basic circuit idea only. For the real built up the designer has to take all other additional influence factors in
consideration too e.g. design rules, power rating, heat dissipation, ...
The following table shows the parameter allocation in the memory:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ROM RAM
1
0
0
1
0
0
0
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
1
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
FUSEBIT
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Application
parameters
2
don't use
don't use
don't use
don't use
don't use
Lot no. LSB
Lot no. MSB
Chip ID
Factory use only
Revision no.
no function
no function
no function
3
4
5
Trimming
6
7
Device Address
8
9
10
11
12
13
14
15
Chip ID
Figure 21: Detailed memory map epc110 “High speed”
Parameter settings can be done by writing complete 16 bit registers only.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
22
Datasheet epc110 - V2.1
www.espros.ch
epc110
Design Precautions: EMC shielding
The sensitivity at pin PD is very high in order to achieve a long operation range of light barriers even without
lenses in front of the IR LED and/or the photo diode. Thus, the pin PD is very sensitive to EMI. Special care
should be taken to keep the PCB track at pin PD as short as possible (a few mm only!). This track should be
kept away from the IR LED signal tracks and from other sources which may induce unwanted signals. It is
strongly recommended to cover the chip, the photodiode and all passive components around the chip with a
metal shield. A recommended part is shown in Figure 22. The pins at the bottom are to solder the shield to
the PCB with electrical connection to GND. The hole in the front is the opening window for the photo diode.
The backside of the PCB below the sensitive area (PD, epc110) shall be a polygon connected to GND to
shield the circuit from the backside as well.
Figure 22: Recommended EMC
shield
Ambient Light
Photodiode DC current can be generated by ambient light, e.g. sunlight. DC current at pin PD does not generate a DC output signal. However,
if IPDDC is above the stated maximal value, the input is saturated. This blocks the detection of AC current pulses.
Photodiode Capacitance
If the photo diode capacity is above the specified value, a lower detection sensitivity and a possible higher sensitivity spread results.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
23
Datasheet epc110 - V2.1
www.espros.ch
epc110
Layout Information (all measures in mm,
)
CSP-10 Package
1.9 +0.0/-0.1
∅ 0.3
0.1524
∅ 0.12
Bottom View
Pin 1
0.5
0.5
Solder balls Sn97.5Ag2.5
0.15
0.5
0.5
2.5
no solder mask inside this area
Figure 23: CSP10: Mechanical dimensions
Recommendations for reliable soldering of solder balls:
Figure 24: CSP10: Layout recommendation
•
•
•
Use a pad layout similar as given in Figure 24. Notice that all tracks should go underneath the solder mask area.
Do not connect any pins direct pin to pin inside of the opening of the solder mask.
In case of the conductors are with a Au-Ni surface finish the preferred landing pad design for the solder balls will be covering the
round landing pad with a gold surface finish as a solderable area only.
QFN-16 Package
Opening in solder mask
Conductor layout
1 0
1 1
9
1 2
NC_GND
NC_GND
LED/SCK
EN/SI
GND
Top View
PD
NC_GND
NC_GND
Shielding of PD pin
1
2
4
3
Figure 25: QFN-16: Layout recommendation
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
24
Datasheet epc110 - V2.1
www.espros.ch
epc110
1.9
Bottom View
Top view
0.5
0.25
2.9 - 3.1
0.3
Figure 26: QFN-16: Mechanical dimensions
Reflow Solder Profile
For infrared or conventional soldering the solder profile has to follow the recommendations of IPC/JEDEC J-STD-020C (min. revision C) for
Pb-free assembly for both types of packages. The peak soldering t emperature (TL) should not exceed +260°C for a maximum of 4 sec.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
25
Datasheet epc110 - V2.1
www.espros.ch
epc110
Packaging Information (all measures in mm)
Tape & Reel Information
The devices are mounted on embossed tape for automatic placement systems. The tape is wound on 178 mm (7 inch) or 330 mm (13 inch)
reels and individually packaged for shipment. General tape-and-reel specification data are available in a separate data sheet and indicate the
tape sizes for various package types. Further tape-and-reel specifications can be found in the Electronic Industries Association (EIA) standard
481-1, 481-2, 481-3.
CSP6 Tape
QFN16 Tape
Pin 1
Pin 1
4
8
Figure 27: CSP10 and QFN16 Tape Dimension. Parts are placed with solder pads on bottom side
ESPROS Photonics AG does not guarantee that there are no empty cavities. Thus, the pick-and-place machine should check the presence of
a chip during picking.
Ordering Information
Type
Package
CSP10
QFN16
RoHS compliance Packaging Method
epc110-CSP10
epc110-QFN16
Yes
Yes
Reel
Reel
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
26
Datasheet epc110 - V2.1
www.espros.ch
epc110
IMPORTANT NOTICE
ESPROS Photonics AG and its subsidiaries (epc) reserve the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the
latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject
to epc’s terms and conditions of sale supplied at the time of order acknowledgment.
epc warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with epc’s standard war-
ranty. Testing and other quality control techniques are used to the extent epc deems necessary to support this warranty. Except where man-
dated by government requirements, testing of all parameters of each product is not necessarily performed.
epc assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications
using epc components. To minimize the risks associated with customer products and applications, customers should provide adequate design
and operating safeguards.
epc does not warrant or represent that any license, either express or implied, is granted under any epc patent right, copyright, mask work
right, or other epc intellectual property right relating to any combination, machine, or process in which epc products or services are used.
Information published by epc regarding third-party products or services does not constitute a license from epc to use such products or
services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other
intellectual property of the third party, or a license from epc under the patents or other intellectual property of epc.
Resale of epc products or services with statements different from or beyond the parameters stated by epc for that product or service voids all
express and any implied warranties for the associated epc product or service. epc is not responsible or liable for any such statements.
epc products are not authorized for use in safety-critical applications (such as life support) where a failure of the epc product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically
governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,
and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of epc products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by epc. Further, Buyers must fully indemnify epc and its representatives against any damages arising out of the use of epc products
in such safety-critical applications.
epc products are neither designed nor intended for use in military/aerospace applications or environments unless the epc products are spe-
cifically designated by epc as military-grade or "enhanced plastic." Only products designated by epc as military-grade meet military specific-
ations. Buyers acknowledge and agree that any such use of epc products which epc has not designated as military-grade is solely at the
Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
epc products are neither designed nor intended for use in automotive applications or environments unless the specific epc products are desig-
nated by epc as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in
automotive applications, epc will not be responsible for any failure to meet such requirements.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
27
Datasheet epc110 - V2.1
www.espros.ch
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