PBA3357/3 [ERICSSON]
PCM Codec, 2-Func, PDIP49, 34.40 X 71.10 MM, DIP-56/49;
| 型号： | PBA3357/3 |
| 厂家： | 
ERICSSON |
| 描述： | PCM Codec, 2-Func, PDIP49, 34.40 X 71.10 MM, DIP-56/49 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总16页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1997
PBA 3357/3
Dual Channel Complete Line
Interface Circuit, DCLIC
Description
Key Features
The PBA 3357/3 is a Dual Channel Complete Line Interface Circuit (DCLIC)
manufactured in thick-film technology.
•
Constant Current
DC performance at VBAT=-40,0 V
The PBA 3357/3 Dual CLIC consists of two Ericsson SLIC´s, two Combo 1 Codecs
and all other necessary components to interface two seperate analogue extensions to
the PCM highway.
ILDC=min 17.3 mA at RLOOP=1800 Ω
•
Two Software programmable receive
gain ranges: (-3.5/-7.0) or
(0/-3.5) dBr. Software receive
gain range is selectable via
hardware wiring
•
•
Simple serial control interface, 8 bit
50
GV1A
Controlled Power-on state:
Open circuit, Receive channel off
and all realys inactive
5
6
51
56
52
54
55
53
RT A
C
GV2A
TSXA
FSA
RingTrip
Net w ork
RTRIPA
SLIC
A
9
8
RINGXA
TIPXA
•
•
•
•
Polarity reversal
v
Recei e
COMBO
A
MCLKA
DXA
Gain
7
Receive channel can be turned off
On-Hook Transmission
RRLYA
Receive
Channel
On/Off
Relay
Driver
14
TESTRLYA
DRA
48
Three relay drivers/line;
a total of six relay drivers
DETA
44
18
45
16
SCLKA
SDIB
•
Terminating impedance
ZTR=200 Ω+ (680 Ω // 100 nF)
LCLKA
15
42
Relay
Driver
Control
RLYA
RLYB
•
•
•
Longitudinal balance; typ 60 dB
Nominal VBAT= - 48 V
SCLKB
LCLKB
Interface 17
Relay
Driver
(ASIC)
46
SDIA
Few additional external
componets needed
•
Small physical size: 34.4 x 71.1 mm
20
DETB
Receive
Channel
On/Off
41
39
25
27
TESTRLYB
RRLYB
TIPXB
DRB
DXB
Relay
Driver
COMBO
26
36
37
Receive
Gain
MCLKB
FSB
B
24
SLIC
RINGXB
RTRIPB
RTCB
B
28
34
33
Ring Trip
TSXB
GV2B
GV1B
Networ
k
23
22
1,10,29,35,38
GND
2,30
VEE
VCC
12,31
4,11,32,40
VBAT
Figure 1: Block Diagram
4-1
PBA 3357/3
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature
Storage temperature range
Power Supply
Tstg
-40
+125
°C
Positive Supply voltage with respect to Ground (GND)
Negative Supply voltage with respect to Ground
Battery voltage with respect to Ground
VCC
VEE
VBAT
-0,4
-6,5
-70
+6,5
+0,4
+0,4
V
V
V
Ring Relay Driver
Relay Supply voltage
Current
VRRLY
IRRLY
VBAT
VBAT
-30
VCC
80
V
mA
Test Relay Driver
Relay Supply voltage
Current
VTRLY
ITRLY
VCC
80
V
mA
Additional Relay Driver
Relay Supply voltage
Current
VRLY
IRLY
VCC
70
V
mA
TIPX and RINGX terminals
Voltage (each terminal), Continous (with respect to GND)
Voltage (each terminal), Pulse tON < 10 ms. tREP>10 s, (Note 1)
Voltage (each terminal), Pulse tON < 1 µs. tREP>10 s, (Note 1)
Voltage (each terminal), Pulse tON < 250 ns. tREP>10 s, (Note 1)
Current (each terminal)
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA -120
IDCMET
-70
-70
-90
1
5
10
15
105
V
V
V
V
mA
-105
Recommended Operating Conditions
Parameter
Symbol
Min
Typical
Max
Unit
Temperature
Ambient temperature range, Operating
Ambient temperature range, Test
Tamb
Tamb
0
+70
°C
°C
+23
Power Supply
Positive Supply voltage with respect to Ground (GND)
Negative Supply voltage with respect to Ground
Batteryvoltage with respect to Ground
VCC
VEE
VBAT
+4,75
-5,25
-56
+5 +5,25
-5 -4,75
V
V
V
-48
-44
Electrical Characteristics
Tamb = 0 - 70 °C, VCC= +5 V ± 5 %, VEE=-5 V ± 5 %, VBAT=-44 - -56 V, RLDC= 600 Ω, ZN=200 Ω+ (680 Ω//100 nF) See also fig 7
Parameter
Condition
Min
Typical
Max
Unit
Battery Feed Characteristics
Line Current
Line Current
Line Voltage
RL ≤ 1800 Ω
RL = 1800 Ω, VBAT= -40V
RL = ∞ Ω, VBAT= -48 V
18,0
17,3
35
28,0
39
mA
mA
V
Battery Feed Characteristics, Polarity Reversad
Line Current
Line Current
Line Voltage
RL ≤1800 Ω
RL = 1800 Ω, VBAT= -40V
RL = ∞ Ω, VBAT= -48 V
-28,0
-39
-18,0
-17,3
-35
mA
mA
V
4-2
PBA 3357/3
Electrical Characteristics cont.
Parameter
Condition
Min
Typical
Max
Unit
Loop Current Detector
Loop Resistance RL
Loop Resistance RL
Loop Resistance RL
Loop Resistance RL
Off hook Detection delay time
Dial Pulse Distortion, (Note 6)
Active, DET output High ("1")
Stand-by, DET output High ("1")
Active, DET output Low ("0")
Stand-by, DET output Low ("0")
-
20
20
kΩ
kΩ
kΩ
kΩ
ms
ms
2,3
2,3
100
10
10 pulses/s,
-10
0
Period 1000 ± 100 ms, (Note 2)
Ring Trip Detector, (Note 6)
Delay time from Off hook ringing to
detection. DET from High to Low
DET minimum output low, "0" time
RL = 1800 Ω, URG= 60 V
150
ms
ms
-
20
30
Ring Relay Driver
On-state Voltage
IOL= 25 mA
IOL= 25 mA
(VCC-2,0) (VCC-1,8)
(VCC-2,0) (VCC-1,8)
(VCC-1,0)
V
V
V
Test Relay Driver
On-state Voltage
Additonal Relay Driver
On-state Voltage
IOL= 25 mA
Power Dissipation per Line
VBAT = - 48 V
Active (Off hook)
Active (Off hook)
Stand-By (On hook) (Note 5)
Active (On hook), (Note 5)
RL= 500 Ω
RL= 0 Ω
RL ≥ 20 kΩ
RL ≥ 20 kΩ
1300
1600
360
mW
mW
mW
mW
400
Gain, Absolute
The absolute reference level at the
2-wire interface, 0 dBm0
P= 1mW, ZTR= 200Ω+(680Ω//100nF)
f= 1014 Hz
0,9008
VRMS
Transmit (A-D), Li=0,0 dBr
Receive (D-A), Lo= 0,0 dBr
Receive (D-A), Lo= -3,5 dBr
Receive (D-A), Lo= -7,0 dBr
Receive (D-A) cancellation
f= 1014 Hz, Level: -10 dBm0
f= 1014 Hz, Level: -10 dBm0
f= 1014 Hz, Level: -10 dBm0
f= 1014 Hz, Level: -10 dBm0
f= 1014 Hz, Level: -10 dBm0
-0,3
-0,4
-3,9
-7,4
0,0 +0,4
0,0 +0,3
dB
dB
dB
dB
dB
-3,5
-7,0
-3,2
-6,7
-50
Attenuation / Frequency Distortion
Transmit connection (A-D)
(CCITT Q552 3.1.1.5)
Reference:
f = 1014 Hz = 200-300 Hz
f = 300-400 Hz
-0,3
-0,3
-0,3
-0,3
-0,3
-0,3
0,0
-
dB
dB
dB
dB
dB
dB
0,0 +1,0
0,0 +0,75
0,0 +0,35
0,0 +0,55
0,0 +1,5
f = 400-600 Hz
f = 600-2400 Hz
f = 2400-3000 Hz
f = 3000-3400 Hz
Receive connection (D-A)
(CCITT Q552 3.1.1.5)
Reference:
f = 1014 Hz
f = 200-400 Hz
f = 400-600 Hz
f = 600-2400 Hz
f = 2400-3000 Hz
f = 3000-3400 Hz
-0,3
-0,3
-0,3
-0,3
-0,3
0,0 +1,0
0,0 +0,75
0,0 +0,35
0,0 +0,55
0,0 +1,5
dB
dB
dB
dB
dB
4-3
PBA 3357/3
Electrical Characteristics cont.
Parameter
Condition
Min
Typical
Max
Unit
Variation of Gain with Input Level, (Note 7)
Transmit (A-D) and
Receive (D-A) connection
(CCITT Q552 3.1.1.4)
Reference: f = 1014 Hz, Level -10 dBm0
Input level = -55 to -50 dBm0
Input level = -50 to -40 dBm0
Input level = -40 to -3 dBm0
Input level = -3 to +3 dBm0
Input level = +3 dBm0,
-1,5
-0,5
-0,3
-0,5
-2,5
0,0
0,0
0,0
0,0
0,0
+1,5
+0,5
+0,3
+0,5
+2,5
dB
dB
dB
dB
dB
VBAT= - 44V RL= 1800Ω
Signal to Total Distortion, (Note 7)
Transmit (A-D) connection
(CCITT Q552 3.3.3)
Li = 0 dBr
Input level = -45 dBm0
Input level = -40 dBm0
Input level = -30 dBm0
Input level = -20 dBm0
Input level = -10 dBm0
Input level = 0 dBm0
19,9
24,9
32,9
35,0
35,0
35,0
dB
dB
dB
dB
dB
dB
Receive (D-A) connection
(CCITT Q552 3.3.3)
Lo = 0 dBr
Input level = -45 dBm0
Input level = -40 dBm0
Input level = -30 dBm0
Input level = -20 dBm0
Input level = -10 dBm0
Input level = 0 dBm0
19,9
24,9
32,9
35,0
35,0
35,0
dB
dB
dB
dB
dB
dB
Receive (D-A) connection
(CCITT Q552 3.3.3)
Lo = -3,5 dBr
Input level = -45 dBm0
Input level = -40 dBm0
Input level = -30 dBm0
Input level = -20 dBm0
Input level = -10 dBm0
Input level = 0 dBm0
18,5
23,2
31,2
34,4
35,0
35,0
dB
dB
dB
dB
dB
dB
Receive (D-A) connection
(CCITT Q552 3.3.3)
Lo = -7,0 dBr
Input level = -45 dBm0
Input level = -40 dBm0
Input level = -30 dBm0
Input level = -20 dBm0
Input level = -10 dBm0
Input level = 0 dBm0
14,5
19,5
28,8
33,8
35,0
35,0
dB
dB
dB
dB
dB
dB
Idle Channel Noise, (CCITT Q552 3.3.2)(Note 8)
Transmit (A-D) connection
Receive (D-A) connection
Li = 0 dBr
Lo = 0, -3,5 or -7,0 dBr
-66 dBm0p
-70 dBm0p
Power Supply Rejection Ratio (PSRR)
VCC to Analog Interface
f= 50 to 4000 Hz
f= 50 to 4000 Hz
f= 50 to 4000 Hz
35
10
25
dB
dB
dB
VEE to Analog Interface
VBAT to Analog Interface
4-4
PBA 3357/3
Electrical Characteristics cont.
Parameter
Condition
Min
Typical
Max
Unit
Impedance
Nominal Impedance, ZTR
ZTR = 200 Ω + (680 Ω // 100 nF)
Return Loss
Note 3
(CCITT Q552 2.1.1.2)
f= 300 Hz
f= 500 to 2000 Hz
f= 3400 Hz
14
18
14
30
35
30
dB
dB
dB
Longitudinal Balance, L-T
(CCITT Q552 2.2.2)
f= 300 to 600 Hz
f= 600 to 3400 Hz
40
46
60
60
dB
dB
Terminal Balance Return Loss, TBRL
(CCITT Q552 3.1.8.1)
Note 4
f= 300 Hz
f= 500 to 2500 Hz
f= 3400 Hz
16
20
16
20
30
20
dB
dB
dB
Stability Balance Return Loss,SBRL
Only applicable when Lo = -3,5 or -7 dBr
ZN="Worst Terminating condition
encountered in normal operation"
Open Circuit, f = 200 to 3600 Hz
Short Circuit, f = 200 to 3600 Hz
2,0
2,0
dB
dB
Outband Signalling
Transmit (A-D) connection
(CCITT Q552 3.1.6)
Input level: -25 dBm0
f= 4600 to 72000 Hz
In-band signal
-50
dBm0
dBm0
Receive (D-A) connection, (Note 7)
(CCITT Q552 3.1.7)
Input level: 0 dBm0
f= 300 to 3400 Hz
Out-band signal (f= 4600 - 72000 Hz)
-25
Intermodulation
Crosstalk
2nd or 3rd order, 4-tone, A-D
2nd or 3rd order, 4-tone, D-A
-41
-41
dB
dB
Input Crosstalk
Output Crosstalk
CCITT Q552 3.1.4.1 (far-end) FEXT
CCITT Q552 3.1.4.2 (far-end) FEXT
-70
-73
dBm0
dBm0
Digital Inputs
Input Low voltage
Inputs: SDI, SCLK, LCLK
Other Inputs
Inputs: SDI, SCLK, LCLK
Other Inputs
0,0
0,0
2,0
2,2
0,8
0,6
VCC
VCC
V
V
V
V
Input High voltage
Input Low current
Input High current
Inputs: SDI, SCLK, LCLK
Other Inputs
Inputs: SDI, SCLK, LCLK
Other Inputs
-20
-10
-20
-10
+20
+10
+20
+10
µA
µA
µA
µA
4-5
PBA 3357/3
Electrical Characteristics cont.
Ref
Parameter
fig
Symbol
Min
Typical Max
Unit
Timing Specification
Frequency of Master Clock, MCLK
Width of Master Clock High
Width of Master Clock Low
Rise time of Master Clock
Fall time of Master Clock
2
2
2
2
2
1/TPM
tWMH
tWML
tRM
2,037 2,048 2,062 MHz
160
160
ns
ns
ns
ns
50
50
tFM
Delay time to valid Data from FS or MCLK,
whichever comes later and Delay time from
FS to Data output disabled
3
tDZF
20
50
165
ns
Delay time from MCLK High to Data output Disabled
2
tDZC
tSDB
tHBD
165
ns
Setup time from DR valid to MCLK, Low
Hold time from MCLK Low to DR Invalid
3
3
50
50
ns
ns
Holding time from BIT Clock Low to the Frame Sync (FS)
3
tHBF
0
ns
Setup time from Frame Sync to BIT Clock
Hold time from 3rd period of BIT Clock
Low to Frame Sync (FS)
3
3
tSFB
tHBFI
80
100
ns
ns
Delay time from MCLK High to Data valid
Setup time from FS to MCLK Low
2
2
tDBD
tSF
0
80
180
ns
ns
Hold time from FS Low to MCLK Low
Delay time TSX Low
2
2
tHF
tXDP
100
ns
ns
140
15
Propagation Delay
4
4
4
4
4
tpLH
tSDS
thSL
thLS
thSD
ns
ns
ns
ns
ns
Min. Setup time SDI-SCLK
Min. Hold time SCLK-LCLK
Hold time LCLK-SCLK
Min. Hold time, SCLK-SDI
5
5
5
5
200
Notes
1. Requires DBAT; see Figure 6.
2. Dial Pulse Distortion at the DET
output. Pulse tone: 8-14 pulses/s,
40 to 77 % duty factor for in-out
application of a external resistance
(200 - 1800 Ω) on the two-wire
terminal.
Hz up to 20 dB @ 500 Hz and falling
log scale from 20 dB @ 2000 Hz
down to 16 dB @ 3400 Hz.
7. At VBAT = -44 V and RLDC = 1800Ω the
SLIC has start to saturate. This will
effect some transmission parameters,
for high signal levels.(> -10dBm0).
5. Power dissipation is measured for
both channels at the same time and
divided by two.
8. The noise increase when the
saturation guard becomes active
arround RLDC ≥1400 Ω but is still
better than CCITT Q552.3.3.2..
3. Rising log scale from 14 dB @ 300
Hz up to 18 dB @ 500 Hz and falling
log scale from 18 dB @ 2000 Hz
down to 14 dB @ 3400 Hz.
6. The state during the pause of the
ringing cadence or pulse dialling
shall be active.
4. Rising log scale from 16 dB @ 300
4-6
PBA 3357/3
Reference Figures
t
XDP
TSX
t
RM
t
t
t
t
T
WML
WMH
3
PM
FM
DZC
8
1
4
5
t
6
7
2
MCLK
FS
t
HOLD
t
HF
t
t
DZC
SF
DBD
2
2
3
3
4
4
5
6
6
8
DX
DR
1
7
7
1
8
5
Figure 2. Short Frame Sync Timing diagram.
3
1
4
5
6
7
8
2
MCLK
t
t
SFB
HBFI
t
FS
DZF
t
HBF
DX
DR
2
2
3
4
4
5
t
6
8
1
7
7
t
t
HBD
SDB
3
HBD
8
1
6
5
Figure 3. Long Frame Sync Timing diagram.
t
t
T
W
W
SCKL
t
t
t
t
SDS
HLS
HDS
HLS
D7
D5
D2
D1
D0
SDI
D6
D4
D3
LCLK
Figure 4. Control Timing diagram.
4-7
PBA 3357/3
56 55 54 53 52 51 50
48
46 45 44
42 41 40 39
36 35 34 33 32 31 30 29
1
2
4
5
6
7
8
9
10 11 12
14 15 16 17 18
20
22 23 24 25 26 27 28
Figure 5. Pin-configuration, 56 pin DIL.
Pin Description
Pin
Symbol
Description
1
2
3
GND
VEE
Ground.
Negative Supply Voltage, - 5V, for the CLIC.
Omitted Pin.
4
5
VBAT
RTC
Battery Voltage, - 48 V to the CLIC.
A ring Trip filter Capacitor input for Channel A. For standard performance of the CLIC, leave the
pin open.
6
7
RTRIP A
RRLY A
Ring Trip network input for Channel A. Connect to the resistor RRT A. The resistor RRT A causes
a voltage drop when Off-hook occurs during ringing. The voltage will cause a change of state in
DET A.
Ring Relay driver output for Channel A. The output is Open-collector, with a Kick-back diode
included, designed to be connected to a negative voltage.
8
TIPX A
RINGX A
GND
Tip lead input for Channel A to the CLIC from the subscriber line (two-wire).
Ring lead input for Channel A to the CLIC from the subscriber line (two-wire).
Ground.
9
10
11
12
13
14
VBAT
Battery Voltage, - 48 V to the CLIC.
VCC
Positive Supply Voltage, + 5V, for the CLIC.
Omitted pin.
TRLY A
RLY A
Test Relay driver output for Channel A. The output is Open-collector, with a Kick-back diode
included, designed to be connected to a negative voltage.
15
Additional Relay driver output for Channel A. The output is Open-collector, with a Kick-back diode
included, designed to be connected to a negative voltage.
16
17
SCLK B
LCLK B
Serial Clock for Channel B. Clocks data into the shift-register on low-to-high transitions (edge)
Latch Clock for Channel B. Latches the data in the shift-register out on the eight parallell output
bits on low-to-high transition (edge).
18
19
20
SDI B
Serial Data Input for Channel B.
Omitted pin.
DET B
Detector output for Channel B. The output is a Open-collector with internal pull-up resistor to VCC.
4-8
PBA 3357/3
Pin Description cont.
Pin
Symbol
Description
21
22
Omitted pin.
GV1 B
Gain Value for Channel B. For a receive gain of 0 to -3,5 dBr, GV1 and GV2 are connected togehter. For
a receive gain of -3,5 to -7,0 dBr, GV1 and GV2 shall be left open.
23
24
25
26
27
28
29
30
31
32
33
34
GV2 B
FS B
see GV1 B.
Frame Sync for Channel B; Transmit and Receive.
PCM Receive Data Input for Channel B.
DR B
MCLK B
DX B
TSX B
GND
Master Clock for Channel B.
PCM Transmit data Output for Channel B; Tri-state.
Time Slot for Channel B; Open-drain. Output pulse low during encoding.
Ground.
VEE
Negative Supply Voltage, - 5V, for the CLIC.
Positive Supply Voltage, + 5V, for the CLIC.
Battery Voltage, - 48 V to the CLIC.
VCC
VBAT
RTC B
RTRIP B
Ring Trip filter Capacitor input for Channel B. For standard performance of the CLIC, leave the pin open.
Ring Trip network input for Channel B. Connect to the resistor RRT B. The resistor RRT B causes a
voltage drop when Off-hook occurs during ringing. The voltage will cause a change of state in DET B.
35
36
37
38
39
GND
Ground.
TIPX B
RINGX B
GND
Tip lead input for Channel B to the CLIC from the subscriber line (two-wire).
Ring lead input for Channel B to the CLIC from the subscriber line (two-wire).
Ground.
RRLY B
Ring Relay driver output for Channel B. The output is Open-collector, with a Kick-back diode included,
designed to be connected to a negative voltage.
40
41
VBAT
Battery Voltage, - 48 V to the CLIC.
TRLY B
Test Relay driver output for Channel B. The output is Open-collector, with a Kick-back diode included,
designed to be connected to a negative voltage.
42
RLY B
Additional Relay driver output for Channel B. The output is Open-collector, with a Kick-back diode
included, designed to be connected to a negative voltage.
43
44
45
Omitted pin.
SCLK A
LCLK A
Serial Clock for Channel A. Clocks data into the shift-register on low-to-high transitions (edge).
Latch Clock for Channel A. Latches the data in the shift-register out on the eight parallell output bits on
low-to-high transition (edge).
46
47
48
49
50
SDI A
DET A
GV1 A
Serial Data Input for Channel A.
Omitted pin.
Detector output for Channel A. The output is a Open-collector with internal pull-up resistor to VCC.
Omitted pin.
Gain Value for Channel A For a receive gain of 0 to -3,5 dBr, GV1 and GV2 are connected togehter. For a
receive gain of -3,5 to -7,0 dBr, GV1 and GV2 shall be left open.
51
52
53
54
55
56
GV2 A
FS A
see GV1 A.
Frame Sync for Channel A Transmit and Receive.
PCM Receive Data Input for Channel A.
Master Clock for Channel A.
DR A
MCLK A
DX A
PCM Transmit data Output for Channel A; Tri-state.
Time Slot for Channel A; Open-drain. Output pulse low during encoding.
TSX A
4-9
PBA 3357/3
Over Voltage Protection
Since all flip-flops in the circuit is
Functional Description and
Applications Information
initually set to zero, it is recommended to
avoid to start with ’FF’, which is the only
single word enable to open the circuit.
The CLIC must be protected against
surge voltages and power cross
conditions.
In figure 6, the line resistors with fuse
function, RF1 and RF2, PTC:s, together
with the voltage clamping device OVPD
form the secondary protection. The PTC
acts as a resettable fuse for non
destructive power contact.
The protection network in figure 6 is
designed to meet requirements in CCITT
k20, Table 1.
If overvoltages with a magnitude
higher than CCITT k20, Table 1, is
expected, a primary protection is
required. A Gas Discharge Tube is
recommended.
ZBAT protects against overvoltage on
VBAT and ensure that the OVP-device
can trigger if the -48V should not be
connected
The capacitor CG Between ground and
the OVP-device should be as close as
possible to the OVP-device.
The OVP-device ground connector
should be as close as possible to the
CLIC ground connector.
General
The PBA 3357/3 is a Dual Complete
Line Interface Circuit. Only a small
number of additional external
components are required.
In case of a requirement for test of the
subscriber line and system, two relays
per line will be needed.
In figure 6 they are relay RL1, RL2,
RL4 and RL5. One ring relay per
channel will be needed to apply the ring
signal to the subscriber line (RL3 and
RL6).
TTL or CMOS use
The integrated circuits of the interface
are LSTTL or CMOS. CMOS use need
specific attention during the board
insertion under back panel power on
condition.
Power-up Sequence
The optimum power-up sequence, in
order to avoid any problem, is: Ground,
VBAT (-48 V), VEE (- 5 V) and VCC (+ 5 V)
in stated order.
If it is not possible to control the
power-up sequence , the following
design must be used:
Ring Trip
The ring trip function has been designed
to the following conditions:
1. 6,2 V Zener diode DVCC, DVEE2
:
•
Unbalanced ringing super-
imposed on the battery voltage.
The zener diodes will protect all +5 V
and -5 V IC´s on the linecard from
overvoltage if Ground being
connected after VCC/VEE and
VBAT.in the power-up sequence.
•
Ring generator data:
Output typical 75 VRMS
min 60 VRMS, max 90 VRMS
Impedance min 20 Ω, max 40 Ω
Frequency typ 25 ± 3 Hz
This due to the voltage dividing
between the decoupling capacitors on
the line card.
•
•
Loop Resistance <1800 Ω
Grounding
On-hook impedance @ 25 Hz
(Ringing signal) is 7,5 to 18 k Ω
One, two or three POT’s (Plain
2. Schottky diode DVEE1
:
The ”grounds”; GND’s shall be tied
together as close as possible; i.e. in one
point on the PCB.
The different ground points on the
linecard shall also be connected
together into one point.
GND should be distributed with a very
low impedance as a ground plane or a
grid in order to sink the overvoltage
current with low voltage drops between
the connectors of the component.
The schottky diode, with low forward
voltage drop, will protect all -5 V IC’s
on the linecard from reverse voltage if
Ground is connected after VEE and
Ordinary Telephone or equal) in parallell
on each line.
In order to sense off-hook during
ringing, two resistors per line is required;
RRT and RRG.
V
BAT.in the power-up sequence.
This due to the voltage dividing
between the decoupling capacitors on
the line card.
They should be 240 Ω, min 2 W.
Note: RRT and RRG must fulfill CCITT
k20. Lightning Surge.
The CLIC state during the pause of
the ringing cadence shall be active due
to longer stabilization time in stand-by
state.
3. Resistor RVEE
:
The resistor will reduce the charging
current into the decoupling capacitors
and limit dV/dt.
Power-up State
At Power-up, the CLIC Control Circuit
makes a reset and put the CLIC in its
power-up state.The power-up state i
Open Circuit and no Relay Drivers
activated. The CLIC will remain in this
state until programmed else by sending
the inverse of the desired command
word (see table page 11) followed by the
desired command word. Example: To set
the CLIC in active state with command
word ’C8’, the inverse of ’C8’, ’37’,
followed by ’C8’ has to be sent. Once
this two word sequence has been sent
the CLIC is enabled to take one-word
command.
4. RC-network RBAT and CBAT
:
Receive Gain Pins (GV1, GV2)
To protect the VBAT - pin from being
exposed to a faster dV/dt - rate than
4 V / µs when connecting to VBAT
The receive gain can have three different
values; 0, -3,5 or -7,0 dBr.
If the pins GV1 (pin 23, 50) and GV2
(pin 22, 51) are shorted, the low gain
equals -3,5 dBr and the high gain equals
0,0 dBr.
If the pins GV1 and GV2 are left open,
the gain values are -7,0 dBr and -3,5 dBr
respectively. High and low gain is
selected with input data to the ASIC.
.
This can be achieved by using a RC-
filter with the time constant (τ) formed
by a 5,1 Ω resistor (RBAT) and a
0,47 µF capacitor (CBAT).
To ensure a fail-safe function in the
system, it is recommended to use
resistors with some type of fuse function
and a Fuse on VCC connection in series
with the power supplies to avoid
resulting failures in the system.
1.
4-10
PBA 3357/3
Control Data
Each channel of PBA 3357/3 has an ASIC which controls all line functions with a 8 bit serial word
Relay
Driver
Test Relay Detector
Gain
Control
SLIC Operation
Receive
Control
Function
Driver
Select
*
*
*
*
*
0
1
*
*
*
0
1
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
0
*
*
*
*
Receive Channel Off
High Gain
Low Gain
Test relay driver
Active (On)
Test relay driver Inactive (Off)
Relay driver Active (On)
Relay driver Inactive (Off)
Operating State
Active Detector
None
*
*
*
*
X
X
*
*
0
0
0
0
0
1
*
*
Open Circiut
Ring Relay driver
Active (Ringing)
Ring Trip
*
*
*
*
0
1
*
*
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
0
1
1
*
*
Active
Loop Current
Ground Key
Loop Current
Ground Key
Loop Current
None
Active
*
*
0
*
*
Stand by
Stand by
Tip open
No Function
*
*
1
*
*
*
*
0
*
*
*
*
X
0
*
*
*
*
*
*
Active, Polarity Reversed Loop Current
Active, Polarity Reversed Ground Key
Stand by, Polarity Reversed Loop Current
Stand by, Polarity Reversed Ground Key
Sequence of Data Input (SDI)
*
*
1
*
*
*
*
0
*
*
*
*
1
*
*
D7
D6
D5
D4
D3 D2 D1
D0
Comments: 1) X = Do not care 2) = Function specified elsewhere in the table.
*
The CLIC will remain in its power-up state until programmed by sending the inverse of the desired command word
followed by the desired command word. Example: To set CLIC in active state with command ’C8’, the inverse of
’C8’, ’37’, followed by ’C8’ has to be sent. To set CLIC in standby state with command ’CA’, the inverse of ’CA’, ’35’,
followed by ’CA’ has to be sent. Once this has been done the CLIC is enabled to take single-word command. The
Power-up state is Open Circuit and no Relay Driver activated.
Example on Control Input:
HEX Word
Binary Word
Function
D7 D6 D5 D4 D3 D2 D1 D0
Relay Driver Off
Testrelay Driver Off
(Bit D7 )
(Bit D6 )
C8
1
1
0
0
1
0
0
0
C
8
Active, Detector = Loop Current (Bit D3, D2, D1 and D5)
Receive Channel On, Low Gain (Bit D0 and D4 )
D7 D6 D5 D4 D3 D2 D1 D0
Relay Driver Off
(Bit D7 )
D2
1
1
0
1
0
0
1
0
Testrelay Driver Off
(Bit D6 )
D
2
Ringing, Detector = Ring Trip
Receive Channel On, High Gain
(Bit D3, D2, D1)
(Bit D0 and D4 )
Note: BIT D7 is sent first, BIT D0 is sent last.
4-11
PBA 3357/3
Application Reference Figures
Subscriber line System
+5 V
System
Bus A
CLIC
LPMA
test bus
test bus
PCM &
R
RTA
CMOS
OR
LSTTL
Circuits
Control
Channel A
R
System
Bus B
F1A
RTRIPA
TIPXA
PCM &
Control
PTC
1A
Line A
R
RGA
Channel B
OVPDA
+5 V
SCLKA
SDIA
LCLKA
SCLKB
SDIB
R
RINGXA
RTCA
F2A
CMOS
OR
LSTTL
Circuits
PTC
2A
C
GA
RL1
RL3
RL2
LCLKB
+5 V
RRLYA
TRLYA
DET A
LS251
Mux
RLYA
DET B
LPMB
R
RTB
-48VOVP
R
F1B
D
RTRIPB
TIPXB
R
BAT
BAT
-48 V
PTC
1B
V
C
BAT
Line B
Z
BAT
BAT
R
RGB
R
OVPDB
VR
-5 V
R
V
VEE
R
RINGXB
RTCB
EE
F2B
PTC
-5 V
2B
C
GB
V
CC
FUSE
V
RL4
RL5
RL6
CC
+5 V
D
VEE2
D
RRLYB
TRLYB
VCC
GND
D
VEE1
RLYB
GND
-48 VOVP
GV1A*G*V2A
GV1*B*GV2B
Ring
Generator
Components within the rectangle
can be shard by four CLIC´s
** Low recieve gain range when open
OVPDRING
Ring signal to
other lines
-5VR
-48 V
Figure 6. Typical Application for Dual CLIC PBA 3357/3 on a 16 Lines Line Card.
Denotation
Type of Component; requirements, name etc
OVPDA, OVPDB
OVPDRING
TISP R3612
Transient supressor, Zener diode type, 200V
D
VCC, DVEE2
Zener diode 6,2 V 1 W; BZX 85 C6V2
Schottky diode 1N5818, 1N5820
Diode 1N4004 or similar
DVEE1
DBAT
ZBAT
Transient supressor, BZW04-58 or SA58A
Relay; 9 V type
RL1-RL6
LPMA, LPMB1)
PBR 522 01/1 2 x 40 Ω, matched, Line Resistor with
PTC and Two 240 Ω resistors.
RVEE, RVR
RBAT
1,0 Ω, ± 20 %, 0,25 W (with fuse function)
5,1 Ω, ± 20 %, 1 W (with fuse function, max 4 DualCLIC’s)
CBAT
0,47 µF, ± 20 %, 100 V.
Recommended types:
1. Ceramic, X7R, with low voltage coefficient;
max 15 % at 50 VDC
2. Metallized polyester film (stacked MKT); Prefered
CGA, CGB
Fuse
0,22 µF, ± 20 %, 100 V. Recommended types: same as CBAT
Fuse Ω 1A depending on the power supply current lr the interface circuits
4-12
PBA 3357/3
Application Reference Figures cont.
VBAT
VBAT
GV1A/B
GV2A/B
+5V
V
CC
-5V
V
EE
DET
PCM output
PCM output
DET
DR A/B
DX A/B
147k
114k
FS
FS A
FS B
RTRIP A/B
DC-LOOP HOLDER
C1
PCM meas instrument
MCLK
MCLK A/B
Vac (input)
ZN
40
40
TIP A/B
LCKL
SCKL
SDI
RLDC
10H
LCKL A/B
SCKL A/B
SDI A/B
RLDC
Vac
(output)
ZN
RING A/B
C2
GND
C1 = C2 ≥ 100 µF
Figure 7. Reference diagram for Transmission Measurement.
4-13
PBA 3357/3
Mechanical Outline
E
2,54 ± 0,2 not acc.
71,1 +0,5/-0,3
max 0,64
3,8 ± 0,3
max 8,0
Figure 8. Mechanical outline.
4-14
PBA 3357/3
4-15
PBA 3357/3
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted
by implication or otherwise under any patent or patent
rights of Ericsson Components. These products are
sold only according to Ericsson Components' general
conditions of sale, unless otherwise confirmed in
writing.
Specifications subject to change without
notice.
1522-PBA 3357/3 Uen Rev. A
© Ericsson Components AB 1997
Ericsson Components AB
S-164 81 Kista-Stockholm, Sweden
Telephone: (08) 757 50 00
4-16
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