PBL386402QNS 概述
Subscriber Line Interface Circuit 用户线接口电路
PBL386402QNS 数据手册
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PDF下载March 2000
PBL 386 40/2
Subscriber Line
Interface Circuit
Description
Key Features
The PBL 386 40/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment.
The PBL 386 40/2 has been optimized for low total line interface cost and a high
degree of flexibility in different applications.
• 24-pin SSOP package
• High and low battery with automatic
switching
• 65 mW on-hook power dissipation in
active state
The PBL 386 40/2 emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with short loop current limiting adjustable to max 45 mA. In the current
limited region the loop feed is nearly constant current with a slight slope correspond-
ing to 2x30 kΩ.
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
A second, lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 40/2 is compatible with both loop and ground start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet the DLC requirements.
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• Programmable signal headroom
• 43V open loop voltage @ -48V battery
feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 kΩ @ -48V)
The PBL 386 40/2 package options are 24-pin SSOP package, 24-pin SOIC and
28-pin PLCC.
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Line voltage measurement
• Polarity reversal
Ring Relay
RRLY
Driver
• Ground key detector
DT
• Tip open state with ring ground
detector
C1
Ring Trip
Comparator
DR
TIPX
RINGX
HP
C2
Input
Decoder
and
C3
• -40°C to +85°C ambient temperature
range
Ground Key
Detector
Control
DET
POV
PSG
PLC
Line Feed
Controller
and
Longitudinal
Signal
VCC
Two-wire
Interface
Suppression
LP
L
PB
VBAT2
VBAT
PBL 386 40/2
386 40/2
PLD
REF
Off-hook
Detector
PBL 386 40/2
AGND
BGND
VTX
RSN
VF Signal
Transmission
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
PTG
Figure 1. Block diagram.
1
PBL 386 40/2
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
TStg
TAmb
TJ
-55
-40
-40
+150
+110
+140
°C
°C
°C
Power supply, -40°C ≤ TAmb ≤ +85°C
V
V
V
V
CC with respect to A/BGND
Bat2 with respect to A/BGND
Bat with respect to A/BGND, continuous
Bat with respect to A/BGND, 10 ms
VCC
VBat2
VBat
VBat
-0.4
VBat
-75
-80
6.5
0.4
0.4
0.4
V
V
V
V
Power dissipation
Continuous power dissipation at TAmb ≤ +85 °C
PD
VG
1.5
W
V
Ground
Voltage between AGND and BGND
Relay Driver
-0.3
+0.3
Ring relay supply voltage
BGND+14 V
Ring trip comparator
Input voltage
Input current
VDT, VDR
IDT, IDR
VBat
-5
AGND
5
V
mA
Digital inputs, outputs (C1, C2, C3, DET)
Input voltage
VID
-0.4
-0.4
VCC
VCC
V
V
Output voltage
VOD
TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V
Maximum supplied TIPX or RINGX current
ITIPX, IRINGX -100
+100
2
mA
V
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA
-80
VBat -10
VBat -25
VBat -35
5
V
10
15
V
TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3
V
Recommended Operating Condition
Parameter
Symbol
Min
Max
Unit
Ambient temperature
TAmb
VCC
VBat
VG
-40
4.75
-58
+85
5.25
-8
°C
V
V
V
V
CC with respect to AGND
Bat with respect to AGND
AGND with respect to BGND
-100
100
mV
Notes
1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.
2. With the diodes DVB and DVB2 included, see figure 12.
3.
RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.
2
PBL 386 40/2
Electrical Characteristics
-40 °C ≤ TAmb ≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, VBat = -58V to -40V, VBat2 =-32V, RLC=32.4 kΩ,
IL = 27 mA. RL = 600 Ω, RF1=RF2=0, RRef = 49.9 kΩ, CHP = 47nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ,
RR = 52.3 kΩ, ROV =∞ unless otherwise specified. Current definition: current is positive if flowing into a pin.
Ref
Parameter
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overhead voltage, VTRO ,ILdc > 18mA
2
Active state
1% THD, ROV = ∞
Note 1
2.7
1.1
VPeak
VPeak
On-Hook, ILdc < 5mA
Input impedance, ZTR
Note 2
0 < f < 100 Hz
active state
IEEE standard 455-1985, ZTRX=736Ω
Normal polarity:
ZT/200
20
Longitudinal impedance, ZLOT, ZLOR
Longitudinal current limit, ILOT, ILOR
Longitudinal to metallic balance, BLM
35
Ω/wire
28
mArms /wire
0.2 kHz < f < 1.0 kHz, Tamb 0-70°C
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C
0.2 kHz < f < 1.0 kHz, Tamb -40-85°C 60
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 55
Reverse polarity:
63
60
66
66
66
66
dB
dB
dB
dB
0.2 kHz < f < 1.0 kHz, Tamb 0-70°C
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C
0.2 kHz < f < 1.0 kHz, Tamb -40-85°C 55
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 55
59
55
66
66
66
66
dB
dB
dB
dB
Longitudinal to metallic balance, BLME
Longitudinal to four wire balance BLFE
3
3
Normal polarity:
0.2 kHz < f < 1.0 kHz, Tamb 0-70°C
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C
0.2 kHz ≤ f ≤ 1.0 kHz, Tamb -40-85°C 60
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 55
Reverse polarity:
0.2 kHz < f < 1.0 kHz, Tamb 0-70°C
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C
63
60
66
66
66
66
dB
dB
dB
dB
ELo
BLME = 20 · Log
BLFE = 20 · Log
VTR
ELo
59
55
66
66
66
66
dB
dB
dB
dB
VTX
0.2 kHz < f < 1.0 kHz, Tamb -40-85°C 55
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 55
Metallic to longitudinal balance, BMLE
VTR
4
0.2 kHz < f < 3.4 kHz
40
50
dB
BMLE = 20 · Log
; ERX = 0
VLo
Figure 2. Overhead voltage, VTRO , two-
wire port
C
TIPX
VTX
1
RL
VTRO
ILDC
RT
PBL 386 40/2
<< RL, RL= 600 Ω
ωC
ERX
RINGX
RSN
RT = 120 kΩ, RRX = 60 kΩ
RRX
Figure 3. Longitudinal to metallic (BLME
)
VTX
TIPX
and Longitudinal to four-wire (BLFE
balance
)
ELo
RLT
C
RT
VTR
PBL 386 40/2
VTX
1
<< 150 Ω, RLR =RLT =RL /2=300Ω
ωC
RLR
RINGX
RSN
RRX
RT = 120 kΩ, RRX = 60 kΩ
3
PBL 386 40/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to longitudinal balance, BFLE
4
0.2 kHz < f < 3.4 kHz
40
50
dB
ERX
BFLE = 20 · Log
VLo
Two-wire return loss, r
|ZTR + ZL|
r = 20 · Log
|ZTR - ZL|
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active, IL < 5 mA
30
20
35
22
- 1.3
dB
dB
V
TIPX idle voltage, VTi
RINGX idle voltage, VRi
active, IL < 5 mA
tip open, IL < 5 mA
active, IL < 5 mA
VBat +3.0
VBat +3.0
VBat +4.3
V
V
V
VTR
Four-wire transmit port (VTX)
Overhead voltage, VTXO, IL > 18mA
5
Load impedance > 20 kΩ,
2.7
VPeak
1% THD, Note 4
On-hook, IL < 5mA
Output offset voltage, ∆VTX
Output impedance, zTX
1.1
-100
VPeak
mV
Ω
0
15
100
50
0.2 kHz < f < 3.4 kHz
Four-wire receive port (RSN)
Receive summing node (RSN) DC voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (IRSN) to metallic loop current (IL)
gain,αRSN
I
RSN = -55 µA
1.15
1.25
8
1.35
20
V
Ω
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
200
ratio
Frequency response
Two-wire to four-wire, g2-4
6
relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz
-0.20
-1.0
0.10
0.1
dB
dB
f = 8.0 kHz, 12 kHz, 16 kHz
Figure 4. Metallic to longitudinal and four-
wire to longitudinal balance
TIPX
VTX
RLT
C
1
<< 150 Ω, RLT =RLR =RL /2 =300Ω
ωC
VTR
RT
PBL 386 40/2
ERX
VLo
RLR
RINGX
RSN
RT = 120 kΩ, RRX = 60 kΩ
RRX
Figure 5. Overhead voltage, VTXO, four-
wire transmit port
C
TIPX
VTX
RL
EL
1
<< RL, RL = 600 Ω
ωC
ILDC
RT
VTXO
PBL 386 40/2
RT = 120 kΩ, RRX = 60 kΩ
RINGX
RSN
RRX
4
PBL 386 40/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to two-wire, g4-2
6
relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
-0.2
-1.0
-2.0
0.1
0
0
dB
dB
dB
16 kHz
Four-wire to four-wire, g4-4
6
6
relative to 0 dBm, 1.0 kHz, EL =0 V
0.3 kHz < f < 3.4 kHz
-0.2
0.1
dB
Insertion loss
Two-wire to four-wire, G2-4
0 dBm, 1.0 kHz, Note 5
VTX
G2-4 = 20 · Log
; ERX = 0
-0.2
0.2
dB
dB
VTR
PTG = AGND
-6.22
-6.02
-5.82
Four-wire to two-wire, G4-2
6
0 dBm, 1.0 kHz, Note 6
VTR
G4-2 = 20 · Log
; EL = 0
-0.2
0.2
dB
ERX
Gain tracking
Two-wire to four-wire
6
6
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to + 3 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz,
-40 dBm to + 3 dBm
-0.1
-0.2
0.1
0.2
dB
dB
Four-wire to two-wire
-0.1
-0.2
0.1
0.2
dB
dB
-55 dBm to -40 dBm
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
C-message weighting
Psophometrical weighting
Note 8
12
-78
dBrnC
dBmp
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
6
0 dBm
0.3 kHz < f < 3.4 kHz
-67
-67
-50
-50
dB
dB
Battery Feed characteristics
Loop current, IL , in the current
limited region, reference A, B & C
Tip open state TIPX current, ILeak
13
18mA ≤ IL ≤ 45 mA
S = closed; R = 7 kΩ, note 10
0.92 IL
IL
1.08 IL
-100
mA
µA
7
7
Tip open state RINGX current, ILRTo
RLRTo = 0Ω, VBat = -48V
RLRTo = 2.5 kΩ, VBat = -48V
ILRTo < 23 mA
IL
mA
mA
17
Tip open state RINGX voltage, VRTo
Tip voltage (ground start)
7
7
VBat + 6
-2.2
V
V
Active state, Tip lead open (S open), -4
Ring lead to ground through 150 Ω
C
TIPX
VTX
Figure 6.
RL
Frequency response, insertion loss,
gain tracking.
VTR
ILDC
RT
PBL 386 40/2
VTX
ERX
1
EL
RINGX
RSN
<< RL, RL = 600 Ω
RRX
ωC
RT = 120 kΩ, RRX = 60 kΩ
5
PBL 386 40/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Tip voltage (ground start)
7
Active state, Tip lead to -48 V
through 7 kΩ (S closed), Ring
lead to ground through 150 Ω
RL = 0Ω
-6
-2.4
V
Open circuit state loop current, ILOC
-100
0
100
µA
Loop current detector
Programmable threshold, ILTh
active, active reverse
,
0.85·ILTh ILTh
0.85·ILTh ILTh
1.15·ILTh mA
1.15·ILTh mA
500
=
ILTh
RLD
RLD in kΩ, ILTh ≥ 7 mA
Tip open state
500
RLD
ILTh
=
Ground key detector
Ground key detector threshold
(ILTIPX and ILRINGX current difference to trigger ground key det.)
10
16
22
mA
Line voltage measurement
Pulse width, tLVM
Note 9
5.5
µs/V
Ring trip comparator
Offset voltage, ∆VDTDR
Input bias current, IB
Input common mode range, VDT, VDR
Ring relay driver
Source resistance, RS = 0 Ω
IB = (IDT + IDR)/2
-20
-200
VBat+1
0
-20
20
200
-1
mV
nA
V
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
Input low voltage, VIL
Input high voltage, VIH
Input low current, IIL
Input high current, IIH
Detector output (DET)
Output Low Voltage
Internal pull-up resistor
Power dissipation (VBat = -48V, VBat2= -32 V)
P1
IOL = 50 mA
VOH = 12 V
0.2
0.5
10
V
µA
0
2.5
0.5
VCC
-50
50
V
V
µA
µA
VIL = 0.5
VIH = 2.5 V
IOL = 0.5 mA
0.7
V
15
10
kΩ
Open circuit state, C1, C2, C3 = 0, 0, 0
Active state, C1, C2, C3 = 0, 1, 0
Longitudinal current = 0 mA, I L=0 mA (on-hook) 65
RL=300 Ω (off-hook)
RL=800 Ω (off-hook)
15
85
mW
P2
mW
mW
mW
P3
P4
730
360
Power supply currents (VBat = -48V)
V
CC current, ICC
VBat current, IBat
CC current, ICC
Open circuit state
1.2
-0.05
2.8
2
4
mA
mA
mA
mA
-0.1
-1.5
V
Active state
On-hook, Long Current = 0 mA
VBat current, IBat
-1.0
Power supply rejection ratios
V
V
CC to 2- or 4-wire port
Bat to 2- or 4-wire port
Active State
f = 1 kHz, Vn = 100mV
30
36
40
42
45
60
dB
dB
dB
VBat2 to 2- or 4-wire port
Temperature guard
Junction threshold temperature, TJG
145
°C
Thermal resistance
24-pin SSOP, θJP24ssop
24-pin SOIC, θJP24soic
28-pin PLCC, θJP28plcc
55
43
39
°C/W
°C/W
°C/W
6
PBL 386 40/2
R
R
S
TIPX
VBExt
PBL 386 40/2
LRTo
RINGX
Figure 7. Tipx voltage.
Notes
1. The overhead voltage can be adjusted with the ROV
5. Pin PTG = Open sets transmit gain to nom. 0.0dB
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistors RF impact the insertion
loss as explained in the text, section Transmission. The
specified insertion loss is for RF = 0.
resistor for higher levels e.g. min 3.1 VPeak and is specified
at the two-wire port with the signal source at the four-wire
receive port.
2. The two-wire impedance is programmable by selection of
external component values according to:
ZTRX = ZT/|G2-4S α RSN| where:
6. The specified insertion loss tolerance does not include
errors caused by external components.
7. The level is specified at the two-wire port.
8. The two-wire idle noise is specified with the port
terminated in 600 Ω (RL) and with the four-wire receive
port grounded (ERX = 0; see figure 6).
ZTRX = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
The four-wire idle noise at VTX is specified with the two-
wire port terminated in 600 Ω (RL). The noise
specification is referenced to a 600 Ω programmed two-
wire impedance level at VTX. The four-wire receive port is
grounded (ERX = 0).
G2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG)
α
RSN = receive current gain, nominally = 200 (current
defined as positive flowing into the receive summ-
ing node, RSN, and when flowing from ring to tip).
3. Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT
into two equal halves and connecting a capacitor from the
common point to ground.
9. Previous state must be active - loop or ground key
detector.
10. If |VBExt| ≥ |VBat + 2 V|, where VBat is the voltage at VBAT pin,
the current ILeak is limited to ≈ 5mA.
4. The overhead voltage can be adjusted with the ROV
resistor for higher levels e.g. min 3.1 VPeak and is specified
at the four-wire transmit port, VTX, with the signal source
at the two-wire port. Note that the gain from the two-wire
port to the four-wire transmit port is G2-4S = 1 (or 0.5 see
pin PTG)
7
PBL 386 40/2
1
2
24 VTX
PTG
RRLY
HP
23 AGND
5
6
25
24
23
22
21
20
19
3
22
21
20
RINGX
BGND
TIPX
RSN
REF
PLC
POV
NC
RINGX
BGND
TIPX
4
REF
PLC
POV
PLD
VCC
NC
5
24-pin SOIC
and
7
28-pin PLCC
6
24-pin SSOP 19
8
VBAT
VBAT2
PSG
VBAT
VBAT2
PSG
7
18 PLD
17 VCC
16 DET
9
8
10
11
9
NC
10
15
C1
LP
DT
DR
11
12
14 C2
13
C3
Figure 8. Pin configuration, 24-pin SOIC, 24-pin SSOP and 28 pin PLCC package, top view.
Pin Description
Refer to figure 8.
PLCC
Symbol
PTG
RRLY
HP
Description
1
2
3
4
5
Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB.
Ring Relay driver output. The relay coil may be connected to maximum +14V.
Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX.
No internal Connection
NC
RINGX
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
6
7
BGND
TIPX
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
8
VBAT
VBAT2
PSG
Battery supply Voltage. Negative with respect to AGND.
An optional second (2) Battery Voltage connects to this pin.
9
10
Programmable Saturation Guard. The resistive part of the DC Feed characteristic is programmed by a
resistor connected from this pin to VBAT.
11
12
13
NC
LP
DT
No internal Connection
Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The external ring trip network connects to this input.
14
DR
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
8
PBL 386 40/2
15
16
17
C3
C2
C1
C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states.
Refer to section "Operating states" for details.
}
18
DET
Detector output. Active low when indicating loop detection and ring trip, active high when indicating
ground key detection.
19
20
21
NC
No internal Connection
VCC
PLD
+5 V power supply.
Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
22
23
POV
PLC
Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in
off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead
voltage can be set to higher values.
Prog. Line Current, the current limit, reference C in figure 13, is programmed by a resistor connected
from this pin to AGND.
24
25
26
REF
NC
A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND.
No internal Connection
RSN
Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)
AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive
gain connect to the receive summing node. A resistor should be connected from this pin to AGND.
27
28
AGND
VTX
Analog Ground, should be tied together with BGND.
Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin
PTG). The two-wire impedance programming network connects between VTX and RSN.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Active state
Tip open state
Active state
-
Ring trip detector (active low)
Loop detector (active low)
Line voltage measurement (note 9)
Loop detector (active low)
Ground key detector (active high)
Loop detector (active low)
Ground key detector (active high)
Active reverse
Active reverse
Table 1. SLIC operating states.
9
PBL 386 40/2
Four-Wire to Two-Wire Gain
From (1), (2) and (3) with EL = 0:
TIPX
TIP
+
I
L
VTR
R
R
P
F
G4−2
=
=
Z
L
VRX
Z
+
TR
VTX
V
TR
RHP
G
+
2-4S
-
ZT
−
ZL
+
E
L
V
TX
R
R
P
ZT
αRSN
-
F
ZRX
-
I
+ G2− 4S (ZL + 2RF + 2RP)
L
RING
RINGX
-
Z
T
Z
For applications where
RX
RSN
+
V
ZT/(αRSN·G2-4S) + 2RF + 2RP is chosen to
be equal to ZL the expression for G4-2
simplifies to:
RX
I /αRSN
L
-
PBL 386 40/2
ZT
1
G4−2 = −
ZRX 2G2− 4S
Figure 9. Simplified ac transmission circuit.
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
ZT
determines the SLIC TIPX to
RINGX impedance at voice
frequencies.
Functional Description
and Applications Infor-
mation
VTX
G4−4
=
=
VRX
ZRX controls four- to two-wire gain.
VRX is the analog ground referenced
receive signal.
ZT
−
G2− 4S (ZL + 2RF + 2RP)
+ G2−4S (ZL + 2RF + 2RP )
ZT
αRSN
ZRX
Transmission
αRSN is the receive summing node
current to metallic loop current
gain = 200.
General
Hybrid Function
A simplified ac model of the transmission
circuits is shown in figure 9. Circuit
analysis yields:
Note that the SLICs two-wire to four-wire
gain, G2-4S, is user programmable
between two fix values. Refer to the
The hybrid function can easily be
implemented utilizing the uncommitted
amplifier in conventional CODEC/filter
combinations. Please, refer to figure 10.
Via impedance ZB a current proportional
to VRX is injected into the summing node
of the combination CODEC/filter ampli-
fier. As can be seen from the expression
for the four-wire to four-wire gain a
voltage proportional to VRX is returned to
VTX. This voltage is converted by RTX to a
current flowing into the same summing
node. These currents can be made to
cancel by letting:
datasheets for values on G2-4S
.
VTX
(1)
(2)
(3)
VTR
=
+ IL (2RF + 2RP )
G2− 4S
VTX VRX
Two-Wire Impedance
IL
+
=
To calculate ZTR, the impedance pre-
sented to the two-wire line by the SLIC
including the fuse and protection
resistors RF and RP, let:
ZT
ZRX
αRSN
VTR = EL - IL · ZL
where:
VRX = 0.
From (1) and (2):
VTX is a ground referenced version of
the ac metallic voltage between the
TIPX and RINGX terminals.
G2-4S is the programmable SLIC two-wire
to four-wire gain (transmit
direction). See note below.
VTR is the ac metallic voltage between
tip and ring.
VTX VRX
ZT
+
= 0(EL = 0)
ZTR
=
+ 2RF + 2RP
RTX
ZB
αRSN G2− 4S
The four-wire to four-wire gain, G4-4,
includes the required phase shift and
thus the balance network ZB can be
calculated from:
Thus with ZTR, αRSN, G2-4S, RP and RF
known:
ZT = αRSN G2− 4S (ZTR − 2RF − 2RP )
V
RX
EL
is the line open circuit ac metallic
voltage.
Z
= −R
=
B
TX
V
TX
Two-Wire to Four-Wire Gain
Z
IL
is the ac metallic current.
T
+ G
(Z + 2R + 2R )
L F P
2−4S
From (1) and (2) with VRX = 0:
Z
α
RF is a fuse resistor.
RP is part of the SLIC protection.
RX
RSN
G
R
TX
Z
(Z + 2R + 2R )
L F P
T
2−4S
VTX
VTR
ZT / αRSN
G2− 4
=
=
ZT
αRSN G2− 4S
+ 2RF + 2RP
ZL
is the line impedance.
10
PBL 386 40/2
When choosing RTX, make sure the output
load of the VTX terminal is >20 kΩ.
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recom-
mended. Contact Ericsson Microelectron-
ics for assistance.
R
FB
The PBL 386 40/2 SLIC may also be
used together with programmable
CODEC/filters. The programmable
CODEC/filter allows for system controller
adjustment of hybrid balance to accom-
modate different line impedances without
change of hardware. In addition, the
transmit and receive gain may be ad-
justed. Please, refer to the programm-
able CODEC/filter data sheets for design
information.
R
TX
VTX
V
T
PBL
386 40/2
Z
Z
Combination
CODEC/Filter
V
T
B
Z
RX
RX
RSN
Longitudinal Impedance
A Feed back loop counteracts longitudi-
nal voltages at the two-wire port by
injecting longitudinal currents in opposing
phase.
Figure 10. Hybrid function.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experi-
ence very small longitudinal voltage
excursions, leaving metallic voltages well
within the SLIC common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20 Ω to longitudinal disturbances. It
should be noted that longitudinal currents
may exceed the dc loop current without
disturbing the vf transmission.
frequency response break point of the ac
loop in the SLIC. Refer to table 1 for
recommended values of CHP.
Example: A CHP value of 150 nF will
position the low end frequency response
3dB break point of the ac loop at 1.8 Hz
(f3dB) according to f3dB = 1/(2·π·RHP·CHP)
where RHP = 600 kΩ.
impedance of the SLIC. The choise of
these programmable components have an
influence on the power supply rejection
ratio (PSRR) from VBAT to the two wire
side at sub-audio frequencies. At these
frequencies capacitor CLP also influences
the transversal to longitudinal balance in
the SLIC. Table 1 suggests suitable values
onCLP fordifferentFeedingcharacteristics.
Typical values of the transversal to longitu-
dinal balance (T-L bal.) at 200Hz is given in
table 1 for the chosen values on CLP.
High-Pass Transmit Filter
The capacitor CTX in figure 12 connected
between the VTX output and the
CODEC/filter forms, together with RTX
and/or the input impedance of a pro-
grammable CODEC/filter, a high-pass
RC filter. It is recommended to position
the 3 dB break point of this filter between
30 and 80 Hz to get a faster response for
the dc steps that may occur at DTMF
signalling.
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 12, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filter-
ing.. The recommended value for CTC
and CRC is 2200 pF. Higher capacitance
values may be used, but care must be
taken to prevent degradation of either
longitudinal balance or return loss. CTC
and CRC contribute to a metallic imped-
ance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to
ground impedance of 1/(2·π·f·CTC) and a
RINGX to ground impedance of 1/
(2·π·f·CRC).
RFeed
RSG
CLP
T-L bal. CHP
@200Hz
[Ω]
[kΩ]
[nF]
[dB]
[nF]
2 50
0
150
100
47
-46
-46
-43
-36
47
2 200
2 400
2 800
60.4
147
301
150
150
150
22
Table 1. RSG , CLP and CHP values for
different Feeding characteristics.
Capacitor CLP
ThecapacitorCLP,whichconnectsbetween
the terminals CLP and VBAT, positions
together with the resistive loop feed resis-
tor RSG (see section Battery Feed), the high
end frequency break point of the low pass
filter in the dc loop in the SLIC. CLP together
withRSG, CHP andZT (seesectionTwo-Wire
Impedance) forms the total two wire output
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and TIPX provides
the separation of the ac signal from the
dc part. CHP positions the low end
11
PBL 386 40/2
The current limit (reference C in figure
13) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
receive output via the resistor RRX, is dc
biased with +1.25V. This makes it
possible to compensate for currents
floating due to dc voltage differences
between RSN and the CODEC output
without using any capacitors. This is
done by connecting a resistor RR be-
tween the RSN terminal and ground.
With current directions defined as in
figure 14, current summation gives:
Battery Feed
The PBL 386 40/2 SLIC emulate resistive
loop Feed, programmable between
2·50Ω and 2·900 Ω, with adjustable
current limitation. In the current limited
region the loop current has a slight slope
corresponding to 2·30 kΩ, see figure 13
reference B.
The open loop voltage measured
between the TIPX and RINGX terminals
is tracking the battery voltage VBat. The
1000
ILProg + 4
RLC
=
where RLC is in kΩ for ILProg in mA.
A second, lower battery voltage may
be connected to the device at terminal
VBAT2 to reduce short loop power
−IRSN = IRT + IRRX + IRR
=
signalling headroom, or overhead voltage dissipation. The SLIC automatically
VTRO, is programmable with a resistor ROV switches between the two battery supply
1,25 1,25 − VCODEC
1,25
RR
+
+
connected between terminal POV on the
SLIC and ground. Please refer to section
voltages without need for external
control. The silent battery switching
RT
RRX
“Programmable overhead voltage(POV)”. occurs when the line voltage passes the
where VCODEC is the reference voltage of
the CODEC at the receive output.
From this equation the resistor RR can be
calculated as
The battery voltage overhead, VOH
depends on the programmed signal
,
value |VB2| - 40·IL - (VOHVirt -1.3),
if IL > 6 mA.
overhead voltage VTRO. VOH defines the
TIPX to RINGX voltage at open loop
conditions according to VTR(at IL = 0 mA)
For correct functionality it is important
to connect the terminal VBAT2 to the
second power supply via the diode DVB2
in figure 12.
1,25
RR
=
1,25 − VCODEC
1,25
RT
= |VBat| - VOH
.
−IRSN
−
−
Refer to table 2 for typical values on
OH and VOHVirt. The overhead voltage is
An optional diode DBB connected
between terminal VB and the VB2 power
supply, see figure 12, will make sure that
the SLIC continues to work on the
second battery even if the first battery
voltage disappears.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the
SLIC and CVB2, DBB and DVB2 are re-
moved.
RRX
V
changed when the line current is ap-
proaching open loop conditions. To
ensure maximum open loop voltage,
even with a leaking telephone line, this
occurs at a line current of approximately
6 mA. When the overhead voltage has
changed, the line voltage is kept nearly
constant with a steep slope correspon-
ding to 2·25 Ω(reference G in figure 13).
The virtual battery overhead, VOHVirt, is
defined as the difference between the
battery voltage and the crossing point of
all possible resistive Feeding slopes, see
figure 13 reference J. The virtual battery
overhead is a theoretical constant
needed to be able to calculate the
Feeding characteristics.
For values on IRSN, see table 3.
The resistor RR has no influence on the
ac transmission.
SLIC
IRSN [µA]
PBL 386 40/2
-55
Table 3. The SLIC internal bias current
with the direction of the current defined
as positive when floating into the terminal
RSN.
Metering applications
For designs with metering applications
please contact Ericsson Microelectronics
for assistance.
CODEC Receive Interface
Programmable overhead voltage(POV)
The PBL 386 40/2 SLIC have got a
completely new receive interface at the
four wire side which makes it possible to
reduce the number of capacitors in the
applications and to fit both single and
dual battery Feed CODECs. The RSN
terminal, connecting to the CODEC
With the POV function the overhead
voltage can be increased.
If the POV pin is left open the overhead
voltage is internally set to 3,2 VPeak in off-
hook and 1,3 VPeak on-hook. If a resistor
ROV is connected between the POV pin
SLIC
VOH(typ)
[V]
VOHVirt(typ)
[V]
PBL 386 40/2 3.0 +VTRO 4.9 +VTRO
7
6
5
4
3
2
1
0
Table 2. Battery overhead.
The resistive loop Feed (reference D in
figure 13) is programmed by connecting
a resistor, RSG, between terminals PSG
and VBAT according to the equation:
off-hook
on-hook
RSG + 2·104
RFeed
=
+ 2RF
200
0
10
20
30
(KΩ)
40
50
60
where RFeed is in Ω for RSG, and RF in Ω.
R
ov
Figure 11. Programmable overhead voltage (POV). RL = 600 Ω or ∞.
12
PBL 386 40/2
RFB
PBL 386 40/2
CTX
RTX
KR
-
PTG
VTX
-
0
+
+
RT
RRLY
HP
AGND
RSN
NC
RB
+12 V /+5V
RRX
0
CGG
DHP
CHP
NC
CODEC/
Filter
RF2
RR
RP2
RING
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
REF
PLC
POV
PLD
VCC
NC
RREF
RLC
ROV
RLD
CRC
CTC
VB
OVP
TIP
RF1
RP1
PBL 386 40/2
DVB2
VB2
VB
VCC
VCC
DBB
DVB
RSG
CVB2
CVCC
DET
C1
CLP
ERG
CVB
R1
LP
RRT
DT
C2
R2
DR
C3
C1
C2
SYSTEM CONTROL
INTERFACE
R3
R4
SLIC No. 2 etc.
CAPACITORS: (Values according to IEC E96
series)
DIODES:
DVB
RESISTORS: (Values according to IEC E96 series)
= 1N4448
RSG
RLD
ROV
RLC
RREF
RR
= 0 Ω
1% 1/10 W
1% 1/10 W
CVB
CVB2
CVCC
CTC
CRC
CHP
CLP
CTX
CGG
C1
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
DVB2
= 1N4448
= 49.9 kΩ
= User programmable
DBB
= 1N4448
DHP
= 1N4448 (Note 2)
= 32.4 kΩ
= 49.9 kΩ
= 64.9 kΩ
= 105 kΩ
= 24.9 kΩ
= 22.1 kΩ
= 52.3 kΩ
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
OVP:
Secondary protection (e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
RT
= 150 nF
= 100 nF
= 220 nF
= 330 nF
= 330 nF
RTX
RB
RRX
RFB
R1
Depending on CODEC / filter
C2
= 604 kΩ
= 604 kΩ
= 249 kΩ
= 280 kΩ
= 330 Ω
= 10 Ω
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
5% 2 W
R2
NOTES:
R3
1. RP1 and RP2 may be omitted if DVB is in place.
R4
2. It is required to connect DHP between terminal
HP and ground if CHP > 47nF
RRT
RP1, RP2
RF1, RF2
1% 1/10 W (Note 1)
= Line resistor, 40 Ω 1% match
Figure 12. Single-channel subscriber line interface with PBL 386 40/2 and combination CODEC/filter.
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The ROV and
corresponding VTRO (signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
VTX can not handle more than 3,2 VPeak.
So if the gain 2-wire to 4-wire is 0dB,
3,2 VPeak is maximum also for the 2-wire
side. Signal levels between 3,2 and
6,4 VPeak on the 2-wire side can be
handled with the PTG shorted so that the
gain G2-4S become -6,02dB. Please note
that the 2-wire impedance, RR and the
4-wire to 4-wire gain has to be recalcu-
lated if the PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 9 mA.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 40/2 SLIC
reduce the dc line current when approxi-
mately 145°C and increases it again
automatically when the temperature
drops. Accordingly transmission is not
lost under high ambient temperature
conditions.
How to use POV:
1. Decide what overhead voltage(VTRO
)
is needed. The POV function is only
needed if the overhead voltage
exceeds 3,2 VPeak
2. In figure 11 the corresponding ROV for
the decided VTRO can be found.
3. If the overhead voltage exceeds
3,2 VPeak , the G2-4S gain has to be
changed to -6,02dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, RR and
the 4-wire to 4-wire gain has to be
recalculated.
The detector output, DET, is forced to
a logic low level when the temperature
guard is active.
13
PBL 386 40/2
DC characteristics
A
A
B
C
B
C
D
D
E
G
F
F
H
J
VTR [V]
|VBat| - VOHVirt - RFeed · (ILProg + 4·10-3)
A:
IL (@ VTR = 0V) = ILProg +
60 · 103
E:
F:
G:
H:
J:
IL ≈ 6 mA
Apparent battery VBat(@ IL = 0) =|VBat| - VOHVirt - RFeed · 4·10-3)
FeedG = 2 · 25 Ω
B:
C:
RFeedB = 2 · 30 kΩ
103
R
ILConst(typ) = ILProg
=
- 4·10-3
RLC
VTROpen = |VBat| - VOH
VTR = |VBat| - VOHVirt - RFeed · (ILProg + 4·10-3)
Virtual battery VBatvirt (@ IL = 4 mA) = |VBat| - VOHVirt
RSG + 2 · 104
D:
RFeed =
200
Figure 13. Battery Feed characteristics (without the protection resistors on the line).
and is calculated according to
Ring Trip Detector
Loop Monitoring Functions
Ring trip detection is accomplished by
connecting an external network to a
comparator in the SLIC with inputs DT
and DR. The ringing source can be
balanced or unbalanced superimposed
on VB or GND. The unbalanced ringing
source may be applied to either the ring
lead or the tip lead with return via the
other wire. A ring relay driven by the
SLIC ring relay driver connects the
ringing source to tip and ring.
The ring trip function is based on a
polarity change at the comparator input
when the line goes off-hook. In the on-
hook state no dc current flows through
the loop and the voltage at comparator
input DT is more positive than the
voltage at input DR. When the line goes
off-hook, while the ring relay is ener-
gized, dc current flows and the compara-
tor input voltage reverses polarity.
Figure 12 gives an example of a ring
500
ILTh
The loop current, ground key and ring trip
detectors report their status through a
common output, DET. The detector to be
connected to DET is selected via the
three bit wide control interface C1, C2
and C3. Please refer to section Control
Inputs for a description of the control
interface.
RLD
=
the current detector is internally filtered
and is not influenced by the ac signal at
the two wire side.
Ground Key Detector
The ground key detector is indicating
when the ground key is pressed (active)
by putting the output pin DET to a logical
high level when selected. The ground
key detector circuit senses the difference
in TIPX and RINGX currents. When the
current at the RINGX side exceeds the
current at the TIPX side with the thres-
hold value the detector is triggered. For
threshold current values, please refer to
the datasheet.
Loop Current Detector
The loop current detector is indicating
that the telephone is off hook and that
current is flowing in the loop by putting
the output DET to a logical low level
when selected.The loop current threshold
value, ILTh, at which the loop current
detector changes state is programmable
by selecting the value of resistor RLD. RLD
connects between pin PLD and ground
14
PBL 386 40/2
trip detection network. This network is
applicable, when the ring voltage super-
imposed on VB and is injected on the ring
lead of the two-wire port. The dc voltage
across sense resistor RRT is monitored by
the ring trip comparator input DT and DR
via the network R1, R2, R3, R4, C1 and C2.
With the line on-hook (no dc current) DT
is more positive than DR and the DET
output will report logic level high, i.e. the
detector is not tripped. When the line
goes off-hook, while ringing, a dc current
will flow through the loop including sense
resistor RRT and will cause input DT to
become more negative than input DR.
This changes output DET to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay,
i.e. ring trip.
PBL386 40/2
VTX
DC-GND
RT
CODEC
I
IRT
IRSN
IRRX
RRX
_
+
RSN
IRR
+1.25 V
UREFcodec
RR
Figure 14. CODEC receive interface.
Ringing State
Active Polarity Reversal State
The ring relay driver and the ring trip
detector are activated and the ring trip
detector is indicating off hook with a logic terminal closest to ground and sources
low level at the detector output.
The SLIC is in the active normal state.
TIPX and RINGX polarity is reversed
from the Active State: RINGX is the
loop current while TIPX is the more
negative terminal and sinks current. Vf
signal transmission is normal. The loop
current or the ground key detector is
activated. The loop current detector is
indicating off hook with a logic low level
and the ground key detector is indicating
active ground key with a logic high level
present at the detector output.
Complete filtering of the 20 Hz ac
component at terminal DT and DR is not
necessary. A toggling DET output can be
examined by a software routine to deter-
mine the duty cycle. When the DET
output is at logic level low for more than
half the time, off-hook condition is
Active States
TIPX is the terminal closest to ground
and sources loop current while RINGX is
the more negative terminal and sinks
loop current. Vf signal transmission is
normal. The loop current or the ground
key detector is activated. The loop
current detector is indicating off hook
with a logic low level and the ground key
detector is indicating active ground key
with a logic high level present at the
detector output.
In PBL 386 40/2 a line voltage meas-
urement feature is available in the active
state, which may be used for line length
estimations or for line test purposes. The
line voltage is presented on the detector
output as a pulse at logic high level with
a pulsewidth of 5.5 µs/V. To start the line
voltage measurement this mode has to
be entered from the Active State with the
loop or ground key detector active. The
pulse presented at the DET output
proportional to the line voltage starts
when entering the line voltage measuring
mode.
indicated.
Relay driver
Overvoltage Protection
The PBL 386 40/2 SLIC incorporates a
ring relay driver designed as open
collector (npn) with a current sinking
capability of 50 mA. The drive transistor
emitter is connected to BGND. The relay
driver has an internal zener diode clamp
for inductive kick-back voltages.
Care must be taken when using the relay
driver together with relays that have high
impedance.
The PBL 386 40/2 SLIC must be pro-
tected against overvoltages on the
telephone line caused by lightning, ac
power contact and induction. Refer to
Maximum Ratings, TIPX and RINGX
terminals, for maximum allowable
continuous and transient ratings that
may be applied to the SLIC.
Secondary Protection
The circuit shown in figure 12 utilizes
series resistors together with a program-
mable overvoltage protector
Control Inputs
The PBL 386 40/2 SLIC have three
digital control inputs, C1, C2 and C3.
A decoder in the SLIC interprets the
control input condition and sets up the
commanded operating state.
(e.g. PowerInnovations TISPPBL2),
serving as a secondary protection.
The TISP PBL2 is a dual forward-
conducting buffered p-gate overvoltage
protector. The protector gate references
the protection (clamping) voltage to
negative supply voltage (i e the battery
voltage, VB ). As the protection voltage
will track the negative supply voltage the
overvoltage stress on the SLIC is
minimized.
C1 to C3 are internal pull-up inputs.
Tip Open State
Open Circuit State
Tip Open State is used for ground start
signalling.
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as
other circuit blocks are powered down.
This causes the SLIC to present a high
impedance to the line. Power dissipation
is at a minimum and no detectors are
active.
In this state the SLICs present a high
impedance to the line on the TIPX pin
and the programmed dc characteristic,
with the longitudinal current compensa-
tion (see section Longitudinal Imped-
ance) not active, to the line on the
RINGX pin.
Positive overvoltages are clamped to
ground by a diode. Negative overvolt-
ages are initially clamped close to the
SLIC negative supply rail voltage and the
The loop current detector is active.
15
PBL 386 40/2
protector will crowbar into a low voltage
on-state condition, by firing an internal
thyristor.
Power-up Sequence
The fuse resistors RF serve the dual
purposes of being non-destructive
energy dissipators, when transients are
clamped and of being fuses, when the
line is exposed to a power cross.
If a PTC is chosen for RF, note that it is
important to always use the PTC´s in
series with resistors not sensitive to
temperature, as the PTC will act as a
capacitance for fast transients and
therefore will not protect the TISP.
No special power-up sequence is
necessary except that ground has to be
present before all power supply voltages.
A gate decoupling capacitor, C GG, is
needed to carry enough charge to supply
a high enough current to quickly turn on
the thyristor in the protector. C GG shall
be placed close to the overvoltage
protection device. Without the capacitor
even the low inductance in the track to
the VBat supply will limit the current and
delay the activation of the thyristor
clamp.
Printed Circuit Board Layout
Care in PCB layout is essential for
proper function. The components
connecting to the RSN input should be
placed in close proximity to that pin, so
that no interference is injected into the
RSN pin. Ground plane surrounding the
RSN pin is advisable.
The two ground pins AGND and BGND
should be connected together on the
PCB at the device location.
The capacitors for the battery should
be connected with short wide leads of the
same length.
Ordering Information
Package
Temp. Range
Part No.
PBL 386 40/2SHT
PBL 386 40/2SOS
PBL 386 40/2SOT
24 pin SSOP Tape & Reel -40° - +85° C
24 pin SOIC Tube
24 pin SOIC Tape & Reel
28 pin PLCC Tube
-40° - +85° C
-40° - +85° C
-40° - +85° C PBL 386 40/2QNS
28 pin PLCC Tape & Reel -40° - +85° C
PBL 386 40/2QNT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted
by implication or otherwise under any patent or patent
rights of Ericsson Microelectronics AB. These
products are sold only according to Ericsson
Microelectronics AB' general conditions of sale,
unless otherwise confirmed in writing.
Specifications subject to change without
notice.
1522-PBL 386 40/2 Uen Rev. B
© Ericsson Microelectronics AB 2000
This product is an original Ericsson
product protected by US, Europe and
other patents.
Ericsson Microelectronics AB
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
16
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