F25L004A-100P [ESMT]
Flash, 512KX8, PDSO8,;
| 型号： | F25L004A-100P |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | Flash, 512KX8, PDSO8, 光电二极管 |
| 文件： | 总32页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F25L004A
4Mbit (512Kx8)
3V Only Serial Flash Memory
ꢀFEATURES
ꢁ
ꢁ
Single supply voltage 2.7~3.6V
ꢁ
ꢁ
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte-Program operations
Speed
- Read max frequency : 33MHz
- Fast Read max frequency : 50MHz; 75MHz; 100MHz
SPI Serial Interface
ꢁ
ꢁ
Low power consumption
- typical active current
- SPI Compatible : Mode 0 and Mode3
- 15µA typical standby current
ꢁ
ꢁ
End of program or erase detection
Reliability
Write Protect ( WP )
- 100,000 typical program/erase cycles
- 20 years Data Retention
ꢁ
ꢁ
Hold Pin (HOLD )
ꢁ
ꢁ
Program
Package available
- 8-pin SOIC 150-mil
- 8-pin SOIC 200-mil
- Byte program time 9µs(typical)
Erase
- Chip erase time 4s(typical)
- Sector erase time 60ms(typical),
block erase time 1sec (typical)
ORDERING INFORMATION
Part No.
Speed
Package
COMMENTS
Pb-free
Part No.
Speed
Package
COMMENTS
Pb-free
8 lead
150 mil
150 mil
200 mil
8 lead
200 mil
300 mil
300 mil
50MHz
F25L004A –100PA 100MHz
F25L004A –50P
SOIC
SOIC
8 lead
SOIC
8 lead
PDIP
F25L004A –100P 100MHz
F25L004A –50PA 50MHz
Pb-free
Pb-free
F25L004A –50P
50MHz
Pb-free
Pb-free
8 lead
SOIC
8 lead
PDIP
F25L004A –100D 100MHz
GENERAL DESCRIPTION
The F25L004A is a 4Megablt, 3V only CMOS Serial Flash
memory device organized as 512K bytes of 8 bits. This device is
packaged in 8-lead SOIC 200mil. ESMT’s memory devices
reliably store memory data even after 100,000 program and
erase cycles.
erased individually without affecting the data in other sectors.
Blocks can be erased individually without affecting the data in
other blocks. Whole chip erase capabilities provide the flexibility
to revise the data in the device.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
The F25L004A features a sector erase architecture. The device
memory array is divided into 128 uniform sectors with 4K byte
each ; 8 uniform blocks with 64K byte each. Sectors can be
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Publication Date: Nov. 2006
Revision: 1.0
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ESMT
F25L004A
PIN CONFIGURATIONS
8-PIN SOIC
0
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
8-PIN PDIP
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
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ESMT
F25L004A
PIN Description
Symbol
SCK
Pin Name
Functions
To provide the timing for serial input and
Serial Clock
output operations
To transfer commands, addresses or data
serially into the device.
SI
Serial Data Input
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
SO
CE
WP
Serial Data Output
Chip Enable
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
Write Protect
To temporality stop serial communication
with SPI flash memory without resetting
the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
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F25L004A
SECTOR STRUCTURE
Table1 : F25L004A Sector Address Table
Block Address
A18 A17 A16
Sector Size
(Kbytes)
Sector
Address range
Block
7
127
:
4KB
:
07F000H – 07FFFFH
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
070000H – 070FFFH
06F000H – 06FFFFH
:
060000H – 060FFFH
05F000H – 05FFFFH
:
050000H – 050FFFH
04F000H – 04FFFFH
:
040000H – 040FFFH
03F000H – 03FFFFH
:
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
6
5
4
3
2
1
0
0
4KB
000000H – 000FFFH
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F25L004A
Table2 : F25L004A Block Protection Table
TOP
Protection Level
Status Register Bit
Protected Memory Area
BP2
0
BP1
0
BP0
0
Block Range
Address Range
None
0
None
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Block 7
70000H – 7FFFFH
60000H – 7FFFFH
40000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
Block 6~7
Block 4~7
Block 0~7
Block 0~7
Block 0~7
Block 0~7
BOTTOM
Protection Level
Status Register Bit
Protected Memory Area
BP2
BP1
0
0
1
1
0
0
1
1
BP0
Block Range
None
Address Range
None
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Bottom 1/8
Bottom 1/4
Bottom 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Block 0
00000H – 0FFFFH
00000H – 1FFFFH
00000H – 3FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
Block 0~1
Block 0~3
Block 0~7
Block 0~7
Block 0~7
Block 0~7
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as WP is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
WP pin driven low (VIL), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
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FUNTIONAL BLOCK DIAGRAM
F25L004A
Flash
Address
Buffers
and
X-Decoder
Latches
Y-Decoder
I/O Butters
and
Control Logic
Data Latches
Serial Interface
CE
SCK
SO
WP
HOLD
SI
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F25L004A
Hold Operation
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 18 for Hold
timing.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD signal does not
SCK
HOLD
Hold
Active
Active
Active
Hold
Figure 1 : HOLD CONDITION WAVEFORM
Write Protection
TABLE3: CONDITIONS TO EXECUTE
WRITE-STATUS- REGISTER (WRSR)
INSTRUCTION
F25L004A provides software Write protection.
The Write Protect pin ( WP ) enables or disables the lockdown
function of the status register. The Block-Protection bits (BP1,
BP0, and BPL) in the status register provide Write protection to
the memory array and the status register. See Table 5 for
Block-Protection description.
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
L
0
Allowed
Write Protect Pin ( WP )
The Write Protect ( WP ) pin enables the lock-down function of
H
X
Allowed
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write-Status-Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 3). When WP
is high, the lock-down function of the BPL bit is disabled.
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Status Register
F25L004A
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress.
Table 4 describes the function of each bit in the software status
register.
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Read/Write
Power-up
Bit
Name
BUSY
WEL
Function
1 = Internal Write operation is in progress
0
0
R
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
1
0
R
0 = Device is not memory Write enabled
2
3
4
5
BP0
BP1
BP2
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
1
1
1
0
R/W
R/W
R/W
N/A
RESERVED Reserved for future use
Auto Address Increment Programming status
6
7
AAI
1 = AAI programming mode
0
0
R
0 = Byte-Program mode
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
BPL
R/W
Note1 : Only BP0,BP1,BP2 and BPL are writable
Note2 : All register bits are volatility
Note3 : All area are protected at power-on (BP2=BP1=BP0=1)
Busy
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If the Write-Enable-Latch bit is set to
“1”, it indicates the device is Write enabled. If the bit is set to “0”
(reset), it indicates the device is not Write enabled and does not
accept any memory Write (Program/ Erase) commands. The
Write-Enable-Latch bit is automatically reset under the following
conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming reached its
highest memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
•
Write-Status-Register instructions
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Instructions
F25L004A
Instructions are used to Read, Write (Erase and Program), and
configure the F25L004A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
transition of CE . Inputs will be accepted on the rising edge of
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Bus Cycle
Cycle Type/
Max
Operation1,2
Freq
1
2
3
4
5
6
SIN
SOUT
SIN
SOUT SIN
SOUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SIN SOUT SIN SOUT SIN SOUT
Read
33 MHz 03H
0BH
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0 Hi-Z
X
X
-
DOUT
High-Speed-Read
X
-
X
-
-
DOUT
Sector-Erase4,5 (4K Byte)
Block-Erase (64K Byte)
20H
-
-
D8H
-
-
60H
Chip-Erase6
Byte-Program5
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
02H
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z
Hi-Z
A7-A0 Hi-Z DIN Hi-Z
Auto-Address-Increment-word
programming (AAI)
Read-Status-Register
(RDSR)
ADH Hi-Z A23-A16 Hi-Z A15-A8
A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z
05H
50H
01H
Hi-Z
Hi-Z
X
-
DOUT
-
-
-
-
Note7
-
-
Note7
-
-
-
Note7
-
-
-
-
-
-
50MHz
Enable-Write-Status-Register
-
-
-
-
-
-
(EWSR)8
Write-Status-Register
(WRSR)8
Hi-Z Data Hi-Z
-.
Write-Enable (WREN) 11
06H
04H
ABH
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write-Disable (WRDI)
100MHz
Read-Electronic-Signature
X
12H
(RES)
20H(Top)
21H(Bottom)
Jedec-Read-ID (JEDEC-ID) 10
9FH
Hi-Z
X
8CH
X
X
13H
-
-
-
-
90H (A0=0)
90H (A0=1)
8CH
12H
12H
8CH
Read-ID (RDID)
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z
A7-A0 Hi-Z
X
X
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable SO to output RY/BY#
Status during AAI (DBSY)
70H
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80H
-
1. Operation: SIN = Serial In, SOUT = Serial Out
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
5. Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type and second byte 21H as
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F25L004A
bottom memory type ; third byte 13H as memory capacity.
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 4Mbit density, once
the data from address location 7FFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23-A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
CE
MODE3
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
SCK MODE1
ADD.
MSB
03
ADD.
ADD.
SI
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOU T
HIGH IMPENANCE
SO
DOUT
MSB
Figure 2 : READ SEQUENCE
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Fast-Read (50 MHz ; 100 MHz)
F25L004A
The High-Speed-Read instruction supporting up to 100 MHz is
initiated by executing an 8-bit command, 0BH, followed by
through all addresses until terminated by a low to high transition
on CE . The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest
memory address is reached, the address pointer will
automatically increment to the beginning (wrap-around) of the
address space, i.e. for 4Mbit density, once the data from address
location 7FFFFH has been read, the next output will be from
address location 000000H.
address bits [A23-A0] and a dummy byte. CE must remain active
low for the duration of the High-Speed-Read cycle. See Figure 3
for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from the
specified address location. The data output stream is continuous
CE
0
1 2
3
4 5 6 7
8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
71 72
80
SCK
SI
0B
ADD.
MSB
ADD.
ADD.
X
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENANCE
SO
DOU T
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3 : HIGH-SPEED-READ SEQUENCE
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Byte-Program
F25L004A
The Byte-Program instruction programs the bits in the selected
byte to the desired data. The selected byte must be in the erased
state (FFH) when initiating a Program operation. A Byte-Program
instruction applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE must remain active low for
the duration of the Byte-Program instruction. The Byte-Program
instruction is initiated by executing an 8-bit command, 02H,
followed by address bits [A23-A0]. Following the address, the data
is input in order from MSB (bit 7) to LSB (bit 0). CE must be
driven high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait TBP for the
completion of the internal self-timed Byte-Program operation.
See Figure 4 for the Byte-Program sequence.
CE
0 1 2 3 4 5 6 7 8
1516
2324
3132
MODE3
MODE0
39
SCK
SI
02
ADD.
MSB
ADD.
ADD.
DIN
MSB
MSB LSB
HIGH IMPENANCE
Figure 4 : BYTE-PROGRAM SEQUENCE
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F25L004A
Auto Address Increment (AAI) WORD Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location.
This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program
instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when
initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD
program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware
detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End-of-Write
Detection section for details.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by
executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data is input sequentially.
The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data(DO) will be programmed into the initial address
[A23-A1] with A0 =0; The second byte of data(D1) will be programmed into the initial address [A23-A1] with A0 =1. CE must be driven
high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid
command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When
the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the
WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command.
Please refer to Figures 7 and Figures 8.
There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI
operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0).
End of Write Detection
There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading
the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end of write detection
method is described in the section below.
Hardware End of Write Detection
The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI
Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD
programming (refer to figure5). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once
an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0”
Indicates the device is busy ; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to
tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to
output software register data during AAI WORD programming (refer to figure6).
FIGURE 5 : ENABLE SO AS HARDWARE RY BY
DURING AAI PROGRAMMING
FIGURE 6 : DISABLE SO AS HARDWARE RY BY
DURING AAI PROGRAMMING
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2006
Revision: 1.0 13/32
ESMT
F25L004A
FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION
FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION
Elite Semiconductor Memory Technology Inc.
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ESMT
64K-Byte Block-Erase
F25L004A
The 64K Byte Block-Erase instruction clears all bits in the
selected block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE must remain active low for the duration of the any
command sequence. The Block-Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits
[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address)
are used to determine the block address (BAX), remaining
address bits can be VIL or VIH. CE must be driven high before
the instruction is executed. The user may poll the Busy bit in the
software status register or wait TBE for the completion of the
internal self-timed Block-Erase cycle. See Figure 9 for the
Block-Erase sequence.
FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2006
Revision: 1.0
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ESMT
4K-Byte-Sector-Erase
F25L004A
The Sector-Erase instruction clears all bits in the selected sector
to FFH. A Sector-Erase instruction applied to a protected
memory area will be ignored. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE must
remain active low for the duration of the any command sequence.
The Sector-Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23-A0]. Address bits
[AMS-A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status register or
wait TSE for the completion of the internal self-timed
Sector-Erase cycle. See Figure 10 for the Sector-Erase
sequence.
CE
15 16
31
23 24
0
1
2
3
4 5 6 7 8
MODE3
MODE0
SCK
SI
20
ADD.
MSB
ADD.
ADD.
MSB
HIGH IMPENANCE
SO
FIGURE 10 : SEQUENCE-ERASE SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2006
Revision: 1.0 16/32
ESMT
F25L004A
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A
Chip-Erase instruction will be ignored if any of the memory area
is protected. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE must remain active
low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command,
60H or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the software status
register or wait TCE for the completion of the internal self-timed
Chip-Erase cycle.
See Figure 11 for the Chip-Erase sequence.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
FIGURE 11 : CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
and remain low until the status data is read.
Read-Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE
See Figure 12 for the RDSR instruction sequence.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
CE must be driven low before the RDSR instruction is entered
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK MODE1
05
SI
MSB
HIGH IMPENANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status
Register Out
Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE
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Revision: 1.0 17/32
ESMT
F25L004A
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
04
MSB
HIGH IMPENANCE
SO
Figure 14 : WRITE DISABLE (WRDI) SEQUENCE
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ESMT
F25L004A
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the
Write-Status-Register (WRSR) instruction and opens the status
register for alteration. The Enable-Write-Status-Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write-Status-Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
BP2, BP1, BP0, and BPL bits of the status register. CE must be
driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 15 for EWSR or WREN and
WRSR instruction sequences.
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 ;BP1 and BP2 bits
Executing the Write-Status-Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lockdown the
status register, but cannot be reset from “1” to “0”.
at the same time. See Table 3 for a summary description of WP
and BPL functions.
CE
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
STATUS
REGISTER IN
7 6 5 4 3 2 1
50 or 06
SI
01
0
MSB
MSB
HIGH IMPENANCE
SO
Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR)
Elite Semiconductor Memory Technology Inc.
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ESMT
F25L004A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure
to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 19 and 20
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V ; TA=0~70oC
Limits
Symbol
Parameter
Test Conditions
Min
Max
Units
IDDR
IDDW
ISB
Read Current
15
mA
CE =0.1 VDD/0.9 VDD@33 MHz, SO=open
CE =VDD
Program and Erase Current
Standby Current
40
75
mA
µA
CE =VDD, VIN=VDD or VSS
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
ILO
VOUT=GND to VDD, VDD=VDD Max
VIL
VIH
VOL
VOH
VDD=VDD Min
0.7 VDD 0.8
Input High Voltage
Output Low Voltage
Output High Voltage
V
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
VDD-0.2 0.2
V
TABLE 7 : RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
10
10
1
TPU-WRITE
µs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2006
Revision: 1.0 20/32
ESMT
F25L004A
Read-Electronic-Signature (RES)
The RES instruction can be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide
access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any ERS instruction
executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress.
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK MODE1
AB
SI
MSB
HIGH IMPENANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status
Register Out
Figure 16 : Read-Electronic-Signature (RES)
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Revision: 1.0 21/32
ESMT
F25L004A
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as F25L004A and the manufacturer as ESMT. The device information can be read
from executing the 8-bit command,.9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the
device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, BFH, identifies the manufacturer as ESMT. Byte2, 20H (for TOP),
21H (for BOTTOM),identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25L004A. The instruction sequence is
shown in Figure17.
The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is
issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH).
CE
0 1 2 3 4 5 6 7 8 9
1819 20 2122 2324 2526 272829 30 3132 3334
MODE3
MODE0
10 1112 1314 1516 17
SCK
SI
9F
HIGH IMPENANCE
SO
8C
20 or 21
13
MSB
MSB
Figure 17 : Jedec Read ID Sequence
Table 9 : JEDEC READ-ID DATA
Device ID
Manufacturer’s ID
Memory Type
Memory Capacity
Byte1
Byte 2
Byte 3
20H (for TOP)
8CH
13H
21H (for Bottom)
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ESMT
F25L004A
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible
to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in
one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0].
Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H.
Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until
terminated by a low to high transition on CE .
Figure 18 : Read-Electronic-Signature
Table 10 : JEDEC READ-ID DATA
Address
Byte1
Byte2
Manufacturer’s ID
00000H
8CH
12H
Device ID
ESMT F25L004A
00001H
12H
8CH
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ESMT
F25L004A
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Cycles
Years
mA
Test Method
1
NEND
Endurance
100,000
10
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
Data Retention
Latch Up
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12 : AC OPERATING CHARACTERISTICS TA=0~70oC
Normal 33MHz Fast 50 MHz Fast 100 MHz
VDD=2.7~3.6V VDD=2.7~3.6V VDD=3.0~3.6V
Symbol
FCLK
Parameter
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Min
Max
Min
Max
Min
Max
Units
MHz
ns
33
50
100
TSCKH
TSCKL
13
13
5
9
9
5
5
ns
1
TCES
5
5
ns
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
ns
1
TCHS
5
5
5
ns
1
TCHH
5
5
5
ns
TCPH
100
100
100
ns
TCHZ
9
9
9
ns
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
TCLZ
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
3
5
5
5
5
ns
TDS
ns
TDH
Data In Hold Time
ns
THLS
ns
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
THHS
ns
THLH
ns
THHH
ns
HOLD High Hold Time
THZ
9
9
9
9
9
9
ns
HOLD Low to High-Z Output
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TLZ
ns
TOH
0
0
0
ns
TV
12
8
7
ns
1. Relative to SCK.
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ESMT
F25L004A
ERASE AND PROGRAMMING PERFORMANCE
Limits
Unit
Parameter
Typ.(2)
Max.(3)
Sector Erase Time
Block Erase Time
60
120
2
ms
1
s
s
Chip Erase Time
4
9
30
300
100
-
Byte Programming Time
Chip Programming Time
Erase/Program Cycles (1)
Data Retention
us
12
s
100,000
20
Cycles
Years
-
Notes:
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 3V.
3.Maximum values measured at 85°C, 2.7V.
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ESMT
F25L004A
FIGURE 19: SERIAL INPUT TIMING DIAGRAM
FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM
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ESMT
F25L004A
FIGURE 21: HOLD TIMING DIAGRAM
FIGURE 22: POWER-UP TIMING DIAGRAM
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ESMT
F25L004A
Input timing reference level
Output timing reference level
0.5VCC
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
Note : Input pulse rise and fall time are <5ns
FIGURE 23 : AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 24: A TEST LOAD EXAMPLE
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ESMT
F25L004A
PACKAGING DIAGRAMS
8-LEAD
SOP ( 150 mil )
8
5
GAUGE PLANE
L
DETAIL "X"
1
4
e
b
D
L1
"X"
SEATING PLANE
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
Norm
1.60
Max
Min
Norm
0.063
0.006
0.057
0.016
Max
Min
Norm
4.90
Max
Min
Norm
0.193
Max
A
A1
A2
b
1.35
0.10
1.25
0.33
0.19
5.80
1.75
0.25
1.55
0.51
0.25
6.20
0.053
0.004
0.049
0.013
0.069
0.010
0.061
0.020
0.010
0.244
D
E
L
4.80
3.80
0.40
5.00
4.00
1.27
0.189
0.150
0.016
0.197
0.157
0.050
0.15
3.90
0.154
1.45
0.66
0.026
0.406
0.203
6.00
e
1.27 BSC
1.05
0.050 BSC
0.041
c
0.0075 0.008
0.228 0.236
1.00
1.10
0.039
0.043
L1
θ
0°
8°
0°
8°
H
---
---
Controlling dimension : millimenter
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ESMT
F25L004A
PACKING
DIMENSIONS
8-LEAD
SOP ( 200 mil )
θ
5
8
4
1
b
e
D
L
L1
SEATING PLANE
DETAIL "X"
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
Norm
---
Max
Min
---
Norm
---
Max
Min
Norm
7.90
Max
Min
Norm
0.311
Max
0.319
0.212
0.032
A
A1
A2
b
---
2.16
0.25
1.91
0.51
0.25
5.33
0.085
0.010
0.075
0.020
0.010
0.210
E
E1
L
7.70
5.18
0.50
8.10
5.38
0.80
0.303
0.204
0.020
0.05
1.70
0.36
0.19
5.13
0.15
1.80
0.41
0.20
5.23
0.002
0.067
0.014
0.007
0.202
0.006
0.071
0.016
0.008
0.206
5.28
0.208
0.65
0.026
e
1.27 BSC
1.37
0.050 BSC
0.054
c
1.27
1.47
0.050
0.058
L1
θ
0°
8°
0°
8°
D
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
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ESMT
F25L004A
PACKING DIMENSIONS
8-Leads P-DIP ( 300 MIL )
D
8
5
0
1
4
S e a tin g P la n e
1
b
b
e
Dimension in mm
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
0.21
A
A1
A2
D
5.00
0.38
3.18
9.02
0.015
0.125
0.355
3.30
9.27
3.43
0.130
0.365
0.135
0.400
10.16
E
7.62 BSC.
6.35
0.300 BSC.
0.250
E1
L
6.22
9.02
6.48
0.245
0.115
0.255
0.150
9.27
10.16
0.130
e
2.54 TYP.
9.02
0.100 TYP.
0.355
eB
b
8.51
9.53
15O
0.335
0O
0.375
15O
0.46 TYP.
1.52 TYP.
7O
0.018 TYP.
0.060 TYP.
7O
b1
θO
0O
Controlling dimension : Inch.
Elite Semiconductor Memory Technology Inc.
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Revision: 1.0 31/32
ESMT
F25L004A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT 's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2006
Revision: 1.0 32/32
相关型号：
F25L004A-100PAIG
3V Only 4 Mbit Serial Flash Memory Operation Temperature Condition -40°C ~85°C
ESMT
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