F50L4G41XB [ESMT]
3.3V 4 Gbit SPI-NAND Flash Memory;
| 型号： | F50L4G41XB |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 3.3V 4 Gbit SPI-NAND Flash Memory |
| 文件： | 总51页 (文件大小：1471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F50L4G41XB (2X)
3.3V 4 Gbit
SPI-NAND Flash Memory
Flash
FEATURES
Single-level cell (SLC) technology
Organization
Security
- Block 0 is valid when shipped from factory with ECC
enabled
- Software write protection with lock register
- Hardware write protection to freeze BP bits
- Lock tight to freeze BP bits during one power cycle
- Permanent block lock protection
- OTP Space: 10 pages one-time programmable NAND
Flash memory area
Quality and reliability
- Endurance: 100,000 PROGRAM/ERASE cycles
- Data retention: JESD47H-compliant; see qualification
report
- Additional: Uncycled data retention: 10 years 24/7 @ 70°C
Operating voltage range
- VCC = 2.7–3.6V
- Page size ×1: 4352 bytes (4096 + 256 bytes)
- Block size: 64 pages (256K + 16K bytes)
- Plane size: 1 × 2048 blocks
Standard and extended SPI-compatible serial bus interface
- Instruction, address on 1 pin; data out on 1, 2, or 4 pins
- Instruction on 1 pin; address, data out on 2 or 4 pins
- Instruction, address on 1 pin; data in on 1 or 4 pins
- Continuous read within block, boot up ready, or
configure-able by feature register
User-selectable internal ECC supported
- 8 bits/sector
Array performance
- 133 MHz clock frequency (MAX)
- Page read: 25μs (MAX) with on-die ECC disabled; 115μs
(MAX) with on-die ECC enabled
- Page program: 200μs (TYP) with on-die ECC disabled;
240μs (TYP) with on-die ECC enabled
- Block erase: 2ms (TYP)
Operating temperature
- Commercial: 0°C to +70°C
Advanced features
- Read page cache mode (x2, x4, Dual, Quad, and Random)
- Read unique ID
- Read parameter page
Device initialization
- Automatic device initialization after power-up
ORDERING INFORMATION
Product ID
Speed
Package
8-contact LGA
8-contact LGA
Comments
F50L4G41XB-104RAG2X
104MHz
133MHz
8x6mm
8x6mm
Pb-free
Pb-free
F50L4G41XB-133RAG2X
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ESMT
F50L4G41XB (2X)
GENERAL DESCRIPTION
Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that provides a cost-effective nonvolatile memory
storage solution where pin count must be kept to a minimum. It is also an alternative solution to SPI NOR, offering superior write
performance and cost per bit over SPI NOR. The hardware interface creates a low pin-count device with a standard pinout that remains
the same from one density to another and supports future upgrades to higher densities without board redesign.
The serial electrical interface follows the industry-standard serial peripheral interface. New command protocols and registers are
defined for SPI operation. The command set resembles common SPI-NOR command sets, modified to handle NAND specific functions
and additional new features.
New features include continuous read within a block for increased performance and to support boot-up functionality. SPI NAND Flash
devices have six signal lines plus VCC and ground (GND). The signal lines are SCK (serial clock), SI, SO (for command/response and
data input/output), and control signals CS#, HOLD#, WP#. This hardware interface creates a low pin-count device with a standard
pinout that remains the same from one density to another, supporting future upgrades to higher densities without board redesign.
Each block of the serial NAND Flash device is divided into 64 programmable pages, each page consisting of 4352 bytes. Each page is
further divided into a 4096-byte data storage region and a 256-byte spare area. The spare area is typically used for memory and error
management functions.
With internal ECC enabled as the default after power on, ECC code is generated internally when a page is written to the memory core.
The ECC code is stored in the spare area of each page. When a page is read to the cache register, the ECC code is calculated again
and compared with the stored value. Errors are corrected if necessary. The device either outputs corrected data or returns an ECC
error status. The internal ECC can be configured off after device initialization. Contact ESMT representative if ECC is required to be
default off after power on.
The first block is valid when shipped from factory. Security functions are also provided including software block protection: Lock tight
and hardware protection modes avoid array data corruption.
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F50L4G41XB (2X)
Architecture
The devices use an industry-standard NAND Flash memory core organized by page/block. The standard parallel NAND Flash
electrical interface and I/O logic are replaced by an SPI interface. The new command protocol set is a modification of the SPI NOR
command set available in the industry. The modifications are specifically to handle functions related to NAND Flash architecture. The
interface supports page and random read/write and internal data move functions. The device also includes an internal ECC feature.
Data is transferred to or from the NAND Flash memory array, page-by-page, to a cache register and a data register. The cache register
is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a
data buffer for the NAND Flash memory array operation.
The NAND Flash memory array is programmed and read in page-based operations; it is erased in block-based operations. The cache
register functions as the buffer memory to enable random data READ/WRITE operations. These devices also use a new SPI status
register that reports the status of device operation.
Functional Block Diagram
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F50L4G41XB (2X)
PIN CONFIGURATION (TOP VIEW)
8-Contact LGA
(LGA 8C, 8mmx6 mm Body, 1.27mm Contact Pitch)
1
2
3
4
8
7
6
5
VCC
CS#
SO (IO1)
WP# (IO2)
VSS
HOLD# (IO3)
SCK
SI (IO0)
Pin Description
Pin Name
Type
Functions
Chip Select: Places the device in active power mode when driven LOW. Deselects the device and
places SO at High-Z when HIGH. After power-up, the device requires a falling edge on CS# before any
command can be written.
The device goes into standby mode when no PROGRAM, ERASE, or WRITE STATUS REGISTER
operation is in progress.
CS#
Input
In the case of write-type instructions, CS# must be driven HIGH after a whole sequence is completed.
Single command and address sequences and array-based operations are registered on CS#.
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on the
rising edge of SCK. Triggers output on SO after the falling edge of SCK. While CS# is HIGH, keep SCK
at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCK until CS# is driven LOW.
SCK
WP#
Input
Input
Write protect: When LOW, prevents overwriting block lock bits (BP[3:0] and TB) if the block register
write disable (BRWD) bit is set. WP# must not be driven by the host during a x4 READ operation. If the
device is deselected, this pin defaults as an input pin.
Hold: Hold functionality is disabled by default except the special part numbers. When enabled, the
external pull-up resistor is necessary to avoid accidental operation being placed on hold.
HOLD# pauses any serial communication with the device without deselecting it. To start the HOLD
condition, the device must be selected, with CS# driven LOW. During HOLD status (HOLD# driven
LOW), SO is High-Z and all inputs at SI and SCK are ignored. Hold mode starts at the falling edge of
HOLD#, provided SCK is also LOW. If SCK is HIGH when HOLD# goes LOW, hold mode is kicked off at
the next falling edge of SCK. Similarly, hold mode is exited at the rising edge of HOLD#, provided SCK
is also LOW. If SCK is HIGH, hold mode ends after the next falling edge of SCK. HOLD# must not be
driven by the host during the x4 READ operation.
HOLD#
Input
Serial I/O: The bidirectional I/O signals transfer address, data, and command information.
The device latches commands, addresses, and data on the rising edge of SCK, and data is shifted out on
the falling edge of the SCK. If the device is deselected, IO[0,2] defaults as an input pin and IO[1,3]
defaults as an output pin.
SI/IO0,
SO/IO1,
IO2, IO3
I/O
SI must not be driven by the host during x2 or x4 READ operations.
VCC: Supply voltage
VCC
VSS
Supply
VSS: Ground
Supply
Do not use: Must be left floating.
No Connect: Not internal connection; can be driven or floated.
DNU
NC
-
-
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ESMT
F50L4G41XB (2X)
Memory Mapping
Note:
1. The 13-bit column address is capable of addressing from 0 to 8191 bytes; however, only bytes 0 through 4351 are valid. Bytes
4352 through 8191 of each page are “out of bounds”, do not exist in the device, and cannot be addressed.
Array Organization
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F50L4G41XB (2X)
Bus Operation
SPI Modes
The device can be driven by a microcontroller with its SPI running in either of two modes depending on clock polarity (CPOL) and clock
phase (CPHA) settings:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.
The difference between the two modes, shown here, is the clock polarity when the bus master is in standby mode and not transferring
data.
• SCK remains at 0 for CPOL = 0, CPHA = 0 (Mode 0)
• SCK remains at 1 for CPOL = 1, CPHA = 1 (Mode 3)
SPI Modes Timing
Note:
1.
While CS# is HIGH, keep SCK at VCC or GND (determined by mode 0 or mode 3). Do not begin toggling SCK until after CS# is
driven LOW.
2.
All timing diagrams shown in this data sheet are mode 0.
SPI Protocols
Standard SPI: Command, address, and data are transmitted on a single data line. Input on SI is latched in on the rising edge of SCK.
Output on SO is available on the falling edge of SCK.
Extended SPI: An extension of the standard SPI protocol. Command and address are transmitted on a single data line through SI.
Data are transmitted on two or four data lines, IO[3:0], depending on the command.
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F50L4G41XB (2X)
Command Definitions
Command Set
Address
Byte
Dummy
Byte
Data
Bytes
Function
Op Code
Comments
RESET
FFh
0Fh
1Fh
9Fh
13h
30h
3Fh
0
1
1
0
3
3
0
0
0
0
1
0
0
0
0
1
1
2
0
0
0
Reset the device
Get features
GET FEATURES
SET FEATURES
READ ID
Set features
Read device ID
Array read
PAGE READ
READ PAGE CACHE RANDOM
READ PAGE CACHE LAST
Cache read
Ending of cache read
Output cache data at column
address
READ FROM CACHE x1
03h, 0Bh
2
1
1 to 4352
READ FROM CACHE x2
READ FROM CACHE x4
3Bh
6Bh
2
2
1
1
1 to 4352
1 to 4352
Output cache data on IO[1:0]
Output cache data on IO[3:0]
Input address/Output cache data
on IO[1:0]
READ FROM CACHE Dual IO
READ FROM CACHE Quad IO
BBh
EBh
2
2
1
2
1 to 4352
1 to 4352
Input address/Output cache data
on IO[3:0]
Sets the WEL bit in the status
register to 1; required to enable
operations that change the content
of the memory array
Clears the WEL bit in the status
register to 0; required to disable
operations that change the content
of the memory array
WRITE ENABLE
WRITE DISABLE
06h
04h
0
0
0
0
0
0
BLOCK ERASE
D8h
10h
3
3
0
0
0
0
Block erase
PROGRAM EXECUTE
Array program
Load program data into cache
register on SI
PROGRAM LOAD x1
PROGRAM LOAD x2
PROGRAM LOAD x4
02h
A2h
32h
2
2
2
0
0
0
1 to 4352
1 to 4352
1 to 4352
Load program data into cache
register on SI[1:0]
Load program data into cache
register on SI[3:0]
PROGRAM LOAD RANDOM
DATA x1
Overwrite cache register with input
data on SI
84h
2
0
1 to 4352
PROGRAM LOAD RANDOM
DATA x2
Overwrite cache register with input
data on SI[1:0]
44h
34h
2Ch
2
2
3
0
0
0
1 to 4352
1 to 4352
0
PROGRAM LOAD RANDOM
DATA x4
Overwrite cache register with input
data on SI[3:0]
PERMANENT BLOCK LOCK
PROTECTION
Permanently protect a specific
group of blocks
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F50L4G41XB (2X)
RESET Operation
The RESET command (FFh) is used to put the memory device into a known condition and to abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. Once the RESET command is issued
to the device, it will take tPOR to reset. During this period, the GET FEATURE command could be issued to monitor the status (OIP)
t
except for the stacked devices. For the stacked devices, no command should be issued until POR. The contents of the memory
location being programmed or the block being erased are no longer valid. The first page data of the first block is auto-loaded to the
cache register.
All other status register bits will be cleared. The ECC status register bits will be updated after a reset. The configuration register bits
CFG[2:0] will be cleared after a reset. All the other configuration register bits will not be reset. The block lock register bits will not be
cleared after reset until the device is power cycled or is written to by SET FEATURE command.
RESET (FFh) Timing
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F50L4G41XB (2X)
WRITE Operations
WRITE ENABLE (06h)
The WRITE ENABLE (06h) command sets the WEL bit in the status register to 1. Write enable is required in the following operations
that change the contents of the memory array:
PAGE PROGRAM
OTP AREA PROGRAM
BLOCK ERASE
WRITE ENABLE (06h) Timing
WRITE DISABLE (04h)
The WRITE DISABLE (04h) command clears the WEL bit in the status register to 0, disabling the following operations:
PAGE PROGRAM
OTP AREA PROGRAM
BLOCK ERASE
WRITE DISABLE (04h) Timing
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F50L4G41XB (2X)
Continuous Read Operation
Description
The device provides a capability to read the whole block with a single command after power-up. Upon power-up this mode is enabled
by default (CONT_RD = 1). Continuous read mode can be disabled (CONT_RD = 0) using SET FEATURE command.
Continuous Read Mode Matrix
CONTI_RD
ECC_ENABLE
Read Mode
Cache read
ECC Status
NA
Output
4096 + 256
4096 + 256
4096
0
0
1
1
0
1
0
1
Cache read
Target page
NA
Continuous read
Continuous read
Target block
4096
Power-up Behaviour
The READ CACHE command doesn't require the starting column address. The device always output the data starting from the first
column (byte 0) of the cache register, and once the end of the cache register is reached, the data output continues through the next
page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of
the block is reached, the output pins become High-Z state. The data output can be terminated by de-selecting the CS#. If the
continuous read is terminated by deselecting the CS# then the device will remain busy for 5μs (OIP = 1), and all the data inside the
data buffer will be lost and un-reliable to use. Below is the outline after the device comes out of power reset and ready to accept
command
READ FROM CACHE (03h, 0Bh, 3Bh, 6Bh, BBh, or EBh) command sequence
Read the data from address 0 until the end of the block or CS# is de-selected.
Read Operation with Continuous Mode On
The normal read mode requires PAGE READ (13h) command to specify which page of the block to read. After the device is not busy,
READ FROM CACHE can be used to output the data continuously. At the end of the block, the output pins become High-Z state. The
data output can be terminated anytime by de-selecting the CS#. If the continuous read is terminated by deselecting the CS# then the
device will remain busy for 5μs (OIP = 1), and all the data inside the data buffer will be lost and un-reliable to use. Below is the outline
of the sequence
PAGE READ Command (13h)
Wait until OIP bit of the status register is busy
READ FROM CACHE (03h, 0Bh, 3Bh, 6Bh, BBh, or EBh) command sequence
Read the data from address 0 until the end of the block or CS# is de-selected.
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F50L4G41XB (2X)
READ Operations
PAGE READ (13h)
The PAGE READ (13h) command transfers data from the NAND Flash array to the cache register. It requires a 24-bit address
consisting of 7 dummy bits and a 17-bit block/page address. After the block/page address is registered, the device starts the transfer
from the main array to the cache register. During this data transfer busy time of tRD, the GET FEATURES command can be issued to
monitor the operation.
Following successful completion of PAGE READ, the READ FROM CACHE command must be issued to read data out of cache. The
command sequence is as follows to transfer data from array to output:
13h (PAGE READ command to cache)
0Fh (GET FEATURES command to read the status)
03h or 0Bh (READ FROM CACHE)
3Bh (READ FROM CACHE x2)
6Bh (READ FROM CACHE x4)
BBh (READ FROM CACHE Dual I/O)
EBh (READ FROM CACHE Quad I/O)
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F50L4G41XB (2X)
PAGE READ (13h) Timing
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F50L4G41XB (2X)
READ FROM CACHE x1 (03h or 0Bh)
The READ FROM CACHE x1 command enables sequentially reading one or more data bytes from the cache buffer. The command is
initiated by driving CS# LOW, shifting in command opcode 03h/0Bh, followed by a 16 bit column address and 8-bit dummy clocks. Both
the commands run at fast mode.
Data is returned from the addressed cache buffer, MSB first, on SO at the falling edge of SCK. The address is automatically
incremented to the next higher address after each byte of data is shifted out, enabling a continuous stream of data. This command is
completed by driving CS# HIGH.
READ FROM CACHE (03h or 0Bh) Timing
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F50L4G41XB (2X)
READ FROM CACHE x2 (3Bh)
The READ FROM CACHE x2 (3Bh) command is similar to READ FROM CACHE x1 (03h or 0Bh) except that data is output on the
following two pins, enabling data transfer at twice the rate: IO0(SI) and IO1(SO).
READ FROM CACHE x2
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F50L4G41XB (2X)
READ FROM CACHE x4 (6Bh)
The READ FROM CACHE x4 (6Bh) command is similar to READ FROM CACHE x1 command, but with the capability to output data
across four data lines.
READ FROM CACHE x4
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F50L4G41XB (2X)
READ FROM CACHE Dual I/O (BBh)
The READ FROM CACHE Dual IO (BBh) command enables improved random access while maintaining two IO pins, IO0 and IO1. It is
similar to the READ FROM CACHE x2 (3Bh) command but with capability to input either the column address or the dummy clocks two
bits per clock, thereby reducing command overhead. Refer to the Electrical Specifications for the supported frequency.
READ FROM CACHE Dual I/O
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F50L4G41XB (2X)
READ FROM CACHE Quad I/O (EBh)
The READ FROM CACHE Quad I/O (EBh) command is similar to the READ FROM CACHE Dual I/O (BBh) command except that
address and data bits are input and output through four pins: IO0, IO1, IO2, and IO3. The quad IO dramatically reduces command
overhead, enabling faster random access to the cache buffer. Refer to the Electrical Specifications for the supported frequency.
READ FROM CACHE Dual I/O
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F50L4G41XB (2X)
READ PAGE CACHE RANDOM (30h)
This mode is not available when continuous mode is enabled. The READ PAGE CACHE RANDOM (30h) command reads the
specified block and page into the data register while the previous page is output from the cache register. This command is accepted by
the die when it is ready (OIP = 0, CRBSY = 0). This command is used to improve the read throughput as follows:
1.
2.
3.
13h – PAGE READ to cache
0Fh – GET FEATURE command to the read status until OIP status bit is changed from 1 to 0
30h – READ PAGE CACHE RANDOM command to transfer data from data register to cache register and kick off the next page
transfer from array to data register
4.
5.
6.
7.
8.
0Fh – GET FEATURE command to read the status until OIP status bit is changed from 1 to 0
03h, 0Bh, 3Bh, 6Bh, BBh, or EBh – READ FROM CACHE TO OUTPUT command
0Fh – GET FEATURE command to read the status until CRBSY = 0
Repeat step 3 to step 6 to read out all expected pages until last page
3Fh – READ PAGE CACHE LAST command to end the read page cache sequence and copy a last page from the data register
to the cache register
9.
0Fh – GET FEATURE command to read the status until OIP status bit is changed from 1 to 0
10. 03h, 0Bh, 3Bh, 6Bh, BBh, or EBh – READ FROM CACHE TO OUTPUT command to read out last page from cache register to
output
The READ PAGE CACHE RANDOM command requires a 24 bit address consisting of 7 dummy bits followed by a 17-bit block/page
address. After the block/page addresses are registered, the device starts to transfer data from data register to cache register for
tRCBSY. After tRCBSY, OIP bit (through GET FEATURE command to check this status bit) goes to 0 from 1, indicating that the cache
register is available and that the specified page in the READ PAGE CACHE RANDOM command is copying from the the Flash array to
the data register. At this point, data can be output from the cache register beginning at the column address specified by READ FROM
CACHE commands.
The status register CRBSY bit value remains at 1, indicating that the specified page in READ PAGE CACHE RANDOM command is
copying from the Flash array to the data register; CRBSY returns to 0 to indicating the copying from array is completed. During tRCBSY,
the error check and correction is also performed.
Note: With an on-die ECC-enabled die, ECC is executed after data is transferred from the data register to the cache register; therefore,
tRCBSY includes this ECC time, which must be factored in when checking the OIP status.
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F50L4G41XB (2X)
READ PAGE CACHE RANDOM Sequence
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F50L4G41XB (2X)
READ PAGE CACHE LAST (3Fh)
The READ PAGE CACHE LAST (3Fh) command ends the READ PAGE CACHE RANDOM sequence and copies a page from the data
register to the cache register. This command is accepted by the die when it is ready (OIP = 0, CRBSY = 0). After this command is
issued, the status register bit OIP goes HIGH and the device is busy (CRBSY = 0, OIP = 1) for tRCBSY. Address is not applied in this
command sequence. When data is completely copied to cache register, OIP goes LOW and READ FROM CACHE commands could
be issued to output data.
READ ID (9Fh)
READ ID reads the 2-byte identifier code programmed into the device, which includes ID and device configuration data as shown in the
table below.
READ ID Table
Byte
Description
7
0
0
6
0
0
5
1
1
4
0
1
3
1
0
2
1
1
1
0
0
0
0
0
Value
2Ch
Byte 0
Byte 1
Manufacturer ID
4Gb 3.3V Device ID
34h
READ ID (9Fh) Timing
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F50L4G41XB (2X)
Parameter Page
The following command flow must be issued by the memory controller to access the parameter page contained within SPI devices:
1.
2.
3.
4.
1Fh – SET FEATURES command with a feature address of B0h and data value for CFG[2:0] = 010b ( to access OTP /
Parameter / Unique ID pages).
13h – PAGE READ command with a block/page address of 0x01h, and then check the status of the read completion using the
GET FEATUR ES (0Fh) command with a feature address of C0h.
03h – READ FROM CACHE command with an address of 0x00h to read the data out of the NAND device (see the following
Parameter Page Data Structure table for a description of the contents of the parameter page.)
1Fh – SET FEATURES command with a feature address of B0h and data value of 00h to exit the parameter page reading.
Parameter Page Data Structure Table
Parameter Table
Byte
0-3
Description
Parameter page signature
Value
4Fh, 4Eh, 46h, 49h
4-5
Revision number
Feature support
00h
6-7
00h
8-9
Optional commands support
Reserved
06h, 00h
00h
10-31
4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h,
20h
32-43
44-63
Device manufacturer
Device model
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 31h, 41h, 42h,
41h, 46h, 44h, 33h, 57h, 20h, 20h, 20h, 20h
64
65-66
67-79
80-83
84-85
86-89
90-91
92-95
96-99
100
Manufacturer ID
2Ch
Date code
00h
Reserved
00h
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
Number of blocks per unit
Number of logical units
Number of address cycles
Number of bits per cell
Bad blocks maximum per unit
Block endurance
00h, 10h, 00h, 00h
00h, 01h
00h, 04h, 00h, 00h
40h, 00h
40h, 00h, 00h, 00h
00h, 08h, 00h, 00h
01h
101
00h
102
01h
103-104
105-106
107
28h, 00h
01h, 05h
08h
Guaranteed valid blocks at beginning of target
Block endurance of guaranteed valid blocks
Number of programs per page
108-109
110
00h
04h
111
Partial programming attributes
00h
112
Number of ECC bits
00h
113
Number of Interleaved address bits
Interleaved operation attributes
00h
114
00h
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F50L4G41XB (2X)
Parameter Table (Continued)
Description
Byte
Value
115-127
128
Reserved
00h
I/O pin capacitance
09h
129-130
131-132
133-134
135-136
137-138
139-140
141-163
164-165
Timing mode support
00h
Program cache timing
tPROG maximum page program time
tERS maximum block erase time
tR maximum page read time
tCCS minimum
00h
58h, 02h
10h, 27h
73h, 00h
00h
Reserved
00h
Vendor-specific revision number
00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 02h, 02h,
B0h, 0Ah, B0h
166-179
Vendor specific
180-247
248
Reserved
00h
ECC maximum correct ability
Die select feature
08h
249
00h
250-253
254-255
256-512
513-768
769-2048
Reserved
00h
Integrity CRC
Calculated
2nd copy of the parameter table
3rd copy of the parameter table
Additional redundant parameter pages
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F50L4G41XB (2X)
Unique ID Page
The following command flow must be issued by the memory controller to access the unique ID page contained within the device:
1.
2.
Issue a SET FEATURES (1Fh) command on a feature address of B0h and data value of 40h (Access to OTP, Parameter,
Unique ID pages, ECC disable).
Issue a PAGE READ (13h) command on a block/page address of 0x00h, and then poll the status register OIP bit until device
ready using the GET FEATURES (0Fh) command issued on a feature address of C0h.
3.
4.
Issue a READ FROM CACHE (03h) command on an address of 0x00h to read the unique ID data out of the NAND device.
To exit reading the unique ID page, issue a SET FEATURES (1Fh) command with a feature address of B0h and data value of
10h or 00h (main array READ, ECC enable/ disable).
The device stores 16 copies of the unique ID data. Each copy is 32 bytes: the first 16 bytes are unique data, and the second 16 bytes
are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16 bytes of
FFh, that copy of the unique ID data is correct. If a non-FFh result is returned, the host can repeat the XOR operation on a subsequent
copy of the unique ID data.
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F50L4G41XB (2X)
Program Operations
PAGE PROGRAM (02h/10h)
A PAGE PROGRAM operation sequence enables the host to input 1 byte to 4352 bytes of data within a page to a cache register, and
moves the data from the cache register to the specified block and page address in the array. If more than 4352 bytes are loaded, then
those additional bytes are ignored by the cache register.
The page program sequence is as follows:
06h (WRITE ENABLE command)
02h (PROGRAM LOAD command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
PROGRAM LOAD x1 (02h)
Prior to performing the PROGRAM LOAD operation, a WRITE ENABLE (06h) command must be issued. As with any command that
changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. WRITE ENABLE is
followed by a PROGRAM LOAD (02h) command. The PROGRAM LOAD command consists of an 8-bit op code, followed by 3 dummy
bits, and a 13-bit column address, and then the data bytes to be programmed. The data bytes are loaded into a cache register that is
4352 bytes long. Only four partial-page programs are allowed on a single page. If more than 4352 bytes are loaded, those additional
bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH.
PROGRAM LOAD (02h) Timing
Note: 1. WRITE ENABLE (06h) and PROGRAM LOAD (02h) are required before PROGRAM EXECUTE (10h) command.
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F50L4G41XB (2X)
PROGRAM EXECUTE (10h)
The PROGRAM EXECUTE command consists of an 8-bit op code, followed by a 24-bit address. After the page/block address is
t
registered, the device starts the transfer from the cache register to the main array and is busy for PROG time. During this busy time,
the status register can be polled to monitor the status of the operation (refer to the status register section). When the operation
completes successfully, the next series of data can be loaded with the PROGRAM LOAD command.
PROGRAM EXECUTE (10h) Timing
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F50L4G41XB (2X)
RANDOM DATA PROGRAM x1 (84h)
The RANDOM DATA PROGRAM operation programs or replaces data in a page with existing data. The random data program
sequence is as follows:
06h (WRITE ENABLE command)
84h (PROGRAM LOAD RANDOM DATA command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
The PROGRAM LOAD RANDOM DATA x1 (84h) operation is similar to PROGRAM LOAD x1 (02h). The difference is that PROGRAM
LOAD X1 command will reset the cache buffer to an all FFh value, while PROGRAM LOAD RANDOM DATA X1 command will only
update the data bytes that are specified by the command input sequence, and the rest of data in the cache buffer will remain
unchanged. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA x1 (84h) command must be issued
with a new column address. After the data is loaded, a PROGRAM EXECUTE (10h) command can be issued to start the programming
operation.
PROGRAM LOAD RANDOM DATA (84h) Timing
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F50L4G41XB (2X)
PROGRAM LOAD x2 (A2h) / PROGRAM LOAD RANDOM DATA x2 (44h)
The PROGRAM LOAD x2 and PROGRAM LOAD RANDOM DATA x2 instructions are similar to the PROGRAM LOAD and PROGRAM
LOAD RANDOM DATA in terms of operation sequence and functionality. The only difference is that x2 instructions will input the data
bytes from 2 I/O pins instead of the single SI pin.
Both PROGRAM LOAD x2 and PROGRAM LOAD RANDOM DATA x2 instructions are the same command sequence. The difference is
that PROGRAM LOAD x2 instruction will reset the cache buffer to all FFh value, while PROGRAM LOAD RANDOM DATA x2
instruction will only update the data bytes that are specified by the command input sequence and the rest of data in the cache buffer will
remain unchanged.
PROGRAM LOAD x2 (A2h) Timing
PROGRAM LOAD x4 (32h) and PROGRAM LOAD RANDOM DATA x4 (34h)
The PROGRAM LOAD x4 (32h) and RANDOM DATA x4 (34h) is similar to PROGRAM LOAD x1 (02h) command and RANDOM DATA
x1 (84h), but with the capability to input the data across four data lines.
PROGRAM LOAD x4 (32h) Timing
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F50L4G41XB (2X)
INTERNAL DATA MOVE
The INTERNAL DATA MOVE command programs or replaces data in a page with existing data. The INTERNAL DATA MOVE
command sequence is as follows:
13h (PAGE READ command to cache)
06h (WRITE ENABLE command)
84h (PROGRAM LOAD RANDOM DATA command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
Prior to performing an INTERNAL DATA MOVE operation, the target page content must be read into the cache register. This is done by
issuing a PAGE READ (13h) command. The PAGE READ command must be followed with a WRITE ENABLE (06h) command in order
to change the contents of memory array. After the WRITE ENABLE command is issued, the PROGRAM LOAD RANDOM DATA (84h)
command, PROGRAM LOAD RANDOM DATA x2 (44h) command, or PROGRAM LOAD RANDOM DATA x4 (34h) can be issued. This
command consists of an 8-bit Op code, followed by 3 dummy bits, a 13-bit column address and the new data to be loaded. If the
random data is not sequential, another PROGRAM LOAD RANDOM command must be issued with the new column address. After all
data are loaded, a PROGRAM EXECUTE (10h) command can be issued to start the programming operation. It is not possible to use
the INTERNAL DATA MOVE operation to move data from one die (LUN) to another.
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F50L4G41XB (2X)
Block Erase Operations
The BLOCK ERASE (D8h) command is used to erase at the block level. The blocks are organized as 64 pages per block. The BLOCK
ERASE command (D8h) operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
06h (WRITE ENABLE command)
D8h (BLOCK ERASE command)
0Fh (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06h) command must be issued. As with any command that
changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. If the WRITE ENABLE
command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE command must be followed by a BLOCK
ERASE (D8h) command. This command requires a 24-bit address consisting of dummy bits followed by a valid block address. After the
address is registered, the control logic automatically controls timing and ERASE and VERIFY operations. The device is busy for tERS
time during the BLOCK ERASE operation. The GET FEATURES (0Fh) command can be used to monitor the status of the operation.
(See the following figure.)
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F50L4G41XB (2X)
BLOCK ERASE (D8h) Timing
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F50L4G41XB (2X)
Features Operations
GET FEATURES (0Fh) and SET FEATURES (1Fh)
The GET FEATURES (0Fh) and SET FEATURES (1Fh) commands either monitor the device status or alter the device configuration
from the default at power-on. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP protect, block locking, SPI NOR like protocol configuration, and ECC correction can be managed by setting
specific bits in feature addresses. Typically, the status register at feature address C0h is read to check the device status, except WEL,
which is a writable bit with the WRITE ENABLE (06h) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless specified otherwise, when the
device is set, it remains set even if a RESET (FFh) command is issued. CFG[2:0] will be cleared to 000 after a reset and the device is
back to normal operation.
GET FEATURES (0Fh) Timing
SET FEATURES (1Fh) Timing
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F50L4G41XB (2X)
Feature Settings
Feature Address Settings and Data Bits
Feature Data Bits
Feature
Address
Register
Notes
7
6
5
4
3
2
1
0
WP#/
HOLD#
Disable
Address = A0h;
Access = R/W
BRWD
BP3
BP2
BP1
BP0
TB
–
Block lock
Configuration
Status
1
2
1
Address = B0h;
Access = R/W
CFG2
CFG1
LOT_EN
ECCS1
ECC_EN
ECCS0
DS_S1
P_Fail
DS_S0
E_Fail
CFG0
WEL
CONTI_RD
OIP
Address = C0h;
Access = R
CRBSY
ECCS2
Notes:
1.
When the WP#/HOLD# disable bit is at the default value of 0, and with BRWD set to 1 and WP# LOW, block lock registers [7:2]
cannot be changed.
2.
DS_Sx are used to adjust the driver strength and CONTI_RD provides capability to enable / disable continuous read.
Driver Strength Configuration (DS_S1/DS_S0)
The driver strength configuration bits (DS_S1/DS_S0) are default at 00 after power-up, when these bits are updated with SET
FEATURE command, they remain active even if a RESET command is issued, until the device is power cycled or these bits are
updated again.
Driver Strength Register Bits Descriptions
DS_S1
DS_S1
Drive Strength (%)1
0
0
1
1
0
1
0
1
100
75
50
25
Note: 1. POR frequency is guaranteed only at 100% drive strength.
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F50L4G41XB (2X)
Security – Volatile Block Protection
The block lock feature protects the entire device or ranges of device blocks from the PROGRAM and ERASE operations. The SET
FEATURE command must be issued to alter the state of block protection. After power-up, the device is in the locked state by default;
block lock register bits BP[3:0] and TB are 1 . Reset will not modify the block protection state. When a PROGRAM/ERASE command is
issued to a locked block, a status register P_Fail bit or E_Fail bit will be set to indicate the operation failure.
The following command sequence unlocks all blocks after power-up: The SET FEATURES REGISTER WRITE (1Fh) operation is
issued, followed by the feature address (A0h). Then, 00h is issued on data bits to unlock all blocks.
Security – Block Protection Bits
Block Lock Register Block Protect Bits
TB
BP3
BP2
BP1
BP0
Protected Portion
Protected Blocks
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
None—all unlocked
Upper 1/1024 locked
Upper 1/512 locked
Upper 1/256 locked
Upper 1/128 locked
Upper 1/64 locked
Upper 1/32 locked
Upper 1/16 locked
Upper 1/8 locked
Upper 1/4 locked
Upper 1/2 locked
All unlocked
None
1023
0
0
1022:1023
1020:1023
1016:1023
1008:1023
992:1023
960:1023
896:1023
768:1023
512:1023
None
0
1
1
1
1
0
0
0
0
All others
All locked
0:1023
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Lower 1/1024 locked
Lower 1/512 locked
Lower 1/256 locked
Lower 1/128 locked
Lower 1/64 locked
Lower 1/32 locked
Lower 1/16 locked
Lower 1/8 locked
Lower 1/4 locked
Lower 1/2 locked
All locked (default)
0:1
0:3
0:7
0:15
0:31
0:63
0:127
0:255
0:511
0:1023
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F50L4G41XB (2X)
Security – Hardware Write Protection
Hardware write protection prevents the block protection state from hardware modifications. In order to utilize this feature, SET
FEATURE command is issued on the feature address A0h and WP#/HOLD# disable bit state is set to 0.
The BRWD bit is operated in conjunction with WP#/Hold# disable bit. When BRWD is set to 1 and WP# is LOW, none of the other
block lock register bits [7:2] can be set. The block lock state cannot be changed, regardless of what is unlocked or locked. Also, when
the WP#/Hold# disable bit is set to 1, the hardware protected mode is disabled.
The default value of BRWD and WP#/Hold# disable bits = 0 after power up.
WP# Timing
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F50L4G41XB (2X)
Security – Device Lock Tight (LOT)
The lock tight mode prevents the block protection state from software modifications. After it is enabled, this mode cannot be disabled
by a software command. Also, BP, TB, and BRWD bits are protected from further software changes. Only another power cycle can
disable the lock tight mode.
The following command sequence enables the lock tight mode: The SET FEATURES REGISTER WRITE (1Fh) operation is issued,
followed by the feature address (B0h). Then, data bits are set to enable LOT (LOT_EN bit = 1).
When the hardware write protection mode is disabled during quad or x4 mode, lock tight can be used to prevent a block protection
state change.
Permanent Block Lock Protection
48 blocks per die (0 to 47) can be permanently locked using PROTECT command. The PROTECT command provides nonvolatile,
irreversible protection of up to twelve groups (48 blocks). Implementation of the protection is group-based, which means that a
minimum of one group (4 blocks) is protected when the PROTECT command is issued. Because block protection is nonvolatile, a
power-on or power-off sequence does not affect the block status after the PROTECT command is issued. The device is shipped from
the factory with no blocks protected so that users can program or erase the blocks before issuing the PROTECT command. Block
protection is also irreversible in that when protection is enabled by issuing the PROTECT command, the protected blocks can no
longer be programmed or erased. If permanent lock is disabled, PROTECT command would be ignored. As with any command that
changes the memory contents, the WRITE ENABLE must be executed. If this command is not issued, then the PROTECT command is
ignored. WRITE ENABLE must be followed by a PROTECT command (2Ch).
The following PROTECT sequence is used:
06h (WRITE ENABLE)
2Ch (PERMANENT BLOCK LOCK PROTECTION)
24-bit address (see the PROTECT Command Details)
After tPROG time, use GET FEATURE command (0Fh) with feature address C0h to verify P_Fail bit
PROTECT Command Cycle
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F50L4G41XB (2X)
PROTECTION Command (2Ch) Details
To enable protection, the PROTECTION command consists of an 8-bit command code, followed by a 24-bit address (7 dummy bits
and an 17-bit page/ block address). Row address bits 11, 10, 9, 8 (named as Y) input the targeted block group information. Where Y
defines the group of blocks to be protected. There are 12 Groups Y where Y = 0000b-1011b:
Y = 0000 protects Group0 = blks 0, 1, 2, 3.
Y = 0001 protects Group1 = blks 4, 5, 6, 7.
......
Y = 1011 protects Group11 = blks 44, 45, 46, 47.
t
After PROG, the targeted block groups are protected. Upon PROTECT operation failure, the status register reports a value of 08h
(P_FAIL = 1 and WEL = 0). Upon PROTECT operation success, the status register reports a value of 00h.
Note: There is no status register to check the PROTECT status of a block or a group. A permanent blocks table should be maintained
and updated after a group is protected.
Permanent Block Lock Protection Disable Mode
This mode disables the ability to accept the PROTECT command. Running this command sequence ensures no more groups can ever
be permanently locked.
The following disable PROTECT sequence is used
SET FEATURE command (1Fh) with B0h mode and data value C2h
06h (WRITE ENABLE)
10h (Execute with block/page address as '0')
After tPROG time, use GET FEATURE command (0Fh) with feature address C0h to verify P_Fail bit
Permanent Block Protection Status Read
To determine whether the device is busy getting the block protection status, use GET FEATURE command at address C0h to check
OIP bit. Once ready, any READ FROM CACHE command could be used to check the target block’s protection status, reading out all
"0" indicate the target block is permanently protected; all "1" indicates target block is not permanently protected.
To exit from permanent block protection status read mode and return to normal array operation mode, issue the SET FEATURE
command (1Fh) to feature address B0h and data value with OTP_CFG[2:0] = 000b.
If the RESET (FFh) command is issued while in permanent block protection status read mode, the device will exit this mode and enter
normal operation mode.
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F50L4G41XB (2X)
Security – One Time Programmable (OTP)
This device offers a protected, one-time programmable NAND Flash memory area. Ten full pages per die are available, and the entire
range is guaranteed. Users can choose how to use the OTP area, such as programming serial numbers or other data for permanent
storage. The OTP area can't be erased. When ECC is enabled, data written in the OTP area is ECC protected. Besides some
additional configuration bits are described in this section.
Enable OTP Access
OTP access needs to be enabled in order to read and write to the OTP region. When the die is in OTP operation mode, all subsequent
PAGE PROGRAM or PAGE READ commands are applied to the OTP area. SET FEATURES command (1Fh) with feature address
B0h and data 50h (OTP operation mode with ECC enabled) or 40h (OTP operation mode with ECC disabled) are used to enable the
OTP access.
After OTP access is enabled, the following sequence is used to program one or more pages:
WRITE ENABLE command (06h)
PROGRAM EXECUTE command (10h) with the row address of page (OTP page address range 02h-0Bh)
Verify until OIP bit not busy using GET FEATURE command (0Fh) with feature address C0h
Using GET FEATURE command (0Fh) with feature address C0h, verify if P_FAIL bit is 0 for the successful operation.
After OTP access is enabled, the following sequence is used to read one or more pages
PAGE READ command (13h) with the page address (02h-0Bh)
Verify until OIP bit is not busy using GET FEATURE command (0Fh) with feature address C0h
Page data using READ FROM CACHE command (03h).
OTP Configuration States
To check the status of OTP data protect, SPI NOR read enable, or permanent block Lock protection, the following sequence is used:
SET FEATURES command (1Fh) with feature address B0h and data (C0h for OTP data protect bit, 82h for NOR read protocol
enable bit, C2h for permanent block lock disable bit)
PAGE READ command (13h) with address 0
Verify until OIP bit not busy using GET FEATURE command (0Fh) with feature address C0h
READ FROM CACHE command (03h) with address 0
Expect the read from cache data all 1 for the mode disabled or all "0" for enabled.
Note: Configuration status of CFG[2:0] can be read using GET FEATURE command (0Fh) with feature address B0h.
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F50L4G41XB (2X)
OTP Protection and Program Prevention
This mode is used to prevent further programming of the pages in the OTP area. To protect and prevent programming the OTP area,
the following sequence is used:
SET FEATURES command (1Fh) with feature address B0h and data C0h (CFG[2:0] = 110b)
WRITE ENABLE command (06h)
PROGRAM EXECUTE command (10h) with the row address 00h
Verify until OIP bit not busy and P_FAIL bit 0 using GET FEATURE command (0Fh) with status register address C0h.
Exit OTP
To exit from OTP operation mode and return the device to normal array operation mode, the SET FEATURES command (1Fh) is
issued. This is followed by setting the feature address = B0h and data CFG[2:0] = 000b. Last, the RESET (FFh) command is issued.
Configuration Registers for Security
CFG2
CFG1
CFG0
State
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
Normal operation
Access to permanent block protect status read mode
Access OTP area/Parameter/Unique ID
Access to OTP data protection bit to lock OTP area
Access to SPI NOR read protocol enable mode
Access to permanent block lock protection disable mode
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F50L4G41XB (2X)
Status Register
The device has an 8-bit status register that software can read during the device operation. All bits are read-only register except WEL,
which could be changed by WRITE DISABLE (04h) and WRITE ENABLE (06h) commands. None of bits can be changed by SET
FEATURE command (1Fh).The status register can be read by issuing the GET FEATURES (0Fh) command, followed by the feature
address (C0h). The status register will output the status of the operation.
Status Register Bit Descriptions
Bit
Bit Name
Description
This bit is set (CRBSY = 1) when READ PAGE CACHE RANDOM command is
executing; this bit remains a 1 until the page specified at READ PAGE CACHE
RANDOM command is transferred from array to data register. When the bit is 0,
the device is in the ready state and background read page cache operation is
completed.
7
Cache read busy (CRBSY)
RESET command is acceptable during CRBSY = 1 and could halt background
read page cache operation and download first page at block 0 into cache
register at default.
See ECC Protection for the ECC status definition.
ECC status is set to 000b either following a RESET or at the beginning of the
READ. It is then updated after the device completes a valid READ operation.
6
5
4
ECC status register (ECCS2)
ECC status register (ECCS1)
ECC status register (ECCS0)
ECC status is invalid if ECC is disabled (via a SET FEATURES command to get
access the configuration register).
After a power-up RESET, ECC status is set to reflect the contents of block 0,
page 0.
Indicates that a program failure has occurred (P_Fail = 1). This bit will also be
set if the user attempts to program a locked or protected region, including the
OTP area.
3
2
1
0
Program fail (P_Fail)
This bit is cleared during the PROGRAM EXECUTE command sequence or a
RESET command (P_Fail = 0).
Indicates that an erase failure has occurred (E_Fail = 1). This bit will also be set
if the user attempts to erase a locked region or if the ERASE operation fails.
Erase fail (E_Fail)
This bit is cleared (E_Fail = 0) at the start of the BLOCK ERASE command
sequence or a RESET command.
Indicates the current status of the write enable latch (WEL) and must be set
(WEL = 1) prior to issuing a PROGRAM EXECUTE or BLOCK ERASE
command. It is set by issuing the WRITE ENABLE command.
Write enable latch (WEL)
Operation in progress (OIP)
WEL can also be cleared (WEL = 0) by issuing the WRITE DISABLE command
or a successful PROGRAM/ERASE operation.
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, READ
PAGE CACHE LAST, BLOCK ERASE, READ PAGE CACHE RANDOM (within
tRCBSY to wait for cache register readiness) or RESET command or a
power-up initialization is executing; the device is busy.
When the bit is 0, the interface is in the ready state.
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F50L4G41XB (2X)
ECC Protection
The device offers an 8-bit data corruption protection by offering internal ECC to obtain the data integrity. The internal ECC can be
enabled or disabled by setting the ECC_EN bit in the configuration register. ECC is enabled after device power-up by default. The
READ and PROGRAM commands operate with internal ECC by default. Reset will not change the existing configuration. To
enable/disable ECC after power on, perform the following command sequence:
Issue the SET FEATURES command (1Fh)
Issue configuration register address (B0h)
Then: To enable ECC, set bit 4 (ECC enable) to 1; To disable ECC, clear bit 4 (ECC enable) to 0
During a PROGRAM operation, the device calculates an expected ECC code on the ECC-protected bytes in the cache register, before
the page is written to the NAND Flash array.
The ECC code is stored in the spare area of the page.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared
with the expected ECC code value read from the array. If a 1–8-bit error is detected, the error is corrected in the cache register.
Only corrected data is output on the I/O bus. The ECC status register bit indicates whether or not the error correction is successful. The
table below describes the ECC protection scheme used throughout a page.
Note: The unique ID and parameter page are not ECC-protected areas. Multiple copies are provided for parameter page to obtain the
data integrity. XOR method is provided for unique ID to verify the data.
With internal ECC, users must accommodate the following (details provided in table below):
Spare area definitions
WRITEs are supported for main and spare areas (user meta data I and II). WRITEs to the ECC area are prohibited
When using partial-page programming, the following conditions must both be met:
In the main user area and user meta data area I, single partial-page programming operations must be used
Within a page, a maximum of four partial-page programming operations can be performed
ECC Status Register Bit Descriptions
Bit 2
Bit 1
Bit 0
Description
0
0
0
0
0
0
1
1
0
1
0
1
No errors
1-3 bit errors detected and corrected
Bit errors greater than 8 bits detected and not corrected
4-6 bit errors detected and corrected. Indicates data refreshment might be taken
7-8 bit errors detected and corrected. Indicates data refreshment must be taken to
guarantee data retention
1
0
1
Others
Reserved
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F50L4G41XB (2X)
ECC Protection
Max Byte
Address
ECC
Protected
Min Byte
Address
Area
Description
1FFh
3FFh
000h
200h
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Main 0
Main 1
Main 2
Main 3
Main 4
Main 5
Main 6
Main 7
Spare 0
Spare 1
Spare 2
Spare 3
Spare 4
Spare 5
Spare 6
Spare 7
User data 0
User data 1
User data 2
User data 3
User data 4
User data 5
User data 6
User data 7
5FFh
400h
7FFh
600h
9FFh
800h
BFFh
DFFh
FFFh
1003h
1007h
100Bh
100Fh
1013h
1017h
101Bh
101Fh
A00h
C00h
E00h
1000h
1004h
1008h
100Ch
1010h
1014h
1018h
101Ch
Reserved (bad block data)
Reserved or meta data II
Reserved or meta data II
Reserved or meta data II
Reserved or meta data II
Reserved or meta data II
Reserved or meta data II
Reserved or meta data II
No
No
No
No
No
No
No
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F50L4G41XB (2X)
Error Management
This NAND Flash device is specified to have the minimum number of valid blocks (NVB) of the total available blocks per die shown in
the table below. This means the devices may have blocks that are invalid when shipped from the factory. An invalid block is one that
contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may
develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide bad-block
management and error-correction algorithms. This ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the
NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to
program the bad-block mark into every location in the 1st or 2nd page of each invalid block. It may not be possible to program every
location in an invalid block with the bad-block mark. However, the first spare area location in each bad block is guaranteed to contain
the bad-block mark. This method is compliant with ONFI factory defect mapping requirements. See the following table for the bad-block
mark.
System software should initially check the first spare area location for non-FFh data on the 1st and 2nd page of each block prior to
performing any PROGRAM or ERASE operations on the NAND Flash device. A bad-block table can then be created, enabling system
software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks may be
marginal, it may not be possible to recover the bad-block marking if the block is erased.
Error Management Details
Description
Requirement
Minimum number of valid blocks per die (NVB
)
2008
Total available blocks per die
2048
First spare area location in the first page of each block
Value programmed for bad block at the first byte of spare area
Minimum required ECC
Byte 2048
00h
8-bit ECC per sector (544) bytes of data
8-bit ECC per 512 bytes (user data) + 8 bytes
(Spare) + 16 bytes (ECC data)
Minimum ECC with internal ECC enabled
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F50L4G41XB (2X)
Power-Up and Power-Down
At power-up and power-down, the device must not be selected; that is, CS# must follow the voltage applied on VCC until VCC reaches
the correct values: VCC, min at power-up and VSS at power-down. NAND Flash devices are designed to prevent data corruption during
power transitions. VCC is internally monitored. After the device VCC has reached the VCC, min, GET FEATURE command can be issued
to poll the status register (OIP) before the first access. Normal precautions must be taken for supply line decoupling to stabilize the VCC
supply. Each device in a system should have the VCC line decoupled by a suitable capacitor (typically 100nF) close to the package
pins.
Note: For power cycle testing, the system must not initiate the power-up sequence until VCC drops down to 0V.
Power-Up
This device supports default device initialization that does not require RESET (FFh) command. When device VCC has reached the write
inhibit voltage, the device automatically starts the initialization. At default setting, first page data is automatically loaded into cache
register. During the initialization, GET FEATURE command could be issued to poll the status register (OIP) before the first access; Or,
the first access can occur 1.25ms after VCC reaches VCC,min
.
Automatic Device Initialization
Notes: 1. A = 1.25ms.
2. B = 2.7V.
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F50L4G41XB (2X)
Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions above values in this specification is not guaranteed. Exposure to absolute maximum
rating conditions for extended periods can affect reliability.
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Supply voltage
I/O voltage
VCC
VCC
TA
-0.6
-0.6
0
4.6
4.6
70
V
V
Operating temperature (ambient)
Storage temperature
°C
°C
TS
-65
150
Note: 1. During infrequent, nonperiodic transitions and for periods less than 20ns, voltage potential between VSS and VCC may
undershoot to –2.0V or overshoot to VCC_MAX + 2.0V.
Operating Conditions
Parameter
Symbol
Min
Type
Max
Unit
Supply voltage
VCC
TA
2.7
0
3.3
25
3.6
70
V
Ambient operating temperature
°C
AC Measurement Conditions
Parameter
Symbol
Min
Max
Unit
Load Capacitance
CL
-
15
pF
ns
V
Input rise and fall time
Input pulse voltage1
-
5
0.8 VCC
V
-
0.2 VCC
0.3 VCC
Input timing reference voltages
Output timing reference voltages
-
V
-
VCC/2
Note: 1. These are Min/Max specifications for dual/quad operations.
AC Measurement I/O Waveform
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F50L4G41XB (2X)
Capacitance
Test
Condition
Description
Symbol
Min.
Max.
Unit
Input / Output Capacitance (IO0, IO1, IO2, IO3)
Input Capacitance (other pins)
CIN
CIN
VOUT = 0V
VIN = 0V
-
-
9
9
pF
pF
Note:
1. These parameters are verified in device characterization and are not 100% tested.
2. The value includes the silicon and package together.
DC Characteristics
Parameter
Input High Voltage
Symbol
Conditions
Min.
Typ
-
Max
Unit
V
VIH
VIL
-
-
0.7 x VCC
VCC +0.4
0.3 x VCC
-
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Input Leakage Current
Output Leakage Current
Page read current
-0.5
-
V
VOH
VOL
ILI
IOH=-100uA
VCC-0.2
-
V
IOL=1.6mA
-
-
-
-
-
-
-
-
0.4
V
-
-
±20
±10
47
uA
uA
mA
mA
mA
uA
ILO
-
-
ICC3
ICC4
ICC5
ICC1
-
37
32
32
30
Program current
-
37
Erase current
-
37
Standby current
CE# = VCC; V IN = VSS or VCC
100
Note:
1. Typical values are given for TA = 25 °C.
2. These parameters are verified in device characterization and are not 100% tested.
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F50L4G41XB (2X)
AC Characteristics
Parameter
Symbol
fC
Min.
-
Max.
Unit
MHz
ns
Clock frequency1,2
Clock LOW time
Clock HIGH time
133
tWL
4.5
4.5
0.1
0.1
80
5
-
-
tWH
ns
Clock rise time (slew rate)
Clock fall time (slew rate)
Command deselect time
Chip select# active setup/hold time relative to SCK
Chip select# non-active setup/hold time relative to SCK
Output disable time
tCRT
tCFT
-
V/ns
V/ns
ns
-
tCS
-
tCSS/ tCSH
tCSH
tDIS
-
ns
5
-
ns
-
20
-
ns
Data input setup time
tSUDAT
tHDDAT
tV
tHO
tWPH
tWPS
2.5
3
ns
Data input hold time
-
ns
Clock LOW to output valid
Output hold time
-
8
-
ns
1.5
100
20
ns
WP# hold time
-
ns
WP# setup time
-
ns
Notes:
1. READ FROM CACHE Dual IO (BBh) and Quad IO (EBh) can run up to 108 MHz.
2. When read protocol similar to SPI NOR is enabled, READ FROM CACHE 03h command can run up to 20 MHz, while READ
FROM CACHE 0Bh command can run up to 133 MHz.
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ESMT
F50L4G41XB (2X)
PROGRAM/READ/ERASE Characteristics
Parameter
Symbol
tERS
Typ
2
Max
10
Unit
BLOCK ERASE operation time (128KB)
PROGRAM PAGE operation time (ECC disabled)
PROGRAM PAGE operation time (ECC enabled)
Page read time (ECC disabled)
ms
200
220
-
600
600
25
tPROG
us
us
tRD
Page read time (ECC enabled)
TBD
115
Data transfer time from data register to cache register
(internal ECC disabled)
-
5
us
us
tRCBSY
Data transfer time from data register to cache register
(internal ECC enabled)
TBD
100
Power-on reset time (device initialization) from VCC MIN
Write inhibit voltage
tPOR
VWI
-
-
1.25
2.5
ms
V
Reset time for READ, PROGRAM, and ERASE operations
(internal ECC disabled)
-
30/35/525
tRST1
NOP2
us
-
Reset time for READ, PROGRAM, and ERASE operations
(internal ECC enabled)
-
-
120/125/615
4
Number of partial-page programming operations supported
Note:
1. For first RESET condition after power-up, tRST will be 1.25ms maximum.
2. In the main user area and in user meta data area I, single partial-page programming operations must be used. Within a page, the
user can perform a maximum of four partial-page programming operations.
Serial Input Timing
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F50L4G41XB (2X)
Serial Output Timing
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F50L4G41XB (2X)
PACKING DIMENSIONS
8-LEAD
LGA ( 8x6 mm )
D
Pin# 1
INDEX
L
DETAIL A
DETAIL A
DETAIL B
DETAIL B
Symbol
Dimension in mm
Dimension in inch
Norm
Min
0.70
0.35
7.90
5.90
Min
0.75
0.40
8.00
6.00
Min
0.80
0.48
8.10
6.10
Min
Max
A
b
D
E
e
0.028
0.014
0.311
0.232
0.030
0.016
0.315
0.236
0.031
0.019
0.319
0.240
1.27 BSC
0.50
0.050 BSC
0.020
L
0.45
0.55
0.018
0.022
Controlling dimension: millimeter
(Revision date: Apr 09 2019)
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ESMT
F50L4G41XB (2X)
Revision History
Revision
Date
Description
1.0
2019.07.30
Original
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F50L4G41XB (2X)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
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