M13S64164A-4BVAG2Y中文资料_数据手册_规格书

ESMT

DDR SDRAM

Features

M13S64164A (2Y)

Automotive Grade

1M x 16 Bit x 4 Banks

Double Data Rate SDRAM

z

Double-data-rate architecture, two data transfers per clock cycle

z

Bi-directional data strobe (DQS)

z

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Four bank operation

CAS Latency : 2, 2.5, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock (CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

V_DD= 2.5V ± 0.2V, V_DDQ= 2.5V ± 0.2V

z

15.6us refresh interval for V grade; 3.9us refresh interval for VA grade

Auto & Self refresh (self refresh is not supported for VA grade)

2.5V I/O (SSTL_2 compatible)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 1/49

ESMT

M13S64164A (2Y)

Automotive Grade

Ordering Information

Product ID

Max Freq.

Package

Comments

Automotive range (V): -40℃ to +85℃

M13S64164A-4TVG2Y

M13S64164A-5TVG2Y

M13S64164A-6TVG2Y

M13S64164A-4BVG2Y

M13S64164A-5BVG2Y

M13S64164A-6BVG2Y

250MHz (DDR500)

66 pin TSOPII

60 Ball BGA

200MHz (DDR400)

166MHz (DDR333)

250MHz (DDR500)

200MHz (DDR400)

166MHz (DDR333)

Pb-free

Automotive range (VA): -40℃ to +105℃

M13S64164A-4TVAG2Y

M13S64164A-5TVAG2Y

M13S64164A-6TVAG2Y

M13S64164A-4BVAG2Y

M13S64164A-5BVAG2Y

M13S64164A-6BVAG2Y

250MHz (DDR500)

66 pin TSOPII

60 Ball BGA

200MHz (DDR400)

166MHz (DDR333)

250MHz (DDR500)

200MHz (DDR400)

166MHz (DDR333)

Pb-free

Functional Block Diagram

CLK

Clock

Generator

Bank D

Bank C

Bank B

CLK

CKE

Row

Address, BA

Address

Buffer

&

Refresh

Counter

Mode Register &

Extended Mode

Register

Bank A

DM

DQS

Sense Amplifier

Column Decoder

Column

Address

Buffer

&

Refresh

Counter

CS

RAS

CAS

WE

Data Control Circuit

DQ

DLL

CLK, CLK

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 2/49

ESMT

M13S64164A (2Y)

Automotive Grade

PIN CONFIGURATION (TOP VIEW)

(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)

BALL CONFIGURATION (TOP VIEW)

(BGA60, 8mmX13mmX1.2mm Body, 0.8mm Ball Pitch)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

1

VSS

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

2

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

1

2

3

7

8

9

3

VDD

DQ0

VDDQ

VSSQ

DQ15

VSS

A

B

C

D

E

F

4

5

6

VSSQ

DQ14 VDDQ DQ13

DQ12 VSSQ DQ11

DQ2

DQ4

DQ6

DQ1

DQ3

7

8

VDDQ

VSSQ

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

DQ10 VDDQ

DQ9

DQ5

DQ7

LDQS VDDQ

DQ8

VSSQ

VSS

UDQS

VDDQ

LDQS

NC

VSSQ

UDQS

NC

VREF

LDM

WE

VDD

CAS

NC

UDM

CLK

VDD

VREF

VSS

G

H

J

CLK

NC

LDM

WE

UDM

CLK

CKE

NC

CS

BA0

A10/AP

A1

NC

A11

A8

CKE

A9

RAS

BA1

CAS

RAS

CS

NC

BA0

BA1

A10/AP

A0

A11

K

L

A0

A2

A7

A9

A8

A6

A5

A7

A1

A6

A2

A5

M

A4

VDD

A3

VSS

A3

A4

VDD

VSS

Pin Description

Pin Name

Function

Pin Name

Function

Address inputs

- Row address A0~A11

- Column address A0~A7

A10/AP: AUTO Precharge

DM is an input mask signal for write data.

LDM corresponds to the data on DQ0~DQ7;

UDM correspond to the data on DQ8~DQ15.

A0~A11,

BA0, BA1

LDM, UDM

BA0, BA1: Bank selects (4 Banks)

DQ0~DQ15 Data-in/Data-out

Clock input

CLK, CLK

CKE

Row address strobe

Column address strobe

Write enable

Clock enable

RAS

CAS

Chip select

CS

V_DDQ

V_SSQ

V_REF

Supply Voltage for DQ

Ground for DQ

WE

V_SS

Ground

V_DD

Power

Reference Voltage for SSTL_2

Bi-directional Data Strobe.

LDQS, UDQS

NC

No connection

LDQS corresponds to the data on DQ0~DQ7;

UDQS correspond to the data on DQ8~DQ15.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

3/49

ESMT

M13S64164A (2Y)

Automotive Grade

Absolute Maximum Rating

Parameter

Voltage on V_DD& V_DDQsupply relative to V_SS

Voltage on inputs relative to V_SS

Symbol

V_DD, V_DDQ

V_INPUT

Value

Unit

V

-1.0 ~ 3.6

V

Voltage on I/O pins relative to V_SS

V_IO

-0.5 ~ V_DDQ+0.5

-40 ~ +85

V

°C

T_A(V grade)

Operating ambient temperature

°C

T^A(VA grade)

T_STG

-40 ~ +105

-55 ~ +150

Storage temperature

°C

W

Power dissipation

P_D

I_OS

1

Short circuit current

50

mA

Note:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operation Conditions & Specifications

DC Operation Conditions

Recommended operating conditions (Voltage reference to V_SS= 0V)

Parameter

Symbol

Min

Max

Unit

Note

Supply voltage

V_DD

V_DDQ

2.3

2.7

V

I/O Supply voltage

I/O Reference voltage

2.7

V_REF

0.49*V_DDQ

V_REF- 0.04

V_REF+ 0.15

-0.3

0.51*V_DDQ

V_REF+ 0.04

V_DDQ+ 0.3

V_REF- 0.15

1

2

I/O Termination voltage (system)

Input logic high voltage

V_TT

V_IH(DC)

V_IL(DC)

Input logic low voltage

V_IN(DC)

-0.3

V_DDQ+ 0.3

V

Input Voltage Level, CLK and CLK inputs

V_ID(DC)

0.36

0.71

V_DDQ+ 0.6

1.4

V

-

3

4

Input Differential Voltage, CLK and CLK inputs

V–I Matching: Pullup to Pulldown Current Ratio

VI (Ratio)

Input leakage current: Any input 0V ≤ V^IN≤ VDD

μ A

I_L

-2

-5

2

5

(All other pins not tested under = 0V)

Output leakage current (DQs are disable; 0V ≤ VOUT ≤ VDDQ)

I_OZ

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 4/49

ESMT

M13S64164A (2Y)

Automotive Grade

DC Operation Conditions - continued

Parameter

Symbol

Min

Max

Unit

Note

Output High Current (Full strength driver)

(V_OUT=V_DDQ-0.373V, min V_REF, min V_TT)

I_OH

-15

mA

5, 7

Output Low Current (Full strength driver)

(V_OUT= 0.373V, max V_REF, max V_TT)

I_OL

I_OH

I_OL

I_OH

I_OL

+15

-9

mA

5, 7

6

Output High Current (Reduced strength driver – 60%)

(V_OUT= V_DDQ-0.763V, min V_REF, min V_TT)

Output Low Current (Reduced strength driver – 60%)

(V_OUT= 0.763V, max V_REF, max V_TT)

+9

6

Output High Current (Reduced strength driver – 30%)

(V_OUT= V_DDQ-1.056V, min V_REF, min V_TT)

-4.5

+4.5

6

Output Low Current (Reduced strength driver – 30%)

(V_OUT= 1.056V, max V_REF, max V_TT)

6

Notes:

1. V_REFis expected to be equal to 0.5* V_DDQof the transmitting device, and to track variations in the DC level of the same.

Peak-to-peak noise on V_REFmay not exceed 2% of the DC value.

2. V_TTis not applied directly to the device. V_TTis system supply for signal termination resistors, is expected to be set

equal to V_REF, and must track variations in the DC level of V_REF

.

3. V_IDis the magnitude of the difference between the input level on CLK and the input level on CLK .

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltages from 0.25 V to 1.0 V. For a given output, it represents

the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the

maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.

5. V_OH= 1.95V, V_OL=0.35V for others.

6. V_OH= 1.9V, V_OL=0.4V for others.

7. The values of I_OH(DC) is based on V_DDQ= 2.3V and V_TT= 1.19V for others.

The values of I_OL(DC) is based on V_DDQ= 2.3V and V_TT= 1.11V for others.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 5/49

ESMT

M13S64164A (2Y)

Automotive Grade

IDD Parameters and Test Conditions

Test Condition

Symbol

Note

Operating Current (one bank Active - Precharge):

t

_RC= t_RC(min); t_CK= t_CK(min); DQ, DM, and DQS inputs changing once per clock cycle;

IDD0

Address and control inputs changing once every two clock cycles; CS = high between valid commands.

Operating Current (one bank Active - Read - Precharge):

One bank open; BL = 4; t_RC= t_RC(min); t_CK= t_CK(min); I_OUT= 0mA;

IDD1

IDD2P

IDD2F

2

Address and control inputs changing once per deselect cycle; CS = high between valid commands

Precharge Power-down Standby Current:

All banks idle; Power-down mode; t_CK= t_CK(min); CKE ≤ V_IL(max); V_IN= V_REFfor DQ, DQS and DM.

Precharge Floating Standby Current:

CS ≥ V_IH(min); All banks idle; CKE ≥ V_IH(min); t_CK= t_CK(min);

Address and other control inputs changing once per clock cycle; V_IN= V_REFfor DQ, DQS, and DM.

Precharge Quiet Standby Current:

IDD2Q

IDD3P

CS ≥ V_IH(min); All banks idle; CKE ≥ V_IH(min); t_CK= t_CK(min);

Address and other control inputs stable at ≥ V_IH(min) or ≤ V_IL(max); V_IN= V_REFfor DQ, DQS, and DM.

Active Power-down Standby Current:

One bank active; Power-down mode; CKE ≤ V_IL(max); t_CK= t_CK(min); V_IN= V_REFfor DQ, DQS, and DM.

Active Standby Current:

CS ≥ V_IH(min); CKE ≥ V_IH(min); One bank active; t_RC= t_RAS(max); t_CK= t_CK(min);

DQ, DM, and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle.

IDD3N

IDD4R

IDD4W

Operating Current (burst read):

BL = 2; Continuous burst reads; One bank active;

Address and control inputs changing once per clock cycle; t_CK= t_CK(min); I_OUT= 0mA;

50% of data changing on every transfer.

Operating Current (burst write):

BL = 2; Continuous burst writes; One bank active;

Address and control inputs changing once per clock cycle; t_CK= t_CK(min);

DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.

Auto Refresh Current:

IDD5

IDD6

t

_RC= t_RFC(min)

Self Refresh Current:

1

2

CKE ≤ 0.2V; external clock on; t_CK= t_CK(min)

Operating Current (Four bank operation):

IDD7

Four-bank interleaving READs (burst = 4) with auto precharge; t_RC= t_RC(min); t_CK= t_CK(min);

Address and control inputs change only during ACTIVE, READ, or WRITE commands; I_OUT= 0mA.

Notes:

1. Enable on-chip refresh and address counters.

2. Random address is changing; 50% of data is changing at every transfer.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 6/49

ESMT

M13S64164A (2Y)

Automotive Grade

IDD Specifications

Version

-5

Symbol

Unit

-4

75

85

-6

IDD0

65

55

65

mA

IDD1

75

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

8

40

35

30

35

15

70

60

50

130

120

70

120

110

60

110

100

50

IDD6

3

IDD7

150

130

110

Input / Output Capacitance

Delta Cap

(max)

Parameter

Package

Symbol

Min

Max

Unit

Note

Input capacitance (A0~A11, BA0~BA1,

CKE, CS , RAS , CAS , WE )

TSOP

BGA

2

TBD

2

4

TBD

4

pF

C_IN1

0.5

0.25

0.5

1,4

TSOP

BGA

C_IN2

C_OUT

C_IN3

1,4

Input capacitance (CLK, CLK )

Data & DQS input/output capacitance

Input capacitance (DM)

TBD

2

TBD

6

TSOP

BGA

1,2,3,4

TBD

2

TBD

4

TSOP

BGA

0.5

TBD

Notes:

1. These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and

DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameter is sampled. For all devices, V_DDQ= 2.5V ± 0.2V, V_DD= 2.5V ± 0.2V. f=100MHz, T_A=25°C, V_OUT(DC) =

V_DDQ/2, V_OUT(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in

loading (to facilitate trace matching at the board level).

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 7/49

ESMT

M13S64164A (2Y)

Automotive Grade

AC Operation Conditions & Timing Specifications

AC Operation Conditions

Parameter

Symbol

Min

Max

Unit

V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

V_IH(AC)

V_IL(AC)

V_ID(AC)

V_REF+ 0.31

V_REF- 0.31

V_DDQ+0.6

V

0.7

V

1

2

Input Differential Voltage, CLK and CLK inputs

V_IX(AC)

0.5*V_DDQ-0.2 0.5*V_DDQ+0.2

V

Input Crossing Point Voltage, CLK and CLK inputs

Notes:

1. V_IDis the magnitude of the difference between the input level on CLK and the input on CLK .

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of

the same.

AC Overshoot / Undershoot Specification

Value

Parameter

Unit

-4 / -5 / -6

1.5

Address, Control

Data, Strobe, Mask

Address, Control

Data, Strobe, Mask

Address, Control

Data, Strobe, Mask

Address, Control

Data, Strobe, Mask

V

Maximum peak amplitude allowed for overshoot

1.2

1.5

V

Maximum peak amplitude allowed for undershoot

Maximum overshoot area above V_DD

1.2

V

4.5

V-ns

2.4

4.5

Maximum undershoot area below V_SS

2.4

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 8/49

ESMT

M13S64164A (2Y)

Automotive Grade

AC Timing Parameter & Specifications (Note: 1~6, 9~10)

-4

-5

-6

Symbol

Unit

Note

Parameter

min

7.5

6

max

12

min

7.5

6

max

12

min

7.5

6

max

12

CL2

CL2.5

CL3

ns

Clock period

t_CK

12

4

12

5

12

6

12

DQ output access time from

CLK/ CLK

t_AC

-0.7

+0.7

-0.7

+0.7

-0.7

+0.7

ns

CLK high-level width

CLK low-level width

t_CH

t_CL

0.45

0.55

0.45

0.55

0.45

0.55

t_CK

DQS output access time from

CLK/ CLK

t_DQSCK

-0.6

+0.6

1.25

-0.6

+0.6

1.25

-0.6

+0.6

1.25

ns

Clock to first rising edge of DQS delay

DQ and DM input setup time (to DQS)

DQ and DM input hold time (to DQS)

t_DQSS

t_DS

0.72

0.4

0.72

0.4

0.75

0.45

t_CK

ns

t_DH

0.4

DQ and DM input pulse width

(for each input)

t_DIPW

t_IS

1.75

0.6

0.7

2.2

1.75

0.6

0.7

2.2

1.75

0.75

0.8

ns

18

Address and Control input setup time

(fast)

15,17~19

16~19

18

Address and Control input hold time

(fast)

t_IH

Address and Control input setup time

(slow)

t_IS

Address and Control input hold time

(slow)

t_IH

0.8

Control and Address input pulse width

(for each input)

t_IPW

2.2

DQS input high pulse width

t_DQSH

t_DQSL

t_DSS

0.35

0.2

0.35

0.2

0.35

0.2

t_CK

ns

DQS input low pulse width

DQS falling edge to CLK setup time

DQS falling edge hold time from CLK

Data strobe edge to output data edge

t_DSH

0.2

t_DQSQ

0.4

22

11

Data-out high-impedance time from

CLK/ CLK

t_HZ

t_LZ

t_HP

+0.7

ns

Data-out low-impedance time from

CLK/ CLK

-0.7

+0.7

0.5

-0.7

+0.7

0.5

-0.7

+0.7

0.5

11

t_CLmin

or

t_CHmin

t_CLmin

or

t_CHmin

t_CLmin

or

t_CHmin

Clock half period

20,21

21

DQ/DQS output hold time from DQS

Data hold skew factor

t_QH

t

_HP- t_QHS

t

_HP- t_QHS

t

_HP- t_QHS

ns

t_QHS

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 9/49

ESMT

M13S64164A (2Y)

Automotive Grade

AC Timing Parameter & Specifications – continued

-4

-5

-6

Parameter

Symbol

Unit

Note

min

max

min

max

min

max

Active to Precharge command

t_RAS

t_RC

40

70K

40

70K

42

70K

ns

Active to Active /Auto Refresh

command period

55

70

55

70

60

72

Auto Refresh to Active / Auto Refresh

command period

t_RFC

ns

Active to Read, Write delay

Precharge command period

t_RCD

t_RP

15

18

ns

Active to Read with Auto Precharge

command

t_RAP

t_RRD

15

10

15

10

18

12

ns

Active bank A to Active bank B

command

Write recovery time

t_WR

t_WTR

t_CCD

15

2

15

2

15

2

ns

t_CK

Write data in to Read command delay

Col. Address to Col. Address delay

1

Average periodic refresh interval for

T_A≤ 85℃

t_REFI

15.6

3.9

15.6

3.9

15.6

3.9

us

14

Average periodic refresh interval for T_A

＞85℃ (VA grade only)

t_REFI

Write preamble

Write postamble

Read preamble

Read postamble

t_WPRE

t_WPST

t_RPRE

t_RPST

0.25

0.4

0.9

0.4

0.25

0.4

0.9

0.4

0.25

0.4

0.9

0.4

t_CK

0.6

1.1

0.6

1.1

0.6

1.1

0.6

12

13

Clock to DQS write preamble setup

time

t_WPRES

0

ns

Mode Register Set command cycle

time

t_MRD

t_XSRD

t_XSNR

2

t_CK

ns

Exit self refresh to Read command

200

75

200

75

200

75

Exit self refresh to non-Read

command

(t_WR/t_CK

)

(t_WR/t_CK

)

(t_WR/t_CK

)

Auto Precharge write recovery +

precharge time

t_DAL

+

t_CK

23

(t_RP/t_CK

)

(t_RP/t_CK

)

(t_RP/t_CK)

Notes:

1. All voltages referenced to V_SS

.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is

not intended to be either a precise representation of the typical system environment nor a depiction of the actual load

presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing

reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a

coaxial transmission line terminated at the tester electronics).

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 10/49

ESMT

M13S64164A (2Y)

Automotive Grade

4. AC timing and IDD tests may use a V_ILto V_IHswing of up to 1.5 V in the test environment, but input timing is still

referenced to V_REF(or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the

specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the

range between V_IL(AC) and V_IH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively

switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not

ring back above (below) the DC input LOW (HIGH) level.

6. Inputs are not recognized as valid until V_REFstabilizes. Exception: during the period before V_REFstabilizes, CKE ≤

0.2V_DDQis recognized as LOW.

7. Enables on-chip refresh and address counters.

8. IDD specifications are tested after the device is properly initialized.

9. The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;

the input reference level for signals other than CLK/ CLK , is V_REF

.

10. The output timing reference voltage level is V_TT.

11. t_HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not

referenced to a specific voltage level but specify when the device output is no longer driving (t_HZ), or begins driving

(t_LZ).

12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this

CLK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.

When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a

previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending

on t_DQSS

.

14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

15. For command/address input slew rate ≥ 1.0 V/ns

16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

17. For CLK & CLK slew rate ≥ 1.0 V/ns

18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be

guaranteed by device design or tester correlation.

19. Slew Rate is measured between V_OH(AC) and V_OL(AC).

20. Min (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device

(i.e. this value can be greater than the minimum specification limits for t_CLand t_CH).....For example, t_CLand t_CHare =

50% of the period, less the half period jitter (t_JIT(HP)) of the clock source, and less the half period jitter due to

crosstalk (t_JIT(crosstalk)) into the clock traces.

21. t_QH= t_HP- t_QHS, where:

t

_HP= minimum half clock period for any given cycle and is defined by clock high or clock low (t_CH, t_CL). t_QHSaccounts

for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition

followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew

and output pattern effects, and p-channel to n-channel variation of the output drivers.

22. t_DQSQConsists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers

for any given cycle.

23. For each of the terms above, if not already an integer, round to the next highest integer.

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

Command Truth Table

BA0,

BA1

A11,

A9~A0

COMMAND

CKEn-1 CKEn

DM

A10/AP

Note

CS RAS CAS

WE

Register

Extended MRS

Mode Register Set

Auto Refresh

H

X

H

L

X

OP CODE

1,2

3

H

L

H

X

Entry

L

H

X

3

Refresh

Self Refresh

L

H

L

H

X

L

H

X

H

X

H

Exit

L

X

Bank Active & Row Addr.

H

V

Row Address

Read &

Column

Address

Column

Address

(A0 ~ A7)

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

H

X

L

H

L

H

L

X

V

Write &

Column

Address

Column

Address

(A0 ~ A7)

4,8

V

H

4,6,8

7

Burst Terminate

Bank Selection

All Banks

H

X

L

H

L

H

L

X

V

X

L

Precharge

X

H

5

H

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

Entry

H

L

H

L

X

Active Power Down Mode

X

Exit

X

H

L

Entry

H

Precharge Power Down

Mode

X

H

L

Exit

L

H

X

Deselect (NOP)

H

L

H

No Operation (NOP)

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Notes:

1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by “Auto”.

Auto/self refresh can be issued only at all banks precharge state.

4. BA0~BA1: Bank select addresses.

If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.

If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.

If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.

5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t_RPafter end of burst.

7. Burst Terminate command is valid at every burst length.

8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding

and coincident DM is “High”. (Write DM latency is 0).

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

Basic Functionality

Power-Up and Initialization Sequence

DDR SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified

may result in undefined operation. No power sequencing is specified during power up and power down given the following

criteria:

V_DDand V_DDQare driven from a single power converter output, AND

V_TTis limited to 1.35 V, AND

V_REFtracks V_DDQ/2

OR, the following relationships must be followed:

V_DDQis driven after or with V_DDsuch that V_DDQ< V_DD+ 0.3 V, AND

V_TTis driven after or with V_DDQsuch that V_TT< V_DDQ+ 0.3 V, AND

V_REFis driven after or with V_DDQsuch that V_REF< V_DDQ+ 0.3 V.

At least one of these two conditions must be met.

Except for CKE, inputs are not recognized as valid until after V_REFis applied. CKE is an SSTL_2 input, but will detect an

LVCMOS LOW level after V_DDis applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee

that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read

access).

After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 μs delay prior

to applying an executable command. Once the 200 μs delay has been satisfied, a DESELECT or NOP command should be

applied, and CKE should be brought HIGH.

Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command

should be issued for the Extended Mode Register, to enable the DLL, and then a MODE REGISTER SET command should be

issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required

between the DLL reset and any executable command. A PRECHARGE ALL command should be applied, placing the device in

the ”all banks idle” state.

Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the

Mode Register, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be

performed.

Following these cycles, the DDR SDRAM is ready for normal operation.

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M13S64164A (2Y)

Automotive Grade

Mode Register Definition

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the register is not defined, therefore the mode register must be written after

EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE

and BA0~BA1 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register).

The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the

mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle

state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing

mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL

reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing

modes and CAS latencies.

BA1 BA0 A11 A10

A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

Address Bus

0

RFU

DLL

TM

Mode Register

Burst Length

CAS Latency

A8

DLL Reset

No

A7

Mode

Normal

Test

A3

Burst Type

Sequential

Interleave

0

1

0

1

0

1

Yes

Burst Length

A2 A1 A0

Length

CAS Latency

A6 A5 A4

Latency

Reserve

2

Sequential Interleave

BA1 BA0

Operating Mode

MRS Cycle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserve

2

Reserve

2

0

1

EMRS Cycle

4

3

8

Reserve

2.5

Reserve

Note: RFU (Reserved for future use) must stay “0” during MRS cycle.

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M13S64164A (2Y)

Automotive Grade

Extended Mode Register Set (EMRS)

The extended mode register stores the data enabling or disabling DLL, and selecting output drive strength. The default value of

the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or

disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR

SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of

address pins A0~A11 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended

mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle

state. A0 is used for DLL enable or disable. A1 and A6 are used for selecting output drive strength. “High” on BA0 is used for

EMRS. All the other address pins except A0~A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table

for specific codes.

Address Bus

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Extended Mode Register

0

1

RFU

DS

RFU

DS DLL

A6

A1

0

Drive Strength

A0

DLL Enable

Enable

0

1

100 % Strength

60 % Strength

RFU

0

1

Disable

0

1

30 % Strength

BA1 BA0 Operating Mode

0

1

MRS Cycle

EMRS Cycle

Note: RFU (Reserved for future use) must stay “0” during EMRS cycle.

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M13S64164A (2Y)

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Burst Address Ordering for Burst Length

Burst

Starting

Sequential Mode

Interleave Mode

Length

Address (A2, A1, A0)

xx0

0, 1

2

4

xx1

x00

x01

x10

x11

000

001

010

011

100

101

110

111

1, 0

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

DLL Enable / Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning

to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode,

the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command

can be issued.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive

strength options, intended for lighter load and/or point-to-point environments.

Mode Register

0

1

2

3

4

5

6

7

C L K

* 1

A n y

C o m m a n d

P r e c h a r g e

A l l B a n k s

M R S

/

E M R S

C O M M A N D

* 2

R P

t

C K

t

M R D

*1: MRS/EMRS can be issued only at all banks precharge state.

*2: Minimum t_RPis required to issue MRS/EMRS command.

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M13S64164A (2Y)

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Precharge

The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,

RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge

each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is

precharged when the command is initiated. For write cycle, t_WR(min) must be satisfied until the precharge command can be

issued. After t_RPfrom the precharge, an active command to the same bank can be initiated.

Burst Selection for Precharge by bank address bits

A10/AP

BA1

BA0

Precharge

Bank A Only

Bank B Only

Bank C Only

Bank D Only

All Banks

0

1

0

1

0

1

X

No Operation & Device Deselect

The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.

The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect

and NOP the device should finish the current operation when this command is issued.

Bank / Row Active

The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the

clock (CLK). The DDR SDRAM has four independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank

Activation command must be applied before any Read or Write operation is executed. The Bank Activation command to the first

Read or Write command must meet or exceed the minimum of RAS to CAS delay time (t_RCDmin). Once a bank has been

activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time

interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t_RRD

min).

Bank Activation Command Cycle ( CAS Latency = 3)

Tn

Tn+1

Tn+2

0

1

2

3

C L K

B a n k

A

B a n k

A

B ank

A

B a n k

B

A d d r e s s

R o w A d d r .

C o l . A d d r .

Row. Ad dr.

R o w A d d r .

R A S - C A S d e l a y

(

t R C D

)

R A S - R A S d e l a y

(

t R R D

)

W r i t e

A

B a n k

A

B a n k

B

B a n k

A

N O P

C o m m a n d

N O P

w i t h A P

A c t i v a t e

R O W C y c l e T i m e

( t R C )

: D o n ' t C a r e

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M13S64164A (2Y)

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Read

This command is used after the row activate command to initiate the burst read of data. The read command is initiated by

activating CS ,RAS , CAS , and deasserting WE at the same clock rising edge as described in the command truth table. The

length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.

Write

This command is used after the row activate command to initiate the burst write of data. The write command is initiated by

activating CS ,RAS , CAS , and WE at the same clock rising edge as describe in the command truth table. The length of the

burst will be determined by the values programmed during the MRS command.

Burst Read Operation

Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is

issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t_RCD

from the bank activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst

(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ

command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR

SDRAM until the burst length is completed.

0

1

2

3

4

5

6

7

8

C L K

CL K

RE A D

A

N OP

NO P

N OP

NO P

C OM MA ND

NO P

N O P

NO P

t RPS T

tR P RE

D QS

DQ ' s

C A S L a t e n cy = 3

DO U T 3

DO U T 0 DO U T 1 DO U T 2

Burst Write Operation

The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the

clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for

burst write cycle. The first data of a burst write cycle must be applied on the DQ pins t_DSprior to data strobe edge enabled after

t_DQSSfrom the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on

each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished,

any additional data supplied to the DQ pins will be ignored.

0

1

*1

2

3

4

5

6

7

8

C L K

NOP

NO P

C O M M A ND

W RITE A

NO P

W RITE

B

NOP

N O P

NO P

tDQ S S m ax

DQS

*1

* 1

tW PRE S

DIN 0 D^{I N1}

DI N2

DI N3 DIN 0

DIN1

DI N 2 DI N3

D Q' s

Note * 1: The specific requirement is that DQS be valid (High or Low) on or before this CLK edge. The case shown (DQS going from

High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS

could be High at this time, depending on t_DQSS

.

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M13S64164A (2Y)

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Read Interrupted by a Read

A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is

interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read

command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this

point the data from the interrupting Read command appears. Read to Read interval is t_CCD(min).

0

1

2

3

4

5

6

7

8

C L K

t C CD ( mi n )

RE A D B

NO P

NOP

NO P

CO MMA ND

RE A D A

NO P

N OP

Hi -Z

DQ S

DOUT B0 DOUT B 1 DOUT B2 DOUT B3

DOUT A0 DOUT A1

DQ ' s

Hi- Z

Read Interrupted by a Write & Burst Terminate

To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O

bus by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the

beginning the write operation, Burt stop command must be applied at least RU(CL) clocks [RU mean round up to the nearest

integer] before the Write command.

0

1

2

3

4

5

6

7

8

C L K

Burs t

Term i nate

N O P

R E A D

N O P

W R I T E

N O P

C O M M A N D

N O P

D Q S

D

OUT 0

OUT 1

DIN 2

D

IN

0

D

IN

1

DIN 3

D Q ' s

The following functionality establishes how a Write command may interrupt a Read burst.

1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate

the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a

Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].

2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.

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M13S64164A (2Y)

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Read Interrupted by a Precharge

A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to

precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.

0

1

2

3

4

5

6

7

8

C L K

1 t C K

N O P

R E A D

Precharge

N O P

C O M M A N D

D Q S

D

OUT 0

OUT 1

DOUT 4 DOUT 5 DOUT 6 DOUT 7

OUT 3

D

DOUT 2

D Q ' s

I n t e r r u p t e d b y p r e c h a r g e

When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before

the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read

burst and when a new Bank Activate command may be issued to the same bank.

1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on

the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new

Bank Activate command may be issued to the same bank after t_RP(RAS precharge time).

2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock

edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once

the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the

same bank after t_RP

.

3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after t_RP

where t_RPbegins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS

Latency. During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest

possible external Precharge command would initiate a precharge operation without interrupting the Read burst as

described in 1 above.

4. For all cases above, t_RPis an analog delay that needs to be converted into clock cycles. The number of clock cycles

between a Precharge command and a new Bank Activate command to the same bank equals t_RP/ t_CK(where t_CKis the

clock cycle time) with the result rounded up to the nearest integer number of clock cycles.

In all cases, a Precharge operation cannot be initiated unless t_RAS(min) [minimum Bank Activate to Precharge time] has been

satisfied. This includes Read with auto precharge commands where t_RAS(min) must still be satisfied such that a Read with

auto precharge command has the same timing as a Read command followed by the earliest possible Precharge command

which does not interrupt the burst.

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M13S64164A (2Y)

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Write Interrupted by a Write

A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the

interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining

addresses are overridden by the new address and data will be written into the device until the programmed burst length is

satisfied.

0

1

2

3

4

5

6

7

8

C L K

1

t C K

W RITE A

W RITE B

NO P

N O P

CO MMA ND

N OP

Hi - Z

Hi- Z

DQ S

DIN A0

DIN A1

DIN B0

DIN B1

DIN B2

DIN B3

DQ ' s

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M13S64164A (2Y)

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Write Interrupted by a Read & DM

A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one

clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is

registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command

(t_WTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command

is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of

that of write command.

0

1

WRITE

*5

2

3

4

5

6

7

8

C L K

N O P

R E A D

N O P

C O M M A N D

t

W T R

t

D Q S S ( m a x )

H i - Z

H i- Z

D Q S

t

W P R E S

D

I N 0

D

I N 1

D

I N 2

DOUT0 DOUT1

D

I N 3

D

I N 4

D

I N 5

D

I N 6

D I N 7

D Q ' s

D M

t

W T R

t

D Q S S ( m i n )

H i - Z

D Q S

D Q ' s

D M

*5

W P R E S

t

D

OUT0 DOUT1

D

I N 0

D

I N 1

D I N 2

D

I N 3

D

I N 4

D

I N 5

D

I N 6

D I N 7

The following functionality established how a Read command may interrupt a Write burst and which input data is not written into

the memory.

1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where

the Write to Read delay is 1 clock cycle is disallowed.

2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately

precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.

3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory

controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.

4. If input Write data is masked by the Read command, the DQS inputs are ignored by the DDR SDRAM.

5. Refer to “Burst write operation”

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ESMT

M13S64164A (2Y)

Automotive Grade

Write Interrupted by a Precharge & DM

A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column

access is allowed. A write recovery time (t_WR) is required from the last data to precharge command. When precharge command

is asserted, any residual data from the burst write cycle must be masked by DM.

0

1

2

3

4

5

6

7

8

C L K

N O P

WRITE A

t

N O P

WRITE B

N O P

Precharge A

C O M M A N D

t

W R

D Q S S ( m a x

)

H i - Z

D Q S

* 5

W P R E S

t

D

INA0

D

INA5

DINB0

D

INA1

D

INA2

D

INA3

D

INA6

D

INA7

D Q ' s

D M

D

INA4

t

W R

t

D Q S S ( m i n )

H i - Z

D Q S

D Q ' s

D M

t

W P R E S * 5

D

INA0

D

INA5

DINB1

D

INA1

D

INA2

D

INA3

D

INA6

D

INA7

DINB0

D

INA4

Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a

DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, t_WR, is used

to indicate the required of time between the last valid write operation and a Precharge command to the same bank.

t_WRstarts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge

that strobes in the precharge command.

1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write

recovery is defined by t_WR

.

2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the

time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the

DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by t_WR

.

3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after t_WR+ t_RPwhere

t_WR+ t_RPstarts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the

Bank Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the

earliest possible external Precharge command without interrupting the Write burst as described in 1 above.

4. In all cases, a Precharge operation cannot be initiated unless t_RAS(min) [minimum Bank Activate to Precharge time] has been

satisfied. This includes Write with auto precharge commands where t_RAS(min) must still be satisfied such that a Write with auto

precharge command has the same timing as a Write command followed by the earliest possible Precharge command which does

not interrupt the burst.

5. Refer to “Burst write operation”

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ESMT

M13S64164A (2Y)

Automotive Grade

Burst Terminate

The burst terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the

clock (CLK). The burst terminate command has the fewest restrictions making it the easiest method to use when terminating a

burst read operation before it has been completed. When the burst terminate command is issued during a burst read cycle, the

pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the

mode register. The burst terminate command, however, is not supported during a write burst operation.

0

1

2

3

4

5

6

7

8

C L K

Burst

Terminate

N O P

R E A D

A

N O P

C O MM A N D

N O P

The burst read ends after a deley equal to the CAS lantency.

D Q S

H i - Z

D

OUT 0

OUT 1

D Q ' s

D

The Burst Terminate command is a mandatory feature for DDR SDRAMs. The following functionality is required.

1. The BST command may only be issued on the rising edge of the input clock, CLK.

2. BST is only a valid command during Read burst.

3. BST during a Write burst is undefined and shall not be used.

4. BST applies to all burst lengths.

5. BST is an undefined command during Read with auto precharge and shall not be used.

6. When terminating a burst Read command, the BST command must be issued L_BST(“BST Latency”) clock cycles before the

clock edge at which the output buffers are tristated, where L_BSTequals the CAS latency for read operations.

7. When the burst terminates, the DQ and DQS pins are tristated.

The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).

DM masking

The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the

data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to

data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.

0

1

2

3

4

5

6

7

8

C L K

C O MM A N D

N O P

W R I T E

t

N O P

D Q S S

D Q S

D Q ' s

D M

H i - Z

D

IN

2

D

IN

5

DIN 6

D

IN

1

D

IN

3

D

I N

4

DIN 7

D

IN 0

t

DS

t

DH

m a s k e d b y D M = H

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ESMT

M13S64164A (2Y)

Automotive Grade

Read With Auto Precharge

If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock

later from a read with auto precharge command when t_RAS(min) is satisfied. If not, the start point of precharge operation will be

delayed until t_RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new

command can not be asserted until the precharge time (t_RP) has been satisfied.

0

1

2

3

4

5

6

7

8

9

C L K

Read A

C O M M A N D

Bank A

ACTIVE

N O P

Auto Precharge

t

R A S ( m i n )

D Q S

H i - Z

CAS Latency = 2

D

DOUT 0

OUT 1

D

OUT 2

D

OUT 3

D Q ' s

D Q S

* Bank can be reactivated at

completion of precharge

t

R P

H i - Z

CAS Latency = 2.5

D

OUT 0

OUT 1

D

OUT 2 DOUT 3

D

D Q ' s

Auto-Precharge starts

When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.

For the same bank

For the different bank

Asserted

Command

4

5

6

4

5

6

READ

Illegal

Legal

Illegal

Legal

READ with AP^*1READ with AP

Active

Illegal

Legal

Precharge

Note 1: AP = Auto Precharge

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

Write with Auto Precharge

If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the

same bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of

the CLK with the t_WRdelay after the last data-in.

0

1

2

3

4

5

6

7

8

C L K

B a n k

A

Write A

Auto Precharge

N O P

C O M M A N D

A C T I V E

D Q S

*Bank can be reactivated

at completion of tRP

D

IN 2

DIN 3

D Q ' s

D

IN 1

D

IN 0

t

W R

t

R P

I n t e r n a l p r e c h a r g e s t a r t

At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.

For the same bank

Asserted

For the different bank

Command

4

5

6

7

8

4

5

6

7

8

WRITE

Illegal

Legal

WRITE

with AP

WRITE

with AP

WRITE with AP^*1

Illegal

READ

Illegal

Legal

Illegal

Legal

Illegal

Legal

READ +

DM^*2

READ+

DM

READ

Illegal

READ

with AP+ with AP+

READ

with AP

READ with AP

Illegal

Legal

DM

Active

Illegal

Legal

Precharge

Illegal

Note: 1. AP = Auto Precharge

2. DM: Refer to “Write Interrupted by a Read & DM“

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ESMT

M13S64164A (2Y)

Automotive Grade

Auto Refresh & Self Refresh

Auto Refresh

An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of

the clock (CLK). All banks must be precharged and idle for t_RP(min) before the auto refresh command is applied. No control of

the external address pins is requires once this cycle has started because of the internal address counter. When the refresh

cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate

command or subsequent auto refresh command must be greater than or equal to the t_RFC(min).

A maximum of eight consecutive AUTO REFRESH commands (with t_RFC(min)) can be posted to any given DDR SDRAM

meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH

command is 8 x t_REFI

.

C L K

Auto

Refresh

C O MM A N D

P R E

C M D

C K E

= H i g h

t

R F C

t

R P

Self Refresh

A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the

clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During

the self refresh operation, all inputs except CKE are ignored. Since CKE is an SSTL_2 input, V_REFmust be maintained during

self refresh. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited

by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high

for longer than t_XSRDfor locking of DLL. Self refresh mode is not supported for VA grade with T_A＞85 ℃.

C L K

Self

Refresh

Auto

Refresh

NOP

NO P

N OP

C O MM A N D

NO P

N OP

NO P

t

X S N R ( m i n )

C K E

t

I S

t

I S

Note: After self refresh exit, input an auto refresh command immediately.

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ESMT

M13S64164A (2Y)

Automotive Grade

Power down

Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are

idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode

is referred to as active power-down.

Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low

must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is at least 1 t_CK+ t_IS.

However, power down duration is limited by the refresh requirements of the device.

The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A

valid command may be applied 1 t_CK+ t_ISafter exit from power down.

C L K

tRP

C K E

tIS

t

IS

C O M M A N D

Precharge

Active

Read

Enter Precharge

power-down

mode

Exit Precharge

power-down

mode

Enter Active

power-down

mode

Exit Active

power-down

mode

Functional Truth Table

Truth Table – CKE ^{[Note 1~4, 6]}

COMMAND n

CKE n-1

CKE n

Current State

Power Down

Self Refresh

ACTION n

NOTE

L

X

Maintain Power Down

Maintain Self Refresh

Exit Power Down

L

X

7

L

H

L

Power Down

Self Refresh

All Banks Idle

Bank(s) Active

All Banks Idle

NOP or DESELECT

AUTO REFRESH

L

Exit Self Refresh

5, 7

H

Precharge Power Down Entry

Active Power Down Entry

Self Refresh Entry

H

L

H

See the Truth Tables as follow

Notes:

1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of DDR SDRAM immediately prior to clock edge n.

3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT and NOP DESELECT or NOP commands should be issued on any clock edges occurring during the t_XSNRor

_XSRDperiod. A minimum of 200 clock cycles is needed before applying any executable command, for the DLL to lock.

t

6. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the

DRAM must be powered down and then restarted through the specified initialization sequence before normal operation

can continue.

7. V_REFmust be maintained during Self Refresh operation.

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ESMT

M13S64164A (2Y)

Automotive Grade

Truth Table – Current State Bank n

Current State

COMMAND / ACTION

NOTE

CS

RAS

CAS

WE

Command to Bank n ^{[Note 1~6,13]}

H

L

X

H

L

X

H

L

X

H

L

DESELECT (NOP / continue previous operation)

No Operation (NOP / continue previous operation)

ACTIVE (select and activate row)

Any

Idle

L

AUTO REFRESH

7

L

MODE REGISTER SET

H

L

H

L

READ (select column & start read burst)

WRITE (select column & start write burst)

PRECHARGE (deactivate row in bank or banks)

READ (select column & start new read burst)

WRITE (select column & start write burst)

PRECHARGE (truncate read burst, start precharge)

BURST TERMINATE

10

Row Active

L

10

H

L

8

H

L

H

L

10

Read

(Auto Precharge

L

10, 12

8

H

L

Disabled)

H

L

9

H

L

READ (select column & start read burst)

WRITE (select column & start new write burst)

PRECHARGE (truncate write burst, start precharge)

10, 11

10

Write

(Auto Precharge

L

Disabled)

H

L

8, 11

Command to Bank m ^{[Note 1~3, 6,13~15]}

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

DESELECT (NOP / continue previous operation)

No Operation (NOP / continue previous operation)

Any command allowed to bank m

ACTIVE (select and activate row)

READ (select column & start read burst)

WRITE (select column & start write burst)

PRECHARGE

Any

Idle

Row Activating,

Active, or

H

L

10

L

Precharging

H

L

H

L

ACTIVE (select and activate row)

READ (select column & start new read burst)

WRITE (select column & start write burst)

PRECHARGE

Read

(Auto Precharge

H

L

10

L

10, 12

disabled)

H

L

H

L

ACTIVE (select and activate row)

READ (select column & start read burst)

WRITE (select column & start new write burst)

PRECHARGE

Write

(Auto Precharge

H

L

10, 11

10

L

disabled)

H

L

H

L

ACTIVE (select and activate row)

READ (select column & start new read burst)

WRITE (select column & start write burst)

PRECHARGE

Read with

H

L

3a, 10

Auto Precharge

L

3a, 10, 12

H

L

H

L

ACTIVE (select and activate row)

READ (select column & start read burst)

WRITE (select column & start new write burst)

PRECHARGE

Write with

Auto Precharge

H

L

3a, 10

L

H

L

Notes:

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after t_XSNRor t_XSRDhas been met (if the previous

state was self refresh).

2. This table is bank - specific, except where noted, i.e., the current state is for a specific bank and the commands shown

are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t_RPhas been met.

Row Active: A row in the bank has been activated, and t_RCDhas been met. No data bursts/accesses and no

register accesses are in progress.

Read / Write: A READ / WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet

terminated or been terminated.

Read / Write with Auto Precharge Enabled: See following text, notes 3a, 3b:

3a. For devices which do not support the optional “concurrent auto precharge” feature, the Read with Auto

Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the

access period and the precharge period. For Read with Auto Precharge, the precharge period is defined

as if the same burst was executed with Auto Precharge disabled and then followed with the earliest

possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto

Precharge, the precharge period begins when t_WRends, with t_WRmeasured as if Auto Precharge was

disabled. The access period starts with registration of the command and ends where the precharge

period (or t_RP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write

with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other

bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other

bank may be applied. In either case, all other related limitations apply (e.g., contention between READ

data and WRITE data must be avoided).

3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge

enabled, or a write with auto precharge enabled, may be followed by any command to the other banks,

as long as that command does not interrupt the read or write data transfer, and all other related

limitations apply (e.g., contention between READ data and WRITE data must be avoided.)

4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands,

or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable

commands to the other bank are determined by its current state and Truth Table.

Precharging: Starts with registration of a PRECHARGE command and ends when t_RPis met. Once t_RPis met, the

bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when t_RCDis met. Once t_RCDis met, the

bank will be in the ”row active” state.

Read/ Write with Auto -

Precharge Enabled: Starts with registration of a READ / WRITE command with AUTO PRECHARGE enabled

and ends when t_RPhas been met. Once t_RPis met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when t_RCis met.

Once t_RFCis met, the DDR SDRAM will be in the ”all banks idle” state.

Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when t_MRD

has been met. Once t_MRDis met, the DDR SDRAM will be in the ”all banks idle” state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t_RPis met.

Once t_RPis met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank - specific; requires that all banks are idle and no bursts are in progress.

8. May or may not be bank - specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

9. Not bank - specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with AUTO PRECHARGE enabled and

Reads or Writes with AUTO PRECHARGE disabled.

11. Requires appropriate DM masking.

12. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst Terminate must be

used to end the READ prior to asserting a WRITE command,

13. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the

DRAM must be powered down and then restarted through the specified initialization sequence before normal operation

can continue.

14. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.

15. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

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ESMT

M13S64164A (2Y)

Automotive Grade

Timing Diagram

Basic Timing (Setup, Hold and Access Time @ BL=4, CL=2)

0

1

2

3

4

5

6

7

8

9

10

C L K

t

C H

t

C H

t

C L

t

C L

t

C K

t

C K

H IG H

C K E

t

I S

C S

t

I H

R A S

C A S

BAa

Ra

B A 0 , B A 1

BAb

A

1 0 /AP

A D D R

( A 0 ~ A n )

C b

Ra

Ca

W E

D Q S

D Q

t

R P S T

t

D Q S S

t

D Q S C K

t

D Q S C K

t

W P S T

t

D Q S L

H i - Z

t

R P R E

H i - Z

t

D Q S H

t

D Q S Q

t

^WPREtDS

t

DH

DS

t

WPRES

t

A C

t

DH

t

H Z

t

L Z

D b 3

Q a 0

Q a 1

Q a 2

Q a 3

D b 0

D b 2

D b 1

t

Q H

D M

READ

ACTIVE

C O MM A N D

WRITE

:

D o n ’t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

Multi Bank Interleaving READ (@ BL=4, CL=2)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

C S

R A S

C A S

B A 0 , B A 1

BAb

R b

BAa

R a

BAb

BAa

A

1 0 /AP

C a

C b

A D D R

( A 0 ~ A n )

W E

D Q S

Q b 1 Q b 2 Q b 3

D Q

D M

Q a3 Qb 0

Q a 1 Q a2

Qa 0

t

CCD

t

RCD

ACTIVE

C O MM A N D

ACTIVE

READ

tRRD

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

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ESMT

M13S64164A (2Y)

Automotive Grade

Multi Bank Interleaving WRITE (@ BL=4)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

C S

R A S

C A S

BAb

Rb

B A 0 , B A 1

BAa

Ra

BAb

BAa

A

1 0 /AP

A D D R

( A 0 ~ A n )

R a

R b

C a

C b

W E

D Q S

D Q

D b3

D b2

D b 0

D a1 Da 2

Db 1

D a 0

D a 3

D M

t

R C D

t

C C D

ACTIVE

C O MM A N D

ACTIVE

WRITE

t

R R D

t

R C D

:

D on ’ t c a r e

1 0 1 2 2 B 1 6 R . B

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ESMT

M13S64164A (2Y)

Automotive Grade

Read with Auto Precharge (@ BL=8)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

C S

R A S

C A S

BAa

B A 0 , B A 1

BAa

A

1 0 /A P

A D DR

( A 0 ~ A n )

C a

R a

W E

A u t o p r e c h a r g e s t a r t

R P

t

N o t e 1

D Q S ( C L = 2 )

D Q ( C L = 2 )

Q a 4 Q a 5

Q a 7

Qa 6

Q a 2

Q a 1

Q a 3

Q a 0

D Q S ( C L = 2 . 5 )

D Q ( C L = 2 . 5 )

Q a 4 Qa 5

Q a 7

Qa 6

Q a 1 Q a 2 Q a 3

Q a 0

D M

C O M M A N D

ACTIVE

READ

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Note: 1. The row active command of the precharge bank can be issued after t_RPfrom this point.

The new read/write command of another activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

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ESMT

M13S64164A (2Y)

Automotive Grade

Write with Auto Precharge (@ BL=8)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

C S

R A S

C A S

B A 0 , B A 1

BAa

A

1 0 /AP

R a

C a

A D D R

( A 0 ~ A n )

W E

t

D A L

A u t o p r e c h a r g e s t a r t

t

W R

t

R P

No t e1

D Q S

D Q

D a 5

D a 1 D a2

Da 4

D a 7

Da 0

D a 3

D a 6

D M

C O MM A N D

ACTIVE

WRITE

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Note: 1. The row active command of the precharge bank can be issued after t_RPfrom this point.

The new read/write command of another activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 35/49

ESMT

M13S64164A (2Y)

Automotive Grade

Write followed by Precharge (@ BL=4)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I GH

C K E

C S

R A S

C A S

B A 0 , B A 1

BAa

A

1 0 /AP

A D D R

( A 0 ~ A n )

C a

W E

t

W R

D Q S

D a 1

D a 3

D a 0

D a 2

D Q

D M

PRE

CHARGE

C O M M A N D

WRITE

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 36/49

ESMT

M13S64164A (2Y)

Automotive Grade

Write Interrupted by Precharge & DM (@ BL=8)

0

1

2

3

4

0

1

2

3

4

5

C L K

H I GH

C K E

C S

R A S

C A S

B A 0 , B A 1

BAc

BAa

BAb

A

1 0 /AP

A D D R

( A 0 ~ A n )

Cc

C a

Cb

W E

D Q S

D a 2

D a 3

D a 1

D a 4 D a 5

D a 7

D c 0 D c 1 D c 2 D c 3

D a 0

D a 6

D b 0 D b 1

D Q

D M

t

C C D

PRE

CHARGE

WRITE

C O M M A N D

WRITE

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

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ESMT

M13S64164A (2Y)

Automotive Grade

Write Interrupted by a Read (@ BL=8, CL=2)

0

1

2

3

4

5

6

7

8

9

10

C L K

HI GH

C K E

C S

R A S

C A S

B A 0 , B A 1

A1 0 /AP

BAa

BAb

A D D R

( A 0~ A n )

C a

C b

W E

D Q S

D a 2

D a 1

D a 3

D a 0

D a 4

D a 5

Qb 0

Q b 4

Q b 6 Q b 6

Q b1 Q b 2

Q b5

Q b3

D Q

D M

t

W T R

WRITE

READ

C O MM A N D

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 38/49

ESMT

M13S64164A (2Y)

Automotive Grade

Read Interrupted by Precharge (@ BL=8)

0

1

2

3

4

5

6

7

8

9

10

C L K

H IG H

C K E

C S

R A S

C A S

B A 0 , B A 1

A1 0 /AP

BAa

BAb

A D D R

( A 0 ~ A n )

C a

W E

D Q S ( C L = 2 )

D Q ( C L = 2 )

2 tCK Valid

Q a 1 Qa 2 Qa 3 Q a 4 Q a5

Q a 0

D Q S ( C L = 2 . 5 )

D Q ( C L= 2 . 5)

2.5 tCK Valid

Q a 1 Qa 2 Qa 3 Q a 4 Q a5

Q a 0

D M

PRE

CHARGE

C O M M A N D

READ

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the

Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst

and when a new Bank Activate command may be issued to the same bank.

1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on

the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank

Activate command may be issued to the same bank after t_RP(RAS Precharge time).

2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock

edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the

last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same

bank after t_RP

.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 39/49

ESMT

M13S64164A (2Y)

Automotive Grade

Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=2)

0

1

2

3

4

5

6

7

8

9

10

C L K

H IG H

C K E

C S

R A S

C A S

B A 0 , B A 1

BAa

BAb

A

1 0 / AP

A D D R

( A 0 ~ A n)

C a

C b

W E

D Q S

D Q

D b 1

D b 2 Db 3

Qa 0 Qa 1

Db 4 d b5

Db 7

Db 0

D b 6

D M

Burst

Terminate

READ

C O M M A N D

WRITE

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 40/49

ESMT

M13S64164A (2Y)

Automotive Grade

Read Interrupted by a Read (@ BL=8, CL=2)

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

C S

R A S

C A S

B A 0 , B A 1

BAa

BAb

A

1 0 /AP

C a

C b

A D D R

( A 0 ~ A n )

W E

D Q S

D Q

Qb 3

Q b2

Q b 5

Q a 1

Q b 1

Q b 4

Q b 7

Q b 0

Q b 6

Q a 0

D M

t

CCD

C O MM A N D

READ

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 41/49

ESMT

M13S64164A (2Y)

Automotive Grade

DM Function (@ BL=8) only for write

0

1

2

3

4

5

6

7

8

9

10

C L K

H I GH

C K E

C S

R A S

C A S

B A 0 , B A 1

A1 0 /AP

BAa

C a

A D D R

( A 0 ~ A n )

W E

D Q S

D a2

D a 1

Da 4 D a 5

D a 7

Da 0

D a 3

D a 6

D Q

D M

C O M M A N D

WRITE

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 42/49

ESMT

M13S64164A (2Y)

Automotive Grade

Power up & Initialization Sequence (based on DDR400)

VDD

V

DDQ

t

VDT >=0

VTT

(system*)

V

REF

t

C K

t

C L

t

C H

CLK

t

I S

t

I H

CKE

LVC OMS LO W LE VE L

t

I S

t

I H

ACT

AR

MRS

AR

PRE

NOP

PRE

EMRS

MRS

COMMAND

DM

t

I S

t

I H

A0-A9

A11-An

RA

BA

CODE

t

I S

t

I S

t

I H

t

I H

t

I S

t

I H

A1 0

CODE

ALL BANKS

t

I H

t

I S

BA0 , BA1

BA0=L,

BA1=L

BA0=L,

BA1=L

BA0=H,

BA1=L

H i g h - Z

H i g h -Z

D Q S

D Q

t

M R D

t

M R D

t

R P

t

R F C

t

R F C

t

M R D

T = 2 0 0 u s

2 0 0 cyc l e s o f C L K * *

E x t e n d e d

M o d e

Re g i s t e r

S e t

P o w e r - u p :

V D D a n d

C L K st a b l e

L o a d

M o d e

R e g i s t e r

( wi t h A 8 = L )

L o a d

Mo de

Re g ist e r

Re set DL L

(wi th A8 = H)

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Notes:

* = V_TTis not applied directly to the device, however t_VTDmust be greater than or equal to zero to avoid device latch-up.

** = t_MRDis required before any command can be applied, and 200 cycles of CLK are required before an executable

command can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the

second PRECHARGE ALL command.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 43/49

ESMT

M13S64164A (2Y)

Automotive Grade

Mode Register Set

0

1

2

3

4

5

6

7

8

9

10

C L K

H I G H

C K E

t

M R D

C S

R A S

C A S

W E

B A 0 , B A 1

A

1 0 /A P

ADDRESS KEY

A D D R

( A 0 ~ A n )

D S

D Q

t

R P

H i g h - Z

D Q S

Any

Command

Mode Register Set

Com mand

Precharge

Command

All Bank

:

D o n ’ t c a r e

1 0 1 2 2 B 1 6 R . B

Note: Power & Clock must be stable for 200us before precharge all banks.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 44/49

ESMT

M13S64164A (2Y)

Automotive Grade

Simplified State Diagram

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 45/49

ESMT

M13S64164A (2Y)

Automotive Grade

PACKING DIMENSIONS

66-LEAD

TSOP(II)

DDR DRAM(400mil)

Symbol

Dimension in inch

Dimension in mm

Min

Norm

Max

Min

Norm

Max

1.2

A

A1

A2

b

0.047

0.006

0.041

0.015

0.013

0.008

0.006

0.002

0.037

0.009

0.005

0.0047

0.004

0.039

0.05

0.95

0.22

0.12

0.1

1

0.15

1.05

0.38

0.33

0.21

0.16

b1

c

0.012

0.3

c1

D

0.005

0.127

22.22 BSC

0.71 REF

11.76

0.875 BSC

0.028 REF

0.463

ZD

E

0.455

0.016

0.471

0.024

11.56

0.4

11.96

0.6

E1

e

0.400 BSC

0.026 BSC

0.02

10.16 BSC

0.65 BSC

0.5

L

L1

θ°

0.031 REF

0.80 REF

0°

8°

0°

8°

θ1°

10°

15°

20°

10°

15°

20°

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

46/49

ESMT

M13S64164A (2Y)

Automotive Grade

PACKING

60-BALL

DIMENSIONS

DDR SDRAM ( 8x13 mm )

Symbol

Dimension in mm

Dimension in inch

Min

Norm

Max

Min

Norm

Max

A

A₁

A₂

Φ_b

D

1.20

0.40

0.80

0.50

8.10

13.10

0.047

0.016

0.031

0.020

0.319

0.516

0.30

0.35

0.012

0.014

0.40

7.90

12.90

0.45

8.00

13.00

6.40

11.0

0.80

1.00

0.016

0.311

0.508

0.018

0.315

0.512

0.252

0.433

0.031

0.039

E

D₁

E₁

e

e₁

Controlling dimension : Millimeter.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

47/49

ESMT

M13S64164A (2Y)

Automotive Grade

Revision History

Revision

Date

Description

1.0

2012.10.29

Original

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 48/49

ESMT

M13S64164A (2Y)

Automotive Grade

Important Notice

No part of this document may be reproduced or duplicated in any form or by any

means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the time

of publication. ESMT assumes no responsibility for any error in this document,

and reserves the right to change the products or specification in this document

without notice.

The information contained herein is presented only as a guide or examples for

the application of our products. No responsibility is assumed by ESMT for any

infringement of patents, copyrights, or other intellectual property rights of third

parties which may result from its use. No license, either express , implied or

otherwise, is granted under any patents, copyrights or other intellectual property

rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and

operating safeguards against injury, damage, or loss from such failure, should be

provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as, but

not limited to, life support devices or system, where failure or abnormal operation

may directly affect human lives or cause physical injury or property damage. If

products described here are to be used for such kinds of application, purchaser

must do its own quality assurance testing appropriate to such applications.

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0 49/49

生命周期：	Contact Manufacturer	包装说明：	TFBGA,
Reach Compliance Code：	unknown	风险等级：	5.65
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	0.7 ns
其他特性：	AUTO REFRESH	JESD-30 代码：	R-PBGA-B60
长度：	13 mm	内存密度：	67108864 bit
内存集成电路类型：	DDR DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	60	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	105 °C	最低工作温度：	-40 °C
组织：	4MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	8 mm
Base Number Matches：	1

型号	制造商	描述	价格	文档
M13S64164A-4BVG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60	获取价格
M13S64164A-4TG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66	获取价格
M13S64164A-4TVAG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66	获取价格
M13S64164A-4TVG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66	获取价格
M13S64164A-5BG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格
M13S64164A-5BG2Y	ESMT	DDR DRAM, 4MX16, 0.7ns, CMOS, PBGA60, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-60	获取价格
M13S64164A-5BIG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格
M13S64164A-5TG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格
M13S64164A-5TIG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格
M13S64164A-6BG	ESMT	1M x 16 Bit x 4 Banks Double Data Rate SDRAM	获取价格

M13S64164A-4BVAG2Y

M13S64164A-4BVAG2Y 概述

M13S64164A-4BVAG2Y 规格参数

M13S64164A-4BVAG2Y 数据手册

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