M53D1G3232A-7.5BG [ESMT]
8M x 32Bit x 4 Banks Mobile DDR SDRAM;型号: | M53D1G3232A-7.5BG |
厂家: | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
描述: | 8M x 32Bit x 4 Banks Mobile DDR SDRAM 动态存储器 双倍数据速率 |
文件: | 总48页 (文件大小:1365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ESMT
(Prliminary)
M53D1G3232A
Mobile DDR SDRAM
8M x 32Bit x 4 Banks
Mobile DDR SDRAM
Features
ò
ò
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
VDD/VDDQ = 1.7V ~ 1.95V
Auto & Self refresh
ò
JEDEC Standard
ò
Internal pipelined double-data-rate architecture, two data
access per clock cycle
ò
ò
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
ò
ò
ò
ò
ò
ò
ò
ò
ò
ò
ò
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
7.8us refresh interval (64ms refresh period, 8K cycle)
LVCMOS-compatible inputs
-
-
PASR (Partial Array Self Refresh)
Internal TCSR (Temperature Compensated Self
Refresh)
-
-
-
DS (Drive Strength)
Deep Power Down (DPD) Mode
Status Read Register (SRR)
Ordering Information
Product ID
Max Freq.
200MHz
166MHz
133MHz
VDD
Package
Comments
M53D1G3232A-5BG
M53D1G3232A-6BG
M53D1G3232A-7.5BG
1.8V
144 ball FBGA
Pb-free
Functional Block Diagram
CLK
Clock
Generator
CLK
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Mode Register &
Extended Mode
Register
Bank A
DQS
DM
Sense Amplifier
Column Decoder
Column
Address
Buffer
CS
RAS
CAS
WE
&
Refresh
Counter
Data Control Circuit
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 1/48
ESMT
(Prliminary)
M53D1G3232A
BALL CONFIGURATION (TOP VIEW)
(BGA144, 12mmX12mmX1.4m Body, 0.8mm Ball Pitch)
Ball Description
Ball Name
Function
Ball Name
Function
Address inputs
DM is an input mask signal for write data.
DM0 corresponds to the data on DQ0~DQ7;
DM1 correspond to the data on DQ8~DQ15;
DM2 correspond to the data on DQ16~DQ23;
DM3 correspond to the data on DQ24~DQ31
- Row address A0~A12
A0~A12,
- Column address A0~A9
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
DM0~DM3
BA0~BA1
DQ0~DQ31
Data-in/Data-out
Clock input
CLK, CLK
CKE
Row address strobe
Column address strobe
Write enable
Clock enable
RAS
CAS
Chip select
CS
VDDQ
VSSQ
NC
Supply Voltage for DQ
Ground for DQ
No connection
WE
VSS
Ground
VDD
Power
Bi-directional Data Strobe.
DQS0 corresponds to the data on DQ0~DQ7;
DQS1 correspond to the data on DQ8~DQ15;
DQS2 correspond to the data on DQ16~DQ23;
DQS3 correspond to the data on DQ24~DQ31
DQS0~DQS3
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1
2/48
ESMT
(Prliminary)
M53D1G3232A
Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating ambient temperature
Storage temperature
Symbol
Value
Unit
V
VIN, VOUT
VDD
-0.5 ~ 2.7
-0.5 ~ 2.7
-0.5 ~ 2.7
0 ~ +70
V
VDDQ
TA
V
°C
TSTG
-55 ~ +150
°C
W
Power dissipation
PD
IOS
1.0
50
Short circuit current
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V)
Parameter
Symbol
Min
1.7
Max
1.95
Unit
V
Note
Supply voltage
VDD
I/O Supply voltage
VDDQ
1.7
1.95
V
Input logic high voltage (for Address and Command)
Input logic low voltage (for Address and Command)
Input logic high voltage (for DQ, DM, DQS)
Input logic low voltage (for DQ, DM, DQS)
Output logic high voltage
VIH (DC)
VIL (DC)
VIHD (DC)
VILD (DC)
VOH (DC)
VOL (DC)
VIN (DC)
0.8 x VDDQ
-0.3
VDDQ + 0.3
0.2 x VDDQ
VDDQ + 0.3
0.3 x VDDQ
-
V
V
0.7 x VDDQ
-0.3
V
V
0.9 x VDDQ
-
V
IOH = -0.1mA
IOL = 0.1mA
Output logic low voltage
0.1 x VDDQ
V
-0.3
VDDQ + 0.3
VDDQ + 0.6
V
Input Voltage Level, CLK and CLK inputs
VID (DC)
0.4 x VDDQ
V
1
Input Differential Voltage, CLK and CLK inputs
Input leakage current
II
μA
μA
-2
-5
2
5
Output leakage current
IOZ
Note:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 3/48
ESMT
(Prliminary)
M53D1G3232A
DC Characteristics
Recommended operating condition (Voltage reference to VSS = 0V)
Version
Parameter
Symbol
Test Condition
Unit
-5
-6
-7.5
tRC= tRC (min); tCK = tCK (min); CKE = HIGH;
Operating Current
(One Bank Active)
IDD0
85
80
70
mA
CS = HIGH between valid commands; address inputs
are SWITCHING; data input signals are STABLE
All banks idle, CKE = LOW; CS = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
μA
IDD2P
600
Precharge Standby
Current in
power-down
mode
All banks idle, CKE = LOW; CS = HIGH, CLK = LOW,
μA
IDD2PS
600
7
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
All banks idle, CKE = HIGH; CS = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
mA
7
2
6
2
IDD2N
IDD2NS
IDD3P
Precharge Standby
Current in non
power-down mode
All banks idle, CKE = HIGH; CS = HIGH, CLK = LOW,
2
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
mA
mA
One bank active, CKE = LOW; CS = HIGH,
tCK = tCK (min); address & control inputs are
SWITCHING; data input signals are STABLE
3.5
Active Standby
Current
in power-down
mode
One bank active, CKE = LOW; CS = HIGH,
IDD3PS
3
9
7
mA
mA
mA
CLK = LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
One bank active, CKE = HIGH, CS = HIGH,
IDD3N
10
7
8
7
t
CK = tCK (min); address & control inputs are
Active Standby
Current
in non power-down
mode
SWITCHING; data input signals are STABLE
One bank active, CKE = HIGH; CS = HIGH,
IDD3NS
CLK= LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
(One Bank Active)
One bank active; BL=4; CL=3; tCK = tCK (min);
continuous read bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data changing each burst
IDD4R
IDD4W
IDD5
115
115
75
105
105
70
95
95
65
15
mA
mA
mA
mA
Operating Current
(Burst Mode)
One bank active; BL=4; tCK = tCK (min); continuous
write bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data changing each burst
Burst refresh; tCK = tCK (min);
CKE = HIGH; address inputs are
SWITCHING; data input signals are
STABLE
tRFC= tRFC(min)
Auto Refresh
Current
IDD5A
15
15
tRFC= tREFI
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 4/48
ESMT
(Prliminary)
M53D1G3232A
°C
TCSR range
Full array
1/2 array
45
85
1050
650
450
350
300
800
550
400
300
250
CKE = LOW, CLK = LOW,
CLK = HIGH; EMRS set to all
0’s; address & control & data bus
inputs are STABLE
Self Refresh Current
IDD6
μA
1/4 array
1/8 array
1/16 array
Deep Power Down
Current
μA
address & control & data inputs are STABLE
IDD8
10
Note: 1. Input slew rate is 1V/ns.
2. IDD specifications are tested after the device is properly initialized.
3. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * V DDQ
HIGH is defined as V IN ≥ 0.9 * V DDQ
STABLE is defined as inputs stable at a HIGH or LOW level;
;
;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
VIHD(AC)
VILD(AC)
Min
0.8 x VDDQ
-0.3
Max
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VDDQ+0.3
0.2 x VDDQ
V
VID(AC)
VIX(AC)
0.6 x VDDQ
0.4 x VDDQ
VDDQ+0.6
V
V
1
2
Input Differential Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
0.6 x VDDQ
Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 1.8V, VDDQ =1.8V, TA = 25°C , f = 1MHz)
Parameter
Symbol
CIN1
Min
TBD
TBD
Max
TBD
TBD
Unit
pF
Input capacitance
(A0~A12, BA0~BA1, CKE, CS , RAS , CAS , WE )
CIN2
pF
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
COUT
CIN3
TBD
TBD
TBD
TBD
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 5/48
ESMT
(Prliminary)
M53D1G3232A
AC Operating Test Conditions (VDD = 1.7V~ 1.95V)
Parameter
Input signal minimum slew rate
Value
1.0
Unit
V/ns
V
Input levels (VIH/VIL)
0.8 x VDDQ / 0.2 x VDDQ
0.5 x VDDQ
Input timing measurement reference level
Output timing measurement reference level
V
0.5 x VDDQ
V
AC Timing Parameter & Specifications
(VDD = 1.7V~1.95V, VDDQ=1.7V~1.95V)
-5
-6
-7.5
Symbol
Unit Note
Parameter
min
5
max
100
100
4.8
min
6
max
100
100
5.5
min
7.5
12
max
100
100
6
CL3
CL2
CL3
CL2
ns
ns
ns
ns
tCK
tCK
ns
ns
tCK
Clock Period
tCK
12
12
2
12
2
tAC(3)
tAC(2)
tCH
2
Access time from
CLK/ CLK
2
6.5
2
6.5
2
6.5
0.55
0.55
6
CLK high-level width
CLK low-level width
0.45
0.45
2
0.55
0.55
5
0.45
0.45
2
0.55
0.55
5.5
0.45
0.45
2
tCL
CL3
CL2
tDQSCK (3)
tDQSCK (2)
tDQSS
Data strobe edge to clock
edge
2
6.5
2
6.5
2
6.5
1.25
Clock to first rising edge of DQS delay
0.75
1.25
0.75
1.25
0.75
Data-in and DM setup time (to DQS)
(fast slew rate)
13,14
,15
tDS
tDH
0.48
0.48
0.58
0.58
1.4
0.6
0.6
0.7
0.7
1.4
0.8
0.8
0.9
0.9
1.4
ns
ns
ns
ns
ns
Data-in and DM hold time (to DQS)
(fast slew rate)
13,14
,15
Data-in and DM setup time (to DQS)
(slow slew rate)
13,14
,16
tDS
Data-in and DM hold time (to DQS)
(slow slew rate)
13,14
,16
tDH
DQ and DM input pulse width (for
each input)
tDIPW
17
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Input setup time (slow slew rate)
Input hold time (slow slew rate)
Control and Address input pulse width
DQS input high pulse width
tIS
tIH
0.9
0.9
1.1
1.1
2.3
0.4
0.4
1.1
1.1
1.3
1.3
2.7
0.4
0.4
1.3
1.3
1.5
1.5
3.0
0.4
0.4
ns
ns
ns
ns
ns
tCK
tCK
15,18
15,18
16,18
16,18
17
tIS
tIH
tIPW
tDQSH
tDQSL
0.6
0.6
0.6
0.6
0.6
0.6
DQS input low pulse width
DQS falling edge to CLK rising-setup
time
tDSS
0.2
0.2
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CLK
rising-hold time
tDSH
tCK
ns
Data strobe edge to output data edge
tDQSQ
0.4
0.5
0.6
20
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 6/48
ESMT
(Prliminary)
M53D1G3232A
AC Timing Parameter & Specifications-continued
-5
-6
-7.5
Symbol
Unit Note
Parameter
min
max
5
min
max
5.5
min
max
6
CL3
CL2
tHZ (3)
tHZ (2)
ns
ns
19
19
Data-out high-impedance
window from CLK/ CLK
6.5
6.5
6.5
Data-out low-impedance window from
CLK/ CLK
tLZ
1
1
1
ns
ns
19
tCLmin
or
tCLmin
or
tCLmin
or
Half Clock Period
tHP
10,11
tCHmin
tCHmin
tCHmin
DQ-DQS output hold time
Data hold skew factor
tQH
tQHS
tRAS
tRC
tHP - tQHS
tHP - tQHS
tHP - tQHS
ns
ns
ns
ns
ns
ns
ns
tCK
11
11
0.5
0.65
70K
0.75
70K
ACTIVE to PRECHARGE command
Row Cycle Time
40
55
72
15
15
1
70K
42
60
72
18
18
1
45
67.5
72
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
Minimum tCKE High/Low time
tRFC
tRCD
tRP
22.5
22.5
1
tCKE
ACTIVE bank A to ACTIVE bank B
command
tRRD
tWR
10
15
2
12
15
2
15
15
2
ns
ns
tCK
WRITE recovery time
Write data in to READ command
delay
tWTR
Col. Address to Col. Address delay
Refresh period
tCCD
tREF
1
1
1
tCK
ms
μs
tCK
tCK
tCK
tCK
tCK
tCK
tCK
64
64
64
Average periodic refresh interval
Write preamble
tREFI
7.8
7.8
7.8
9
tWPRE
tWPST
tRPRE (3)
tRPRE (2)
tRPST
0.25
0.4
0.25
0.4
0.25
0.4
Write postamble
0.6
1.1
1.1
0.6
0.6
1.1
1.1
0.6
0.6
1.1
1.1
0.6
22
23
23
CL3
DQS read preamble
CL2
0.9
0.9
0.9
0.5
0.5
0.5
DQS read postamble
0.4
0.4
0.4
READ of SRR to next valid command
MRS for SRR to READ
tSRC
CL + 1
2
CL + 1
2
CL + 1
2
tSRR
Clock to DQS write preamble setup
time
tWPRES
0
0
0
ns
21
24
Load Mode Register / Extended Mode
register cycle time
tMRD
tXSR
tXP
2
112.5
2
2
112.5
1
2
112.5
1
tCK
ns
tCK
Exit self refresh to first valid command
Exit power-down mode to first valid
command
(tWR/tCK
)
(tWR/tCK
)
(tWR/tCK
)
Auto precharge write recovery +
Precharge time
tDAL
+
+
+
ns
25
(tRP/tCK
)
(tRP/tCK
)
(tRP/tCK)
Notes:
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 7/48
ESMT
(Prliminary)
M53D1G3232A
1. All voltages referenced to VSS
.
2. All parameters assume proper device initialization.
3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device operation are
guaranteed for the full voltage and temperature range specified.
4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission
line terminated at the tester electronics). For the half strength driver with a nominal 10 pF load parameters tAC and tQH are
expected to be in the same range. However, these parameters are not subject to production test but are estimated by design /
characterization. Use of IBIS or other simulation tools for system design validation is suggested.
I/O
Z = 50 ohms
0
Timing Reference Load
20 pF
5. The CLK/ CLK input reference voltage level (for timing referenced to CLK/CLK ) is the point at which CLK and CLK cross;
the input reference voltage level for signals other than CLK/CLK is VDDQ/2.
6. The timing reference voltage level is VDDQ/2.
7. AC and DC input and output voltage levels are defined in AC/DC operation conditions.
8. A CLK/ CLK differential slew rate of 2.0 V/ns is assumed for all parameters.
9. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given Mobile DDR,
meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 8 x tREFI
.
10. Refer to the smaller of the actual clock low time and the actual clock high time as provided to the device.
11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during power-down or self-refresh modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC)
to VIL(AC) for falling input signals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no
writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in
progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in
the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
24. There must be at least two clock pulses during the tXSR period.
25. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP
.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 8/48
ESMT
(Prliminary)
M53D1G3232A
Command Truth Table
A12~A11,
A9~A0
COMMAND
CKEn-1 CKEn
DM BA0,1 A10/AP
Note
CS RAS CAS
WE
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1,2
1,2
3
H
L
L
L
H
X
X
X
Entry
L
H
X
3
3
3
Refresh
Self Refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
X
X
Bank Active & Row Addr.
H
V
V
Row Address
Read &
Column
Address
Column
Address
(A0~A9)
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Entry
L
H
L
4
4
H
X
L
L
H
H
L
L
H
L
X
Write &
Column
Address
Column
Address
(A0~A9)
4,8
4,6,8
H
H
X
L
V
X
V
H
L
H
X
H
X
L
Deep Power Down Mode
H
X
X
X
Exit
L
H
X
L
L
H
H
H
H
H
L
Burst Terminate
H
H
X
X
X
X
7
5
Bank Selection
All Banks
V
X
L
Precharge
L
L
H
L
X
H
H
L
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
H
Entry
Exit
H
L
L
H
L
X
X
X
X
X
Active Power Down Mode
X
H
L
H
L
Entry
Exit
H
L
Precharge Power Down
Mode
X
X
H
L
H
X
Deselect (NOP)
H
L
H
No Operation (NOP)
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A12 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding and
coincident DM is “High”. (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 9/48
ESMT
(Prliminary)
M53D1G3232A
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a high state (all other inputs may be undefined.)
-
Apply VDD before or at the same time as VDDQ.
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK, CLK ), apply NOP.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
13
14
15
16
17
18
19
20
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
C S
t
R F C
t
R F C
t
R P
t
M R D
t
M R D
R A S
C A S
A D D R
K e y
K e y
R A
B A 1
B A 0
B S
B S
R A
A10 /AP
H i g h - Z
D Q
W E
D Q M
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
A u t o R e f r e s h
A u t o R e f r e s h
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
E x t e n d e d M o d e
R e g i s t e r S e t
:
D o n ' t c a r e
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1
10/48
ESMT
(Prliminary)
M53D1G3232A
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS latency,
addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of different
applications. The default value of the register is not defined, therefore the mode register must be written in the power up sequence
of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0~BA1 (The Mobile
DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address
pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7~A12 is used for test mode. A7~A12 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1 BA0
A12~ A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Mode Register
0*
0*
0*
Burst Length
CAS Latency
A3
0
Burst Type
Sequential
Interleave
1
Burst Length
Length
CAS Latency
A2
A1
A0
A6
0
A5
0
A4
Latency
Sequential Interleave
BA1 BA0
Operating Mode
MRS
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved Reserved
0
0
1
1
0
1
0
1
0
0
2
4
2
4
SRR
0
1
EMRS
0
1
3
8
8
Reserved
1
0
Reserved
Reserved
Reserved
Reserved
16
16
1
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
1
1
1
1
* BA0~BA1 and A12~A7 should stay “0” during MRS cycle
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 11/48
ESMT
(Prliminary)
M53D1G3232A
Burst Address Ordering for Burst Length
Sequential Mode
Starting Column
Address
Burst
Interleave Mode
Length
A3
A2
A1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
0, 1
2
4
1, 0
1, 0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1
3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2
4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3
5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4
6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5
7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6
8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7
9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8
A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A
C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B
D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C
E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D
F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, B, A, D, C, F, E
2, 3, 0, 1, 6, 7, 4, 5, A, B, 8, 9, E, F, C, D
3, 2, 1, 0, 7, 6, 5, 4, B, A, 9, 8, F, E, D, C
4, 5, 6, 7, 0, 1, 2, 3, C, D, E, F, 8, 9, A, B
5, 4, 7, 6, 1, 0, 3, 2, D, C, F, E, 9, 8, B, A
6, 7, 4, 5, 2, 3, 0, 1, E, F, C, D, A, B, 8, 9
7, 6, 5, 4, 3, 2, 1, 0, F, E, D, C, B, A, 9, 8
8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7
9, 8, B, A, D, C, F, E, 1, 0, 3, 2, 5, 4, 7, 6
A, B, 8, 9, E, F, C, D, 2, 3, 0, 1, 6, 7, 4, 5
B, A, 9, 8, F, E, D, C, 3, 2, 1, 0, 7, 6, 5, 4
C, D, E, F, 8, 9, A, B, 4, 5, 6, 7, 0, 1, 2, 3
D, C, F, E, 9, 8, B, A, 5, 4, 7, 6, 1, 0, 3, 2
E, F, C, D, A, B, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
F, E, D, C, B, A, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
16
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1
12/48
ESMT
(Prliminary)
M53D1G3232A
Extended Mode Register Set (EMRS)
The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE , BA0
and high on BA1 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in
the extended mode register. Refer to the table for specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as long
as all banks are in the idle state.
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control
the self refresh cycle automatically according to the device temperature.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
BA1 BA0
0*
A12 ~ A8
0*
A7 A6 A5 A4 A3
DS TCSR
A2 A1 A0
PASR
Address bus
1
Extended Mode Register Set
A2-A0
000
001
Self Refresh Coverage
Full array
1/2 array (BA1 = 0)
1/4 array
(BA1 = BA0 =0)
Reserved
010
011
100
PASR
Reserved
1/8 array
(BA1 = BA0 = Row Addr MSB** =0)
101
1/16 array
(BA1 = BA0 = Row Addr 2 MSB =0)
Reserved
110
111
Internal TCSR
A7-A5
Drive Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
3/4 Strength
000
001
010
011
100
DS
* BA0 and A12~ A8 should stay “0” during EMRS cycle.
** MSB: most significant bit
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1
13/48
ESMT
(Prliminary)
M53D1G3232A
Status Register Set (SRR)
The status read register is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the device.
The SRR is read via the MRS command with BA0 = 1 and BA1 = 0. The sequence to perform an SRR command is as follows:
1. The device must be properly initialized and in the idle or all banks precharged state.
2. Issue a MODE REGISTER SET command with BA[1:0] = 01 and all address pins set to 0.
3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time.
4. Issue a READ command.
5. Subsequent commands to the device must be issued tSRC after the SRR READ command is issued; only NOP or DESELECT
commands are supported during tSRC
.
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first bit of the burst, with the output being
“Don’t Care” on the second bit of the burst.
DQ31 ~ DQ16
Reserved
DQ15 ~ DQ13 DQ12 DQ11 DQ10 ~ DQ8
DQ 7 ~ DQ 4
Revision ID
DQ 3 ~ DQ0
I/O Bus
Density
DT
DW
Refresh Rate
Manufacturer ID
Status Register
DQ12 Device Type
DQ11 Device Width
0
1
LPDDR
LPDDR2
0
1
16 bits
32 bits
Refresh
DQ15 DQ14 DQ13 Density
DQ10 DQ9 DQ8
DQ3 DQ2 DQ1 DQ0 Manufacturer ID
Multiplier*
Reserved
Reserved
Reserved
2X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
128Mb
256Mb
512Mb
1Gb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Samsung
Infineon
Elpida
2Gb
1X
Reserved
Reserved
Reserved
Reserved
Winbond
ESMT
Reserved
Reserved
Reserved
Reserved
0.25X
Reserved
NVM
Reserved
Reserved
Reserved
Reserved
Micron
DQ7
0
DQ6
DQ5
0
DQ4
0
Revision ID
The manufacturer’s revision number starts at ‘0000’
and increments by ‘0001’ each time a change in the
specification (AC timings or feature set), IBIS (pull up
or pull-down characteristics), or process occurs.
0
…
X
...
…
X
…
X
X
* Refresh multiplier is based on the memory device on-board temperature sensor. Required average periodic refresh interval = tREFI
× multiplier.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 14/48
ESMT
(Prliminary)
M53D1G3232A
0
1
2
3
4
5
6
7
8
C L K
C L K
t
S R R
t
S R C
NOP
PRE1
NOP2
Co m mand
READ
NOP
R P
MRS
0
NOP
NOP
Valid
t
Ad dress
BA0=1
BA1=0
B A 0 , B A 1
C L = 33
D Q S
Note 5
SRR
D Q
4
Out
Note:
1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands (tSRR), and between the READ and the
next VALID command (tSRC).
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown as an example only.
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control
inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both
Deselect and NOP, the device should finish the current operation when this command is issued.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 15/48
ESMT
(Prliminary)
M53D1G3232A
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The Mobile DDR SDRAM has four independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
2
3
4
5
6
C L K
C L K
B a n k
A
B a n k
A
B a n k
A
B a n k
B
A d d r e s s
C o l . A d d r .
Ro w . Ad d r.
R o w A d d r .
R o w A d d r .
R A S - C A S d e l a y
N O P
(
t
R C D
)
R A S - R A S d e l a y ( t R R D )
B a n k
A
W r i t e
A
B a n k
B
B a n k
A
N O P
C o m m a n d
N O P
A c t i v a t e
w i t h A u t o
P r e c h a r g e
A c t i v a t e
A c t i v a t e
R O W C y c l e T i m e
( t R C )
: D o n 't Ca r e
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , RAS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth
table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , RAS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The
length of the burst will be determined by the values programmed during the MRS command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 16/48
ESMT
(Prliminary)
M53D1G3232A
Essential Functionality for Mobile DDR SDRAM
Burst Read Operation
Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst read
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK)
after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of
burst and burst length. The first output data is available after the CAS Latency from the READ command, and the consecutive
data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR SDRAM until the burst length is
completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
N O P
N O P
N O P
N O P
R E A D
A
N O P
N O P
N O P
C O M M A N D
N O P
t D Q S C K
t R P R E
t D Q S C K
t R P S T
D Q S
t D Q S Q ( m a x )
C A S L a t e n c y = 3
t A C
D o ut 3
t Q H
D ou t 0 D o u t1 D o ut 2
D Q ' s
t Q H
tQ H S
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock
(CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write
cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled
after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on
each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
N O P
N O P
N O P
N O P
W R I TE A
W R I T E B
N O P
N O P
P R E B
C O M M A N D
t
W R
t
D Q S S ( m a x )
D Q S
t
W P R E S
D i n 2 D i n 3
D i n 1 D i n 2 D i n 3
D Q ' s
D i n 1
D i n 0
D i n 0
t
W R
t
D Q S S ( m i n )
D Q S
D Q ' s
t
W P R E S
D i n 3
D i n 2
D i n 1 D i n 2 D i n 3 D i n 0 D i n 1
D i n 0
t
D S
t
D H
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
Revision : 0.1 17/48
ESMT
(Prliminary)
M53D1G3232A
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 clock.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
t
C C D ( m i n )
RE A D B
N O P
N O P
N O P
N O P
N O P
R E A D A
N O P
N O P
C O M M A N D
t
D Q S C K
H i - Z
D Q S
D Q ' s
t
R P S T
t
R P R E
H i - Z
Dout
B0
Dout
Dout
A
0
Dout
A
1
B1 Dout B2 Dout B3
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O
bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning
the write operation, Burt Terminate command must be applied at least RU(CL) clocks 〔RU means round up to the nearest integer〕
before the Write command.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
B urs t
Te rm in at e
N O P
N O P
R E A D
N O P
W R I T E
N O P
N O P
C O M M A N D
N O P
t
D Q S S
t
t
D Q S C K
R P R E
t
R P S T
D Q S
t
W P S T
t
W P R E S
t
A C
Dout 0
Dout 1
Din 0 Din 1 Din 2 Din 3
D Q ' s
t
W P R E
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU (CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
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ESMT
(Prliminary)
M53D1G3232A
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
1 t C K
N O P
N O P
N O P
N O P
R E A D
Precha rge
N O P
N O P
N O P
C O M M A N D
t D Q S C K
t R P R E
D Q S
t A C
Dout 1
Dout 6 Dout 7
Dout 5
Dout 0
Dout 2
Dout 4
Dout 3
D Q ' s
I n t e r r u p t e d b y p r e c h a r g e
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before
the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst
and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP
.
3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with auto precharge commands where tRAS(min) must still be satisfied such that a Read with auto
precharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
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ESMT
(Prliminary)
M53D1G3232A
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses
are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
1 t C K
WRITE A
NO P
N OP
N OP
N OP
N OP
WRITE B
N OP
NO P
C OM M AN D
D QS
D Q' s
Din
A
0
Din
A
1
Din B
0
Din B
1
Din B
2
Din B3
t
C C D
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ESMT
(Prliminary)
M53D1G3232A
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to
avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is
initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of
write command.
<Burst Length = 8, CAS Latency = 3>
0
1
WRITE
5)
2
3
4
5
6
7
8
C L K
C L K
N O P
N O P
N O P
N O P
N O P
N O P
R E A D
N O P
C O M M A N D
t
W T R
t
D Q S S ( m a x )
H i - Z
H i - Z
D Q S
t
W P R E S
D o u t 0
D o u t 1
D i n a 6
D i n a 0 D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5
D i n a 7
D Q ' s
D M
t
W T R
t
D Q S S ( m i n )
H i - Z
H i - Z
D Q S
D Q ' s
D M
5)
W P R E S
t
D o u t 0
D o u t 1
D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
D i n a 0
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the
memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM.
5. It is illegal for a Read command interrupt a Write with auto precharge command.
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ESMT
(Prliminary)
M53D1G3232A
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted,
any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
C L K
C L K
P r e c h a r g e A
N O P
WRITE A
N O P
N O P
WRITE B
N O P
N O P
N O P
C O M M A N D
t
D Q S S ( m a x
)
t
W R
t
D Q S S ( m a x )
H i - Z
H i - Z
D Q S
t
W P R E S
t
W P R E S
D i n a 0 D i n a 1 D i n a 2 D i n a 3
D i n b 0
D Q ' s
D M
t
W R
t
D Q S S ( m i n )
t
D Q S S ( m i n )
H i - Z
H i - Z
D Q S
D Q ' s
D M
t
W P R E S
t
W P R E S
D i n a 4 D i n a 5 D i n a 6 D i n a 7
D i n a 1 D i n a 2 D i n a 3
D i n b 1
D i n b 0
D i n a 0
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow “Write recovery” which is the time
required by a Mobile DDR SDRAM core to properly store a full “0” or “1” level before a Precharge operation. For Mobile DDR
SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge
command to the same bank.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge
that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR
.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR
.
3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP
where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes
in the Bank Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same
time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with auto precharge commands where tRAS(min) must still be satisfied such that a Write with auto
precharge command has the same timing as a Write command followed by the earliest possible Precharge command which
does not interrupt the burst.
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ESMT
(Prliminary)
M53D1G3232A
Burst Terminate
The Burst Terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The Burst Terminate command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the Burst Terminate command is issued during a burst read cycle, the pair of data
and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
Burst Terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
2
3
4
5
6
7
8
C L K
C L K
Burst
Terminate
N O P
N O P
N O P
C O M M A N D
R E A D
A
N O P
N O P
N O P
N O P
The burst read ends after a deley equal to the CAS lantency.
D Q S
H i - Z
H i - Z
D Q ' s
Dout 1
Dout 0
The Burst Terminate command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with auto precharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
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ESMT
(Prliminary)
M53D1G3232A
DM masking
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
C L K
C L K
C O MM A N D
N O P
N O P
N O P
N O P
N O P
N O P
W R I T E
N O P
N O P
t
D Q S S
D Q S
D Q ' s
D M
H i - Z
H i - Z
t
W P R E S
D i n a 1 D i n a 2 D i n a 3 D i n a 4 D i n a 5 D i n a 6 D i n a 7
D i n a 0
m a s k e d b y D M = H
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ESMT
(Prliminary)
M53D1G3232A
Read with Auto Precharge
If a read with auto precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2
clock later from a read with auto precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will
be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
9
10
0
1
2
3
4
5
6
7
8
C L K
C L K
Read
Auto Precharge
A
C O M M A N D
B a n k
A
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
A C T I V E
t
R P
Bank can be reactivated at
completion of tRP
1)
D Q S
D Q ' s
H i - Z
H i - Z
Dout 0 Dout 1
Dout 2 Dout 3
Auto-Precharge starts
t
R A S ( m i n )
Note: The row active command of the precharge bank can be issued after tRP from this point.
For Same Bank
For Different Bank
Asserted
Command
5
6
7
5
6
7
READ
READ + AP1
READ + No AP
READ + AP
Illegal
Illegal
Illegal
Illegal
Legal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Active
Precharge
Legal
Note: 1. AP = Auto Precharge
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ESMT
(Prliminary)
M53D1G3232A
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of the CLK
with the tWR delay after the last data-in.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
9
10
11
12
C L K
C L K
Write
Auto Precharge
A
B a n k
A
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
C O M M A N D
N O P
N O P
A C T I V E
D Q S
* B a n k c a n b e r e a c t i v a t e d a t
c o m p l e t i o n o f t R P
D Q ' s
D
IN
0
D
IN
1
DIN 2
D
IN 3
t W
R
t R P
I n t e r n a l p r e c h a r g e s t a r t
Note: The row active command of the precharge bank can be issued after tRP from this point.
For Same Bank
7
For Different Bank
Asserted
Command
5
6
8
9
10
5
6
7
8
9
WRITE
WRITE + WRITE +
NO AP NO AP
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
WRITE +
AP1
WRITE + WRITE +
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Illegal
Illegal
Legal
Illegal
Illegal
AP
AP
READ
READ +
READ +
No AP+ DM
READ +
No AP
Illegal
No AP + DM2
READ + AP
READ +
AP+ DM
READ +
AP+ DM
READ +
AP
Illegal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Precharge
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by Precharge & DM”
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ESMT
(Prliminary)
M53D1G3232A
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the
clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given Mobile DDR, meaning
that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x tREFI
.
C L K
C L K
Auto
Refresh
C O M M A N D
P R E
C M D
C K E
= H ig h
t
R F C
t
R P
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock
(CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self
refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power
consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than tXSR
.
C L K
C L K
Self
Refresh
Auto
Refresh
N OP
N OP
N O P
C O MM A N D
NOP
N OP
NO P
t
X S R ( m i n )
C K E
t
I S
t
I S
Note: After self refresh exit, input an auto refresh command immediately.
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ESMT
(Prliminary)
M53D1G3232A
Power Down
Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is
referred to as active power-down.
Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low
must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is specified by tCKE. However,
power down duration is limited by the refresh requirements of the device.
The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid
command may be applied tXP after exit from power down.
C L K
C L K
tCKE
tRP
tCKE
tXP
tXP
C K E
tIS
tIS
tIS
t
IS
C O MM A N D
Precharge
Active
Read
Enter Precharge
power-down
mode
Exit Precharge
power-down
mode
Enter Active
power-down
mode
Exit Active
power-down
mode
Functional Truth Table
Truth Table – CKE [Note 1~10]
COMMAND n
CKE n-1
CKE n
Current State
Power Down
ACTION n
NOTE
L
L
L
X
Maintain Power Down
Maintain Self Refresh
Maintain Deep Power Down
Exit Power Down
L
Self Refresh
X
L
L
Deep Power Down
Power Down
X
L
H
H
H
L
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
AUTO REFRESH
BURST TERMINATE
5,6,9
5,7,10
5,8
5
L
Self Refresh
Exit Self Refresh
L
Deep Power Down
All Banks Idle
Bank(s) Active
All Banks Idle
All Banks Idle
Exit Deep Power Down
Precharge Power Down Entry
Active Power Down Entry
Self Refresh Entry
H
H
L
5
H
H
L
L
Enter Deep Power Down
H
H
See the other Truth Tables
Notes:
1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of Mobile DDR immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power Down exit procedure must be followed the figure of Deep Power Down Mode Entry & Exit Cycle.
9. The clock must toggle at least once during the tXP period.
10. The clock must toggle at least once during the tXSR time.
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ESMT
(Prliminary)
M53D1G3232A
Truth Table – Current State Bank n
Current State
COMMAND / ACTION
NOTE
CS
RAS
CAS
WE
Command to Bank n [Note 1~12]
H
X
H
L
X
H
H
L
X
H
H
H
L
DESELECT (NOP / continue previous operation)
Any
L
No Operation (NOP / continue previous operation)
ACTIVE (select and activate row)
L
Idle
L
L
L
L
L
L
L
L
L
L
L
L
L
AUTO REFRESH
9
9
L
L
MODE REGISTER SET
H
H
L
L
H
L
READ (select column & start read burst)
WRITE (select column & start write burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column & start new read burst)
WRITE (select column & start write burst)
PRECHARGE (truncate read burst, start precharge)
BURST TERMINATE
Row Active
L
H
L
L
4
H
H
L
H
L
5
Read
(Auto Precharge
Disabled)
L
5, 12
H
H
L
L
H
H
H
L
L
10
5,11
5
H
L
READ (select column & start read burst)
WRITE (select column & start new write burst)
PRECHARGE (truncate write burst, start precharge)
Write
(Auto Precharge
Disabled)
L
H
L
11
Command to Bank m [Note 1~3,6, 11~16]
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
DESELECT (NOP / continue previous operation)
No Operation (NOP / continue previous operation)
Any command allowed to bank m
ACTIVE (select and activate row)
READ (select column & start read burst)
WRITE (select column & start write burst)
PRECHARGE
Any
Idle
Row Activating,
Active, or
Precharging
H
H
L
16
16
L
H
H
L
L
L
H
H
L
ACTIVE (select and activate row)
READ (select column & start new read burst)
WRITE (select column & start write burst)
PRECHARGE
Read
(Auto Precharge
disabled)
H
H
L
16
L
12,16
H
H
L
L
L
H
H
L
ACTIVE (select and activate row)
READ (select column & start read burst)
WRITE (select column & start new write burst)
PRECHARGE
Write
(Auto Precharge
H
H
L
11,16
16
L
disabled)
H
H
L
L
L
H
H
L
ACTIVE (select and activate row)
READ (select column & start new read burst)
WRITE (select column & start write burst)
PRECHARGE
H
H
L
13,16
Read with
Auto Precharge
L
12,13,16
H
H
L
L
L
H
H
L
ACTIVE (select and activate row)
READ (select column & start read burst)
WRITE (select column & start new write burst)
PRECHARGE
Write with
Auto Precharge
H
H
L
13,16
13,16
L
H
L
Notes:
1. The table applies when both CKE n-1 and CKE n are HIGH, and after tXSR or tXP has been met if the previous state was Self
Refresh or Power Down.
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2016
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ESMT
(Prliminary)
M53D1G3232A
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for
precharging.
5. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.
6. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses
are in progress.
Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
7. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and the part of Command to Bank n, according to the part of
Command to Bank m.
Precharging: starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will
be in the idle state.
Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be
in the ‘row active’ state.
Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP
has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
8. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied to
each positive clock edge during these states.
Refreshing: starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the device
will be in an ‘all banks idle’ state.
Accessing Mode Register: starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the device will be in an ‘all banks idle’ state.
Precharging All: starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank
will be in the idle state.
9. Not bank-specific; requires that all banks are idle and no bursts are in progress.
10. Not bank-specific. BURST TERMINATE affects the most recent read burst, regardless of bank.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be
issued to end the READ prior to asserting a WRITE command.
13. Read with AP enabled and Write with AP enabled: the Read with Auto Precharge enabled or Write with Auto Precharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all the data in the burst. For Write with AP, the precharge period begins when tWR
ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and
ends where the precharge period (or tRP) begins. During the precharge period of the Read with AP enabled or Write with AP
enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access
period, only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related
limitations apply (e.g. contention between READ data and WRITE data must be avoided).
14. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
15. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
16. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and
WRITEs with Auto Precharge disabled.
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ESMT
(Prliminary)
M53D1G3232A
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
t
C H
t
C L
t
C K
0
1
2
3
4
5
6
7
8
9
10
11
12
13
C L K
C L K
H I G H
C K E
t
I S
C S
t
I H
R A S
C A S
B A 0 , B A 1
BAa
Ra
BAa
BAb
A
1 0 /AP
AD D R
( A 0 ~ A n )
Ra
Ca
Cb
W E
t
D S H
t
D S S
t
D Q S S
t
R P S T
t
D Q S L
tW P S T
H i - Z
t
R P R E
Hi - Z
H i - Z
H i - Z
H i - Z
D Q S
D Q
t
Q H
t
D Q S H
W P R E
t
W P R E S
t
D Q S C K
L Z
t
D Q S Q
t
H Z
t
t
H i -Z
D b 2
D b 3
Q a 0
Q a1 Q a 2
Q a 3
D b 0 Db 1
t
D S tD H
t
A C
t
Q H S
D M
C O MM A N D
READ
WRITE
Active
10122B32R.B
Note: tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
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ESMT
(Prliminary)
M53D1G3232A
Multi Bank Interleaving READ (@BL=4, CL=3)
11
12
0
1
2
3
4
5
6
7
8
9
10
13
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAb
BAa
BAb
B A 0 , B A 1
A
1 0 /AP
R a
R a
R b
R b
C a
C b
A DD R
( A0 ~ An )
W E
D Q S
D Q s
D M
t
R R D
t
C C D
H i - Z
H i - Z
Q b 1
Qb 3
Q a 0 Q a 1 Q a 2 Qa 3 Q b 0
Q b 2
t
R C D
C O MM A N D
ACTIVE
ACTIVE
READ
READ
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Multi Bank Interleaving WRITE (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAb
BAa
BAb
B A 0 , B A 1
A
1 0 /AP
R a
R a
R b
R b
t
R R D
t
C C D
C b
C a
A D D R
( A 0 ~ A n )
W E
D Q S
D Q
H i- Z
H i - Z
D a 1
Db 0 Db 1
D b3
Da 0
D a 2 D a 3
D b 2
D M
t
R C D
C O M M A N D
ACTIVE
ACTIVE
WRITE
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Read with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H IG H
C K E
C S
R A S
C A S
BAa
BAa
B A 0 , B A 1
A
1 0 /AP
R a
R a
A D D R
C a
(A 0 ~ A n)
W E
A u t o p r e c h a r g e s t a r t
R P
t
1)
No t e
D Q S ( C L = 3 )
D Q ( C L = 3)
H i - Z
H i - Z
Q a 4 Qa 5
Q a0
Q a7
Q a 1 Q a 2 Q a 3
Q a 6
D M
A C T I V E
R E A D
C O MM A N D
10122B32R.B
Note: The row active command of the precharge bank can be issued after tRP from this point.
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ESMT
(Prliminary)
M53D1G3232A
Write with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAa
R a
R a
B A 0 , B A 1
A
1 0 /AP
C a
A D D R
( A 0 ~ A n )
W E
t
D A L
A u t o p r e c h a r g e s t a r t
R P
t
W R
t
No t e 1
D Q S
D Q
D a 2
D a 5
D a 0 D a 1
D a 3 Da 4
D a 6 D a 7
D M
C O M M A N D
ACTIVE
WRITE
10122B32R.B
Note: The row active command of the precharge bank can be issued after tRP from this point.
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ESMT
(Prliminary)
M53D1G3232A
Read Interrupted by Precharge (@BL=8)
.
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAa
B A 0 , B A 1
A
1 0 /A P
A D D R
( A 0 ~ A n )
C a
W E
H i - Z
H i - Z
D Q S
D Q s
2
t
C K V a l i d
Q a 2
Q a 5
Qa 0
Q a 1
Qa 3 Qa 4
D M
PRE
CHARGE
C O M M A N D
READ
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Read Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
B A 0 , B A 1
BAa
BAb
A
1 0 /AP
A D D R
C a
C b
( A 0 ~ A n )
W E
H i - Z
H i- Z
D Q S
D Q s
Q a 0 Q a 1 Q b 0 Q b 1
Q b 4 Q b 5
Q b 6 Q b7
Q b 2 Q b 3
D M
C O M M A N D
READ
READ
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Read Interrupted by a Write & Burst Terminate (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H IG H
C K E
C S
R A S
C A S
BAa
BAb
B A 0 , B A 1
A
1 0 / AP
A D D R
( A 0 ~A n )
C a
C b
W E
H i - Z
H i - Z
D Q S
D Q s
Qa 0 Q a 1
D b 0
Db 1 D b 2 D b 3
D b 4 Db 5 D b 6 D b 7
D M
Burst
Terminate
C O M M A N D
READ
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Write followed by Precharge (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAa
B A 0 , B A 1
A
1 0 /AP
A D D R
C a
( A 0 ~ A n )
W E
t
W R
D Q S
D a 0 D a 1 D a 2 D a 3
D Q
D M
PRE
CHARGE
C O M M A N D
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Write Interrupted by Precharge & DM (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
BAa
BAa
BAb
B A 0 , B A 1
A
1 0 /AP
A D D R
Cb
C a
( A 0 ~ A n )
W E
D Q S
D b 5
D a 1 D a 2 D a 3
D a 5 D a 6
D a 7
D b 0
D b 1
D b 4
D a 0
D a 4
D b 2 D b 3
D Q
D M
t
W R
PRE
CHARGE
C O MM A N D
WRITE
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Write Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
B A 0 , B A 1
BAa
BAb
A
1 0 /AP
A D D R
( A 0 ~ A n )
C a
C b
W E
H i - Z
H i - Z
D Q S
D a 2
D a 0 D a 1
D a 3 D a 4 D a 5
M a s k e c d b y D M
Q b 2
Q b 4 Q b 5
Q b 0 Qb 1
Q b 3
D Q
D M
t
W T R
C O M M A N D
READ
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
DM Function (@BL=8) only for write
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
H I G H
C K E
C S
R A S
C A S
B A 0 , B A 1
A1 0 /AP
BAa
C a
A D D R
( A 0 ~ A n )
W E
D Q S ( C L = 3 )
D Q ( C L = 3 )
D M
D a 2
D a 1
D a 4 D a5
D a 7
Da 0
D a3
D a 6
C O MM A N D
WRITE
10122B32R.B
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ESMT
(Prliminary)
M53D1G3232A
Deep Power Down Mode Entry & Exit Cycle
Note:
DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM:
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of
the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the
device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the
clock. While CKE is low.
2) Clock must be stable before exited deep power down mode.
3) Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) 200
μs wait time is required to exit from Deep Power Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
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ESMT
(Prliminary)
M53D1G3232A
Mode Register Set
0
1
2
3
4
5
6
7
8
9
1 0
11
1 2
1 3
14
1 5
1 6
1 7
1 8
19
C L K
C L K
HIGH
C K E
C S
R A S
C A S
W E
K E Y
K E Y
K E Y
BA0 , BA 1
A1 0/AP
A D D RE S S K E Y
A D D R
( A 0 ~ A n )
Hi-Z
D Q S
D Q s
t
R P
t
M R D
Hi-Z
D M
C O MM A N D
P r e c h a r g e
Co mm a n d
A l l B a n k
A n y
C o m m a n d
10122B32R.B
M RS
C o m m a n d
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ESMT
(Prliminary)
M53D1G3232A
Simplified State Diagram
PREALL = Precharge All Banks
Write = Write w/o Auto Precharge
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
Write A = Write with Auto Precharge
Read = Read w/o Auto Precharge
Read A = Read with Auto Precharge
PRE = Precharge
BST = Burst Terminate
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power-Down
SRR = Status Register Read
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ESMT
(Prliminary)
M53D1G3232A
PACKING DIMENSIONS
144-BALL FBGA DDR DRAM (12x12mm)
Symbol
Dimension in mm
Dimension in inch
Min
1.14
0.30
0.40
11.90
Norm
Max
1.40
0.40
0.50
12.10
Min
Norm
Max
0.055
0.016
0.020
0.476
____
____
A
A1
Φb
D
E
D1
0.049
0.012
0.016
0.469
0.35
0.45
12.00
12.00
8.80
8.80
0.80
0.10
0.10
0.12
0.15
0.08
12/12
0.014
0.018
0.472
0.472
0.346
0.346
0.031
0.004
0.004
0.005
0.004
0.006
12/12
11.90
12.10
0.469
0.476
____
____
____
____
____
____
____
____
____
____
____
____
E1
e
aaa
bbb
ddd
eee
fff
MD/ME
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46/48
ESMT
(Prliminary)
M53D1G3232A
Revision History
Revision
Date
2014.04.01
Description
0.1
Original
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ESMT
(Prliminary)
M53D1G3232A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.
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