ESP32-D0WDQ6-V3_技术文档

ESP32 Series

Datasheet

Including:

ESP32-D0WD-V3

ESP32-D0WDQ6-V3

ESP32-D0WD

ESP32-D0WDQ6

ESP32-D2WD

ESP32-S0WD

ESP32-U4WDH

Version 3.4

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About This Guide

This document provides the specifications of ESP32 family of chips.

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owners, and are hereby acknowledged.

Contents

1 Overview

1

2

3

4

5

1.1 Featured Solutions

1.1.1 Ultra-Low-Power Solution

1.1.2 Complete Integration Solution

1.2 Wi-Fi Key Features

1.3 BT Key Features

1.4 MCU and Advanced Features

1.4.1 CPU and Memory

1.4.2 Clocks and Timers

1.4.3 Advanced Peripheral Interfaces

1.4.4 Security

1.5 Applications (A Non-exhaustive List)

1.6 Block Diagram

2 Pin Definitions

2.1 Pin Layout

6

2.2 Pin Description

2.3 Power Scheme

2.4 Strapping Pins

8

11

12

3 Functional Description

3.1 CPU and Memory

3.1.1 CPU

15

16

18

19

20

21

22

3.1.2 Internal Memory

3.1.3 External Flash and SRAM

3.1.4 Memory Map

3.2 Timers and Watchdogs

3.2.1 64-bit Timers

3.2.2 Watchdog Timers

3.3 System Clocks

3.3.1 CPU Clock

3.3.2 RTC Clock

3.3.3 Audio PLL Clock

3.4 Radio

3.4.1 2.4 GHz Receiver

3.4.2 2.4 GHz Transmitter

3.4.3 Clock Generator

3.5 Wi-Fi

3.5.1 Wi-Fi Radio and Baseband

3.5.2 Wi-Fi MAC

3.6 Bluetooth

3.6.1 Bluetooth Radio and Baseband

3.6.2 Bluetooth Interface

3.6.3 Bluetooth Stack

22

23

3.6.4 Bluetooth Link Controller

3.7 RTC and Low-Power Management

4 Peripherals and Sensors

4.1 Descriptions of Peripherals and Sensors

4.1.1 General Purpose Input / Output Interface (GPIO)

4.1.2 Analog-to-Digital Converter (ADC)

4.1.3 Hall Sensor

25

26

27

28

29

30

4.1.4 Digital-to-Analog Converter (DAC)

4.1.5 Touch Sensor

4.1.6 Ultra-Low-Power Co-processor

4.1.7 Ethernet MAC Interface

4.1.8 SD/SDIO/MMC Host Controller

4.1.9 SDIO/SPI Slave Controller

4.1.10 Universal Asynchronous Receiver Transmitter (UART)

4.1.11 I²C Interface

4.1.12 I²S Interface

4.1.13 Infrared Remote Controller

4.1.14 Pulse Counter

4.1.15 Pulse Width Modulation (PWM)

4.1.16 LED PWM

4.1.17 Serial Peripheral Interface (SPI)

4.1.18 Accelerator

4.2 Peripheral Pin Configurations

5 Electrical Characteristics

5.1 Absolute Maximum Ratings

5.2 Recommended Operating Conditions

5.3 DC Characteristics (3.3 V, 25 °C)

5.4 Reliability Qualifications

35

36

37

38

39

40

5.5 RF Power-Consumption Specifications

5.6 Wi-Fi Radio

5.7 Bluetooth Radio

5.7.1 Receiver – Basic Data Rate

5.7.2 Transmitter – Basic Data Rate

5.7.3 Receiver – Enhanced Data Rate

5.7.4 Transmitter – Enhanced Data Rate

5.8 Bluetooth LE Radio

5.8.1 Receiver

5.8.2 Transmitter

6 Package Information

42

43

7 Part Number and Ordering Information

8 Learning Resources

8.1 Must-Read Documents

44

8.2 Must-Have Resources

Appendix A – ESP32 Pin Lists

A.1. Notes on ESP32 Pin Lists

A.2. GPIO_Matrix

45

47

52

A.3. Ethernet_MAC

A.4. IO_MUX

Revision History

54

List of Tables

1

2

3

4

5

6

7

8

9

Pin Description

8

12

13

14

17

23

25

26

30

35

36

37

38

39

40

43

45

47

52

Description of ESP32 Power-up and Reset Timing Parameters

Strapping Pins

Parameter Descriptions of Setup and Hold Times for the Strapping Pin

Memory and Peripheral Mapping

Power Consumption by Power Modes

ADC Characteristics

ADC Calibration Results

Capacitive-Sensing GPIOs Available on ESP32

10 Peripheral Pin Configurations

11 Absolute Maximum Ratings

12 Recommended Operating Conditions

13 DC Characteristics (3.3 V, 25 °C)

14 Reliability Qualifications

15 RF Power-Consumption Specifications

16 Wi-Fi Radio Characteristics

17 Receiver Characteristics – Basic Data Rate

18 Transmitter Characteristics – Basic Data Rate

19 Receiver Characteristics – Enhanced Data Rate

20 Transmitter Characteristics – Enhanced Data Rate

21 Receiver Characteristics – BLE

22 Transmitter Characteristics – BLE

23 ESP32 Ordering Information

24 Notes on ESP32 Pin Lists

25 GPIO_Matrix

26 Ethernet_MAC

List of Figures

1

2

3

4

5

6

7

8

9

Functional Block Diagram

5

6

ESP32 Pin Layout (QFN 6*6, Top View)

ESP32 Pin Layout (QFN 5*5, Top View)

ESP32 Power Scheme

7

11

14

16

42

43

ESP32 Power-up and Reset Timing

Setup and Hold Times for the Strapping Pin

Address Mapping Structure

QFN48 (6x6 mm) Package

QFN48 (5x5 mm) Package

10 ESP32 Part Number

1. Overview

ESP32 is a single 2.4 GHz Wi-Fi-and-Bluetooth combo chip designed with the TSMC ultra-low-power 40 nm

technology. It is designed to achieve the best power and RF performance, showing robustness, versatility and

reliability in a wide variety of applications and power scenarios.

The ESP32 series of chips includes ESP32-D0WD-V3, ESP32-D0WDQ6-V3, ESP32-D0WD, ESP32-D0WDQ6,

ESP32-D2WD, ESP32-S0WD, and ESP32-U4WDH, among which, ESP32-D0WD-V3, ESP32-D0WDQ6-V3, and

ESP32-U4WDH are based on ECO V3 wafer.

For details on part numbers and ordering information, please refer to Section 7.

For details on ECO V3 instructions, please refer to ESP32 ECO V3 User Guide.

1.1 Featured Solutions

1.1.1 Ultra-Low-Power Solution

ESP32 is designed for mobile, wearable electronics, and Internet-of-Things (IoT) applications. It features all the

state-of-the-art characteristics of low-power chips, including fine-grained clock gating, multiple power modes, and

dynamic power scaling. For instance, in a low-power IoT sensor hub application scenario, ESP32 is woken up

periodically and only when a specified condition is detected. Low-duty cycle is used to minimize the amount of

energy that the chip expends. The output of the power amplifier is also adjustable, thus contributing to an optimal

trade-off between communication range, data rate and power consumption.

Note:

For more information, refer to Section 3.7 RTC and Low-Power Management.

1.1.2 Complete Integration Solution

ESP32 is a highly-integrated solution for Wi-Fi-and-Bluetooth IoT applications, with around 20 external com-

ponents. ESP32 integrates an antenna switch, RF balun, power amplifier, low-noise receive amplifier, filters,

and power management modules. As such, the entire solution occupies minimal Printed Circuit Board (PCB)

area.

ESP32 uses CMOS for single-chip fully-integrated radio and baseband, while also integrating advanced calibration

circuitries that allow the solution to remove external circuit imperfections or adjust to changes in external condi-

tions. As such, the mass production of ESP32 solutions does not require expensive and specialized Wi-Fi testing

equipment.

1.2 Wi-Fi Key Features

• 802.11 b/g/n

• 802.11 n (2.4 GHz), up to 150 Mbps

• WMM

• TX/RX A-MPDU, RX A-MSDU

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1. Overview

• Immediate Block ACK

• Defragmentation

• Automatic Beacon monitoring (hardware TSF)

• 4 × virtual Wi-Fi interfaces

• Simultaneous support for Infrastructure Station, SoftAP, and Promiscuous modes

Note that when ESP32 is in Station mode, performing a scan, the SoftAP channel will be changed.

• Antenna diversity

Note:

For more information, please refer to Section 3.5 Wi-Fi.

1.3 BT Key Features

• Compliant with Bluetooth v4.2 BR/EDR and BLE specifications

• Class-1, class-2 and class-3 transmitter without external power amplifier

• Enhanced Power Control

• +12 dBm transmitting power

• NZIF receiver with –94 dBm BLE sensitivity

• Adaptive Frequency Hopping (AFH)

• Standard HCI based on SDIO/SPI/UART

• High-speed UART HCI, up to 4 Mbps

• Bluetooth 4.2 BR/EDR BLE dual mode controller

• Synchronous Connection-Oriented/Extended (SCO/eSCO)

• CVSD and SBC for audio codec

• Bluetooth Piconet and Scatternet

• Multi-connections in Classic BT and BLE

• Simultaneous advertising and scanning

1.4 MCU and Advanced Features

1.4.1 CPU and Memory

• Xtensa^®single-/dual-core 32-bit LX6 microprocessor(s), up to 600 MIPS (200 MIPS for ESP32-S0WD/ESP32-

U4WDH, 400 MIPS for ESP32-D2WD)

• 448 KB ROM

• 520 KB SRAM

• 16 KB SRAM in RTC

• QSPI supports multiple flash/SRAM chips

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1. Overview

1.4.2 Clocks and Timers

• Internal 8 MHz oscillator with calibration

• Internal RC oscillator with calibration

• External 2 MHz ~ 60 MHz crystal oscillator (40 MHz only for Wi-Fi/BT functionality)

• External 32 kHz crystal oscillator for RTC with calibration

• Two timer groups, including 2 × 64-bit timers and 1 × main watchdog in each group

• One RTC timer

• RTC watchdog

1.4.3 Advanced Peripheral Interfaces

• 34 × programmable GPIOs

• 12-bit SAR ADC up to 18 channels

• 2 × 8-bit DAC

• 10 × touch sensors

• 4 × SPI

• 2 × I²S

• 2 × I²C

• 3 × UART

• 1 host (SD/eMMC/SDIO)

• 1 slave (SDIO/SPI)

• Ethernet MAC interface with dedicated DMA and IEEE 1588 support

• CAN 2.0

• IR (TX/RX)

• Motor PWM

• LED PWM up to 16 channels

• Hall sensor

1.4.4 Security

• Secure boot

• Flash encryption

• 1024-bit OTP, up to 768-bit for customers

• Cryptographic hardware acceleration:

– AES

– Hash (SHA-2)

– RSA

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1. Overview

– ECC

– Random Number Generator (RNG)

1.5 Applications (A Non-exhaustive List)

• Generic Low-power IoT Sensor Hub

– Agriculture robotics

• Generic Low-power IoT Data Loggers

• Cameras for Video Streaming

• Over-the-top (OTT) Devices

• Speech Recognition

• Image Recognition

• Mesh Network

• Audio Applications

– Internet music players

– Live streaming devices

– Internet radio players

– Audio headsets

• Health Care Applications

– Health monitoring

– Baby monitors

• Home Automation

– Light control

– Smart plugs

• Wi-Fi-enabled Toys

– Remote control toys

– Proximity sensing toys

– Educational toys

– Smart door locks

• Smart Building

– Smart lighting

– Energy monitoring

• Industrial Automation

– Industrial wireless control

– Industrial robotics

• Smart Agriculture

• Wearable Electronics

– Smart watches

– Smart bracelets

• Retail & Catering Applications

– POS machines

– Smart greenhouses

– Smart irrigation

– Service robots

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1. Overview

1.6 Block Diagram

Embedded Flash

Bluetooth

link

controller

Bluetooth

baseband

RF

receive

SPI

I2C

Clock

generator

Wi-Fi

baseband

Wi-Fi MAC

RF

transmit

I2S

SDIO

UART

CAN

Core and memory

Cryptographic hardware

acceleration

2 ꢀor 1ꢁ x Xtensa® 32-

bit LX6 Microprocessors

SHA

AES

RSA

RNG

ETH

ROM

SRAM

IR

PWM

Touch sensor

DAC

RTC

ULP

co-processor

Recovery

memory

PMU

ADC

Figure 1: Functional Block Diagram

Note:

Products in the ESP32 series differ from each other in terms of their support for embedded flash and the number of CPUs

they have. For details, please refer to Section 7 Part Number and Ordering Information.

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2. Pin Deﬁnitions

2. Pin Definitions

2.1 Pin Layout

VDDA

LNA_IN

1

2

3

4

5

6

7

8

9

36 GPIO23

35 GPIO18

VDD3P3

34 GPIO5

VDD3P3

33 SD_DATA_1

32 SD_DATA_0

31 SD_CLK

30 SD_CMD

29 SD_DATA_3

28 SD_DATA_2

27 GPIO17

SENSOR_VP

SENSOR_CAPP

SENSOR_CAPN

SENSOR_VN

CHIP_PU

ESP32

49 GND

VDET_1 10

VDET_2 11

32K_XP 12

26 VDD_SDIO

25 GPIO16

Figure 2: ESP32 Pin Layout (QFN 6*6, Top View)

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2. Pin Deﬁnitions

VDDA

LNA_IN

1

2

3

4

5

6

7

8

9

38 GPIO19

37 VDD3P3_CPU

36 GPIO23

VDD3P3

35 GPIO18

SENSOR_VP

34 GPIO5

SENSOR_CAPP

SENSOR_CAPN

SENSOR_VN

CHIP_PU

33 SD_DATA_1

32 SD_DATA_0

31 SD_CLK

30 SD_CMD

29 SD_DATA_3

28 SD_DATA_2

27 GPIO17

ESP32

49 GND

VDET_1 10

VDET_2 11

32K_XP 12

32K_XN 13

GPIO25 14

26 VDD_SDIO

25 GPIO16

Figure 3: ESP32 Pin Layout (QFN 5*5, Top View)

Note:

For details on ESP32’s part numbers and the corresponding packaging, please refer to Section 7 Part Number and Ordering

Information.

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2. Pin Deﬁnitions

2.3 Power Scheme

ESP32’s digital pins are divided into three different power domains:

• VDD3P3_RTC

• VDD3P3_CPU

• VDD_SDIO

VDD3P3_RTC is also the input power supply for RTC and CPU.

VDD3P3_CPU is also the input power supply for CPU.

VDD_SDIO connects to the output of an internal LDO whose input is VDD3P3_RTC. When VDD_SDIO is connected

to the same PCB net together with VDD3P3_RTC, the internal LDO is disabled automatically. The power scheme

diagram is shown below:

VDD3P3_RTC

VDD3P3_CPU

1.8 V

LDO

1.1 V

LDO

1.1 V

VDD_SDIO

3.3 V/1.8 V

SDIO

Domain

RTC

CPU

Domain

Figure 4: ESP32 Power Scheme

The internal LDO can be configured as having 1.8 V, or the same voltage as VDD3P3_RTC. It can be powered off

via software to minimize the current of flash/SRAM during the Deep-sleep mode.

Notes on CHIP_PU:

• The illustration below shows the ESP32 power-up and reset timing. Details about the parameters are listed

in Table 2.

t

0

1

VDD3P3_RTC Min

VDD

V_{IL_nRST}

CHIP_PU

Figure 5: ESP32 Power-up and Reset Timing

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2. Pin Deﬁnitions

Table 2: Description of ESP32 Power-up and Reset Timing Parameters

Parameters

t₀

Description

Min.

Unit

Time between the 3.3 V rails being brought up and CHIP_PU being

activated

50

µs

Duration of CHIP_PU signal level < V_{IL_nRST}(refer to its value in

Table 13 DC Characteristics) to reset the chip

t₁

µs

• In scenarios where ESP32 is powered on and off repeatedly by switching the power rails, while there is a

large capacitor on the VDD33 rail and CHIP_PU and VDD33 are connected, simply switching off the CHIP_PU

power rail and immediately switching it back on may cause an incomplete power discharge cycle and failure

to reset the chip adequately.

An additional discharge circuit may be required to accelerate the discharge of the large capacitor on rail

VDD33, which will ensure proper power-on-reset when the ESP32 is powered up again. Please find the

discharge circuit in Figure ESP32-WROOM-32 Peripheral Schematics, in ESP32-WROOM-32 Datasheet.

• When a battery is used as the power supply for the ESP32 series of chips and modules, a supply voltage

supervisor is recommended, so that a boot failure due to low voltage is avoided. Users are recommended

to pull CHIP_PU low if the power supply for ESP32 is below 2.3 V. For the reset circuit, please refer to Figure

ESP32-WROOM-32 Peripheral Schematics, in ESP32-WROOM-32 Datasheet.

Notes on power supply:

• The operating voltage of ESP32 ranges from 2.3 V to 3.6 V. When using a single-power supply, the recom-

mended voltage of the power supply is 3.3 V, and its recommended output current is 500 mA or more.

• When VDD_SDIO 1.8 V is used as the power supply for external flash/PSRAM, a 2-kohm grounding resistor

should be added to VDD_SDIO. For the circuit design, please refer to Figure ESP32-WROVER Schematics,

in ESP32-WROVER Datasheet.

• When the three digital power supplies are used to drive peripherals, e.g., 3.3 V flash, they should comply

with the peripherals’ specifications.

2.4 Strapping Pins

There are five strapping pins:

• MTDI

• GPIO0

• GPIO2

• MTDO

• GPIO5

Software can read the values of these five bits from register ”GPIO_STRAPPING”.

During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches

of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip

is powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of

VDD_SDIO and other initial system settings.

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2. Pin Deﬁnitions

Each strapping pin is connected to its internal pull-up/pull-down during the chip reset. Consequently, if a strapping

pin is unconnected or the connected external circuit is high-impedance, the internal weak pull-up/pull-down will

determine the default input level of the strapping pins.

To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host

MCU’s GPIOs to control the voltage level of these pins when powering on the chip.

After reset release, the strapping pins work as normal-function pins.

Refer to Table 3 for a detailed boot-mode configuration by strapping pins.

Table 3: Strapping Pins

Voltage of Internal LDO (VDD_SDIO)

Default

3.3 V

0

1.8 V

1

MTDI

Pull-down

Booting Mode

SPI Boot

1

Default

Pull-up

Download Boot

GPIO0

0

GPIO2 Pull-down

Don’t-care

Enabling/Disabling Debugging Log Print over U0TXD During Booting

Default

Pull-up

U0TXD Active

U0TXD Silent

0

MTDO

1

Timing of SDIO Slave

FE Sampling FE Sampling RE Sampling RE Sampling

Default

Pull-up

FE Output

RE Output

FE Output

RE Output

MTDO

GPIO5

0

1

0

1

Note:

• FE: falling-edge, RE: rising-edge.

• Firmware can configure register bits to change the settings of “Voltage of Internal LDO (VDD_SDIO)” and “Timing

of SDIO Slave”, after booting.

• For ESP32 chips that contain an embedded flash, users need to note the logic level of MTDI. For example, ESP32-

D2WD contains an embedded flash that operates at 1.8 V, therefore, the MTDI should be pulled high. ESP32-

U4WDH contains an embedded flash that operates at 3.3 V, therefore, the MTDI should be low.

The illustration below shows the setup and hold times for the strapping pin before and after the CHIP_PU signal

goes high. Details about the parameters are listed in Table 4.

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2. Pin Deﬁnitions

t

0

1

V_{IL_nRST}

CHIP_PU

V_IH

Strapping pin

Figure 6: Setup and Hold Times for the Strapping Pin

Table 4: Parameter Descriptions of Setup and Hold Times for the Strapping Pin

Parameters

Description

Min.

0

Unit

ms

t₀

t₁

Setup time before CHIP_PU goes from low to high

Hold time after CHIP_PU goes high

1

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3. Functional Description

This chapter describes the functions integrated in ESP32.

3.1 CPU and Memory

3.1.1 CPU

ESP32 contains one or two low-power Xtensa^®32-bit LX6 microprocessor(s) with the following features:

• 7-stage pipeline to support the clock frequency of up to 240 MHz (160 MHz for ESP32-S0WD, ESP32-

D2WD, and ESP32-U4WDH)

• 16/24-bit Instruction Set provides high code-density

• Support for Floating Point Unit

• Support for DSP instructions, such as a 32-bit multiplier, a 32-bit divider, and a 40-bit MAC

• Support for 32 interrupt vectors from about 70 interrupt sources

The single-/dual-CPU interfaces include:

• Xtensa RAM/ROM Interface for instructions and data

• Xtensa Local Memory Interface for fast peripheral register access

• External and internal interrupt sources

• JTAG for debugging

3.1.2 Internal Memory

ESP32’s internal memory includes:

• 448 KB of ROM for booting and core functions

• 520 KB of on-chip SRAM for data and instructions

• 8 KB of SRAM in RTC, which is called RTC FAST Memory and can be used for data storage; it is accessed

by the main CPU during RTC Boot from the Deep-sleep mode.

• 8 KB of SRAM in RTC, which is called RTC SLOW Memory and can be accessed by the co-processor during

the Deep-sleep mode.

• 1 Kbit of eFuse: 256 bits are used for the system (MAC address and chip configuration) and the remaining

768 bits are reserved for customer applications, including flash-encryption and chip-ID.

• Embedded flash

Note:

Products in the ESP32 series differ from each other, in terms of their support for embedded flash and the size of it. For

details, please refer to Section 7 Part Number and Ordering Information.

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3. Functional Description

3.1.3 External Flash and SRAM

ESP32 supports multiple external QSPI flash and SRAM chips. More details can be found in Chapter SPI in

the ESP32 Technical Reference Manual. ESP32 also supports hardware encryption/decryption based on AES to

protect developers’ programs and data in flash.

ESP32 can access the external QSPI flash and SRAM through high-speed caches.

• Up to 16 MB of external flash can be mapped into CPU instruction memory space and read-only memory

space simultaneously.

– When external flash is mapped into CPU instruction memory space, up to 11 MB + 248 KB can be

mapped at a time. Note that if more than 3 MB + 248 KB are mapped, cache performance will be

reduced due to speculative reads by the CPU.

– When external flash is mapped into read-only data memory space, up to 4 MB can be mapped at a

time. 8-bit, 16-bit and 32-bit reads are supported.

• External SRAM can be mapped into CPU data memory space. SRAM up to 8 MB is supported and up to 4

MB can be mapped at a time. 8-bit, 16-bit and 32-bit reads and writes are supported.

Note:

After ESP32 is initialized, firmware can customize the mapping of external SRAM or flash into the CPU address space.

3.1.4 Memory Map

The structure of address mapping is shown in Figure 7. The memory and peripheral mapping of ESP32 is shown

in Table 5.

Figure 7: Address Mapping Structure

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3. Functional Description

Table 5: Memory and Peripheral Mapping

End Address

Category

Target

SPI2

Start Address

0x3FF6_4000

0x3FF6_5000

0x3FF6_6000

0x3FF6_7000

0x3FF6_8000

0x3FF6_9000

0x3FF6_C000

0x3FF6_D000

0x3FF6_E000

0x3FF6_F000

0x3FF7_0000

0x3FF7_5000

End Address

0x3FF6_4FFF

0x3FF6_5FFF

0x3FF6_6FFF

0x3FF6_7FFF

0x3FF6_8FFF

0x3FF6_AFFF

0x3FF6_CFFF

0x3FF6_DFFF

0x3FF6_EFFF

0x3FF6_FFFF

0x3FF7_0FFF

0x3FF7_5FFF

Size

4 KB

8 KB

4 KB

SPI3

SYSCON

I2C1

SDMMC

EMAC

PWM1

I2S1

Peripheral

UART2

PWM2

PWM3

RNG

3.2 Timers and Watchdogs

3.2.1 64-bit Timers

There are four general-purpose timers embedded in the chip. They are all 64-bit generic timers which are based

on 16-bit prescalers and 64-bit auto-reload-capable up/down-timers.

The timers feature:

• A 16-bit clock prescaler, from 2 to 65536

• A 64-bit timer

• Configurable up/down timer: incrementing or decrementing

• Halt and resume of time-base counter

• Auto-reload at alarming

• Software-controlled instant reload

• Level and edge interrupt generation

3.2.2 Watchdog Timers

The chip has three watchdog timers: one in each of the two timer modules (called the Main Watchdog Timer,

or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). These watchdog timers are

intended to recover from an unforeseen fault causing the application program to abandon its normal sequence. A

watchdog timer has four stages. Each stage may trigger one of three or four possible actions upon the expiry of

its programmed time period, unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, core

reset, and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip, including

the RTC itself. A timeout value can be set for each stage individually.

During flash boot the RWDT and the first MWDT start automatically in order to detect, and recover from, booting

problems.

The watchdogs have the following features:

• Four stages, each of which can be configured or disabled separately

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• A programmable time period for each stage

• One of three or four possible actions (interrupt, CPU reset, core reset, and system reset) upon the expiry of

each stage

• 32-bit expiry counter

• Write protection that prevents the RWDT and MWDT configuration from being inadvertently altered

• SPI flash boot protection

If the boot process from an SPI flash does not complete within a predetermined time period, the watchdog

will reboot the entire system.

3.3 System Clocks

3.3.1 CPU Clock

Upon reset, an external crystal clock source is selected as the default CPU clock. The external crystal clock source

also connects to a PLL to generate a high-frequency clock (typically 160 MHz).

In addition, ESP32 has an internal 8 MHz oscillator. The application can select the clock source from the external

crystal clock source, the PLL clock or the internal 8 MHz oscillator. The selected clock source drives the CPU

clock directly, or after division, depending on the application.

3.3.2 RTC Clock

The RTC clock has five possible sources:

• external low-speed (32 kHz) crystal clock

• external crystal clock divided by 4

• internal RC oscillator (typically about 150 kHz, and adjustable)

• internal 8 MHz oscillator

• internal 31.25 kHz clock (derived from the internal 8 MHz oscillator divided by 256)

When the chip is in the normal power mode and needs faster CPU accessing, the application can choose the

external high-speed crystal clock divided by 4 or the internal 8 MHz oscillator. When the chip operates in the

low-power mode, the application chooses the external low-speed (32 kHz) crystal clock, the internal RC clock or

the internal 31.25 kHz clock.

3.3.3 Audio PLL Clock

The audio clock is generated by the ultra-low-noise fractional-N PLL. More details can be found in Chapter Reset

and Clock in the ESP32 Technical Reference Manual.

3.4 Radio

The radio module consists of the following blocks:

• 2.4 GHz receiver

• 2.4 GHz transmitter

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• bias and regulators

• balun and transmit-receive switch

• clock generator

3.4.1 2.4 GHz Receiver

The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them

to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,

RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits and baseband filters are integrated in the

chip.

3.4.2 2.4 GHz Transmitter

The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the an-

tenna with a high-powered Complementary Metal Oxide Semiconductor (CMOS) power amplifier. The use of digital

calibration further improves the linearity of the power amplifier, enabling state-of-the-art performance in delivering

up to +20.5 dBm of power for an 802.11b transmission and +18 dBm for an 802.11n transmission.

Additional calibrations are integrated to cancel any radio imperfections, such as:

• Carrier leakage

• I/Q phase matching

• Baseband nonlinearities

• RF nonlinearities

• Antenna matching

These built-in calibration routines reduce the amount of time required for product testing, and render the testing

equipment unnecessary.

3.4.3 Clock Generator

The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All

components of the clock generator are integrated into the chip, including all inductors, varactors, filters, regulators

and dividers.

The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are

optimized on-chip with patented calibration algorithms which ensure the best performance of the receiver and the

transmitter.

3.5 Wi-Fi

ESP32 implements a TCP/IP and full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS)

STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled with

minimal host interaction to minimize the active-duty period.

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3.5.1 Wi-Fi Radio and Baseband

The ESP32 Wi-Fi Radio and Baseband support the following features:

• 802.11b/g/n

• 802.11n MCS0-7 in both 20 MHz and 40 MHz bandwidth

• 802.11n MCS32 (RX)

• 802.11n 0.4 µs guard-interval

• up to 150 Mbps of data rate

• Receiving STBC 2×1

• Up to 20.5 dBm of transmitting power

• Adjustable transmitting power

• Antenna diversity

ESP32 supports antenna diversity with an external RF switch. One or more GPIOs control the RF switch and

selects the best antenna to minimize the effects of channel fading.

3.5.2 Wi-Fi MAC

The ESP32 Wi-Fi MAC applies low-level protocol functions automatically. They are as follows:

• 4 × virtual Wi-Fi interfaces

• Simultaneous Infrastructure BSS Station mode/SoftAP mode/Promiscuous mode

• RTS protection, CTS protection, Immediate Block ACK

• Defragmentation

• TX/RX A-MPDU, RX A-MSDU

• TXOP

• WMM

• CCMP (CBC-MAC, counter mode), TKIP (MIC, RC4), WAPI (SMS4), WEP (RC4) and CRC

• Automatic beacon monitoring (hardware TSF)

3.6 Bluetooth

The chip integrates a Bluetooth link controller and Bluetooth baseband, which carry out the baseband protocols

and other low-level link routines, such as modulation/demodulation, packet processing, bit stream processing,

frequency hopping, etc.

3.6.1 Bluetooth Radio and Baseband

The Bluetooth Radio and Baseband support the following features:

• Class-1, class-2 and class-3 transmit output powers, and a dynamic control range of up to 24 dB

• π/4 DQPSK and 8 DPSK modulation

• High performance in NZIF receiver sensitivity with over 94 dBm of dynamic range

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• Class-1 operation without external PA

• Internal SRAM allows full-speed data-transfer, mixed voice and data, and full piconet operation

• Logic for forward error correction, header error control, access code correlation, CRC, demodulation, en-

cryption bit stream generation, whitening and transmit pulse shaping

• ACL, SCO, eSCO and AFH

• A-law, µ-law and CVSD digital audio CODEC in PCM interface

• SBC audio CODEC

• Power management for low-power applications

• SMP with 128-bit AES

3.6.2 Bluetooth Interface

• Provides UART HCI interface, up to 4 Mbps

• Provides SDIO / SPI HCI interface

• Provides PCM / I²S audio interface

3.6.3 Bluetooth Stack

The Bluetooth stack of the chip is compliant with the Bluetooth v4.2 BR/EDR and Bluetooth LE specifications.

3.6.4 Bluetooth Link Controller

The link controller operates in three major states: standby, connection and sniff. It enables multiple connections,

and other operations, such as inquiry, page, and secure simple-pairing, and therefore enables Piconet and Scat-

ternet. Below are the features:

• Classic Bluetooth

– Device Discovery (inquiry, and inquiry scan)

– Connection establishment (page, and page scan)

– Multi-connections

– Asynchronous data reception and transmission

– Synchronous links (SCO/eSCO)

– Master/Slave Switch

– Adaptive Frequency Hopping and Channel assessment

– Broadcast encryption

– Authentication and encryption

– Secure Simple-Pairing

– Multi-point and scatternet management

– Sniff mode

– Connectionless Slave Broadcast (transmitter and receiver)

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– Enhanced power control

– Ping

• Bluetooth Low Energy

– Advertising

– Scanning

– Simultaneous advertising and scanning

– Multiple connections

– Asynchronous data reception and transmission

– Adaptive Frequency Hopping and Channel assessment

– Connection parameter update

– Data Length Extension

– Link Layer Encryption

– LE Ping

3.7 RTC and Low-Power Management

With the use of advanced power-management technologies, ESP32 can switch between different power modes.

• Power modes

– Active mode: The chip radio is powered on. The chip can receive, transmit, or listen.

– Modem-sleep mode: The CPU is operational and the clock is configurable. The Wi-Fi/Bluetooth base-

band and radio are disabled.

– Light-sleep mode: The CPU is paused. The RTC memory and RTC peripherals, as well as the ULP

co-processor are running. Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake

up the chip.

– Deep-sleep mode: Only the RTC memory and RTC peripherals are powered on. Wi-Fi and Bluetooth

connection data are stored in the RTC memory. The ULP co-processor is functional.

– Hibernation mode: The internal 8-MHz oscillator and ULP co-processor are disabled. The RTC recovery

memory is powered down. Only one RTC timer on the slow clock and certain RTC GPIOs are active.

The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode.

Table 6: Power Consumption by Power Modes

Power mode

Description

Wi-Fi Tx packet

Power consumption

Please refer to

Active (RF working)

Wi-Fi/BT Tx packet

Wi-Fi/BT Rx and listening

Table 15 for details.

*

Dual-core chip(s)

30 mA ~ 68 mA

N/A

240 MHz

160 MHz

Single-core chip(s)

Dual-core chip(s)

Single-core chip(s)

Dual-core chip(s)

The CPU is

*

27 mA ~ 44 mA

27 mA ~ 34 mA

20 mA ~ 31 mA

Modem-sleep

powered on.

Normal speed: 80 MHz

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Power mode

Light-sleep

Deep-sleep

Description

-

Power consumption

20 mA ~ 25 mA

0.8 mA

Single-core chip(s)

The ULP co-processor is powered on.

ULP sensor-monitored pattern

150 µA

100 µA @1% duty

10 µA

RTC timer + RTC memory

Hibernation

Power off

RTC timer only

5 µA

CHIP_PU is set to low level, the chip is powered off.

1 µA

Note:

• * Among the ESP32 series of SoCs, ESP32-D0WD-V3, ESP32-D0WDQ6-V3, ESP32-D0WD, and ESP32-D0WDQ6

have a maximum CPU frequency of 240 MHz, ESP32-D2WD, ESP32-S0WD, and ESP32-U4WDH have a maximum

CPU frequency of 160 MHz.

• When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, power consumption

changes accordingly.

• In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU load and

the peripherals used.

• During Deep-sleep, when the ULP co-processor is powered on, peripherals such as GPIO and I²C are able to

operate.

• When the system works in the ULP sensor-monitored pattern, the ULP co-processor works with the ULP sensor

periodically and the ADC works with a duty cycle of 1%, so the power consumption is 100 µA.

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4.1 Descriptions of Peripherals and Sensors

4.1.1 General Purpose Input / Output Interface (GPIO)

ESP32 has 34 GPIO pins which can be assigned various functions by programming the appropriate registers.

There are several kinds of GPIOs: digital-only, analog-enabled, capacitive-touch-enabled, etc. Analog-enabled

GPIOs and Capacitive-touch-enabled GPIOs can be configured as digital GPIOs.

Most of the digital GPIOs can be configured as internal pull-up or pull-down, or set to high impedance. When

configured as an input, the input value can be read through the register. The input can also be set to edge-trigger

or level-trigger to generate CPU interrupts. Most of the digital IO pins are bi-directional, non-inverting and tristate,

including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as

the SDIO, UART, SPI, etc. (More details can be found in the Appendix, Table IO_MUX.) For low-power operations,

the GPIOs can be set to hold their states.

4.1.2 Analog-to-Digital Converter (ADC)

ESP32 integrates 12-bit SAR ADCs and supports measurements on 18 channels (analog-enabled pins). The ULP-

coprocessor in ESP32 is also designed to measure voltage, while operating in the sleep mode, which enables

low-power consumption. The CPU can be woken up by a threshold setting and/or via other triggers.

With appropriate settings, the ADCs can be configured to measure voltage on 18 pins maximum.

Table 7 describes the ADC characteristics.

Table 7: ADC Characteristics

Parameter

Description

Min Max Unit

RTC controller; ADC connected to an

external 100 nF capacitor; DC signal input;

ambient temperature at 25 °C;

Wi-Fi&BT off

DNL (Differential nonlinearity)

–7

7

LSB

INL (Integral nonlinearity)

Sampling rate

–12

12 LSB

RTC controller

-

200 ksps

DIG controller

2

Msps

Notes:

• When atten=3 and the measurement result is above 3000 (voltage at approx. 2450 mV), the ADC accuracy

will be worse than described in the table above.

• To get better DNL results, users can take multiple sampling tests with a filter, or calculate the average value.

• The input voltage range of GPIO pins within VDD3P3_RTC domain should strictly follow the DC characteristics

provided in Table 13. Otherwise, measurement errors may be introduced, and chip performance may be

affected.

By default, there are ±6% differences in measured results between chips. ESP-IDF provides couple of calibration

methods for ADC1. Results after calibration using eFuse Vref value are shown in Table 8. For higher accuracy,

users may apply other calibration methods provided in ESP-IDF, or implement their own.

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Table 8: ADC Calibration Results

Parameter

Total error

Description

Min Max Unit

Atten=0, effective measurement range of 100 ∼ 950 mV

Atten=1, effective measurement range of 100 ∼ 1250 mV

Atten=2, effective measurement range of 150 ∼ 1750 mV

Atten=3, effective measurement range of 150 ∼ 2450 mV

–23

–30

–40

–60

23 mV

30 mV

40 mV

60 mV

4.1.3 Hall Sensor

ESP32 integrates a Hall sensor based on an N-carrier resistor. When the chip is in the magnetic field, the Hall

sensor develops a small voltage laterally on the resistor, which can be directly measured by the ADC.

4.1.4 Digital-to-Analog Converter (DAC)

Two 8-bit DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The

design structure is composed of integrated resistor strings and a buffer. This dual DAC supports power supply as

input voltage reference. The two DAC channels can also support independent conversions.

4.1.5 Touch Sensor

ESP32 has 10 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the GPIOs

with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit allow relatively

small pads to be used. Arrays of pads can also be used, so that a larger area or more points can be detected.

The 10 capacitive-sensing GPIOs are listed in Table 9.

Table 9: Capacitive-Sensing GPIOs Available on ESP32

Capacitive-sensing signal name

Pin name

GPIO4

GPIO0

GPIO2

MTDO

MTCK

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

MTDI

MTMS

GPIO27

32K_XN

32K_XP

4.1.6 Ultra-Low-Power Co-processor

The ULP processor and RTC memory remain powered on during the Deep-sleep mode. Hence, the developer can

store a program for the ULP processor in the RTC slow memory to access the peripheral devices, internal timers

and internal sensors during the Deep-sleep mode. This is useful for designing applications where the CPU needs

to be woken up by an external event, or a timer, or a combination of the two, while maintaining minimal power

consumption.

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4.1.7 Ethernet MAC Interface

An IEEE-802.3-2008-compliant Media Access Controller (MAC) is provided for Ethernet LAN communications.

ESP32 requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber,

etc.). The PHY is connected to ESP32 through 17 signals of MII or nine signals of RMII. The following features are

supported on the Ethernet MAC (EMAC) interface:

• 10 Mbps and 100 Mbps rates

• Dedicated DMA controller allowing high-speed transfer between the dedicated SRAM and Ethernet MAC

• Tagged MAC frame (VLAN support)

• Half-duplex (CSMA/CD) and full-duplex operation

• MAC control sublayer (control frames)

• 32-bit CRC generation and removal

• Several address-filtering modes for physical and multicast address (multicast and group addresses)

• 32-bit status code for each transmitted or received frame

• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 512

words (32-bit)

• Hardware PTP (Precision Time Protocol) in accordance with IEEE 1588 2008 (PTP V2)

• 25 MHz/50 MHz clock output

4.1.8 SD/SDIO/MMC Host Controller

An SD/SDIO/MMC host controller is available on ESP32, which supports the following features:

• Secure Digital memory (SD mem Version 3.0 and Version 3.01)

• Secure Digital I/O (SDIO Version 3.0)

• Consumer Electronics Advanced Transport Architecture (CE-ATA Version 1.1)

• Multimedia Cards (MMC Version 4.41, eMMC Version 4.5 and Version 4.51)

The controller allows up to 80 MHz clock output in three different data-bus modes: 1-bit, 4-bit and 8-bit. It supports

two SD/SDIO/MMC4.41 cards in a 4-bit data-bus mode. It also supports one SD card operating at 1.8 V.

4.1.9 SDIO/SPI Slave Controller

ESP32 integrates an SD device interface that conforms to the industry-standard SDIO Card Specification Version

2.0, and allows a host controller to access the SoC, using the SDIO bus interface and protocol. ESP32 acts as the

slave on the SDIO bus. The host can access the SDIO-interface registers directly and can access shared memory

via a DMA engine, thus maximizing performance without engaging the processor cores.

The SDIO/SPI slave controller supports the following features:

• SPI, 1-bit SDIO, and 4-bit SDIO transfer modes over the full clock range from 0 to 50 MHz

• Configurable sampling and driving clock edge

• Special registers for direct access by host

• Interrupts to host for initiating data transfer

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• Automatic loading of SDIO bus data and automatic discarding of padding data

• Block size of up to 512 bytes

• Interrupt vectors between the host and the slave, allowing both to interrupt each other

• Supports DMA for data transfer

4.1.10 Universal Asynchronous Receiver Transmitter (UART)

ESP32 has three UART interfaces, i.e., UART0, UART1 and UART2, which provide asynchronous communication

(RS232 and RS485) and IrDA support, communicating at a speed of up to 5 Mbps. UART provides hardware

management of the CTS and RTS signals and software flow control (XON and XOFF). All of the interfaces can be

accessed by the DMA controller or directly by the CPU.

4.1.11 I²C Interface

ESP32 has two I²C bus interfaces which can serve as I²C master or slave, depending on the user’s configuration.

The I²C interfaces support:

• Standard mode (100 Kbit/s)

• Fast mode (400 Kbit/s)

• Up to 5 MHz, yet constrained by SDA pull-up strength

• 7-bit/10-bit addressing mode

• Dual addressing mode

Users can program command registers to control I²C interfaces, so that they have more flexibility.

4.1.12 I²S Interface

Two standard I²S interfaces are available in ESP32. They can be operated in master or slave mode, in full duplex

and half-duplex communication modes, and can be configured to operate with an 8-/16-/32-/48-/64-bit resolution

as input or output channels. BCK clock frequency, from 10 kHz up to 40 MHz, is supported. When one or

both of the I²S interfaces are configured in the master mode, the master clock can be output to the external

DAC/CODEC.

Both of the I²S interfaces have dedicated DMA controllers. PDM and BT PCM interfaces are supported.

4.1.13 Infrared Remote Controller

The infrared remote controller supports eight channels of infrared remote transmission and receiving. By program-

ming the pulse waveform, it supports various infrared protocols. Eight channels share a 512 x 32-bit block of

memory to store the transmitting or receiving waveform.

4.1.14 Pulse Counter

The pulse counter captures pulse and counts pulse edges through seven modes. It has eight channels, each of

which captures four signals at a time. The four input signals include two pulse signals and two control signals.

When the counter reaches a defined threshold, an interrupt is generated.

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4.1.15 Pulse Width Modulation (PWM)

The Pulse Width Modulation (PWM) controller can be used for driving digital motors and smart lights. The controller

consists of PWM timers, the PWM operator and a dedicated capture sub-module. Each timer provides timing in

synchronous or independent form, and each PWM operator generates a waveform for one PWM channel. The

dedicated capture sub-module can accurately capture events with external timing.

4.1.16 LED PWM

The LED PWM controller can generate 16 independent channels of digital waveforms with configurable periods

and duties.

The 16 channels of digital waveforms operate with an APB clock of 80 MHz. Eight of these channels have the

option of using the 8 MHz oscillator clock. Each channel can select a 20-bit timer with configurable counting range,

while its accuracy of duty can be up to 16 bits within a 1 ms period.

The software can change the duty immediately. Moreover, each channel automatically supports step-by-step duty

increase or decrease, which is useful for the LED RGB color-gradient generator.

4.1.17 Serial Peripheral Interface (SPI)

ESP32 features three SPIs (SPI, HSPI and VSPI) in slave and master modes in 1-line full-duplex and 1/2/4-line

half-duplex communication modes. These SPIs also support the following general-purpose SPI features:

• Four modes of SPI transfer format, which depend on the polarity (CPOL) and the phase (CPHA) of the SPI

clock

• Up to 80 MHz (The actual speed it can reach depends on the selected pads, PCB tracing, peripheral char-

acteristics, etc.)

• up to 64-byte FIFO

All SPIs can also be connected to the external flash/SRAM and LCD. Each SPI can be served by DMA con-

trollers.

4.1.18 Accelerator

ESP32 is equipped with hardware accelerators of general algorithms, such as AES (FIPS PUB 197), SHA (FIPS

PUB 180-4), RSA, and ECC, which support independent arithmetic, such as Big Integer Multiplication and Big

Integer Modular Multiplication. The maximum operation length for RSA, ECC, Big Integer Multiply and Big Integer

Modular Multiplication is 4096 bits.

The hardware accelerators greatly improve operation speed and reduce software complexity. They also support

code encryption and dynamic decryption, which ensures that code in the flash will not be hacked.

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4.2 Peripheral Pin Configurations

Table 10: Peripheral Pin Configurations

Interface

Signal

Function

ADC1_CH0

ADC1_CH1

ADC1_CH2

ADC1_CH3

ADC1_CH4

ADC1_CH5

ADC1_CH6

ADC1_CH7

ADC2_CH0

ADC2_CH1

ADC2_CH2

ADC2_CH3

ADC2_CH4

ADC2_CH5

ADC2_CH6

ADC2_CH7

ADC2_CH8

ADC2_CH9

DAC_1

SENSOR_VP

SENSOR_CAPP

SENSOR_CAPN

SENSOR_VN

32K_XP

32K_XN

VDET_1

VDET_2

GPIO4

ADC

Two 12-bit SAR ADCs

GPIO0

GPIO2

MTDO

MTCK

MTDI

MTMS

GPIO27

GPIO25

GPIO26

GPIO25

GPIO26

GPIO4

DAC

Two 8-bit DACs

DAC_2

TOUCH0

TOUCH1

TOUCH2

TOUCH3

TOUCH4

TOUCH5

TOUCH6

TOUCH7

TOUCH8

TOUCH9

MTDI

GPIO0

GPIO2

MTDO

MTCK

Touch Sensor

Capacitive touch sensors

MTDI

MTMS

GPIO27

32K_XN

32K_XP

MTDI

MTCK

JTAG

JTAG for software debugging

MTMS

MTDO

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Interface

Signal

Function

HS2_CLK

MTMS

MTDO

GPIO2

GPIO4

MTDI

HS2_CMD

SD/SDIO/MMC Host

Controller

HS2_DATA0

Supports SD memory card V3.01 standard

HS2_DATA1

HS2_DATA2

HS2_DATA3

MTCK

PWM0_OUT0~2

PWM1_OUT_IN0~2

PWM0_FLT_IN0~2

PWM1_FLT_IN0~2

PWM0_CAP_IN0~2

PWM1_CAP_IN0~2

PWM0_SYNC_IN0~2

PWM1_SYNC_IN0~2

SD_CLK

Three channels of 16-bit timers generate

PWM waveforms. Each channel has a pair

of output signals, three fault detection

signals, three event-capture signals, and

three sync signals.

Motor PWM

Any GPIO Pins

MTMS

MTDO

GPIO2

GPIO4

MTDI

SD_CMD

SDIO interface that conforms to the

industry standard SDIO 2.0 card

specification

SDIO/SPI Slave

Controller

SD_DATA0

SD_DATA1

SD_DATA2

SD_DATA3

MTCK

U0RXD_in

U0CTS_in

U0DSR_in

U0TXD_out

U0RTS_out

U0DTR_out

Two UART devices with hardware

flow-control and DMA

U1RXD_in

UART

Any GPIO Pins

U1CTS_in

U1TXD_out

U1RTS_out

U2RXD_in

U2CTS_in

U2TXD_out

U2RTS_out

I2CEXT0_SCL_in

I2CEXT0_SDA_in

I2CEXT1_SCL_in

I2CEXT1_SDA_in

I2CEXT0_SCL_out

I2CEXT0_SDA_out

I2CEXT1_SCL_out

I2CEXT1_SDA_out

I²C

Any GPIO Pins

Two I²C devices in slave or master mode

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Interface

Signal

Function

ledc_hs_sig_out0~7

ledc_ls_sig_out0~7

I2S0I_DATA_in0~15

I2S0O_BCK_in

I2S0O_WS_in

16 independent channels @80 MHz

clock/RTC CLK. Duty accuracy: 16 bits.

LED PWM

Any GPIO Pins

I2S0I_BCK_in

I2S0I_WS_in

I2S0I_H_SYNC

I2S0I_V_SYNC

I2S0I_H_ENABLE

I2S0O_BCK_out

I2S0O_WS_out

I2S0I_BCK_out

I2S0I_WS_out

Stereo input and output from/to the audio

codec; parallel LCD data output; parallel

camera data input

I2S0O_DATA_out0~23

I2S1I_DATA_in0~15

I2S1O_BCK_in

I2S1O_WS_in

I2S

Any GPIO Pins

I2S1I_BCK_in

I2S1I_WS_in

I2S1I_H_SYNC

I2S1I_V_SYNC

I2S1I_H_ENABLE

I2S1O_BCK_out

I2S1O_WS_out

I2S1I_BCK_out

I2S1I_WS_out

I2S1O_DATA_out0~23

RMT_SIG_IN0~7

RMT_SIG_OUT0~7

HSPIQ_in/_out

HSPID_in/_out

Infrared Remote

Controller

Eight channels for an IR transmitter and

receiver of various waveforms

Any GPIO Pins

Standard SPI consists of clock,

chip-select, MOSI and MISO. These SPIs

can be connected to LCD and other

external devices. They support the

following features:

HSPICLK_in/_out

HSPI_CS0_in/_out

HSPI_CS1_out

HSPI_CS2_out

VSPIQ_in/_out

General Purpose

SPI

Any GPIO Pins

• Both master and slave modes;

• Four sub-modes of the SPI transfer

format;

VSPID_in/_out

VSPICLK_in/_out

VSPI_CS0_in/_out

VSPI_CS1_out

VSPI_CS2_out

• Configurable SPI frequency;

• Up to 64 bytes of FIFO and DMA.

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4. Peripherals and Sensors

Interface

Signal

Function

SPIHD

SD_DATA_2

SD_DATA_3

SD_CMD

SD_CLK

SD_DATA_0

SD_DATA_1

MTMS

SPIWP

SPICS0

SPICLK

SPIQ

SPID

HSPICLK

HSPICS0

MTDO

Supports Standard SPI, Dual SPI, and

Quad SPI that can be connected to the

external flash and SRAM

HSPIQ

MTDI

Parallel QSPI

HSPID

MTCK

HSPIHD

GPIO4

HSPIWP

GPIO2

VSPICLK

GPIO18

GPIO5

VSPICS0

VSPIQ

GPIO19

GPIO23

GPIO21

GPIO22

GPIO0

VSPID

VSPIHD

VSPIWP

EMAC_TX_CLK

EMAC_RX_CLK

EMAC_TX_EN

EMAC_TXD0

EMAC_TXD1

EMAC_TXD2

EMAC_TXD3

EMAC_RX_ER

EMAC_RX_DV

EMAC_RXD0

EMAC_RXD1

EMAC_RXD2

EMAC_RXD3

EMAC_CLK_OUT

GPIO5

GPIO21

GPIO19

GPIO22

MTMS

MTDI

MTCK

GPIO27

GPIO25

GPIO26

U0TXD

MTDO

EMAC

Ethernet MAC with MII/RMII interface

GPIO16

EMAC_CLK_OUT_180 GPIO17

EMAC_TX_ER

GPIO4

EMAC_MDC_out

EMAC_MDI_in

Any GPIO Pins

EMAC_MDO_out

EMAC_CRS_out

EMAC_COL_out

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4. Peripherals and Sensors

Interface

Signal

Function

pcnt_sig_ch0_in0

pcnt_sig_ch1_in0

pcnt_ctrl_ch0_in0

pcnt_ctrl_ch1_in0

pcnt_sig_ch0_in1

pcnt_sig_ch1_in1

pcnt_ctrl_ch0_in1

pcnt_ctrl_ch1_in1

pcnt_sig_ch0_in2

pcnt_sig_ch1_in2

pcnt_ctrl_ch0_in2

pcnt_ctrl_ch1_in2

pcnt_sig_ch0_in3

pcnt_sig_ch1_in3

pcnt_ctrl_ch0_in3

pcnt_ctrl_ch1_in3

pcnt_sig_ch0_in4

pcnt_sig_ch1_in4

pcnt_ctrl_ch0_in4

pcnt_ctrl_ch1_in4

pcnt_sig_ch0_in5

pcnt_sig_ch1_in5

pcnt_ctrl_ch0_in5

pcnt_ctrl_ch1_in5

pcnt_sig_ch0_in6

pcnt_sig_ch1_in6

pcnt_ctrl_ch0_in6

pcnt_ctrl_ch1_in6

pcnt_sig_ch0_in7

pcnt_sig_ch1_in7

pcnt_ctrl_ch0_in7

pcnt_ctrl_ch1_in7

Operating in seven different modes, the

pulse counter captures pulse and counts

pulse edges.

Pulse Counter

Any GPIO Pins

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5. Electrical Characteristics

5.1 Absolute Maximum Ratings

Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the

device. These are stress ratings only, and do not refer to the functional operation of the device that should follow

the recommended operating conditions.

Table 11: Absolute Maximum Ratings

Symbol

Parameter

Min

Max Unit

3.6

VDDA, VDD3P3, VDD3P3_RTC, Voltage applied to power supply pins per

–0.3

V

VDD3P3_CPU, VDD_SDIO

I_output

T_store

power domain

*

Cumulative IO output current

Storage temperature

-

1200 mA

150 °C

–40

* The chip worked properly after a 24-hour test in ambient temperature at 25 °C, and the IOs in three domains (VDD3P3_RTC,

VDD3P3_CPU, VDD_SDIO) output high logic level to ground.

5.2 Recommended Operating Conditions

Table 12: Recommended Operating Conditions

Symbol

Parameter

Min Typ Max Unit

VDDA, VDD3P3_RTC ¹

VDD3P3, VDD_SDIO (3.3 V mode) ²power domain

Voltage applied to power supply pins per

2.3 3.3

1.8 3.3

3.6

V

VDD3P3_CPU

Voltage applied to power supply pin

3.6

-

V

A

I_{V DD}

T ³

Current delivered by external power supply

Operating temperature

0.5

-

–40

125 °C

1. When writing eFuse, VDD3P3_RTC should be at least 3.3 V.

2. • VDD_SDIO works as the power supply for the related IO, and also for an external device. Please refer to the Appendix

IO_MUX of this datasheet for more details.

• VDD_SDIO can be sourced internally by the ESP32 from the VDD3P3_RTC power domain:

– When VDD_SDIO operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 6 Ω resistor, therefore, there

will be some voltage drop from VDD3P3_RTC.

– When VDD_SDIO operates at 1.8 V, it can be generated from ESP32’s internal LDO. The maximum current this

LDO can offer is 40 mA, and the output voltage range is 1.65 V ~ 2.0 V.

• VDD_SDIO can also be driven by an external power supply.

• Please refer to Power Scheme, section 2.3, for more information.

3. The operating temperature of ESP32-D2WD and ESP32-U4WDH ranges from –40 °C to 105 °C, due to the flash em-

bedded in them. The other chips in this series have no embedded flash, so their range of operating temperatures is –40

°C ~ 125 °C.

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5. Electrical Characteristics

5.3 DC Characteristics (3.3 V, 25 °C)

Table 13: DC Characteristics (3.3 V, 25 °C)

Symbol

C_IN

V_IH

V_IL

Parameter Min Typ

Max Unit

Pin capacitance

-

2

-

VDD¹+0.3

0.25×VDD¹

pF

V

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

0.75×VDD¹

–0.3

V

I_IH

-

50 nA

I_IL

-

0.8×VDD¹

-

V_OH

V_OL

-

V

0.1×VDD¹

VDD3P3_CPU

power domain ^{1, 2}

VDD3P3_RTC

power domain ^{1, 2}

VDD_SDIO power

domain ^{1, 3}

High-level source current

(VDD¹= 3.3 V,

-

40

20

-

mA

I_OH

V_OH>= 2.64 V,

output drive strength set

to the maximum)

Low-level sink current

(VDD¹= 3.3 V, V_OL= 0.495 V,

I_OL

-

28

-

mA

output drive strength set to the maximum)

Resistance of internal pull-up resistor

Resistance of internal pull-down resistor

Low-level input voltage of CHIP_PU

to power off the chip

R_{P U}

R_{P D}

-

45

-

kΩ

V_{IL_nRST}

-

0.6

V

Notes:

1. Please see Table IO_MUX for IO’s power domain. VDD is the I/O voltage for a particular power domain of pins.

2. For VDD3P3_CPU and VDD3P3_RTC power domain, per-pin current sourced in the same domain is gradually reduced

from around 40 mA to around 29 mA, V_OH>=2.64 V, as the number of current-source pins increases.

3. For VDD_SDIO power domain, per-pin current sourced in the same domain is gradually reduced from around 30 mA to

around 10 mA, V_OH>=2.64 V, as the number of current-source pins increases.

5.4 Reliability Qualifications

Table 14: Reliability Qualifications

Reliability tests

Standards

Test conditions

±500 V, all pins

Result

Pass

Electro-Static Discharge Sensitivity

(ESD), Charge Device Mode (CDM) ¹

Electro-Static Discharge Sensitivity

(ESD), Human Body Mode (HBM) ²

JEDEC EIA/JESD22-C101

JEDEC EIA/JESD22-A114

JEDEC STANDARD NO.78

±1500 V, all pins

Pass

±50 mA ~ ±200 mA, room

temperature, test for IO

1.5 × Vmax, room temper-

ature, test for V_supply

Latch-up (Over-current test)

Latch-up (Over-voltage test)

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5. Electrical Characteristics

Reliability tests

Standards

Test conditions

Result

Pass

30 °C, 60% RH, 192

hours, IR × 3 @260 °C

Moisture Sensitivity Level (MSL)

J-STD-020, MSL 3

1. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

2. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

5.5 RF Power-Consumption Specifications

The power consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF

port. All transmitters’ measurements are based on a 50% duty cycle.

Table 15: RF Power-Consumption Specifications

Mode

Min

Typ Max Unit

Transmit 802.11b, DSSS 1 Mbps, POUT = +19.5 dBm

Transmit 802.11g, OFDM 54 Mbps, POUT = +16 dBm

Transmit 802.11n, OFDM MCS7, POUT = +14 dBm

Receive 802.11b/g/n

-

240

190

-

mA

180

95 ~ 100

130

Transmit BT/BLE, POUT = 0 dBm

Receive BT/BLE

95 ~ 100

5.6 Wi-Fi Radio

Table 16: Wi-Fi Radio Characteristics

Parameter

Condition

Min Typical

Max Unit

Operating frequency range ^note1

Output impedance ^note2

-

2412

-

note 2

13

2484 MHz

-

Ω

11n, MCS7

12

14 dBm

TX power ^note3

11b mode

18.5

19.5

–98

–88

–93

–75

–93

–73

–90

–70

27

20.5 dBm

11b, 1 Mbps

11b, 11 Mbps

11g, 6 Mbps

11g, 54 Mbps

11n, HT20, MCS0

11n, HT20, MCS7

11n, HT40, MCS0

11n, HT40, MCS7

11g, 6 Mbps

11g, 54 Mbps

11n, HT20, MCS0

11n, HT20, MCS7

-

dBm

dB

Sensitivity

13

dB

Adjacent channel rejection

27

dB

12

dB

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5. Electrical Characteristics

1. Device should operate in the frequency range allocated by regional regulatory authorities. Target operating frequency

range is configurable by software.

2. The typical value of ESP32’s Wi-Fi radio output impedance is different between chips in different QFN packages. For

ESP32 chips with a QFN 6×6 package, the value is 30+j10 Ω. For ESP32 chips with a QFN 5×5 package, the value is

35+j10 Ω.

3. Target TX power is configurable based on device or certification requirements.

5.7 Bluetooth Radio

5.7.1 Receiver – Basic Data Rate

Table 17: Receiver Characteristics – Basic Data Rate

Parameter

Conditions

Min Typ Max Unit

–90 –89 –88 dBm

Sensitivity @0.1% BER

Maximum received signal @0.1% BER

Co-channel C/I

-

0

-

+7

-

dBm

dB

-

F = F0 + 1 MHz

F = F0 – 1 MHz

F = F0 + 2 MHz

F = F0 – 2 MHz

F = F0 + 3 MHz

F = F0 – 3 MHz

30 MHz ~ 2000 MHz

2000 MHz ~ 2400 MHz

2500 MHz ~ 3000 MHz

3000 MHz ~ 12.5 GHz

-

–6 dB

-

–25 dB

–33 dB

–25 dB

–45 dB

Adjacent channel selectivity C/I

-

–10

–27

–10

–36

-

dBm

-

dBm

Out-of-band blocking performance

Intermodulation

-

5.7.2 Transmitter – Basic Data Rate

Table 18: Transmitter Characteristics – Basic Data Rate

Parameter

Conditions

Min

Typ Max Unit

RF transmit power (see note under Table 18)

Gain control step

-

0

3

-

dBm

dB

-

RF power control range

+20 dB bandwidth

-

–12

-

+9 dBm

-

0.9

–47

–55

–60

-

MHz

dBm

F = F0 ± 2 MHz

-

Adjacent channel transmit power

F = F0 ± 3 MHz

-

F = F0 ± > 3 MHz

-

∆ f1

∆ f2

ICFT

-

155 kHz

avg

133.7

-

kHz

-

max

/∆ f1

avg

-

0.92

–7

avg

kHz

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5. Electrical Characteristics

Parameter

Drift rate

Conditions

Min

Typ Max Unit

-

0.7

6

-

kHz/50 µs

kHz

Drift (DH1)

Drift (DH5)

6

kHz

Note:

There are a total of eight power levels from 0 to 7, and the transmit power ranges from –12 dBm to 9 dBm. When the

power level rises by 1, the transmit power increases by 3 dB. Power level 4 is used by default and the corresponding

transmit power is 0 dBm.

5.7.3 Receiver – Enhanced Data Rate

Table 19: Receiver Characteristics – Enhanced Data Rate

Parameter

Conditions

π/4 DQPSK

Min Typ Max Unit

Sensitivity @0.01% BER

Maximum received signal @0.01% BER

Co-channel C/I

-

–90 –89 –88 dBm

-

0

11

-

dBm

dB

-

F = F0 + 1 MHz

F = F0 – 1 MHz

F = F0 + 2 MHz

F = F0 – 2 MHz

F = F0 + 3 MHz

F = F0 – 3 MHz

–7

–25

–35

–25

–45

Adjacent channel selectivity C/I

8DPSK

Sensitivity @0.01% BER

Maximum received signal @0.01% BER

C/I c-channel

-

–84 –83 –82 dBm

-

–5

18

-

dBm

dB

-

F = F0 + 1 MHz

F = F0 – 1 MHz

F = F0 + 2 MHz

F = F0 – 2 MHz

F = F0 + 3 MHz

F = F0 – 3 MHz

2

–25

–38

Adjacent channel selectivity C/I

5.7.4 Transmitter – Enhanced Data Rate

Table 20: Transmitter Characteristics – Enhanced Data Rate

Parameter

Conditions

Min

Typ Max Unit

RF transmit power (see note under Table 18)

Gain control step

-

0

-

dBm

dB

3

-

RF power control range

π/4 DQPSK max w0

–12

-

+9 dBm

kHz

–0.72

-

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5. Electrical Characteristics

Parameter

Conditions

Min

-

Typ Max Unit

π/4 DQPSK max wi

π/4 DQPSK max |wi + w0|

8DPSK max w0

-

–6

–7.42

0.7

-

kHz

%

-

8DPSK max wi

-

–9.6

–10

4.28

100

13.3

5.8

8DPSK max |wi + w0|

π/4 DQPSK modulation accuracy

-

RMS DEVM

99% DEVM

Peak DEVM

RMS DEVM

99% DEVM

Peak DEVM

F = F0 ± 1 MHz

F = F0 ± 2 MHz

F = F0 ± 3 MHz

F = F0 +/– > 3 MHz

-

%

-

%

-

%

8 DPSK modulation accuracy

-

100

14

%

-

%

-

–46

–40

–46

-

dBm

-

In-band spurious emissions

EDR differential phase coding

-

–53 dBm

-

100

-

%

5.8 Bluetooth LE Radio

5.8.1 Receiver

Table 21: Receiver Characteristics – BLE

Parameter

Conditions

-

Min Typ Max Unit

–94 –93 –92 dBm

Sensitivity @30.8% PER

Maximum received signal @30.8% PER

Co-channel C/I

-

0

-

+10

–5

–25

–35

–25

–45

-

dBm

dB

-

F = F0 + 1 MHz

F = F0 – 1 MHz

F = F0 + 2 MHz

F = F0 – 2 MHz

F = F0 + 3 MHz

F = F0 – 3 MHz

30 MHz ~ 2000 MHz

-

dB

-

dB

-

dB

Adjacent channel selectivity C/I

-

dB

-

dB

–10

dBm

2000 MHz ~ 2400 MHz –27

2500 MHz ~ 3000 MHz –27

3000 MHz ~ 12.5 GHz –10

-

Out-of-band blocking performance

Intermodulation

-

–36

-

5.8.2 Transmitter

Table 22: Transmitter Characteristics – BLE

Parameter

Conditions

-

Min

-

Typ Max Unit

dBm

RF transmit power (see note under Table 18)

0

-

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5. Electrical Characteristics

Parameter

Conditions

Min

Typ Max Unit

Gain control step

RF power control range

-

3

-

dB

-

–12

+9 dBm

F = F0 ± 2 MHz

-

–52

–58

–60

-

dBm

Adjacent channel transmit power

F = F0 ± 3 MHz

-

F = F0 ± > 3 MHz

-

∆ f1

∆ f2

ICFT

-

265 kHz

avg

247

-

kHz

max

/∆ f1

avg

-

0.92

–10

0.7

2

-

avg

kHz

Drift rate

Drift

kHz/50 µs

kHz

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6. Package Information

Pin 1

Pin 2

Pin 3

Pin 1

Pin 2

Pin 3

Figure 8: QFN48 (6x6 mm) Package

3

2 1

Pin 1 Pin 2 Pin 3

Figure 9: QFN48 (5x5 mm) Package

Note:

The pins of the chip are numbered in an anti-clockwise direction from Pin 1 in the top view.

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7. Part Number and Ordering Information

ESP32

-

D

0

WD

H

Q6

V3

Wafer version 3

Package

Q6=QFN 6*6

N/A=QFN 5*5

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢆꢉꢊꢅꢋꢉꢆ

Connection

WD=Wi-Fi b/g/n + BT/BLE dual mode

Embedded ﬂash

0=No embedded ﬂash

2=2 MB ﬂash

4=4 MB ﬂash

Core

D=Dual core

Sꢀꢁ=Single core

Figure 10: ESP32 Part Number

The table below provides the ordering information of the ESP32 series of chips.

Table 23: ESP32 Ordering Information

Ordering code

Core

Embedded flash

Package

QFN 5*5

QFN 6*6

QFN 5*5

QFN 6*6

QFN 5*5

ESP32-D0WD-V3

ESP32-D0WDQ6-V3

ESP32-D0WD

Dual core

Single core

No embedded flash

ESP32-D0WDQ6

ESP32-D2WD

No embedded flash

2 MB embedded flash (40 MHz)

No embedded flash

ESP32-S0WD

ESP32-U4WDH

4 MB embedded flash (80 MHz)

Note: All above chips support Wi-Fi b/g/n + BT/BLE Dual Mode connection.

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8. Learning Resources

8.1 Must-Read Documents

Click on the following links to access documents related to ESP32.

• ESP32 ECO V3 User Guide

This document describes differences between V3 and previous ESP32 silicon wafer revisions.

• ECO and Workarounds for Bugs in ESP32

This document details hardware errata and workarounds in the ESP32.

• ESP-IDF Programming Guide

It hosts extensive documentation for ESP-IDF, ranging from hardware guides to API reference.

• ESP32 Technical Reference Manual

The manual provides detailed information on how to use the ESP32 memory and peripherals.

• ESP32 Hardware Resources

The zip files include schematics, PCB layout, Gerber and BOM list.

• ESP32 Hardware Design Guidelines

The guidelines provide recommended design practices when developing standalone or add-on systems

based on the ESP32 series of products, including the ESP32 chip, the ESP32 modules and development

boards.

• ESP32 AT Instruction Set and Examples

This document introduces the ESP32 AT commands, explains how to use them, and provides examples of

several common AT commands.

• Espressif Products Ordering Information

8.2 Must-Have Resources

Here are the ESP32-related must-have resources.

• ESP32 BBS

This is an Engineer-to-Engineer (E2E) Community for ESP32, where you can post questions, share knowl-

edge, explore ideas, and solve problems together with fellow engineers.

• ESP32 GitHub

ESP32 development projects are freely distributed under Espressif’s MIT license on GitHub. This channel

of communication has been established to help developers get started with ESP32 and encourage them to

share their knowledge of ESP32-related hardware and software.

• ESP32 Tools

This is a webpage where users can download ESP32 Flash Download Tools and the zip file ”ESP32 Certifi-

cation and Test”.

• ESP-IDF

This webpage links users to the official IoT development framework for ESP32.

• ESP32 Resources

This webpage provides the links to all available ESP32 documents, SDK and tools.

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Appendix A

Appendix A – ESP32 Pin Lists

A.1. Notes on ESP32 Pin Lists

Table 24: Notes on ESP32 Pin Lists

No.

1

Description

In Table IO_MUX, the boxes highlighted in yellow indicate the GPIO pins that are input-only.

Please see the following note for further details.

GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull-

up/pull-down circuitry. The pin names are: SENSOR_VP (GPIO36), SENSOR_CAPP (GPIO37),

SENSOR_CAPN (GPIO38), SENSOR_VN (GPIO39), VDET_1 (GPIO34), VDET_2 (GPIO35).

The pins are grouped into four power domains: VDDA (analog power supply), VDD3P3_RTC

(RTC power supply), VDD3P3_CPU (power supply of digital IOs and CPU cores), VDD_SDIO

(power supply of SDIO IOs). VDD_SDIO is the output of the internal SDIO-LDO. The voltage of

SDIO-LDO can be configured at 1.8 V or be the same as that of VDD3P3_RTC. The strapping

pin and eFuse bits determine the default voltage of the SDIO-LDO. Software can change the

voltage of the SDIO-LDO by configuring register bits. For details, please see the column “Power

Domain” in Table IO_MUX.

2

3

The functional pins in the VDD3P3_RTC domain are those with analog functions, including the

32 kHz crystal oscillator, ADC, DAC, and the capacitive touch sensor. Please see columns

“Analog Function 1~3” in Table IO_MUX.

4

5

These VDD3P3_RTC pins support the RTC function, and can work during Deep-sleep. For

example, an RTC-GPIO can be used for waking up the chip from Deep-sleep.

The GPIO pins support up to six digital functions, as shown in columns “Function 1~6” In Table

IO_MUX. The function selection registers will be set as “N-1”, where N is the function number.

Below are some definitions:

• SD_* is for signals of the SDIO slave.

• HS1_* is for Port 1 signals of the SDIO host.

• HS2_* is for Port 2 signals of the SDIO host.

6

• MT* is for signals of the JTAG.

• U0* is for signals of the UART0 module.

• U1* is for signals of the UART1 module.

• U2* is for signals of the UART2 module.

• SPI* is for signals of the SPI01 module.

• HSPI* is for signals of the SPI2 module.

• VSPI* is for signals of the SPI3 module.

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Appendix A

No.

Description

Each column about digital “Function” is accompanied by a column about “Type”. Please see

the following explanations for the meanings of “type” with respect to each “function” they are

associated with. For each “Function-N”, “type” signifies:

• I: input only. If a function other than “Function-N” is assigned, the input signal of

“Function-N” is still from this pin.

• I1: input only. If a function other than “Function-N” is assigned, the input signal of

“Function-N” is always “1”.

• I0: input only. If a function other than “Function-N” is assigned, the input signal of

“Function-N” is always “0”.

7

• O: output only.

• T: high-impedance.

• I/O/T: combinations of input, output, and high-impedance according to the function sig-

nal.

• I1/O/T: combinations of input, output, and high-impedance, according to the function

signal. If a function is not selected, the input signal of the function is “1”.

For example, pin 30 can function as HS1_CMD or SD_CMD, where HS1_CMD is of an “I1/O/T”

type. If pin 30 is selected as HS1_CMD, this pin’s input and output are controlled by the SDIO

host. If pin 30 is not selected as HS1_CMD, the input signal of the SDIO host is always “1”.

Each digital output pin is associated with its configurable drive strength. Column “Drive

Strength” in Table IO_MUX lists the default values. The drive strength of the digital output

pins can be configured into one of the following four options:

• 0: ~5 mA

8

• 1: ~10 mA

• 2: ~20 mA

• 3: ~40 mA

The default value is 2.

The drive strength of the internal pull-up (wpu) and pull-down (wpd) is ~75 µA.

Column “At Reset” in Table IO_MUX lists the status of each pin during reset, including input-

enable (ie=1), internal pull-up (wpu) and internal pull-down (wpd). During reset, all pins are

output-disabled.

9

Column “After Reset” in Table IO_MUX lists the status of each pin immediately after reset,

including input-enable (ie=1), internal pull-up (wpu) and internal pull-down (wpd). After reset,

each pin is set to “Function 1”. The output-enable is controlled by digital Function 1.

Table Ethernet_MAC is about the signal mapping inside Ethernet MAC. The Ethernet MAC

supports MII and RMII interfaces, and supports both the internal PLL clock and the external

clock source. For the MII interface, the Ethernet MAC is with/without the TX_ERR signal. MDC,

MDIO, CRS and COL are slow signals, and can be mapped onto any GPIO pin through the

GPIO-Matrix.

10

11

12

Table GPIO Matrix is for the GPIO-Matrix. The signals of the on-chip functional modules can

be mapped onto any GPIO pin. Some signals can be mapped onto a pin by both IO-MUX

and GPIO-Matrix, as shown in the column tagged as “Same input signal from IO_MUX core”

in Table GPIO Matrix.

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Appendix A

No.

13

Description

*In Table GPIO_Matrixꢀthe column “Default Value if unassigned” records the default value of

the an input signal if no GPIO is assigned to it. The actual value is determined by register

GPIO_FUNCm_IN_INV_SEL and GPIO_FUNCm_IN_SEL. (The value of m ranges from 1 to

255.)

A.2. GPIO_Matrix

Table 25: GPIO_Matrix

Same input

Signal

Default value

signal from

if unassigned* IO_MUX

core

Output enable

Input signals

No.

Output signals

of output signals

0

SPICLK_in

0

1

0

yes

no

SPICLK_out

SPIQ_out

SPICLK_oe

SPIQ_oe

SPID_oe

SPIHD_oe

SPIWP_oe

SPICS0_oe

SPICS1_oe

SPICS2_oe

HSPICLK_oe

HSPIQ_oe

HSPID_oe

HSPICS0_oe

HSPIHD_oe

HSPIWP_oe

1’d1

1

SPIQ_in

2

SPID_in

SPID_out

3

SPIHD_in

SPIHD_out

4

SPIWP_in

SPIWP_out

5

SPICS0_in

SPICS0_out

SPICS1_out

SPICS2_out

HSPICLK_out

HSPIQ_out

6

SPICS1_in

7

SPICS2_in

no

8

HSPICLK_in

HSPIQ_in

yes

no

9

10

11

12

13

14

15

16

17

18

23

24

25

26

27

28

29

30

31

32

33

34

HSPID_in

HSPID_out

HSPICS0_in

HSPIHD_in

HSPIWP_in

U0RXD_in

HSPICS0_out

HSPIHD_out

HSPIWP_out

U0TXD_out

U0CTS_in

U0RTS_out

1’d1

U0DSR_in

U0DTR_out

1’d1

U1RXD_in

yes

no

U1TXD_out

1’d1

U1CTS_in

U1RTS_out

1’d1

I2S0O_BCK_in

I2S1O_BCK_in

I2S0O_WS_in

I2S1O_WS_in

I2S0I_BCK_in

I2S0I_WS_in

I2CEXT0_SCL_in

I2CEXT0_SDA_in

pwm0_sync0_in

pwm0_sync1_in

pwm0_sync2_in

pwm0_f0_in

I2S0O_BCK_out

I2S1O_BCK_out

I2S0O_WS_out

I2S1O_WS_out

I2S0I_BCK_out

I2S0I_WS_out

I2CEXT0_SCL_out

I2CEXT0_SDA_out

sdio_tohost_int_out

pwm0_out0a

pwm0_out0b

pwm0_out1a

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

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Appendix A

Same input

signal from

IO_MUX

core

no

Signal

No.

Default value

if unassigned

Output enable

Input signals

Output signals

of output signals

35

36

37

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

pwm0_f1_in

0

pwm0_out1b

1’d1

pwm0_f2_in

no

pwm0_out2a

1’d1

-

no

pwm0_out2b

1’d1

pcnt_sig_ch0_in0

pcnt_sig_ch1_in0

pcnt_ctrl_ch0_in0

pcnt_ctrl_ch1_in0

pcnt_sig_ch0_in1

pcnt_sig_ch1_in1

pcnt_ctrl_ch0_in1

pcnt_ctrl_ch1_in1

pcnt_sig_ch0_in2

pcnt_sig_ch1_in2

pcnt_ctrl_ch0_in2

pcnt_ctrl_ch1_in2

pcnt_sig_ch0_in3

pcnt_sig_ch1_in3

pcnt_ctrl_ch0_in3

pcnt_ctrl_ch1_in3

pcnt_sig_ch0_in4

pcnt_sig_ch1_in4

pcnt_ctrl_ch0_in4

pcnt_ctrl_ch1_in4

HSPICS1_in

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

-

1’d1

no

HSPICS1_out

HSPICS2_out

VSPICLK_out_mux

VSPIQ_out

VSPID_out

VSPIHD_out

VSPIWP_out

VSPICS0_out

VSPICS1_out

VSPICS2_out

ledc_hs_sig_out0

ledc_hs_sig_out1

ledc_hs_sig_out2

ledc_hs_sig_out3

ledc_hs_sig_out4

ledc_hs_sig_out5

ledc_hs_sig_out6

HSPICS1_oe

HSPICS2_oe

VSPICLK_oe

VSPIQ_oe

VSPID_oe

VSPIHD_oe

VSPIWP_oe

VSPICS0_oe

VSPICS1_oe

VSPICS2_oe

1’d1

HSPICS2_in

no

VSPICLK_in

yes

no

VSPIQ_in

VSPID_in

VSPIHD_in

VSPIWP_in

VSPICS0_in

VSPICS1_in

VSPICS2_in

no

pcnt_sig_ch0_in5

pcnt_sig_ch1_in5

pcnt_ctrl_ch0_in5

pcnt_ctrl_ch1_in5

pcnt_sig_ch0_in6

pcnt_sig_ch1_in6

pcnt_ctrl_ch0_in6

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

no

1’d1

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Appendix A

Same input

Signal

No.

Default value

if unassigned

signal from

IO_MUX

core

no

-

Output enable

Input signals

Output signals

of output signals

78

pcnt_ctrl_ch1_in6

pcnt_sig_ch0_in7

pcnt_sig_ch1_in7

pcnt_ctrl_ch0_in7

pcnt_ctrl_ch1_in7

rmt_sig_in0

0

-

ledc_hs_sig_out7

ledc_ls_sig_out0

ledc_ls_sig_out1

ledc_ls_sig_out2

ledc_ls_sig_out3

ledc_ls_sig_out4

ledc_ls_sig_out5

ledc_ls_sig_out6

ledc_ls_sig_out7

rmt_sig_out0

1’d1

79

80

81

82

83

84

rmt_sig_in1

85

rmt_sig_in2

86

rmt_sig_in3

87

rmt_sig_in4

88

rmt_sig_in5

rmt_sig_out1

89

rmt_sig_in6

rmt_sig_out2

90

rmt_sig_in7

rmt_sig_out3

91

-

rmt_sig_out4

92

-

rmt_sig_out6

94

-

rmt_sig_out7

95

I2CEXT1_SCL_in

I2CEXT1_SDA_in

host_card_detect_n_1

host_card_detect_n_2

host_card_write_prt_1

host_card_write_prt_2

host_card_int_n_1

host_card_int_n_2

pwm1_sync0_in

pwm1_sync1_in

pwm1_sync2_in

pwm1_f0_in

1

0

1

0

no

I2CEXT1_SCL_out

I2CEXT1_SDA_out

96

97

host_ccmd_od_pullup_en_n 1’d1

98

host_rst_n_1

host_rst_n_2

gpio_sd0_out

gpio_sd1_out

gpio_sd2_out

gpio_sd3_out

gpio_sd4_out

gpio_sd5_out

gpio_sd6_out

gpio_sd7_out

pwm1_out0a

pwm1_out0b

pwm1_out1a

pwm1_out1b

pwm1_out2a

pwm1_out2b

pwm2_out1h

pwm2_out1l

pwm2_out2h

pwm2_out2l

pwm2_out3h

1’d1

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

pwm1_f1_in

pwm1_f2_in

pwm0_cap0_in

pwm0_cap1_in

pwm0_cap2_in

pwm1_cap0_in

pwm1_cap1_in

pwm1_cap2_in

pwm2_flta

pwm2_fltb

pwm2_cap1_in

pwm2_cap2_in

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Same input

Signal

No.

Default value

if unassigned

signal from

Output enable

Input signals

Output signals

IO_MUX

core

no

-

of output signals

119

120

121

122

123

124

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

pwm2_cap3_in

pwm3_flta

0

1

0

-

pwm2_out3l

1’d1

pwm2_out4h

pwm3_fltb

pwm2_out4l

pwm3_cap1_in

pwm3_cap2_in

pwm3_cap3_in

I2S0I_DATA_in0

I2S0I_DATA_in1

I2S0I_DATA_in2

I2S0I_DATA_in3

I2S0I_DATA_in4

I2S0I_DATA_in5

I2S0I_DATA_in6

I2S0I_DATA_in7

I2S0I_DATA_in8

I2S0I_DATA_in9

I2S0I_DATA_in10

I2S0I_DATA_in11

I2S0I_DATA_in12

I2S0I_DATA_in13

I2S0I_DATA_in14

I2S0I_DATA_in15

-

I2S0O_DATA_out0

I2S0O_DATA_out1

I2S0O_DATA_out2

I2S0O_DATA_out3

I2S0O_DATA_out4

I2S0O_DATA_out5

I2S0O_DATA_out6

I2S0O_DATA_out7

I2S0O_DATA_out8

I2S0O_DATA_out9

I2S0O_DATA_out10

I2S0O_DATA_out11

I2S0O_DATA_out12

I2S0O_DATA_out13

I2S0O_DATA_out14

I2S0O_DATA_out15

I2S0O_DATA_out16

I2S0O_DATA_out17

I2S0O_DATA_out18

I2S0O_DATA_out19

I2S0O_DATA_out20

I2S0O_DATA_out21

I2S0O_DATA_out22

I2S0O_DATA_out23

I2S1I_BCK_out

-

I2S1I_BCK_in

I2S1I_WS_in

I2S1I_DATA_in0

I2S1I_DATA_in1

I2S1I_DATA_in2

I2S1I_DATA_in3

I2S1I_DATA_in4

I2S1I_DATA_in5

I2S1I_DATA_in6

I2S1I_DATA_in7

0

no

I2S1I_WS_out

I2S1O_DATA_out0

I2S1O_DATA_out1

I2S1O_DATA_out2

I2S1O_DATA_out3

I2S1O_DATA_out4

I2S1O_DATA_out5

I2S1O_DATA_out6

I2S1O_DATA_out7

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Appendix A

Same input

Signal

No.

Default value

if unassigned

signal from

Output enable

Input signals

Output signals

IO_MUX

core

no

-

of output signals

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

I2S1I_DATA_in8

0

-

I2S1O_DATA_out8

I2S1O_DATA_out9

I2S1O_DATA_out10

I2S1O_DATA_out11

I2S1O_DATA_out12

I2S1O_DATA_out13

I2S1O_DATA_out14

I2S1O_DATA_out15

I2S1O_DATA_out16

I2S1O_DATA_out17

I2S1O_DATA_out18

I2S1O_DATA_out19

I2S1O_DATA_out20

I2S1O_DATA_out21

I2S1O_DATA_out22

I2S1O_DATA_out23

pwm3_out1h

1’d1

I2S1I_DATA_in9

1’d1

I2S1I_DATA_in10

1’d1

I2S1I_DATA_in11

1’d1

I2S1I_DATA_in12

1’d1

I2S1I_DATA_in13

1’d1

I2S1I_DATA_in14

1’d1

I2S1I_DATA_in15

1’d1

-

1’d1

-

1’d1

-

1’d1

-

1’d1

-

1’d1

-

1’d1

-

1’d1

-

1’d1

I2S0I_H_SYNC

0

-

no

-

1’d1

I2S0I_V_SYNC

pwm3_out1l

1’d1

I2S0I_H_ENABLE

pwm3_out2h

1’d1

I2S1I_H_SYNC

pwm3_out2l

1’d1

I2S1I_V_SYNC

pwm3_out3h

1’d1

I2S1I_H_ENABLE

pwm3_out3l

1’d1

-

pwm3_out4h

1’d1

-

pwm3_out4l

1’d1

U2RXD_in

0

-

yes

no

-

U2TXD_out

1’d1

U2CTS_in

U2RTS_out

1’d1

emac_mdc_i

emac_mdc_o

emac_mdc_oe

emac_mdo_o_e

emac_crs_oe

emac_col_oe

1’d1

emac_mdi_i

emac_mdo_o

emac_crs_i

emac_crs_o

emac_col_i

emac_col_o

pcmfsync_in

bt_audio0_irq

pcmclk_in

bt_audio1_irq

1’d1

pcmdin

bt_audio2_irq

1’d1

-

ble_audio0_irq

ble_audio1_irq

ble_audio2_irq

pcmfsync_out

1’d1

-

1’d1

-

1’d1

-

pcmfsync_en

pcmclk_en

pcmdout_en

1’d1

-

pcmclk_out

-

pcmdout

-

ble_audio_sync0_p

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Appendix A

Same input

Signal

No.

Default value

if unassigned

signal from

Output enable

Input signals

Output signals

IO_MUX

of output signals

core

214

215

224

225

226

227

228

-

ble_audio_sync1_p

ble_audio_sync2_p

sig_in_func224

sig_in_func225

sig_in_func226

sig_in_func227

sig_in_func228

1’d1

-

A.3. Ethernet_MAC

Table 26: Ethernet_MAC

PIN Name

GPIO0

Function6

MII (int_osc)

TX_CLK (I)

RX_CLK (I)

TX_EN(O)

TXD[0](O)

TXD[1](O)

TXD[2](O)

TXD[3](O)

RX_ER(I)

MII (ext_osc)

RMII (int_osc)

RMII (ext_osc)

EMAC_TX_CLK

EMAC_RX_CLK

EMAC_TX_EN

EMAC_TXD0

EMAC_TXD1

EMAC_TXD2

EMAC_TXD3

EMAC_RX_ER

EMAC_RX_DV

EMAC_RXD0

EMAC_RXD1

EMAC_RXD2

EMAC_RXD3

EMAC_CLK_OUT

TX_CLK (I)

RX_CLK (I)

TX_EN(O)

TXD[0](O)

TXD[1](O)

TXD[2](O)

TXD[3](O)

RX_ER(I)

RX_DV(I)

RXD[0](I)

RXD[1](I)

RXD[2](I)

RXD[3](I)

-

CLK_OUT(O)

EXT_OSC_CLK(I)

GPIO5

-

GPIO21

TX_EN(O)

GPIO19

TXD[0](O)

GPIO22

TXD[1](O)

MTMS

-

MTDI

-

MTCK

-

GPIO27

RX_DV(I)

CRS_DV(I)

GPIO25

RXD[0](I)

GPIO26

RXD[1](I)

U0TXD

RXD[2](I)

-

MTDO

RXD[3](I)

-

GPIO16

CLK_OUT(O)

GPIO17

EMAC_CLK_OUT_180 CLK_OUT_180(O) -

CLK_OUT_180(O) -

GPIO4

EMAC_TX_ER

TX_ERR(O)*

MDC(O)

MDIO(IO)

CRS(I)

TX_ERR(O)*

MDC(O)

MDIO(IO)

CRS(I)

-

In GPIO Matrix*

-

MDC(O)

MDIO(IO)

-

COL(I)

*Notes: 1. The GPIO Matrix can be any GPIO. 2. The TX_ERR (O) is optional.

A.4. IO_MUX

For the list of IO_MUX pins, please see the next page.

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Revision History

Date

Version

V3.4

Release notes

Added one chip variant: ESP32-U4WDH

2020-04-27

Updated some figures in Table 6, 16, 17, 19, 21, 22

Added a note under Table 18

Added two chip variants: ESP32-D0WD-V3 and ESP32-D0WDQ6-V3.

Added a note under Table 7.

2020.01

2019.10

V3.3

V3.2

Updated Figure 5: ESP32 Power-up and Reset Timing.

Added pin-pin mapping between ESP32-D2WD and the embedded flash under

Table 1 Pin Description;

2019.07

2019.04

2019.02

V3.1

V3.0

V2.9

Updated Figure 10 ESP32 Part Number.

Added information about the setup and hold times for the strapping pins in Section

2.4: Strapping Pins.

Applied new formatting to Table 1: Pin Description;

Fixed typos with respect to the ADC1 channel mappings in Table 10: Peripheral

Pin Configurations.

Changed the RF power control range in Table 18, Table 20 and Table 22 from –12

~ +12 to –12 ~ +9 dBm;

2019.01

V2.8

Small text changes.

Updated Section 1.5;

2018.11

2018.10

V2.7

V2.6

Updated pin statuses at reset and after reset in Table IO_MUX.

Updated QFN package drawings in Chapter 6: Package Information.

• Added ”Cumulative IO output current” entry to Table 11: Absolute Maximum

Ratings;

2018.08

V2.5

• Added more parameters to Table 13: DC Characteristics;

• Changed the power domain names in Table IO_MUX to be consistent with

the pin names.

• Deleted information on Packet Traffic Arbitration (PTA);

• Added Figure 5: ESP32 Power-up and Reset Timing in Section 2.3: Power

Scheme;

2018.07

2018.06

V2.4

V2.3

• Added the power consumption of dual-core SoCs in Table 6: Power Con-

sumption by Power Modes;

• Updated section 4.1.2: Analog-to-Digital Converter (ADC).

Added the power consumption at CPU frequency of 160 MHz in Table 6: Power

Consumption by Power Modes.

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Revision History

Date

Version

Release notes

• Changed the voltage range of VDD3P3_RTC from 1.8-3.6V to 2.3-3.6V in

Table 1: Pin Description;

• Updated Section 2.3: Power Scheme;

• Updated Section 3.1.3: External Flash and SRAM;

• Updated Table 6: Power Consumption by Power Modes;

• Deleted content about temperature sensor;

Changes to electrical characteristics:

• Updated Table 11: Absolute Maximum Ratings;

• Added Table 12: Recommended Operating Conditions;

• Added Table 13: DC Characteristics;

2018.05

V2.2

• Added Table 14: Reliability Qualifications;

• Updated the values of ”Gain control step” and ”Adjacent channel transmit

power” in Table 18: Transmitter Characteristics - Basic Data Rate;

• Updated the values of ”Gain control step”, ”π/4 DQPSK modulation accu-

racy”, ”8 DPSK modulation accuracy” and ”In-band spurious emissions” in

Table 20: Transmitter Characteristics – Enhanced Data Rate;

• Updated the values of ”Gain control step”, ”Adjacent channel transmit

power” in Table 22: Transmitter Characteristics - BLE.

• Deleted software-specific features;

• Deleted information on LNA pre-amplifier;

• Specified the CPU speed and flash speed of ESP32-D2WD;

• Added notes to Section 2.3: Power Scheme.

2018.01

2017.12

V2.1

V2.0

Added a note on the sequence of pin number in Chapter 6.

• Updated the description of the pin CHIP_PU in Table 1;

• Added a note to Section 2.3: Power Scheme;

• Updated the description of the chip’s system reset in Section 2.4: Strapping

Pins;

2017.10

2017.08

V1.9

V1.8

• Added a description of antenna diversity and selection to Section 3.5.1;

• Deleted ”Association sleep pattern” in Table 6 and added notes to Active

sleep and Modem-sleep.

• Added Table 4.2 in Section 4;

• Corrected a typo in Figure 1.

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Revision History

Date

Version

Release notes

• Changed the transmitting power to +12 dBm; the sensitivity of NZIF receiver

to -97 dBm in Section 1.3;

• Added a note to Table 1 Pin Description;

• Added 160 MHz clock frequency in section 3.1.1;

• Changed the transmitting power from 21 dBm to 20.5 dBm in Section 3.5.1;

• Changed the dynamic control range of class-1, class-2 and class-3 transmit

output powers to ”up to 24 dBm”; and changed the dynamic range of NZIF

receiver sensitivity to ”over 97 dB” in Section 3.6.1;

• Updated Table 6: Power Consumption by Power Modes, and added two

notes to it;

2017.08

V1.7

• Updated sections 4.1.1, 4.1.9;

• Updated Table 11: Absolute Maximum Ratings;

• Updated Table 15: RF Power Consumption Specifications, and changed the

duty cycle on which the transmitters’ measurements are based by 50%.

• Updated Table 16: Wi-Fi Radio Characteristics and added a note on “Output

impedance” to it;

• Updated parameter ”Sensitivity” in Table 17, 19, 21;

• Updated parameters ”RF transmit power” and ”RF power control range”,

and added parameter ”Gain control step” in Table 18, 20, 22;

• Deleted Chapters: ”Touch Sensor” and ”Code Examples”;

• Added a link to certification download.

Corrected two typos:

• Changed the number of external components to 20 in Section 1.1.2;

• Changed the number of GPIO pins to 34 in Section 4.1.1.

2017.06

V1.6

V1.5

• Changed the power supply range in Section: 1.4.1 CPU and Memory;

• Updated the note in Section 2.3: Power Scheme;

• Updated Table 11: Absolute Maximum Ratings;

• Changed the drive strength values of the digital output pins in Note 8, in

Table 24: Notes on ESP32 Pin Lists;

• Added the option to subscribe for notifications of documentation changes.

• Added a note to the frequency of the external crystal oscillator in Section

1.4.2: Clocks and Timers;

• Added a note to Section 2.4: Strapping Pins;

• Updated Section 3.7: RTC and Low-Power Management;

• Changed the maximum driving capability from 12 mA to 80 mA, in Table 11:

Absolulte Maximum Ratings;

2017.05

2017.04

V1.4

V1.3

• Changed the input impedance value of 50Ω, in Table 16: Wi-Fi Radio Char-

acteristics, to output impedance value of 30+j10 Ω;

• Added a note to No.8 in Table 24: Notes on ESP32 Pin Lists;

• Deleted GPIO20 in Table IO_MUX.

• Added Appendix: ESP32 Pin Lists;

• Updated Table: Wi-Fi Radio Characteristics;

• Updated Figure: ESP32 Pin Layout (for QFN 5*5).

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ESP32 Datasheet V3.4

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Revision History

Date

Version

V1.2

Release notes

• Added a note to Table: Pin Description;

• Updated the note in Section: Internal Memory.

2017.03

• Added Chapter: Part Number and Ordering Information;

• Updated Section: MCU and Advanced Features;

• Updated Section: Block Diagram;

• Updated Chapter: Pin Definitions;

2017.02

2016.08

V1.1

V1.0

• Updated Section: CPU and Memory;

• Updated Section: Audio PLL Clock;

• Updated Section: Absolute Maximum Ratings;

• Updated Chapter: Package Information;

• Updated Chapter: Learning Resources.

First release.

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ESP32 Datasheet V3.4

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型号：	ESP32-D0WDQ6-V3
厂家：	ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
描述：	32-bit MCU & 2.4 GHz Wi-Fi & BT/BLE SoCs
文件：	总64页 (文件大小：1076K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ESP32-D0WDQ6-V3 [ESPRESSIF]

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