ES6425 [ESS]
Digital Media Processor 2 Product Brief; 数字媒体处理器2产品简介
| 型号： | ES6425 |
| 厂家： | 
ESS Technology,Inc |
| 描述： | Digital Media Processor 2 Product Brief |
| 文件： | 总8页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ES6425
Digital Media Processor 2
Product Brief
ESS Technology, Inc.
DESCRIPTION
FEATURES
• Single-chip digital audio and video decoder and
The ES6425 Digital Media Processor 2 (DMP2) is a high
performance single-chip audio/video decoder for a wide
series of applications such as networked or non-
networked/flash memory media players. This second
generation of Digital Media Processor has an enhanced
performance engine to decode MPEG-4 video at D1
resolution with state-of-the-art progressive scan
NTSC/PAL video encoder for brilliant and sharp, flicker-
free output to the video display.
processor.
• MPEG-4 Advanced Simple Profile* at full screen D1 video
playback (playability is dependent on memory card
bandwidth).
• MPEG-2 video playback (playability is dependent on
memory card bandwidth).
• MPEG-1 video playback.
• Motion JPEG playback.
At the heart of the ES6425 is the ESS proprietary
Programmable Multimedia Processor core consisting of
32-bit RISC and 64-bit DSP processors that enable
simultaneous parallel execution of system commands and
specialized multimedia decoding tasks. The ES6425
includes a memory controller which interfaces to 8-bit or
16-bit DRAM with up to 128-Mb capacity.
• JPEG photo playback.
• Progressive JPEG photo playback.
• MP3 music playback.
• WMA music playback (Microsoft license required).
• Dolby Digital decode (ES6425FDF only)
• AAC audio decode and playback.
• ESS Music Slideshow.
The ES6425 performs video processing to provide high-
resolution display of MPEG-1, MPEG-2, and MPEG-4
videos and JPEG photos. The integrated NTSC/PAL TV-
encoder provides composite, S-video, and YUV outputs.
The ES6425 includes an On-Screen-Display (OSD)
controller to provide a user friendly setup menu to enable
or modify the various audio decoding and video display
features. A CCIR656/601 digital video output port is also
present.
• S/PDIF digital audio output.
• Integrated NTSC/PAL encoder with pixel adaptive de-
interlacer and five 10-bit 54 MHz video DACs.
• High-quality progressive scan video output for flicker-free
video display.
• Simultaneous Composite, S-Video, and YUV outputs.
• CCIR656/601 YUV 4:2:2 output.
The ES6425 also performs audio processing for Wave,
MP3, AAC, Dolby Digital, and WMA playback along with
a 7-band graphic equalizer. The ES6425 has a multi-
channel audio serial port compliant to I2S format for
interfacing to an external audio DAC and ADC. An S/PDIF
output port is also integrated for transmitting digital audio
streams.
• On-Screen-Display controller with 3-bit blending to
provide 256 colors display.
• Integrated I2S serial port for up to 5.1 channel audio
output and stereo input.
• Direct interface for IDE devices and flash memory cards
A 16-bit host interface present in the ES6425 connects to
many different storage solutions including Compact
Flash, Smart Media, xD-Picture Card, and IDE hard
drives. Similarly, a serial interface is built-in to interface to
SD, xD, MultiMediaCard, and Memory Stick
devices.
including CF, MS, MS Pro, SD, xD, MMC, and SM.
• DRAM memory controller with interface to 8-bit or 16-bit
SDRAM for up to 16 MB of memory.
• 16-bit SRAM interface for connecting to boot EPROM or
flash memory.
The ES6425 is available in an industry-standard 208-pin
Plastic Quad Flat Pack (PQFP) device package.
• Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi.
ESS Technology, Inc.
SAM0529-091305
1
ES6425 PRODUCT BRIEF
ES6425 PINOUT DIAGRAM
ES6425 PINOUT DIAGRAM
The device pinout for the ES6425 is shown in Figure 1. The
pound symbol (#) denotes an active-low signal.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VEE
HA2/AUX4[4]
VEE
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
I2CDATA/AUX0
I2C_CLK/AUX1
IOW#/AUX2
VSS
VSS
VEE
DCS1#
DB15
DB14
DB13
DB12
VEE
IORD#/AUX3
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VSS
DB11
DB10
DB9
VCC
LCS0#/PIXOUT_CLK
LCS1#
LCS2#
LCS3#
VSS
DB8
DB7
DB6
VSS
LD0
VCC
LD1
DB5
LD2
DB4
LD3
DB3
LD4
DB2
VEE
DB1
ES6425
VSS
DB0
LD5
VSS
LD6
VEE
LD7
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
LD8
LD9
LD10
LD11
VSS
VEE
LD12
VSS
LD13
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN1
LA0
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
LA1
LA2
LA3
VSS
Figure 1 ES6425 Device Pinout
Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation (GMC).
2
SAM0529-091305
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
ES6425 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6425. The
pound symbol (#) denotes an active-low signal.
Table 1 ES6425 Pin Description
Name
Pin Numbers
I/O
Definition
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
VEE
P
I/O power supply.
2-7, 10-16, 19-23,
204-207
LA[21:0]
VSS
O
G
I
RISC port address bus.
Ground.
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
9, 35, 44, 83, 121,
139, 172
VCC
Core power supply.
RESET#
TDMDX
24
I
O
I
Reset input (active-low); (5V tolerant input).
TDM transmit data.
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read during reset.
25
RSEL
Selection
16-bit ROM
8-bit ROM
RSEL
0
1
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
28
29
30
31
I
I
TDM receive data; (5V tolerant input).
TDM clock; (5V tolerant input).
TDM frame sync; (5V tolerant input).
TDM output enable (active-low).
Audio transmit frame sync.
I
O
O
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for proper
operation; read during reset.
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DCLK x 4.5
DCLK x 5.0
Bypass mode
DCLK x 4.0
DCLK x 4.25
DCLK x 4.75
DCLK x 5.5
DCLK x 6.0
32
SEL_PLL2
I
TSD0
O
I
Audio transmit serial data output 0.
33
SEL_PLL0
Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
ESS Technology, Inc.
SAM0529-091305
3
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1 ES6425 Pin Description (Continued)
Name
Pin Numbers
I/O
O
I
Definition
TSD1
Audio transmit serial data output 1.
36
37
SEL_PLL1
TSD2
Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.
O
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-kΩ resistor for proper operation.
MCLK
TBCK
39
40
I/O
I/O
Audio master clock for audio DAC.
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
SPDIF
SEL_PLL3
NC
O
I
S/PDIF output.
41
Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset.
No connect.
38, 42
—
I
RSD
45
Audio receive serial data; (5V tolerant input).
Audio receive frame sync; (5V tolerant input).
Audio receive bit clock; (5V tolerant input).
Camera and YUV input 3.
RWS
46
I
RBCK
47
I
CAMIN3
XIN
48
I
49
I
27-MHz crystal input.
XOUT
50
O
P
G
O
O
O
O
O
O
O
O
I/O
O
O
O
I
27-MHz crystal output.
AVEE
51
Analog power for PLL.
AVSS
52
53-58, 61-66
69
Analog ground for PLL.
DMA[11:0]
DCAS#
DOE#
DRAM address bus.
DRAM column address strobe (active-low).
DRAM output enable (active-low).
DRAM clock enable.
70
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0]
DCS[1:0]#
DQM
71
DRAM write enable (active-low).
DRAM row address strobe (active-low).
SDRAM bank select 0.
72
73
74
SDRAM bank select 1.
77-82, 85-90, 93-96
DRAM data bus.
97,100
101
SDRAM chip select (active-low).
Data input/output mask.
DSCK
102
Output clock to SDRAM.
DCLK
105
Clock input to PLL; (5V tolerant input).
4
SAM0529-091305
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1 ES6425 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
O
Video DAC output:
DAC V
DAC Y
(pin 113)
DAC C
(pin 108) (pin 106)
DAC U
Value
(pin 114)
CVBS1
CVBS1
N/A
0
1
Y
Y
N/A
CVBS2
N/A
CVBS2
N/A
Pr
C
C
2
Y
C
3
CVBS1
CVBS1
CVBS1
N/A
N/A
N/A
Y
N/A
N/A
Pb
Pb
B
4
5
6
Y
Pr
7
SYNC
CHROMA
CVBS1
CVBS1
SYNC
N/A
G
R
106
UDAC
8
Y
Pr
Pb
B
9
G
R
10
11
12
13
G
B
R
G
B
R
Y
Pb
Pr
Pr
CVBS1
Y
Pb
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV0
O
O
I
YUV pixel 0 output data.
CCIR656 output pixel 0.
PIXOUT0
VREF
Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor.
YUV pixel 1 output data.
YUV1
107
108
109
110
O
O
O
O
O
I
PIXOUT1
CDAC
CCIR656 output pixel 1.
Chrominance signal for Y/C processing display.
YUV pixel 2 output data.
YUV2
PIXOUT2
COMP
YUV3
CCIR656 output pixel 2.
Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
YUV pixel 3 output data.
O
O
I
PIXOUT3
RSET
CCIR656 output pixel 3.
DAC current adjustment resistor input.
YUV pixel 4 output data.
YUV4
O
O
P
G
O
O
O
O
O
O
PIXOUT4
ADVEE
ADVSS
YDAC
CCIR656 output pixel 4.
111
112
Analog power.
Analog ground for video DAC.
Luma component for Y/C processing display.
YUV pixel 5 output data.
YUV5
113
114
PIXOUT5
VDAC
CCIR656 output pixel 5.
Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV pixel 6 output data.
YUV6
PIXOUT6
CCIR656 output pixel 6.
ESS Technology, Inc.
SAM0529-091305
5
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1 ES6425 Pin Description (Continued)
Name
Pin Numbers
I/O
O
Definition
YUV7
YUV pixel 7 output data.
115
PIXOUT7
PCLK2XSCN
CAMIN4
PCLKQSCN
AUX3[2]
CAMIN5
VSYNC#
AUX3[1]
CAMIN6
HSYNC#
AUX3[0]
CAMIN7
HD[5:0]
AUX1[5:0]
HD6
O
CCIR656 output pixel 7.
I/O
I
27-MHz video pixel clock.
116
117
Camera and YUV input 4.
O
13.5-MHz video output pixel clock.
Aux3 data I/O; (5V tolerant input).
Camera and YUV input 5
I/O
I
I/O
I/O
I
Vertical sync (active-low); (5V tolerant input).
Aux3 data I/O; (5V tolerant input).
Camera and YUV input 6.
118
I/O
I/O
I
Horizontal sync (active-low); (5V tolerant input).
Aux3 data I/O; (5V tolerant input).
Camera and YUV input 7.
119
122-127
128
I/O
I/O
I/O
I/O
O
Host data bus; (5V tolerant input).
Aux1 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux1 data I/O; (5V tolerant input).
VFD data output.
AUX1[6]
VFD_DOUT
HD7
I/O
I/O
I
Host data bus; (5V tolerant input).
Aux1 data I/O; (5V tolerant input).
VFD data input.
AUX1[7]
VFD_DIN
HD8
131
132
I/O
I/O
I
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
VFD clock.
AUX2[0]
VFD_CLK
HD9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O; (5V tolerant input).
Host data bus; (5V tolerant input).
Aux2 data I/O 7; (5V tolerant input).
IR remote control; (5V tolerant input).
Host write request (active-low).
Aux4 data I/O 1; (5V tolerant input).
133
134
135
136
137
140
AUX2[1]
HD10
AUX2[2]
HD11
AUX2[3]
HD12
AUX2[4]
HD13
AUX2[5]
HD14
AUX2[6]
HD15
AUX2[7]
IR
141
142
HWRQ#
AUX4[1]
O
I/O
6
SAM0529-091305
ESS Technology, Inc.
ES6425 PRODUCT BRIEF
ES6425 PIN DESCRIPTION
Table 1 ES6425 Pin Description (Continued)
Name
Pin Numbers
I/O
O
Definition
HRRQ#
AUX4[0]
CAMIN2
HIRQ
Host read request (active-low).
Aux4 data I/O 0; (5V tolerant input).
Camera and YUV input 2.
143
I/O
I
O
Host interrupt.
144
145
146
149
150
AUX4[7]
HRST#
AUX3[5]
HIORDY
AUX3[3]
HWR#
I/O
O
Aux4 data I/O 7; (5V tolerant input).
Host reset (active-low).
I/O
I
Aux3 data I/O 5; (5V tolerant input).
Host I/O ready.
I/O
O
Aux3 data I/O 3; (5V tolerant input).
Host write (active-low).
AUX4[5]
HRD#
I/O
O
Aux4 data I/O 5; (5V tolerant input).
Host read (active-low).
AUX4[6]
HIOCS16#
AUX3[4]
CAMCLK
HCS1FX#
AUX3[7]
HCS3FX#
AUX3[6]
HA[2:0]
AUX4[4:2]
AUX0
I/O
I
Aux4 data I/O 6; (5V tolerant input).
Device 16 bit data transfer (active-low).
Aux3 data I/O 4; (5V tolerant input).
Camera and YUV port pixel clock.
Host select 1 (active-low).
151
I/O
I
O
152
153
I/O
O
Aux3 data I/O 7; (5V tolerant input).
Host select 3 (active-low).
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Aux3 data I/O 6; (5V tolerant input).
Host address bus.
154, 155, 158
160
Aux4 data I/Os 2, 3, and 4; (5V tolerant input).
Auxiliary port 0 (open collector); (5V tolerant input).
I2C data I/O; (5V tolerant input).
Auxiliary port 1 (open collector); (5V tolerant input).
I2C clock I/O; (5V tolerant input).
I/O write strobe (LCS1) (active-low).
Auxiliary port 2; (5V tolerant input).
I/O read strobe (LCS1) (active-low).
Auxiliary port 3; (5V tolerant input).
Auxiliary ports 4-7; (5V tolerant input).
RISC port output enable (active-low).
RISC port chip select 0 (active-low).
CCIR656 output pixel clock.
I2CDATA
AUX1
161
I2C_CLK
IOW#
162
AUX2
I/O
O
IOR#
165
AUX3
I/O
I/O
O
AUX4-7
LOE#
166-169
170
LCS0#
O
173
PIXOUT_CLK
LCS[3:1]#
O
174-176
O
RISC port chip select [3:1] (active-low).
178-182, 185-191,
194-197
LD[15:0]
I/O
RISC port data bus; (5V tolerant input).
LWRLL#
LWRHL#
CAMIN0
CAMIN1
198
199
202
203
O
O
I
RISC port low-byte write enable (active-low).
RISC port high-byte write enable (active-low).
Camera and YUV input 0.
I
Camera and YUV input 1.
ESS Technology, Inc.
SAM0529-091305
7
ES6425 PRODUCT BRIEF
SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6425 board design is
shown in Figure 2.
Video
Audio
ROM/Flash
(1 MB)
ADC
Audio
DAC
SDRAM
(4/16 MB)
ES6425
DMP2
Speakers
S/PDIF
A/V Receiver
IR Remote
EEPROM
IDE HDD
Memory Cards
Figure 2 ES645 System Block Diagram
ORDERING INFORMATION
Part Number
ES6425FF
Description
Package
Digital Media Processor 2 with lead-free leads.
208-pin PQFP
208-pin PQFP
ES6425FDF
Digital Media Processor 2 with Dolby Digital support and lead-free leads.
The letter F at the end of the part number identifies the package type PQFP.
The second letter F at the end of the part number indicates lead-free leads with the device.
No part of this publication may be reproduced, stored in a retrieval MPEG is the Moving Picture Experts Group of the ISO/IEC. References
system, transmitted, or translated in any form or by any means, to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
electronic, mechanical, manual, optical, or otherwise, without the prior
written permission of ESS Technology, Inc.
draft ISO 11172 dated January 9, 1992.
Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow
are trademarks of ESS Technology, Inc.
ESS Technology, Inc. makes no representations or warranties
regarding the content of this document.
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
Dolby is a trademark of Dolby Laboratories, Inc.
All specifications are subject to change without prior notice.
Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of
ESS Technology, Inc. assumes no responsibility for any errors SRS Labs., Inc.
contained herein.
All other trademarks are trademarks of their respective companies and
are used for identification purposes only.
U.S. patents pending.
8
http://www.esstech.com
© 2005 ESS Technology, Inc.
SAM0529-091305
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