08F1928 [ETC]

TRANSISTOR MOSFET TO-247 ; 晶体管MOSFET TO- 247\n
08F1928
型号: 08F1928
厂家: ETC    ETC
描述:

TRANSISTOR MOSFET TO-247
晶体管MOSFET TO- 247\n

晶体 晶体管
文件: 总8页 (文件大小:150K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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by MTW35N15E/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
35 AMPERES  
150 VOLTS  
N–Channel Enhancement–Mode Silicon Gate  
This advanced TMOS E–FET is designed to withstand high  
energy in the avalanche and commutation modes. The new energy  
efficient design also offers a drain–to–source diode with a fast  
recovery time. Designed for low voltage, high speed switching  
applications in power supplies, converters and PWM motor  
controls, these devices are particularly well suited for bridge circuits  
where diode speed and commutating safe operating areas are  
critical and offer additional safety margin against unexpected  
voltage transients.  
R
= 0.05 OHM  
DS(on)  
D
Avalanche Energy Specified  
Source–to–Drain Diode Recovery Time Comparable to a  
Discrete Fast Recovery Diode  
G
Diode is Characterized for Use in Bridge Circuits  
CASE 340K–01, Style 1  
TO–247AE  
I
and V  
Specified at Elevated Temperature  
DSS  
Isolated Mounting Hole Reduces Mounting Hardware  
DS(on)  
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
Unit  
Drain–Source Voltage  
V
150  
Vdc  
Vdc  
DSS  
Drain–Gate Voltage (R  
= 1.0 M)  
Gate–Source Voltage — Continuous  
V
DGR  
150  
GS  
V
± 20  
± 40  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t 10 µs)  
I
I
35  
26.9  
105  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
180  
1.45  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
55 to 150  
600  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 80 Vdc, V  
= 10 Vdc, I = 20 Apk, L = 3.0 mH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
θJC  
R
θJA  
0.70  
62.5  
°C/W  
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds  
T
L
260  
°C  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 3  
Motorola, Inc. 1996  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain–Source Breakdown Voltage  
V
(BR)DSS  
(V  
GS  
= 0 Vdc, I = 250 µAdc)  
150  
210  
Vdc  
mV/°C  
D
Temperature Coefficient (Positive)  
Zero Gate Voltage Drain Current  
I
µAdc  
DSS  
(V  
DS  
(V  
DS  
= 150 Vdc, V  
= 150 Vdc, V  
= 0 Vdc)  
= 0 Vdc, T = 125°C)  
10  
100  
GS  
GS  
J
Gate–Body Leakage Current (V  
= ± 20 Vdc, V  
= 0)  
DS  
I
100  
nAdc  
GS  
GSS  
ON CHARACTERISTICS (1)  
Gate Threshold Voltage  
V
GS(th)  
(V  
DS  
= V , I = 250 µAdc)  
2.0  
7.0  
4.0  
Vdc  
mV/°C  
GS  
D
Temperature Coefficient (Negative)  
Static Drain–Source On–Resistance (V  
= 10 Vdc, I = 17.5 Adc)  
R
V
0.05  
Ohm  
Vdc  
GS  
D
DS(on)  
Drain–Source On–Voltage (V  
= 10 Vdc)  
GS  
(I = 17.5 Adc, T = 125°C)  
DS(on)  
(I = 35 Adc)  
1.45  
1.8  
1.7  
D
D
J
Forward Transconductance (V  
= 10 Vdc, I = 17.5 Adc)  
g
FS  
11  
18  
mhos  
pF  
DS  
D
DYNAMIC CHARACTERISTICS  
Input Capacitance  
C
3600  
855  
5040  
1170  
330  
iss  
(V  
DS  
= 25 Vdc, V  
GS  
f = 1.0 MHz)  
= 0 Vdc,  
Output Capacitance  
C
oss  
Reverse Transfer Capacitance  
C
165  
rss  
SWITCHING CHARACTERISTICS (2)  
Turn–On Delay Time  
t
28  
170  
90  
56  
346  
180  
210  
137  
ns  
d(on)  
(V  
DD  
= 75 Vdc, I = 35 Adc,  
D
Rise Time  
t
r
V
= 10 Vdc,  
GS  
G
Turn–Off Delay Time  
Fall Time  
t
d(off)  
R
= 9.1 )  
t
f
103  
98  
Gate Charge  
(See Figure 8)  
Q
T
Q
1
Q
2
Q
3
nC  
19  
(V  
DS  
= 120 Vdc, I = 35 Adc,  
D
V
GS  
= 10 Vdc)  
49  
40  
SOURCE–DRAIN DIODE CHARACTERISTICS  
Forward On–Voltage (1)  
V
Vdc  
ns  
SD  
(I = 35 Adc, V  
= 0 Vdc)  
S
GS  
= 0 Vdc, T = 125°C)  
0.95  
0.9  
1.5  
(I = 35 Adc, V  
S
GS  
J
Reverse Recovery Time  
(See Figure 14)  
t
200  
167  
32  
rr  
t
a
(I = 35 Adc, V  
= 0 Vdc,  
S
GS  
dI /dt = 100 A/µs)  
S
t
b
Reverse Recovery Stored Charge  
Q
1.63  
µC  
RR  
INTERNAL PACKAGE INDUCTANCE  
Internal Drain Inductance  
(Measured from the drain lead 0.25from package to center of die)  
L
4.5  
13  
nH  
nH  
D
Internal Source Inductance  
(Measured from the source lead 0.25from package to source bond pad)  
L
S
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.  
(2) Switching characteristics are independent of operating junction temperature.  
2
Motorola TMOS Power MOSFET Transistor Device Data  
TYPICAL ELECTRICAL CHARACTERISTICS  
70  
60  
50  
40  
30  
20  
10  
0
70  
V
= 10 V  
GS  
9.0 V  
V
10 V  
DS  
T
= 25°C  
J
8.0 V  
60  
50  
40  
30  
20  
10  
7.0 V  
6.0 V  
100°C  
25°C  
5.0 V  
3.5  
T
= 55°C  
J
0
0
0.5  
V
1.0  
1.5  
2.0  
2.5  
3.0  
4.0  
2.0  
3.0  
4.0  
, GATE–TO–SOURCE VOLTAGE (VOLTS)  
GS  
5.0  
6.0  
7.0  
8.0  
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)  
V
DS  
Figure 1. On–Region Characteristics  
Figure 2. Transfer Characteristics  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0.047  
0.045  
0.043  
0.041  
0.039  
0.037  
0.035  
V
GS  
= 10 V  
T
= 25°C  
J
T
= 100°C  
J
V
= 10 V  
15 V  
GS  
25°C  
55°C  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
I , DRAIN CURRENT (AMPS)  
D
40  
50  
60  
70  
I
, DRAIN CURRENT (AMPS)  
D
Figure 3. On–Resistance versus Drain Current  
and Temperature  
Figure 4. On–Resistance versus Drain Current  
and Gate Voltage  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1000  
100  
10  
T
= 125°C  
V
= 10 V  
J
V
= 0 V  
GS  
= 17.5 A  
GS  
I
D
100°C  
1.0  
25°C  
0.1  
– 50  
– 25  
0
25  
50  
75  
100  
C)  
125  
150  
0
50  
100  
150  
T , JUNCTION TEMPERATURE (  
°
V
DS  
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)  
J
Figure 5. On–Resistance Variation with  
Temperature  
Figure 6. Drain–To–Source Leakage  
Current versus Voltage  
Motorola TMOS Power MOSFET Transistor Device Data  
3
POWER MOSFET SWITCHING  
Switching behavior is most easily modeled and predicted  
by recognizing that the power MOSFET is charge controlled.  
The lengths of various switching intervals (t) are deter-  
mined by how fast the FET input capacitance can be charged  
by current from the generator.  
The capacitance (C ) is read from the capacitance curve at  
iss  
a voltage corresponding to the off–state condition when cal-  
culating t  
and is read at a voltage corresponding to the  
d(on)  
on–state when calculating t  
.
d(off)  
At high switching speeds, parasitic circuit elements com-  
plicate the analysis. The inductance of the MOSFET source  
lead, inside the package and in the circuit wiring which is  
common to both the drain and gate current paths, produces a  
voltage at the source which reduces the gate drive current.  
The voltage is determined by Ldi/dt, but since di/dt is a func-  
tion of drain current, the mathematical solution is complex.  
The MOSFET output capacitance also complicates the  
mathematics. And finally, MOSFETs have finite internal gate  
resistance which effectively adds to the resistance of the  
driving source, but the internal resistance is difficult to mea-  
sure and, consequently, is not specified.  
The resistive switching time variation versus gate resis-  
tance (Figure 9) shows how typical switching performance is  
affected by the parasitic circuit elements. If the parasitics  
were not present, the slope of the curves would maintain a  
value of unity regardless of the switching speed. The circuit  
used to obtain the data is constructed to minimize common  
inductance in the drain and gate circuit loops and is believed  
readily achievable with board mounted components. Most  
power electronic loads are inductive; the data in the figure is  
taken with a resistive load, which approximates an optimally  
snubbed inductive load. Power MOSFETs may be safely op-  
erated into an inductive load; however, snubbing reduces  
switching losses.  
The published capacitance data is difficult to use for calculat-  
ing rise and fall because drain–gate capacitance varies  
greatly with applied voltage. Accordingly, gate charge data is  
used. In most cases, a satisfactory estimate of average input  
current (I  
) can be made from a rudimentary analysis of  
G(AV)  
the drive circuit so that  
t = Q/I  
G(AV)  
During the rise and fall time interval when switching a resis-  
tive load, V remains virtually constant at a level known as  
GS  
the plateau voltage, V  
. Therefore, rise and fall times may  
SGP  
be approximated by the following:  
t = Q x R /(V  
– V )  
GSP  
r
2
G
GG  
t = Q x R /V  
f
2
G
GSP  
where  
V
= the gate drive voltage, which varies from zero to V  
GG  
GG  
R
= the gate drive resistance  
G
and Q and V  
are read from the gate charge curve.  
GSP  
2
During the turn–on and turn–off delay times, gate current is  
not constant. The simplest calculation uses appropriate val-  
ues from the capacitance curves in a standard equation for  
voltage change in an RC network. The equations are:  
t
t
= R  
= R  
C
C
In [V  
/(V  
GG GG  
– V  
)]  
GSP  
d(on)  
G
iss  
In (V  
/V  
GG GSP  
)
d(off)  
G
iss  
space  
10000  
8000  
6000  
4000  
2000  
0
V
= 0 V  
V
= 0 V  
T
= 25°C  
DS  
GS  
J
C
rss  
C
iss  
C
oss  
C
rss  
10  
5
0
5
10  
15  
20  
25  
V
V
DS  
GS  
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)  
Figure 7. Capacitance Variation  
4
Motorola TMOS Power MOSFET Transistor Device Data  
1000  
12  
10  
120  
100  
QT  
V
= 75 V  
= 35 A  
= 10 V  
= 25°C  
DD  
I
V
T
D
GS  
V
GS  
J
Q2  
Q1  
8.0  
6.0  
4.0  
2.0  
0
80  
60  
40  
t
t
r
100  
f
t
d(off)  
T
= 25°C  
= 35 A  
J
I
D
t
d(on)  
20  
0
V
Q3  
20  
DS  
10  
0
10  
, GATE RESISTANCE (OHMS)  
G
100  
0
40  
60  
80  
100  
Q , TOTAL CHARGE (nC)  
R
T
Figure 8. Gate–To–Source and Drain–To–Source  
Voltage versus Total Charge  
Figure 9. Resistive Switching Time  
Variation versus Gate Resistance  
DRAIN–TO–SOURCE DIODE CHARACTERISTICS  
35  
V
T
= 0 V  
GS  
= 25  
30  
25  
20  
15  
10  
5
°C  
J
0
0.5  
0.55  
0.6  
0.65  
0.7  
0.75  
0.8  
0.85  
0.9  
0.95  
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)  
SD  
Figure 10. Diode Forward Voltage versus Current  
SAFE OPERATING AREA  
The Forward Biased Safe Operating Area curves define  
the maximum simultaneous drain–to–source voltage and  
drain current that a transistor can handle safely when it is for-  
ward biased. Curves are based upon maximum peak junc-  
able operation, the stored energy from circuit inductance dis-  
sipated in the transistor while in avalanche must be less than  
the rated limit and adjusted for operating conditions differing  
from those specified. Although industry practice is to rate in  
terms of energy, avalanche energy capability is not a con-  
stant. The energy rating decreases non–linearly with an in-  
crease of peak current in avalanche and peak junction  
temperature.  
tion temperature and a case temperature (T ) of 25°C. Peak  
C
repetitive pulsed power limits are determined by using the  
thermal response data in conjunction with the procedures  
discussed in AN569, “Transient Thermal Resistance–General  
Data and Its Use.”  
Although many E–FETs can withstand the stress of drain–  
to–source avalanche at currents up to rated pulsed current  
Switching between the off–state and the on–state may tra-  
verse any load line provided neither rated peak current (I  
)
DM  
) is exceeded and the transition time  
(I  
), the energy rating is specified at rated continuous cur-  
DM  
nor rated voltage (V  
DSS  
rent (I ), in accordance with industry custom. The energy rat-  
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-  
r f  
ing must be derated for temperature as shown in the  
accompanying graph (Figure 12). Maximum energy at cur-  
aged over a complete switching cycle must not exceed  
(T  
– T )/(R ).  
J(MAX)  
C
θJC  
rents below rated continuous I can safely be assumed to  
A Power MOSFET designated E–FET can be safely used  
D
in switching circuits with unclamped inductive loads. For reli-  
Motorola TMOS Power MOSFET Transistor Device Data  
equal the values indicated.  
5
SAFE OPERATING AREA  
600  
1000  
100  
V
= 20 V  
GS  
SINGLE PULSE  
= 25  
R
LIMIT  
DS(on)  
I
= 35 A  
D
THERMAL LIMIT  
PACKAGE LIMIT  
500  
400  
300  
200  
T
°C  
C
10 µs  
10  
100  
µs  
1 ms  
100  
0
10 ms  
DC  
1.0  
0.1  
1.0  
10  
100  
1000  
25  
50  
75  
100  
125  
C)  
150  
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)  
T , STARTING JUNCTION TEMPERATURE (  
°
DS  
J
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
Figure 12. Maximum Avalanche Energy versus  
Starting Junction Temperature  
1.0  
D = 0.05  
0.2  
0.1  
0.05  
P
(pk)  
0.1  
R
(t) = r(t) R  
JC θJC  
θ
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
0.02  
0.01  
t
READ TIME AT t  
T
1
1
SINGLE PULSE  
t
– T = P R (t)  
(pk) θJC  
2
J(pk)  
C
DUTY CYCLE, D = t /t  
1 2  
0.01  
1.0E–05  
1.0E–04  
1.0E–03  
1.0E–02  
1.0E–01  
1.0E+00  
1.0E+01  
t, TIME (s)  
Figure 13. Thermal Response  
di/dt  
I
S
t
rr  
t
t
a
b
TIME  
0.25 I  
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform  
6
Motorola TMOS Power MOSFET Transistor Device Data  
PACKAGE DIMENSIONS  
–T–  
E
–Q–  
M
M
0.25 (0.010)  
T B  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
–B–  
C
4
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
U
L
MILLIMETERS  
INCHES  
DIM  
A
B
C
D
E
MIN  
19.7  
15.3  
4.7  
1.0  
1.27 REF  
2.0  
5.5 BSC  
2.2  
0.4  
14.2  
MAX  
20.3  
15.9  
5.3  
MIN  
MAX  
0.799  
0.626  
0.209  
0.055  
A
K
0.776  
0.602  
0.185  
0.039  
0.050 REF  
0.079  
R
1
2
3
1.4  
F
2.4  
0.094  
–Y–  
G
H
J
K
L
0.216 BSC  
P
2.6  
0.8  
14.8  
0.087  
0.016  
0.559  
0.102  
0.031  
0.583  
5.5 NOM  
0.217 NOM  
P
3.7  
3.55  
5.0 NOM  
5.5 BSC  
3.0  
4.3  
3.65  
0.146  
0.140  
0.197 NOM  
0.217 BSC  
0.118 0.134  
0.169  
0.144  
V
H
Q
R
U
V
F
J
G
D
3.4  
M
S
0.25 (0.010)  
Y
Q
STYLE 1:  
PIN 1. GATE  
2. DRAIN  
3. SOURCE  
4. DRAIN  
CASE 340K–01  
ISSUE O  
Motorola TMOS Power MOSFET Transistor Device Data  
7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and  
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola  
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,includingTypicals”  
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of  
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other  
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury  
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Motorola was negligent regarding the design or manufacture of the part. Motorola and  
Opportunity/Affirmative Action Employer.  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal  
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USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;  
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MTW35N15E/D  

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