24AA014/24LC014 [ETC]
24AA014/24LC014 Device Datasheet ; 24AA014 / 24LC014器件数据表
| 型号： | 24AA014/24LC014 |
| 厂家： | 
ETC |
| 描述： | 24AA014/24LC014 Device Datasheet
|
| 文件： | 总22页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA014/24LC014
1K I2C™ Serial EEPROM
Device Selection Table
Package Types
PDIP/SOIC
Part
Number
VCC
Range
Max
Clock
Temp.
Range
A0
8
VCC
1
A1
A2
7
6
5
WP
2
3
4
24AA014 1.8V - 5.5V 400 kHz(1)
24LC014 2.5V - 5.5V 400 kHz
Note 1: 100 kHz for VCC < 2.5V
I
I
SCL
SDA
VSS
Features
TSSOP/MSOP
1
8
• Single-supply with operation down to 1.8V
• Low-power CMOS technology
A0
A1
A2
VCC
WP
SCL
SDA
2
3
4
7
6
5
- 1 mA active current, typical
VSS
- 1 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
• Hardware write protection for entire array
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz and 400 kHz clock compatibility
• Page write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 10 ms max. write cycle
Block Diagram
WP
A0 A1 A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles
• ESD protection > 4,000V
SDA
SCL
• Data retention > 200 years
Write-Protect
Circuitry
VCC
VSS
• 8-pin PDIP, SOIC, TSSOP and MSOP packages
• Available for extended temperature ranges
YDEC
- Industrial (I):
-40°C to +85°C
Sense Amp.
R/W Control
Description
The Microchip Technology Inc. 24AA014/24LC014 is a
1 Kbit Serial Electrically Erasable PROM with opera-
tion down to 1.8V. The device is organized as a single
block of 128 x 8-bit memory with a 2-wire serial inter-
face. Low current design permits operation with typical
standby and active currents of only 1 µA and 1 mA,
respectively. The device has a page write capability for
up to 16 bytes of data. Functional address lines allow
the connection of up to eight 24AA014/24LC014
devices on the same bus for up to 8 Kbits of contiguous
EEPROM memory. The device is available in the
standard 8-pin PDIP, 8-pin SOIC (150 mil), TSSOP and
MSOP packages.
Pin Function Table
Name
Function
VSS
SDA
Ground
Serial Data
Serial Clock
SCL
VCC
Power Supply
Chip Selects
A0, A1, A2
WP
Hardware Write-Protect
2003 Microchip Technology Inc.
DS21809B-page 1
24AA014/24LC014
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply across the
specified operating ranges unless
otherwise noted.
VCC = +1.8V to +5.5V
Industrial (I): TA = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High-level input voltage
VIH
0.7 VCC
—
—
0.3 VCC
—
V
V
V
V
Low-level input voltage
VIL
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
VHYS
VOL
0.05 VCC
—
(Note 1)
0.40
IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current
ILI
—
—
—
±1
±1
10
µΑ
µA
pF
VIN = 0.1V to 5.5V, WP = Vss
VOUT = 0.1V to 5.5V
Output leakage current
ILO
Pin capacitance (all inputs/outputs)
CIN, COUT
VCC = 5.0V (Note 1)
TA = 25°C, f = 1 MHz
Operating current
Standby current
ICC Read
ICC Write
ICCS
—
—
—
1
3
1
mA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
VCC = 5.5V, SDA = SCL = VCC
WP = VSS, A0, A1, A2 = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
DS21809B-page 2
2003 Microchip Technology Inc.
24AA014/24LC014
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply across the specified
operating ranges unless otherwise noted.
Vcc = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C
Vcc = 1.8V - 5.5V Vcc = 2.5V - 5.5V
STD MODE FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period, the first
clock pulse is generated
Start condition setup time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
Start condition
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
—
—
250
50
20 +0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression TSP
(SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
TWC
—
10
—
—
10
—
ms Byte or Page mode
1M
1M
cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at
www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
THIGH
TF
TR
SCL
TSU:STA
TLOW
THD:DAT
TSU:DAT
TSU:STO
SDA
IN
THD:STA
TSP
TBUF
TAA
SDA
OUT
2003 Microchip Technology Inc.
DS21809B-page 3
24AA014/24LC014
2.0
2.1
PIN DESCRIPTIONS
SDA Serial Data
3.0
FUNCTIONAL DESCRIPTION
The 24AA014/24LC014 supports a bidirectional, 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device that generates the serial
clock (SCL), controls the bus access and generates the
Start and Stop conditions while the 24AA014/24LC014
works as slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2
The levels on the inputs A0, A1 and A2 are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA014/24LC014 devices may be
connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
2.4
WP
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled. If the WP pin is tied to VSS the hardware
write protection is disabled.
2.5
Noise Protection
The 24AA014/24LC014 employs a VCC threshold
detector circuit that disables the internal erase/write
logic if the VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
DS21809B-page 4
2003 Microchip Technology Inc.
24AA014/24LC014
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, though only the last sixteen will
be stored when doing a write operation. When an over-
write does occur, it will replace data in a first-in first-out
fashion.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.5
Acknowledge
4.1
Bus not Busy (A)
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Note:
The 24AA014/24LC014 does not generate
any Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2).
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A) (B)
(C)
(D)
(C) (A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
2003 Microchip Technology Inc.
DS21809B-page 5
24AA014/24LC014
FIGURE 5-1:
CONTROL BYTE FORMAT
5.0
DEVICE ADDRESSING
Read/Write Bit
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code; for
the 24AA014/24LC014 this is set as ‘1010’ binary for
read and write operations. The next three bits of the
control byte are the Chip Select bits (A2, A1, A0). The
chip-select bits allow the use of up to eight 24AA014/
24LC014 devices on the same bus and are used to
select which device is accessed. The Chip Select bits
in the control byte must correspond to the logic levels
on the corresponding A2, A1 and A0 pins for the device
to respond. These bits are in effect the three Most
Significant bits of the word address.
Chip Select
Control Code
Bits
S
1
0
1
0
A2 A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. Following the Start condition, the 24AA014/
24LC014 monitors the SDA bus, checking the control
byte being transmitted. Upon receiving a ‘1010’ code
and appropriate Chip Select bits, the slave device out-
puts an Acknowledge signal on the SDA line. Depend-
ing on the state of the R/W bit, the 24AA014/24LC014
will select a read or write operation.
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA014/24LC014 devices on
the same bus. In this case, software can use A0 of the
control byte as address bit A8, A1 as address bit A9
and A2 as address bit A10. It is not possible to
sequentially read across device boundaries.
DS21809B-page 6
2003 Microchip Technology Inc.
24AA014/24LC014
The higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an inter-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if write protection is enabled.
6.0
6.1
WRITE OPERATIONS
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24AA014/
24LC014. After receiving another Acknowledge signal
from the 24AA014/24LC014, the master device will
transmit the data word to be written into the addressed
memory location. The 24AA014/24LC014 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and the
24AA014/24LC014 will not generate Acknowledge
signals during this time (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if write protection is enabled.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary that the
application software prevent page write
operations that would attempt to cross a
page boundary.
6.2
Page Write
The write-control byte, word address and the first data
byte are transmitted to the 24AA014/24LC014 in the
same way as in a byte write. But instead of generating
a Stop condition, the master transmits up to 15 addi-
tional data bytes to the 24AA014/24LC014 that are
temporarily stored in the on-chip page buffer and will be
written into the memory once the master has transmit-
ted a Stop condition. Upon receipt of each word, the
four lower order address pointer bits are internally
incremented by one.
6.3
WRITE PROTECTION
The WP pin must be tied to VCC or VSS. If tied to VCC,
the entire array will be write-protected. If the WP pin is
tied to VSS, write operations to all address locations are
allowed.
FIGURE 6-1:
BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
O
P
ADDRESS (n)
DATA (n)
DATA (n +1)
DATA (n + 15)
SDA LINE
S
P
A
A
A
C
K
A
C
K
A
C
K
C
C
BUS ACTIVITY
K
K
2003 Microchip Technology Inc.
DS21809B-page 7
24AA014/24LC014
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a write command (R/W = 0). If the device is still busy
with the write cycle, no ACK will be returned. If no ACK
is returned, the Start bit and control byte must be re-
sent. If the cycle is complete, the device will return the
ACK and the master can then proceed with the next
read or write command. See Figure 7-1 for a flow
diagram of this operation.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS21809B-page 8
2003 Microchip Technology Inc.
24AA014/24LC014
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal address pointer is set. The master then issues
the control byte again but with the R/W bit set to a ‘1’.
The 24AA014/24LC014 will then issue an acknowl-
edge and transmits the eight-bit data word. The master
will not acknowledge the transfer but does generate a
Stop condition and the 24AA014/24LC014 discontin-
ues transmission (Figure 8-2). After this command, the
internal address counter will point to the address
location following the one that was just read.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24AA014/24LC014 contains an address counter
that maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to ‘1’, the 24AA014/24LC014 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does
generate a Stop condition and the 24AA014/24LC014
discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24AA014/24LC014
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a
random read. This directs the 24AA014/24LC014 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3).
8.2
Random Read
To provide sequential reads the 24AA014/24LC014
contains an internal address pointer which is incre-
mented by one at the completion of each operation.
This address pointer allows the entire memory contents
to be serially read during one operation. The internal
address pointer will automatically roll over from
address 0FFh to address 000h.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24AA014/24LC014 as part of a write operation.
FIGURE 8-1:
CURRENT ADDRESS READ
S
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
A
R
T
DATA
BYTE
SDA LINE
P
S
A
C
K
N
O
A
C
K
BUS ACTIVITY
2003 Microchip Technology Inc.
DS21809B-page 9
24AA014/24LC014
FIGURE 8-2:
RANDOM READ
S
T
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
CONTROL
WORD
ADDRESS (n)
CONTROL
BYTE
A
R
T
DATA (n)
BYTE
O
P
S
P
S
SDA LINE
N
O
A
C
K
A
C
K
A
A
C
K
C
K
BUS ACTIVITY
FIGURE 8-3:
BUS ACTIVITY
SEQUENTIAL READ
S
T
CONTROL
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
MASTER
O
P
BYTE
P
SDA LINE
A
C
K
A
C
K
A
A
N
C
C
O
K
K
BUS ACTIVITY
A
C
K
DS21809B-page 10
2003 Microchip Technology Inc.
24AA014/24LC014
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
T/XXXNNN
24LC014
I/P12F
YYWW
0321
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
T/XXYYWW
24LC014
I/SN0321
NNN
12F
Example:
8-Lead TSSOP
4L14
I321
12F
XXXX
TYWW
NNN
Part
TSSOP/MSOP
Number
Marking Code
24AA014
24LC014
4A14
4L14
Example:
8-Lead MSOP
XXXXT
4L14I
32112F
YWWNNN
Legend: XX...X Customer specific information*
T
Temperature grade (I,E)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
2003 Microchip Technology Inc.
DS21809B-page 11
24AA014/24LC014
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21809B-page 12
2003 Microchip Technology Inc.
24AA014/24LC014
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
A
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2003 Microchip Technology Inc.
DS21809B-page 13
24AA014/24LC014
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
A1
A2
φ
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
3.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.035
.004
.251
.173
.118
.024
4
.037
.006
.256
.177
.122
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
3.00
0.60
4
§
.002
.246
.169
.114
.020
0
Overall Width
6.25
4.30
2.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21809B-page 14
2003 Microchip Technology Inc.
24AA014/24LC014
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
Molded Package Thickness
Standoff
.030
.000
.033
-
.037
.006
0.75
0.00
0.85
-
0.95
0.15
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
.118 BSC
3.00 BSC
3.00 BSC
L
.016
.024
.037 REF
.031
0.40
0.60
0.95 REF
0.80
Footprint (Reference)
Foot Angle
F
φ
c
0°
.003
.009
5°
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
.006
B
α
β
.012
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
-
-
5°
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
2003 Microchip Technology Inc.
DS21809B-page 15
24AA014/24LC014
APPENDIX A: REVISION HISTORY
Revision B
Corrections to Section 1.0, Electrical Characteristics.
DS21809B-page 16
2003 Microchip Technology Inc.
24AA014/24LC014
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
DS21809B-page 17
24AA014/24LC014
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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Reader Response
Total Pages Sent ________
RE:
From:
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Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
24AA014/24LC014
DS21809B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21809B-page 18
2003 Microchip Technology Inc.
24AA014/24LC014
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
a) 24AA014-I/P: Industrial Temperature,
1.8V, PDIP package.
Temperature Package
Range
b) 24AA014-I/SN: Industrial Temperature,
1.8V, SOIC Package.
c) 24AA014T-I/ST: Industrial Temperature,
1.8V, TSSOP Package, Tape and Reel
Device:
24AA014: 1.8V, 1 Kbit Addressable Serial EEPROM
24AA014T: 1.8V, 1 Kbit Addressable Serial EEPROM
(Tape and Reel)
24LC014: 2.5V, 1 Kbit Addressable Serial EEPROM
24LC014T: 2.5V, 1 Kbit Addressable Serial EEPROM
(Tape and Reel)
a) 24LC014-I/P: Industrial Temperature,
2.5V, PDIP Package.
b) 24LC014T-I/SN: Industrial Temperature,
2.5V, SOIC Package, Tape and Reel
c) 24LC014T-I/MS: Industrial Temperature,
2.5V, MSOP Package, Tape and Reel.
Temperature Range:
Package:
I
=
-40°C to +85°C
P
=
=
=
=
Plastic DIP, (300 mil Body), 8-lead
Plastic SOIC, (150 mil Body)
TSSOP, 8-lead
SN
ST
MS
MSOP, 8-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
DS21809B-page 19
24AA014/24LC014
NOTES:
DS21809B-page 20
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS21809B-page 21
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
2355 West Chandler Blvd.
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Tel: 480-792-7200
Suite 22, 41 Rawson Street
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Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
200 Middle Road
#07-02 Prime Centre
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Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
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Tel: 770-640-0034
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Taiwan
Kaohsiung Branch
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China - Chengdu
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Taiwan
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Italy
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San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
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Fax: 408-436-7955
India
Toronto
Divyasree Chambers
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Japan
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Tel: 905-673-0699
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS21809B-page 22
2003 Microchip Technology Inc.
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