24AA128E/ST14 [ETC]
EEPROM ; EEPROM\n
| 型号： | 24AA128E/ST14 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总28页 (文件大小：553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA128/24LC128/24FC128
M
128K I2C™CMOS Serial EEPROM
Features
Description
• Low power CMOS technology
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.8 V to
5.5 V). It has been developed for advanced, low power
applications such as personal communications or data
acquisition. This device also has a page-write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (150 and 208 mil), TSSOP, MSOP,
DFN and 14-lead TSSOP packages.
- Maximum write current 3 mA at 5.5 V
- Maximum read current 400 µA at 5.5 V
- Standby current 100 nA typical at 5.5 V
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles
Block Diagram
• Electrostatic discharge protection > 4000 V
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN
packages
A0 A1 A2WP
HV GENERATOR
• 14-lead TSSOP package
I/O
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
CONTROL
LOGIC
XDEC
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
-40°C to +125°C
PAGE LATCHES
- Automotive (E):
I/O
SCL
Device Selection Table
YDEC
SDA
Part
VCC
Max. Clock
Frequency
Temp.
Number
Range
Ranges
VCC
VSS
(1)
24AA128
1.8-5.5 V
400 kHz
I
SENSE AMP
R/W CONTROL
24LC128
24FC128
2.5-5.5 V
2.5-5.5 V
400 kHz
1 MHz
I, E
I
Note 1: 100 kHz for VCC < 2.5 V.
Package Types
PDIP/SOIC
TSSOP/MSOP *
TSSOP
DFN
14
13
12
11
10
9
1
VCC
WP
NC
NC
NC
SCL
SDA
A0
A0
1
8
VCC
1
2
3
4
A0
A1
8
7
6
5
VCC
WP
1
2
3
4
8
7
6
5
A0
A1
VCC
WP
2
3
4
5
6
7
A1
A1
A2
2
3
4
7
6
5
WP
NC
NC
NC
A2
A2
SCL
SDA
SCL
SDA
A2
SCL
SDA
VSS
VSS
VSS
8
VSS
* Pins A0 and A1 are no connects for the MSOP package only.
*24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices.
2002 Microchip Technology Inc.
DS21191J-page 1
24AA128/24LC128/24FC128
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC............................................................................................................................................................................6.5 V
All inputs and outputs w.r.t. VSS ....................................................................................................... -0.6 V to VCC +1.0 V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temp. with power applied ..........................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.1
24AA128/24LC128/24FC128 DC Specifications
Electrical Characteristics:
DC SPECIFICATIONS
Industrial (I):
VCC = +1.8 V to 5.5 V TAMB = -40°C to +85°C
VCC = +2.5 V to 5.5 V TAMB = -40°C to 125°C
Automotive (E):
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
Conditions
D1
—
A0, A1, A2, SCL, SDA, and
WP pins:
High level input voltage
Low level input voltage
—
—
—
—
—
D2
D3
VIH
VIL
0.7 VCC
—
V
V
V
—
0.3 VCC
VCC ≥ 2.5 V
0.2 VCC
VCC < 2.5 V
D4
VHYS
Hysteresis of Schmitt Trigger 0.05 VCC
—
V
VCC ≥ 2.5 V (Note 1)
inputs
(SDA, SCL pins)
D5
D6
VOL
ILI
Low level output voltage
Input leakage current
Output leakage current
—
—
0.40
±10
V
IOL = 3.0 mA @ VCC = 4.5 V
IOL = 2.1 mA @ VCC = 2.5 V
µA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7
D8
ILO
—
—
±10
10
µA
pF
VOUT = VSS or VCC
CIN,
Pin capacitance
(all inputs/outputs)
VCC = 5.0 V (Note 1)
COUT
TAMB = 25°C, fC= 1 MHz
D9
ICC Read Operating current
ICC Write
—
—
—
400
3
1
µA
mA
µA
VCC = 5.5 V, SCL = 400 kHz
VCC = 5.5 V
TAMB = -40°C to +85°C
SCL = SDA = VCC = 5.5 V
A0, A1, A2, WP = VSS
D10
ICCS
Standby current
—
5
µA
TAMB = -40°C to 125°C
SCL = SDA = VCC = 5.5 V
A0, A1, A2, WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
DS21191J-page 2
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
1.2
24AA128/24LC128/24FC128 AC SPECIFICATIONS
Electrical Characteristics:
AC SPECIFICATIONS
Industrial (I):
VCC = +1.8 V to 5.5 V TAMB = -40°C to +85°C
Automotive (E): VCC = +2.5 V to 5.5 V TAMB = -40°C to 125°C
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
Conditions
1
2
3
4
FCLK Clock frequency
—
—
—
100
400
kHz 1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
1000
2.5 V ≤ VCC ≤ 5.5 V 24FC128
THIGH Clock high time
4000
—
—
—
—
—
—
ns
ns
ns
1.8 V ≤ VCC < 2.5 V
600
2.5 V ≤ VCC ≤ 5.5 V
500
2.5 V ≤ VCC ≤ 5.5 V 24FC128
TLOW Clock low time
4700
1300
500
—
—
—
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
2.5 V ≤ VCC ≤ 5.5 V 24FC128
TR
SDA and SCL rise time
(Note 1)
1000
1.8 V ≤ VCC < 2.5 V
300
2.5 V ≤ VCC ≤ 5.5 V
300
2.5 V ≤ VCC ≤ 5.5 V 24FC128
5
6
TF
SDA and SCL fall time
—
300
ns
ns
All except, 24FC128
(Note 1)
—
100
2.5 V ≤ VCC ≤ 5.5 V 24FC128
THD:STA START condition hold time
4000
600
250
—
—
—
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
2.5 V ≤ VCC ≤ 5.5 V 24FC128
7
TSU:STA START condition setup time
4700
—
—
—
ns
1.8 V ≤ VCC < 2.5 V
600
2.5 V ≤ VCC ≤ 5.5 V
250
2.5 V ≤ VCC ≤ 5.5 V 24FC128
8
9
THD:DAT Data input hold time
TSU:DAT Data input setup time
0
—
ns
ns
(Note 2)
250
100
100
—
—
—
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
2.5 V ≤ VCC ≤ 5.5 V 24FC128
10
11
12
13
14
TSU:STO STOP condition setup time
TSU:WP WP setup time
4000
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.8 V ≤ VCC < 2.5 V
600
2.5 V ≤ VCC ≤ 5.5 V
250
2.5 V ≤ VCC ≤ 5.5 V 24FC128
4000
1.8 V ≤ VCC < 2.5 V
600
2.5 V ≤ VCC ≤ 5.5 V
600
2.5 V ≤ VCC ≤ 5.5 V 24FC128
THD:WP WP hold time
4700
1300
1300
—
—
—
4700
1300
500
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
2.5 V ≤ VCC ≤ 5.5 V 24FC128
TAA Output valid from clock
3500
1.8 V ≤ VCC < 2.5 V
(Note 2)
900
2.5 V ≤ VCC ≤ 5.5 V
400
2.5 V ≤ VCC ≤ 5.5 V 24FC128
TBUF Bus free time: Time the bus
must be free before a new
transmission can start
—
—
—
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
2.5 V ≤ VCC ≤ 5.5 V 24FC128
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model, which can be obtained on Microchip’s website:
www.microchip.com.
2002 Microchip Technology Inc.
DS21191J-page 3
24AA128/24LC128/24FC128
1.2
24AA128/24LC128/24FC128 AC SPECIFICATIONS (Continued)
Electrical Characteristics:
AC SPECIFICATIONS
Industrial (I):
VCC = +1.8 V to 5.5 V TAMB = -40°C to +85°C
Automotive (E): VCC = +2.5 V to 5.5 V TAMB = -40°C to 125°C
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
Conditions
15
TOF Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB
250
250
ns
All except, 24FC128 (Note 1)
24FC128 (Note 1)
16
17
18
TSP Input filter spike suppression
—
—
50
5
ns
All except, 24FC128 (Notes 1
and 3)
—
(SDA and SCL pins)
TWC Write cycle time (byte or
page)
ms
—
Endurance
1,000,000
—
cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model, which can be obtained on Microchip’s website:
www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
4
D4
2
SCL
7
3
10
8
9
SDA
IN
6
16
14
12
13
SDA
OUT
(protected)
(unprotected)
WP
11
DS21191J-page 4
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
8-pin
PDIP
8-pin
SOIC
8-pin
14-pin
8-pin
8-pin
DFN
Function
TSSOP
TSSOP
MSOP
A0
A1
(NC)
A2
VSS
SDA
SCL
(NC)
WP
VCC
1
2
—
3
4
5
6
—
7
1
2
—
3
4
5
6
—
7
1
2
—
3
4
5
6
—
7
1
2
—
—
1,2
3
4
5
6
—
7
1
2
—
3
4
5
6
—
7
User Configurable Chip Select
User Configurable Chip Select
Not Connected
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write Protect Input
3, 4, 5
6
7
8
9
10, 11,12
13
8
8
8
14
8
8
+1.8 V to 5.5 V (24AA128)
+2.5 V to 5.5 V (24LC128)
+2.5 V to 5.5 V (24FC128)
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
This input is used to synchronize the data transfer to
and from the device.
2.4
Write Protect (WP)
For the MSOP package only, pins A0 and A1 are not
connected.
This pin can be connected to either VSS, VCC or left
floating. Internal pull-down circuitry on this pin will keep
the device in the unprotected state if left floating. If tied
to VSS or left floating, normal memory operation is
enabled (read/write the entire memory 0000-3FFF).
If tied to VCC, WRITE operations are inhibited. Read
operations are not affected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different chip
select bit combinations. If these pins are left uncon-
nected, the inputs will be pulled down internally to VSS.
If they are tied to VCC or driven high, the internal pull-
down circuitry is disabled.
In most applications, the chip address inputs A0, A1,
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For appli-
cations in which these pins are controlled by a micro-
controller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
3.0
FUNCTIONAL DESCRIPTION
The 24XX128 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access and generates the
START and STOP conditions while the 24XX128 works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device deter-
mines which mode is activated.
2.2
Serial Data (SDA)
This is a bi-directional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
2002 Microchip Technology Inc.
DS21191J-page 5
24AA128/24LC128/24FC128
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
4.5
Acknowledge
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse, which is associated with this acknowledge
bit.
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
Note: The 24XX128 does not generate any
acknowledge bits if an internal
programming cycle is in progress.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24XX128) will leave the data line HIGH
to enable the master to generate the STOP condition.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line, while the
clock (SCL) is HIGH, determines a STOP condition. All
operations must end with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
STOP
CONDITION
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
DS21191J-page 6
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code. For the
24XX128, this is set as 1010binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX128 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three most significant bits of the word
address.
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
0
A2 A1 A0 R/W ACK
Slave Address
Start Bit
Acknowledge Bit
5.1
Contiguous Addressing Across
Multiple Devices
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
chip select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX128 MSOP packages can be con-
nected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A13…A0 are used, the upper two address bits are
don’t care bits. The upper address bits are transferred
first, followed by the less significant bits.
Following the start condition, the 24XX128 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010code and appro-
priate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX128 will select a read or
write operation.
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 1 Mbit by add-
ing up to eight 24XX128s on the same bus. In this case,
software can use A0 of the control byte as address bit
A14; A1 as address bit A15; and A2 as address bit A16.
It is not possible to sequentially read across device
boundaries.
For the MSOP package, up to two 24XX128 devices
can be added for up to 256 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A16. Bits A0 (A14) and A1 (A15) of the con-
trol byte must always be set to logic ‘0’ for the MSOP.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
A
A
A
2
A
1
A
0
A
A
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
X
X
10
12 11
13
CONTROL
CODE
CHIP
X = Don’t Care Bit
SELECT
BITS
2002 Microchip Technology Inc.
DS21191J-page 7
24AA128/24LC128/24FC128
condition, the address counter will roll over and the pre-
viously received data will be overwritten. As with the
byte write operation, once the stop condition is
received, an internal write cycle will begin (Figure 6-2).
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the com-
mand but no write cycle will occur, no data will be writ-
ten and the device will immediately accept a new
command.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start condition from the master, the
control code (four bits), the chip select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX128. The next byte is the least sig-
nificant address byte. After receiving another acknowl-
edge signal from the 24XX128, the master device will
transmit the data word to be written into the addressed
memory location. The 24XX128 acknowledges again
and the master generates a stop condition. This ini-
tiates the internal write cycle and during this time the
24XX128 will not generate acknowledge signals
(Figure 6-1). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command but no write cycle will occur, no data will
be written and the device will immediately accept a new
command. After a byte write command, the internal
address counter will point to the address location fol-
lowing the one that was just written.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-3FFF) when the pin is tied to VCC. If tied
to VSS or left floating, the write protection is disabled.
The WP pin is sampled at the STOP bit for every write
command (Figure 1-1). Toggling the WP pin after the
STOP bit will have no effect on the execution of the
write cycle.
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a phys-
ical page boundary, the result is that
the data wraps around to the beginning
of the current page (overwriting data
previously stored there), instead of
being written to the next page, as
might be expected. It is, therefore, nec-
essary for the application software to
prevent page write operations that
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX128 in much the same
way as in a byte write. The exception is that instead of
generating a stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer and will be written into memory
once the master has transmitted a stop condition. Upon
receipt of each word, the six lower address pointer bits
are internally incremented by ‘1’. If the master should
transmit more than 64 bytes prior to generating the stop
would attempt to cross
boundary.
a
page
FIGURE 6-1:
BYTE WRITE
S
BUS ACTIVITY
T
A
R
T
S
CONTROL
BYTE
ADDRESS
ADDRESS
LOW BYTE
MASTER
T
O
P
HIGH BYTE
DATA
A A A
SDA LINE
X X
S 1 0 1 0
0
P
2 1 0
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = don’t care bit
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
S
T
CONTROL
BYTE
ADDRESS
ADDRESS
LOW BYTE
BUS ACTIVITY
HIGH BYTE
DATA BYTE 0
DATA BYTE 63
O
P
MASTER
A A A
2 1 0
SDA LINE
X X
P
S 1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
A
C
K
C
K
BUS ACTIVITY
X = don’t care bit
DS21191J-page 8
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the STOP condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a START condition, followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2002 Microchip Technology Inc.
DS21191J-page 9
24AA128/24LC128/24FC128
8.2
Random Read
8.0
READ OPERATION
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX128 as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master gener-
ates a start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. The master then issues the
control byte again but with the R/W bit set to a ‘1’. The
24XX128 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition, which
causes the 24XX128 to discontinue transmission
(Figure 8-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX128 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address n(nis any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX128 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a STOP condition and the
24XX128 discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24XX128 transmits the
first data byte, the master issues an acknowledge as
opposed to the STOP condition used in a random read.
This acknowledge directs the 24XX128 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a STOP condition. To provide sequential reads,
the 24XX128 contains an internal address pointer
which is incremented by one at the completion of each
operation. This address pointer allows the entire mem-
ory contents to be serially read during one operation.
The internal address pointer will automatically roll over
from address 3FFF to address 0000 if the master
acknowledges the byte received from the array
address 3FFF.
FIGURE 8-1:
CURRENT ADDRESS
READ
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA
BYTE
O
P
A A A
2 1 0
SDA LINE
S 1 0 1 0
1
P
A
C
K
N
O
A
C
K
BUS ACTIVITY
FIGURE 8-2:
RANDOM READ
S
T
A
R
T
S
BUS ACTIVITY
MASTER
T
A
R
T
S
T
CONTROL
BYTE
ADDRESS
ADDRESS
LOW BYTE
CONTROL
BYTE
DATA
BYTE
HIGH BYTE
O
P
A A A
A A A
SDA LINE
X X
S 1 0 1 0
0
S 1 0 1 0
1
P
2 1 0
2 1 0
A
C
K
A
C
K
A
C
K
N
O
A
C
A
C
K
BUS ACTIVITY
X = Don’t Care Bit
FIGURE 8-3:
SEQUENTIAL READ
S
CONTROL
BUS ACTIVITY
MASTER
T
BYTE
DATA (n)
DATA (n + 1)
DATA (n + X)
DATA (n + 2)
O
P
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
BUS ACTIVITY
DS21191J-page 10
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
24AA128
I/P017
0110
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
24LC128
I/SN0110
NNN
017
8-Lead SOIC (208 mil)
Example:
XXXXXXXX
24LC128
I/SM
0110017
XXXXXXXX
YYWWNNN
Example:
8-Lead TSSOP
XXXX
XYWW
4LC
I101
NNN
017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
YY
WW
NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard device marking consists of Microchip part number, year code, week code, and traceability
code. For device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office.
2002 Microchip Technology Inc.
DS21191J-page 11
24AA128/24LC128/24FC128
Package Marking Information (Continued)
8-Lead MSOP
Example:
XXXXXX
YWWNNN
4L128I
101017
8-Lead DFN
Example:
XXXXXXXX
XXXXXXXX
YYWWNNN
24LC128
XXXXXXXX
0110017
14-Lead TSSOP
Example:
XXXXXXXX
YYWW
24LC128I
0110
NNN
017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
YY
WW
NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard device marking consists of Microchip part number, year code, week code, and traceability
code. For device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office.
DS21191J-page 12
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
1
n
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
8
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
8
.100
.155
.130
2.54
3.94
3.30
.140
.170
.145
3.56
2.92
4.32
3.68
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2002 Microchip Technology Inc.
DS21191J-page 13
24AA128/24LC128/24FC128
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45×
c
A2
A
f
β
L
A1
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
8
MAX
n
p
A
A2
A1
E
E1
D
h
L
f
c
B
α
β
Number of Pins
Pitch
Overall Height
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
Standoff
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21191J-page 14
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
E
E1
p
D
2
1
n
B
α
c
A2
A
f
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
A
A2
A1
E
E1
D
L
f
c
B
α
β
Number of Pins
Pitch
Overall Height
8
.050
.075
.074
.005
.313
.208
.205
.025
4
1.27
.070
.080
1.78
1.75
1.97
1.88
0.13
7.95
5.28
5.21
0.64
4
2.03
Molded Package Thickness
Standoff
.069
.002
.300
.201
.202
.020
0
.008
.014
0
.078
.010
.325
.212
.210
.030
8
.010
.020
15
1.98
0.25
8.26
5.38
5.33
0.76
8
0.25
0.51
15
§
0.05
7.62
5.11
5.13
0.51
0
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
.009
.017
12
0.20
0.36
0
0.23
0.43
12
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
2002 Microchip Technology Inc.
DS21191J-page 15
24AA128/24LC128/24FC128
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
A1
A2
φ
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
Overall Height
8
.026
0.65
A
.043
1.10
0.95
0.15
6.50
4.50
3.10
0.70
8
Molded Package Thickness
A2
A1
E
.033
.035
.004
.251
.173
.118
.024
4
.037
.006
.256
.177
.122
.028
8
0.85
0.05
6.25
4.30
2.90
0.50
0
0.90
0.10
6.38
4.40
3.00
0.60
4
Standoff
§
.002
.246
.169
.114
.020
0
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
E1
D
L
φ
c
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21191J-page 16
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
p
E1
D
2
1
B
n
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
8
n
p
Number of Pins
Pitch
8
.026
0.65
Overall Height
Molded Package Thickness
A
A2
A1
E
E1
D
.044
1.18
.030
.034
.038
.006
.200
.122
.122
.028
.039
0.76
0.05
0.86
0.97
0.15
.5.08
3.10
3.10
0.70
1.00
Standoff
§
.002
.184
.114
.114
.016
.035
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint (Reference)
Foot Angle
.193
.118
.118
.022
.037
4.90
3.00
3.00
0.55
0.95
4.67
2.90
2.90
0.40
0.90
L
F
φ
0
6
0
6
c
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
.004
.010
.006
.012
.008
.016
0.10
0.25
0.15
0.30
0.20
0.40
B
α
β
7
7
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
2002 Microchip Technology Inc.
DS21191J-page 17
24AA128/24LC128/24FC128
8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Formerly MLF)
E
p
B
E1
n
L
R
D1
D
D2
PIN 1
EXPOSED
METAL
PADS
ID
1
2
E2
BOTTOM VIEW
TOP VIEW
α
A2
A3
A
A1
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
8
1.27 BSC
0.85
MAX
n
p
A
Number of Pins
Pitch
8
.050 BSC
.033
Overall Height
Molded Package Thickness
Standoff
Base Thickness
Overall Length
Molded Package Length
Exposed Pad Length
Overall Width
.039
1.00
0.80
0.05
A2
A1
A3
E
E1
E2
D
D1
D2
B
.026
.0004
.031
.002
0.65
.000
.152
0.00
0.01
0.20 REF.
4.92 BSC
4.67 BSC
4.00
5.99 BSC
5.74 BSC
2.31
.008 REF.
.194 BSC
.184 BSC
.158
.236 BSC
.226 BSC
.091
.163
3.85
4.15
Molded Package Width
Exposed Pad Width
Lead Width
.085
.014
.020
.097
.019
.030
2.16
0.35
0.50
2.46
0.47
0.75
.016
.024
0.40
0.60
Lead Length
L
Tie Bar Width
Mold Draft Angle Top
R
α
.014
.356
12
12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-113
DS21191J-page 18
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Continued)
M
SOLDER
MASK
M
p
B
PACKAGE
EDGE
L
Units
INCHES
NOM
.050 BSC
.016
MILLIMETERS*
NOM
Dimension Limits
MIN
.014
MAX
.019
MIN
MAX
0.47
p
Pitch
Pad Width
Pad Length
1.27 BSC
B
L
M
0.35
0.50
0.13
0.40
0.60
.020
.005
.024
.030
.006
0.75
0.15
Pad to Solder Mask
*Controlling Parameter
Drawing No. C04-2113
2002 Microchip Technology Inc.
DS21191J-page 19
24AA128/24LC128/24FC128
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
f
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
Overall Height
14
.026
0.65
A
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
A2
A1
E
E1
D
L
f
c
.033
.002
.246
.169
.193
.020
0
.004
.007
0
.035
.004
.251
.173
.197
.024
4
.006
.010
5
.037
.006
.256
.177
.201
.028
8
.008
.012
10
0.85
0.05
6.25
4.30
4.90
0.50
0
0.09
0.19
0
0.90
0.10
6.38
4.40
5.00
0.60
4
0.15
0.25
5
Standoff
§
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.20
0.30
10
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS21191J-page 20
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
Preliminary
DS21191J-page 21
24AA128/24LC128/24FC128
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Reader Response
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RE:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
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Literature Number:
DS21191J
Device:
24AA128/24LC128/24FC128
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS21191J-page 22
Preliminary
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
a)
24AA128-I/P:
Industrial Temperature,
Temperature Package
Range
PDIP package.
b)
c)
d)
24AA128T-I/SN: Tape and Reel,
Industrial Temp., SOIC package.
24AA128-I/ST: Industrial Temperature,
TSSOP package.
Device:
24AA128:
128 Kbit 1.8V I2C Serial EEPROM
24AA128-I/MS: Industrial Temperature,
MSOP package.
24AA128T: 128 Kbit 1.8V I2C Serial EEPROM
(Tape and Reel)
24LC128:
128 Kbit 2.5V I2C Serial EEPROM
a)
24LC128-E/P: Extended Temperature,
PDIP package.
24LC128T: 128 Kbit 2.5V I2C Serial EEPROM
(Tape and Reel)
b)
c)
d)
24LC128-I/SN: Industrial Temperature,
SOIC package.
24FC128:
128 Kbit 1 MHz I2C Serial EEPROM
24FC128T: 128 Kbit 1 MHz I2C Serial EEPROM
(Tape and Reel)
24LC128T-I/SN: Tape and Reel,
Industrial Temperature, SOIC package.
24LC128-I/MS: Industrial Temperature,
MSOP package.
Temperature Range:
Package:
I
=
=
-40°C to +85°C
-40°C to +125°C
E
a)
24FC128-I/P:
Industrial Temperature,
PDIP package.
b)
c)
24FC128-I/SN: Industrial Temperature,
SOIC package.
P
=
=
=
=
=
=
=
Plastic DIP (300 mil body), 8-lead
SN
SM
ST
Plastic SOIC (150 mil body), 8-lead
Plastic SOIC (208 mil body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
24FC128T-I/SN: Tape and Reel,
Industrial Temperature, SOIC package
ST14
MF
Plastic TSSOP (4.4 mm), 14-lead
Dual, Flat, No Lead (DFN)(6x5 mm body), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
MS
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
Preliminary
DS21191J-page23
24AA128/24LC128/24FC128
NOTES:
DS21191J-page24
Preliminary
2002 Microchip Technology Inc.
24AA128/24LC128/24FC128
NOTES:
2002 Microchip Technology Inc.
Preliminary
DS21191J-page25
24AA128/24LC128/24FC128
NOTES:
DS21191J-page 26
Preliminary
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
®
PICmicro 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21191J - page 27
M
WORLDWIDE SALES AND SERVICE
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AMERICAS
ASIA/PACIFIC
Microchip Technology Japan K.K.
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Corporate Office
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05/16/02
DS21191J-page 28
2002 Microchip Technology Inc.
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